GS820E32AT-180/166/133/4/5 TQFP Commercial Temp Industrial Temp 64K x 32 2Mb Synchronous Burst SRAM Features • FT pin for user-configurable flow through or pipelined operation • Dual Cycle Deselect (DCD) operation • 3.3 V +10%/–5% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipelined mode • Byte Write (BW) and/or Global Write (GW) operation • Common data inputs and data outputs • Clock Control, registered, address, data, and control • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC standard 100-lead TQFP package • Pb-Free 100-lead TQFP package available Functional Description Applications The GS820E32A is a 2,097,152-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Controls Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address Rev: 1.07 10/2004 180 MHz–133 MHz 3.3 V VDD 3.3 V and 2.5 V I/O counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Flow Through/Pipeline Reads The function of the Data Output Register can be controlled by the user via the FT mode pin (Pin 14 in the TQFP). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipelined mode, activating the rising-edge-triggered Data Output Register. DCD Pipelined Reads The GS820E32A is a DCD (Dual Cycle Deselect) pipelined synchronous SRAM. SCD (Single Cycle Deselect) versions are also available. DCD SRAMs pipeline disable commands to the same degree as read commands. DCD SRAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of the clock. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS820E32A operates on a 3.3 V power supply and all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuit. 1/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, GSI Technology GS820E32AT-180/166/133/4/5 Parameter Synopsis Pipeline 3-1-1-1 Flow Through 2-1-1-1 Rev: 1.07 10/2004 tCycle tKQ IDD tCycle tKQ IDD -180 5.5 ns 3.2 ns 155 mA 9.1 ns 8 ns 100 mA -166 6 ns 3.5 ns 140 mA 10 ns 8.5 ns 90 mA -133 (-4) 7.5 ns 4 ns 115 mA 12 ns 10 ns 80 mA -5 10 ns 5 ns 90 mA 15 ns 12 ns 65 mA 2/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, GSI Technology GS820E32AT-180/166/133/4/5 A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A GS82032A 100-Pin TQFP Pinout NC DQC DQC VDDQ NC DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA NC LBO A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A NC VSS DQC DQC DQC DQC VSS VDDQ DQC DQC FT VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 64K x 32 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev: 1.07 10/2004 3/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, GSI Technology GS820E32AT-180/166/133/4/5 TQFP Pin Description Symbol Type Description A 0, A 1 I Address field LSBs and Address Counter preset Inputs A I Address Inputs DQA DQB DQC DQD I/O Data Input and Output pins NC No Connect BW I Byte Write—Writes all enabled bytes; active low BA , BB I Byte Write Enable for DQA, DQB Data I/Os; active low BC , BD I Byte Write Enable for DQC, DQD Data I/Os; active low CK I Clock Input Signal; active high GW I Global Write Enable—Writes all bytes; active low E 1, E 3 I Chip Enable; active low E2 I Chip Enable; active high G I Output Enable; active low ADV I Burst address counter advance enable; active low ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep Mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active low VDD I Core power supply VSS I I/O and Core Ground VDDQ I Output driver power supply Rev: 1.07 10/2004 4/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, GSI Technology GS820E32AT-180/166/133/4/5 GS82032A Block Diagram A0–An Register D Q A0 A0 D0 A1 Q0 A1 D1 Q1 Counter Load A LBO ADV Memory Array CK ADSC ADSP Q D Register GW BW BA D Q Register D 32 Q BB 32 4 Register D Q D Q D Register Q Q Register D Register BC BD Register D Q Register E1 E2 E3 D Q Register D Q FT G ZZ Rev: 1.07 10/2004 Power Down DQx1–DQx8 Control 5/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, GSI Technology GS820E32AT-180/166/133/4/5 Mode Pin Functions Mode Name Pin Name Burst Order Control LBO Output Register Control FT Power Down Control ZZ State Function L Linear Burst H or NC Interleaved Burst L Flow Through H or NC Pipeline L or NC Active H Standby, IDD = ISB Note: There are pull-up devices on the LBO and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above table. Burst Counter Sequences Linear Burst Sequence Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 1st address 00 01 10 11 2nd address 01 10 11 00 2nd address 01 00 11 10 3rd address 10 11 00 01 3rd address 10 11 00 01 4th address 11 00 01 10 4th address 11 10 01 00 Note: The burst counter wraps to initial state on the 5th clock. Rev: 1.07 10/2004 Note: The burst counter wraps to initial state on the 5th clock. 6/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, GSI Technology GS820E32AT-180/166/133/4/5 Byte Write Truth Table Function GW BW BA BB BC BD Notes Read H H X X X X 1 Read H L H H H H 1 Write byte A H L L H H H 2, 3 Write byte B H L H L H H 2, 3 Write byte C H L H H L H 2, 3, 4 Write byte D H L H H H L 2, 3, 4 Write all bytes H L L L L L 2, 3, 4 Write all bytes L X X X X X Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. Rev: 1.07 10/2004 7/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, GSI Technology GS820E32AT-180/166/133/4/5 Synchronous Truth Table Operation Address Used State Diagram Key5 E1 E2 Deselect Cycle, Power Down None X H X X Deselect Cycle, Power Down None X L F Deselect Cycle, Power Down None X L Read Cycle, Begin Burst External R Read Cycle, Begin Burst External Write Cycle, Begin Burst ADV W3 DQ4 L X X High-Z L X X X High-Z F H L X X High-Z L T L X X X Q R L T H L X F Q External W L T H L X T D Read Cycle, Continue Burst Next CR X X H H L F Q Read Cycle, Continue Burst Next CR H X X H L F Q Write Cycle, Continue Burst Next CW X X H H L T D Write Cycle, Continue Burst Next CW H X X H L T D Read Cycle, Suspend Burst Current X X H H H F Q Read Cycle, Suspend Burst Current H X X H H F Q Write Cycle, Suspend Burst Current X X H H H T D ADSP ADSC Write Cycle, Suspend Burst Current H X X H H T D Notes: 1. X = Don’t Care, H = High, L = Low 2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. 6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.07 10/2004 8/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, GSI Technology GS820E32AT-180/166/133/4/5 Simplified State Diagram X Deselect W R Simple Burst Synchronous Operation Simple Synchronous Operation W X R R First Write CW First Read CR CR W X R R X Burst Write Burst Read X CR CW CR Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, E3) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and assumes ADSP is tied high and ADV is tied low. Rev: 1.07 10/2004 9/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, GSI Technology GS820E32AT-180/166/133/4/5 Simplified State Diagram with G X Deselect W R W X R R First Write CR CW W CW W X First Read X CR R Burst Write R CR CW W Burst Read X CW CR Notes: 1. The diagram shows supported (tested) synchronous state transitions, plus supported transitions that depend upon the use of G. 2. Use of “Dummy Reads” (Read Cycles with G high) may be used to make the transition from Read cycles to Write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles. 3. Transitions shown in gray assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.07 10/2004 10/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, GSI Technology GS820E32AT-180/166/133/4/5 Absolute Maximum Ratings (All voltages reference to VSS) Symbol Description Value Unit VDD Voltage on VDD Pins –0.5 to 4.6 V VDDQ Voltage in VDDQ Pins –0.5 to VDD V VCK Voltage on Clock Input Pin –0.5 to 6 V VI/O Voltage on I/O Pins –0.5 to VDDQ+0.5 (≤ 4.6 V max.) V VIN Voltage on Other Input Pins –0.5 to VDD+0.5 (≤ 4.6 V max.) V IIN Input Current on Any Pin +/–20 mA Output Current on Any I/O Pin +/–20 mA IOUT PD Package Power Dissipation 1.5 W TSTG Storage Temperature –55 to 125 oC TBIAS Temperature Under Bias –55 to 125 o C Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Recommended Operating Conditions Parameter Symbol Min. Typ. Max. Unit Notes Supply Voltage VDD 3.135 3.3 3.6 V 1 I/O Supply Voltage VDDQ 2.375 2.5 VDD V 1 Input High Voltage VIH 1.7 — VDD+0.3 V 2 Input Low Voltage VIL –0.3 — 0.8 V 2 Ambient Temperature (Commercial Range Versions) TA 0 25 70 °C 3 TA –40 25 85 °C 3 Ambient Temperature (Industrial Range Versions) Notes: 1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V ≤ VDDQ ≤ 2.375 V (i.e., 2.5 V I/O) and 3.6 V ≤ VDDQ ≤ 3.135 V (i.e., 3.3 V I/O) and quoted at whichever condition is worst case. 2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers. 3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of Industrial Temperature Range versions end with the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 4. Input Under/overshoot voltage must be –2 V > Vi < VDD+2 V with a pulse width not to exceed 20% tKC. Rev: 1.07 10/2004 11/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, GSI Technology GS820E32AT-180/166/133/4/5 Undershoot Measurement and Timing Overshoot Measurement and Timing VIH 20% tKC VDD +- 2.0 V VSS 50% 50% VDD VSS – 2.0 V 20% tKC VIL Capacitance (TA = 25°C, f = 1 MHZ, VDD = 3.3 V) Parameter Symbol Test conditions Typ. Max. Unit Control Input Capacitance CI VDD = 3.3 V 3 4 pF Input Capacitance CIN VIN = 0 V 4 5 pF COUT VOUT = 0 V 6 7 pF Output Capacitance Note: This parameter is sample tested. AC Test Conditions Parameter Conditions Input high level 2.3 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level 1.25 V Output reference level 1.25 V Output load Fig. 1& 2 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ 4. Device is deselected as defined by the Truth Table. Output Load 1 DQ 50Ω 30pF* VT = 1.25 V * Distributed Test Jig Capacitance Rev: 1.07 10/2004 12/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, GSI Technology GS820E32AT-180/166/133/4/5 DC Electrical Characteristics Parameter Symbol Test Conditions Min Max IIL VIN = 0 to VDD –1 uA 1 uA ZZ Input Current IINZZ VDD ≥ VIN ≥ VIH 0V ≤ VIN ≤ VIH –1 uA –1 uA 1 uA 300 uA Mode Pin Input Current IINM VDD ≥ VIN ≥ VIL 0V ≤ VIN ≤ VIL –300 uA –1 uA 1 uA 1 uA Output Leakage Current IOL Output Disable, VOUT = 0 to VDD –1 uA 1 uA Output High Voltage VOH IOH = –mA, VDDQ = 2.375 V 1.7 V Output High Voltage VOH IOH = –mA, VDDQ = 3.135 V 2.4 V Output Low Voltage VOL IOL = mA Input Leakage Current (except mode pins) 0.4 V Operating Currents -180 -133 (-4) -5 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C Unit IDD Pipeline 155 160 140 145 115 120 90 95 mA IDD Flow Through 100 105 90 95 80 85 65 70 mA ISB Flow Through 10 15 10 15 10 15 10 15 mA IDD Pipeline 35 40 30 35 30 35 25 30 mA IDD Flow Through 25 30 25 30 20 25 20 25 mA Parameter Test Conditions Symbol Operating Current Device Selected; All other inputs ≥VIH or ≤ VIL Output open Standby Current ZZ ≥ VDD – 0.2 V Deselect Current Device Deselected; All other inputs ≥ VIH or ≤ VIL Rev: 1.07 10/2004 -166 13/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, GSI Technology GS820E32AT-180/166/133/4/5 AC Electrical Characteristics Pipeline Flow Through Parameter Symbol Clock Cycle Time -180 -166 -133(-4) -5 Unit Min Max Min Max Min Max Min Max tKC 5.5 — 6 — 7.5 — 10 — ns Clock to Output Valid tKQ — 3.2 — 3.5 — 4 — 5 ns Clock to Output Invalid tKQX 1.5 — 1.5 — 1.5 — 1.5 — ns Clock to Output in Low-Z tLZ1 1.5 — 1.5 — 1.5 — 1.5 — ns Clock Cycle Time tKC 9.1 — 10 — 12 — 15 — ns Clock to Output Valid tKQ — 8 — 8.5 — 10 — 12 ns Clock to Output Invalid tKQX 3 — 3 — 3 — 3 — ns 1 3 — 3 — 3 — 3 — ns Clock to Output in Low-Z tLZ Clock HIGH Time tKH 1.3 — 1.3 — 1.3 — 1.3 — ns Clock LOW Time tKL 1.5 — 1.5 — 1.5 — 1.5 — ns Clock to Output in High-Z tHZ1 1.5 3.2 1.5 3.5 1.5 4 1.5 5 ns G to Output Valid tOE — 3.2 — 3.5 — 4 — 5 ns G to output in Low-Z tOLZ1 0 — 0 — 0 — 0 — ns G to output in High-Z tOHZ1 — 3.2 — 3.5 — 4 — 5 ns Setup time tS 1.5 — 1.5 — 1.5 — 1.5 — ns Hold time tH 0.5 — 0.5 — 0.5 — 0.5 — ns ZZ setup time 2 tZZS 5 — 5 — 5 — 5 — ns ZZ hold time tZZH2 1 — 1 — 1 — 1 — ns ZZ recovery tZZR 20 — 20 — 20 — 20 — ns Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.07 10/2004 14/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, GSI Technology GS820E32AT-180/166/133/4/5 Pipeline Mode Timing (DCD) Begin Read A Cont Deselect Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont Deselect Deselect tKL tKH tKC CK ADSP tS ADSC initiated read tH ADSC tS tH ADV tS tH Ao–An A B C tS GW tS tH BW tH tS Ba–Bd tS Deselected with E1 tH E1 tS E2 and E3 only sampled with ADSC tH E2 tS tH E3 G tS tOE DQa–DQd Hi-Z Rev: 1.07 10/2004 tOHZ Q(A) tKQ tH D(B) tHZ tLZ tKQX Q(C) Q(C+1) 15/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Q(C+2) Q(C+3) © 2000, GSI Technology GS820E32AT-180/166/133/4/5 Flow Through Mode Timing (DCD) Begin Read A Cont Deselect Write B Read C Read C+1 Read C+2 Read C+3 Read C Deselect tKL tKH tKC CK ADSP Fixed High tS tH tS tH ADSC initiated read ADSC tH tS tS tH ADV tS tH Ao–An A B C tS tH GW tS tH BW tH tS Ba–Bd tS Deselected with E1 tH E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP and ADSC E2 tS tH E1 masks ADSP E3 G tH tS tOE tKQ DQa–DQd Rev: 1.07 10/2004 tOHZ Q(A) tKQX tHZ tLZ D(B) Q(C) Q(C+1) Q(C+2) 16/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Q(C+3) Q(C) © 2000, GSI Technology GS820E32AT-180/166/133/4/5 Sleep Mode Timing tKH tKC tKL CK Setup Hold ADSP ADSC tZZR tZZS tZZH ZZ Application Tips Single and Dual Cycle Deselect SCD devices force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention. Rev: 1.07 10/2004 17/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, GSI Technology GS820E32AT-180/166/133/4/5 GS820E32A Output Driver Characteristics 60 Pull Down Drivers 40 20 VDDQ I Out 0 I Out (mA) VOut VSS -20 -40 Pull Up Drivers -60 -80 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 V Out (Pull Dow n) VDDQ - V Out (Pull Up) 3.6V PD LD Rev: 1.07 10/2004 3.3V PD LD 3.1V PD LD 3.1V PU LD 3.3V PU LD 18/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 3.6V PU LD © 2000, GSI Technology GS820E32AT-180/166/133/4/5 TQFP Package Drawing (Package T) L Min. Nom. Max A1 Standoff 0.05 0.10 0.15 A2 Body Thickness 1.35 1.40 1.45 b Lead Width 0.20 0.30 0.40 c Lead Thickness 0.09 — 0.20 D Terminal Dimension 21.9 22.0 22.1 D1 Package Body 19.9 20.0 20.1 E Terminal Dimension 15.9 16.0 16.1 E1 Package Body 13.9 14.0 14.1 e Lead Pitch — 0.65 — L Foot Length 0.45 0.60 0.75 L1 Lead Length — 1.00 — Y Coplanarity θ Lead Angle L1 c e D D1 Description Pin 1 Symbol θ b A1 A2 0.10 Y 0° — 7° E1 E Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 1.07 10/2004 19/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, GSI Technology GS820E32AT-180/166/133/4/5 Ordering Information for GSI Synchronous Burst RAMs Speed2 TA (MHz/ns) 3 Org Part Number1 Type Package 64K x 32 GS820E32AT-180 Pipeline/Flow Through TQFP 180/8 C 64K x 32 GS820E32AT-166 Pipeline/Flow Through TQFP 166/8.5 C 64K x 32 GS820E32AT-133 Pipeline/Flow Through TQFP 133/10 C 64K x 32 GS820E32AT-4 Pipeline/Flow Through TQFP 133/10 C 64K x 32 GS820E32AT-5 Pipeline/Flow Through TQFP 100/12 C 64K x 32 GS820E32AT-180I Pipeline/Flow Through TQFP 180/8 I 64K x 32 GS820E32AT-166I Pipeline/Flow Through TQFP 166/8.5 I 64K x 32 GS820E32AT-133I Pipeline/Flow Through TQFP 133/10 I 64K x 32 GS820E32AT-4I Pipeline/Flow Through TQFP 133/10 I 64K x 32 GS820E32AT-5I Pipeline/Flow Through TQFP 100/12 I 64K x 32 GS820E32AGT-180 Pipeline/Flow Through Pb-free TQFP 180/8 C 64K x 32 GS820E32AGT-166 Pipeline/Flow Through Pb-free TQFP 166/8.5 C 64K x 32 GS820E32AGT-133 Pipeline/Flow Through Pb-free TQFP 133/10 C 64K x 32 GS820E32AGT-4 Pipeline/Flow Through Pb-free TQFP 133/10 C 64K x 32 GS820E32AGT-5 Pipeline/Flow Through Pb-free TQFP 100/12 C 64K x 32 GS820E32AGT-180I Pipeline/Flow Through Pb-free TQFP 180/8 I 64K x 32 GS820E32AGT-166I Pipeline/Flow Through Pb-free TQFP 166/8.5 I 64K x 32 GS820E32AGT-133I Pipeline/Flow Through Pb-free TQFP 133/10 I 64K x 32 Pipeline/Flow Through Pb-free TQFP 133/10 I GS820E32AGT-4I Status 64K x 32 GS820E32AGT-5I Pipeline/Flow Through Pb-free TQFP 100/12 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS820E32AT-166IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.07 10/2004 20/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, GSI Technology GS820E32AT-180/166/133/4/5 Revision History DS/DateRev. Code: Old; New Types of Changes Revisions Format or Content GS82032 Rev 1.03 2/ 2000D;GS820321.04 3/ 2000E Content • First Release of A version. Added “A” Version to 82032T/Q, 820E32TQ, and 820H32TQ GS820321.04 3/2000E; GS82032A_r1_05 Content • Complete rewrite of datasheet in order to reflect parts available GS82032A_r1_05; GS82032A_r1_06 Content • Reactivated 180 MHz speed bin • Updated format GS82032A_r1_06; GS82032A_r1_07 Content Rev: 1.07 10/2004 • Added Pb-free information for TQFP 21/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, GSI Technology