Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs 119- and 209-Pin BGA Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipeline operation • Single/Dual Cycle Deselect selectable (x36 and x72) • Dual Cycle Deselect only (x18) • IEEE 1149.1 JTAG-compatible Boundary Scan • ZQ mode pin for user-selectable high/low output drive • 2.5 V or 3.3 V +10%/–5% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to SCD x36/x72 Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 119- and 209-bump BGA package Pipeline 3-1-1-1 3.3 V 2.5 V Flow Through 2-1-1-1 3.3 V 2.5 V tKQ tCycle Curr (x18) Curr (x36) Curr (x72) Curr (x18) Curr (x36) Curr (x72) -250 -225 -200 -166 -150 -133 Unit 2.3 2.5 3.0 3.5 3.8 4.0 ns 4.0 4.4 5.0 6.0 6.6 7.5 ns 365 560 660 360 550 640 335 510 600 330 500 590 305 460 540 305 460 530 265 400 460 260 390 450 245 370 430 240 360 420 215 330 380 215 330 370 mA mA mA mA mA mA tKQ tCycle 6.0 7.0 6.5 7.5 7.5 8.5 8.5 10 10 10 11 15 ns ns Curr (x18) Curr (x36) Curr (x72) Curr (x18) Curr (x36) Curr (x72) 235 300 350 235 300 340 230 300 350 230 300 340 210 270 300 210 270 300 200 270 300 200 270 300 195 270 300 195 270 300 150 200 220 145 190 220 mA mA mA mA mA mA Functional Description Applications The GS832418/36/72 is a 37,748,736-bit high performance 2-die synchronous SRAM module with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Controls Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edgetriggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated Rev: 1.00 10/2001 250 MHz–133MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode . Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register. SCD and DCD Pipelined Reads The GS832436(B/C) and the GS832472(C) are SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAMs. The GS832418(B/C) is a DCD-only SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure the x36 or x72 versions of this SRAM for either mode of operation using the SCD mode input. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. FLXDrive™ The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS832418/36/72 operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible. 1/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology). © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) GS832472B Pad Out 209-Bump BGA—Top View 1 2 3 4 5 6 7 8 9 10 11 A DQG5 DQG1 A15 E2 ADSP ADSC ADV E3 A17 DQB1 DQB5 A B DQG6 DQG2 BC BG NC BW A16 BB BF DQB2 DQB6 B C DQG7 DQG3 BH BD NC E1 NC BE BA DQB3 DQB7 C D DQG8 DQG4 VSS NC NC G GW NC VSS DQB4 DQB8 D E DQPG9 DQPC9 VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPF9 DQPB9 E F DQC4 DQC8 VSS VSS VSS ZQ VSS VSS VSS DQF8 DQF4 F G DQC3 DQC7 VDDQ VDDQ VDD MCH VDD VDDQ VDDQ DQF7 DQF3 G H DQC2 DQC6 VSS VSS VSS MCL VSS VSS VSS DQF6 DQF2 H J DQC1 DQC5 VDDQ VDDQ VDD MCL VDD VDDQ VDDQ DQF5 DQF1 J K NC NC CK NC VSS MCL VSS NC NC NC NC K L DQH1 DQH5 VDDQ VDDQ VDD FT VDD VDDQ VDDQ DQA5 DQA1 L M DQH2 DQH6 VSS VSS VSS MCL VSS VSS VSS DQA6 DQA2 M N DQH3 DQH7 VDDQ VDDQ VDD SCD VDD VDDQ VDDQ DQA7 DQA3 N P DQH4 DQH8 VSS VSS VSS ZZ VSS VSS VSS DQA8 DQA4 P R DQPD9 DQPH9 VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPA9 DQPE9 R T DQD8 DQD4 VSS NC NC LBO NC NC VSS DQE4 DQE8 T U DQD7 DQD3 NC A14 A13 A12 A11 A10 A18 DQE3 DQE7 U V DQD6 DQD2 A9 A8 A7 A1 A6 A5 A4 DQE2 DQE6 V W DQD5 DQD1 TMS TDI A3 A0 A2 TDO TCK DQE1 DQE5 W 11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch Rev: 1.00 10/2001 2/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) GS832436C Pad Out 209-Bump BGA—Top View 1 2 3 4 5 6 7 8 9 10 11 A NC NC A15 E2 ADSP ADSC ADV E3 A17 DQB1 DQB5 A B NC NC BC NC A19 BW A16 BB NC DQB2 DQB6 B C NC NC NC BD NC E1 NC NC BA DQB3 DQB7 C D NC NC VSS NC NC G GW NC VSS DQB4 DQB8 D E NC DQPC9 VDDQ VDDQ VDD VDD VDD VDDQ VDDQ NC DQPB9 E F DQC4 DQC8 VSS VSS VSS ZQ VSS VSS VSS NC NC F G DQC3 DQC7 VDDQ VDDQ VDD MCH VDD VDDQ VDDQ NC NC G H DQC2 DQC6 VSS VSS VSS MCL VSS VSS VSS NC NC H J DQC1 DQC5 VDDQ VDDQ VDD MCL VDD VDDQ VDDQ NC NC J K NC NC CK NC VSS MCL VSS NC NC NC NC K L NC NC VDDQ VDDQ VDD FT VDD VDDQ VDDQ DQA5 DQA1 L M NC NC VSS VSS VSS MCL VSS VSS VSS DQA6 DQA2 M N NC NC VDDQ VDDQ VDD SCD VDD VDDQ VDDQ DQA7 DQA3 N P NC NC VSS VSS VSS ZZ VSS VSS VSS DQA8 DQA4 P R DQPD9 NC VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPA9 NC R T DQD8 DQD4 VSS NC NC LBO NC NC VSS NC NC T U DQD7 DQD3 NC A14 A13 A12 A11 A10 A18 NC NC U V DQD6 DQD2 A9 A8 A7 A1 A6 A5 A4 NC NC V W DQD5 DQD1 TMS TDI A3 A0 A2 TDO TCK NC NC W 11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch Rev: 1.00 10/2001 3/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) GS832418C Pad Out 209-Bump BGA—Top View 1 2 3 4 5 6 7 8 9 10 11 A NC NC A15 MCH ADSP ADSC ADV MCL A17 NC NC A B NC NC BB NC A19 BW A16 NC NC NC NC B C NC NC NC NC NC E1 A20 NC BA NC NC C D NC NC VSS NC NC G GW NC VSS NC NC D E NC DQPB9 VDDQ VDDQ VDD VDD VDD VDDQ VDDQ NC NC E F DQB4 DQB8 VSS VSS VSS ZQ VSS VSS VSS NC NC F G DQB3 DQB7 VDDQ VDDQ VDD MCH VDD VDDQ VDDQ NC NC G H DQB2 DQB6 VSS VSS VSS MCL VSS VSS VSS NC NC H J DQB1 DQB5 VDDQ VDDQ VDD MCL VDD VDDQ VDDQ NC NC J K NC NC CK NC VSS MCL VSS NC NC NC NC K L NC NC VDDQ VDDQ VDD FT VDD VDDQ VDDQ DQA5 DQA1 L M NC NC VSS VSS VSS MCL VSS VSS VSS DQA6 DQA2 M N NC NC VDDQ VDDQ VDD MCL VDD VDDQ VDDQ DQA7 DQA3 N P NC NC VSS VSS VSS ZZ VSS VSS VSS DQA8 DQA4 P R NC NC VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPA9 NC R T NC NC VSS NC NC LBO NC NC VSS NC NC T U NC NC NC A14 A13 A12 A11 A10 A18 NC NC U V NC NC A9 A8 A7 A1 A6 A5 A4 NC NC V W NC NC TMS TDI A3 A0 A2 TDO TCK NC NC W 11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch Rev: 1.00 10/2001 4/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) GS832418/36/72 209-Bump BGA Pin Description Pin Location Symbol Type Description W6, V6 A0, A1 I Address field LSBs and Address Counter Preset Inputs. W7, W5, V9, V8, V7, V5, V4, V3, U8, U7, U6, U5, U4, A3, B7, A9, U9 An I Address Inputs B5 A19 I Address Inputs (x36/x18 Versions) C7 A20 I Address Inputs (x18 Version) L11, M11, N11, P11, L10, M10, N10, P10, R10 A10, B10, C10, D10, A11, B11, C11, D11, E11 J1, H1, G1, F1, J2, H2, G2, F2, E2 W2, V2, U2, T2, W1, V1, U1, T1, R1 W10, V10, U10, T10, W11, V11, U11, T11, R11 J11, H11, G11, F11, J10, H10, G10, F10, E10 A2, B2, C2, D2, A1, B1, C1, D1, E1 L1, M1, N1, P1, L2, M2, N2, P2, R2 DQA1–DQA9 DQB1–DQB9 DQC1–DQC9 DQD1–DQD9 DQE1–DQE9 DQF1–DQF9 DQG1–DQG9 DQH1–DQH9 I/O Data Input and Output pins (x72 Version) L11, M11, N11, P11, L10, M10, N10, P10, R10 A10, B10, C10, D10, A11, B11, C11, D11, E11 J1, H1, G1, F1, J2, H2, G2, F2, E2 W2, V2, U2, T2, W1, V1, U1, T1, R1 DQA1–DQA9 DQB1–DQB9 DQC1–DQC9 DQD1–DQD9 I/O Data Input and Output pins (x36 Version) L11, M11, N11, P11, L10, M10, N10, P10, R10 J1, H1, G1, F1, J2, H2, G2, F2, E2 DQA1–DQA9 DQB1–DQB9 I/O Data Input and Output pins (x18 Version) C9, B8 BA, BB I Byte Write Enable for DQA, DQB I/Os; active low B3, C4 BC,BD I Byte Write Enable for DQC, DQD I/Os; active low (x72/x36 Versions) C8, B9, B4, C3 BE, BF, BG,BH I Byte Write Enable for DQE, DQF, DQG, DQH I/Os; active low (x72 Version) B5 NC — No Connect (x72 Version) C7 NC — No Connect (x72/x36 Versions) W10, V10, U10, T10, W11, V11, U11, T11, R11 J11, H11, G11, F11, J10, H10, G10, F10, E10 A2, B2, C2, D2, A1, B1, C1, D1, E1 L1, M1, N1, P1, L2, M2, N2, P2, R2, C8, B9, B4, C3 NC — No Connect (x36/x18 Versions) B3, C4 NC — No Connect (x18 Version) C5, D4, D5, D8, K1, K2, K4, K8, K9, K10, K11, T4, T5, T7, T8, U3 NC — No Connect K3 CK I Clock Input Signal; active high D7 GW I Global Write Enable—Writes all bytes; active low C6 E1 I Chip Enable; active low A8 E3 I Chip Enable; active low (x72/x36 Versions) A4 E2 I Chip Enable; active high (x72/x36 Versions) Rev: 1.00 10/2001 5/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) GS832418/36/72 209-Bump BGA Pin Description Pin Location Symbol Type Description D6 G I Output Enable; active low A7 ADV I Burst address counter advance enable; active low A5, A6 ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low P6 ZZ I Sleep Mode control; active high L6 FT I Flow Through or Pipeline mode; active low T6 LBO I Linear Burst Order mode; active low N6 SCD I Single Cycle Deselect/Dual Cycle Deselect Mode Control ( x72/x36 Versions) G6 MCH I Must Connect High A4 MCH I Must Connect High (x18 version) H6, J6, K6, M6 MCL Must Connect Low A8, N6 MCL Must Connect Low (x18 version) B6 BW I Byte Enable; active low F6 ZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) W3 TMS I Scan Test Mode Select W4 TDI I Scan Test Data In W8 TDO O Scan Test Data Out W9 TCK I Scan Test Clock E5, E6, E7, G5, G7, J5, J7, L5, L7, N5, N7, R5, R6, R7 VDD I Core power supply D3, D9, F3, F4, F5, F7, F8, F9, H3, H4, H5, H7, H8, H9, K5, K7, M3, M4, M5, M7, M8, M9, P3, P4, P5, P7, P8, P9, T3, T9 VSS I I/O and Core Ground E3, E4, E8, E9, G3, G4, G8, G9, J3, J4, J8, J9, L3, L4, L8, L9, N3, N4, N8, N9, R3, R4, R8, R9 VDDQ I Output driver power supply Rev: 1.00 10/2001 6/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) GS832436B Pad Out 119-Bump BGA—Top View 1 2 3 4 5 6 7 A VDDQ A6 A7 ADSP A8 A9 VDDQ A B NC A18 A4 ADSC A15 A17 NC B C NC A5 A3 VDD A14 A16 NC C D DQC4 DQPC9 VSS ZQ VSS DQPB9 DQB4 D E DQC3 DQC8 VSS E1 VSS DQB8 DQB3 E F VDDQ DQC7 VSS G VSS DQB7 VDDQ F G DQC2 DQC6 BC ADV BB DQB6 DQB2 G H DQC1 DQC5 VSS GW VSS DQB5 DQB1 H J VDDQ VDD NC VDD NC VDD VDDQ J K DQD1 DQD5 VSS CK VSS DQA5 DQA4 K L DQD2 DQD6 BD SCD BA DQA6 DQA3 L M VDDQ DQD7 VSS BW VSS DQA7 VDDQ M N DQD3 DQD8 VSS A1 VSS DQA8 DQA2 N P DQD4 DQPD9 VSS A0 VSS DQPA9 DQA1 P R NC A2 LBO VDD FT A13 NC R T NC NC A10 A11 A12 A19 ZZ T U VDDQ TMS TDI TCK TDO NC VDDQ U 7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch Rev: 1.00 10/2001 7/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) GS832418B Pad Out 119-Bump BGA—Top View 1 2 3 4 5 6 7 A VDDQ A6 A7 ADSP A8 A9 VDDQ A B NC A18 A4 ADSC A15 A17 NC B C NC A5 A3 VDD A14 A16 NC C D DQB1 NC VSS ZQ VSS DQPA9 NC D E NC DQB2 VSS E1 VSS NC DQA8 E F VDDQ NC VSS G VSS DQA7 VDDQ F G NC DQB3 BB ADV NC NC DQA6 G H DQB4 NC VSS GW VSS DQA5 NC H J VDDQ VDD NC VDD NC VDD VDDQ J K NC DQB5 VSS CK VSS NC DQA4 K L DQB6 NC NC VSS BA DQA3 NC L M VDDQ DQB7 VSS BW VSS NC VDDQ M N DQB8 NC VSS A1 VSS DQA2 NC N P NC DQPB9 VSS A0 VSS NC DQA1 P R NC A2 LBO VDD FT A13 NC R T NC A10 A11 A20 A12 A19 ZZ T U VDDQ TMS TDI TCK TDO NC VDDQ U 7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch Rev: 1.00 10/2001 8/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) GS832418/36 119-Bump BGA Pin Description Pin Location Symbol Type Description P4, N4 A0, A1 I Address field LSBs and Address Counter Preset Inputs R2, C3, B3, C2, A2, A3, A5, A6, T3, T5, R6, C5, B5, C6, B6, B2 An I Address Inputs T4, T6 An T2 NC — No Connect (x36 Version) T2, T6, T4 An I Address Input (x18 Version) K7, L7, N7, P7, K6, L6, M6, N6 H7, G7, E7, D7, H6, G6, F6, E6 H1, G1, E1, D1, H2, G2, F2, E2 K1, L1, N1, P1, K2, L2, M2, N2 DQA1–DQA8 DQB1–DQB8 DQC1–DQC8 DQD1–DQD8 I/O Data Input and Output pins. (x36 Version) P6, D6, D2, P2 DQA9, DQB9, DQC9, DQD9 I/O Data Input and Output pins. (x36 Version) L5, G5, G3, L3 BA, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low (x36 Version) P7, N6, L6, K7, H6, G7, F6, E7, D6 D1, E2, G2, H1, K2, L1, M2, N1, P2 DQA1–DQA9 DQB1–DQB9 I/O Data Input and Output pins (x18 Version) L5, G3 BA, BB I Byte Write Enable for DQA, DQB I/Os; active low (x18 Version) B1, C1, R1, T1, U6, B7, C7, J3, J5, R7 NC — No Connect P6, N7, M6, L7, K6, H7, G6, E6, D7, D2, E1, F2, G1, H2, K1, L2, N2, P1, G5, L3 NC — No Connect (x18 Version) K4 CK I Clock Input Signal; active high M4 BW I Byte Write—Writes all enabled bytes; active low H4 GW I Global Write Enable—Writes all bytes; active low E4 E1 I Chip Enable; active low F4 G I Output Enable; active low G4 ADV I Burst address counter advance enable; active low A4, B4 ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low T7 ZZ I Sleep mode control; active high R5 FT I Flow Through or Pipeline mode; active low R3 LBO I Linear Burst Order mode; active low D4 ZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) L4 SCD I Single Cycle Deselect/Dual Cyle Deselect Mode Control (x36 version) U2 TMS I Scan Test Mode Select Rev: 1.00 10/2001 Address Input (x36 Version) 9/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) GS832418/36 119-Bump BGA Pin Description Pin Location Symbol Type Description U3 TDI I Scan Test Data In U5 TDO O Scan Test Data Out U4 TCK I Scan Test Clock J2, C4, J4, R4, J6 VDD I Core power supply D3, E3, F3, H3, K3, M3, N3, P3, D5, E5, F5, H5, K5, M5, N5, P5 VSS I I/O and Core Ground L4 VSS I I/O and Core Ground A1, F1, J1, M1, U1, A7, F7, J7, M7, U7 VDDQ I Output driver power supply Rev: 1.00 10/2001 10/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) GS832418/36/72 Block Diagram Register A0–An D Q A0 A0 D0 Q0 A1 A1 D1 Q1 Counter Load A LBO ADV Memory Array CK ADSC ADSP Q D Register GW BW BA D Q 36 36 Register D Q BB 4 Register D Q D Q D Q Register Register D Q Register BC BD Register D 36 Q 36 Register E1 D Q 36 Register D Q FT G ZZ 36 Power Down SCD DQx0–DQx9 Control Note: Only x36 version shown for simplicity. Rev: 1.00 10/2001 11/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) GS832418 Die Layout TDI Inputs Die A x18 16Mb TDO TDI Die B x18 16Mb TDO 18 I/Os GS832436 Die Layout TDI Inputs Die A x18 16Mb TDO TDI 18 I/Os Inputs Die A x36 32Mb TDO TDI 36 I/Os Rev: 1.00 10/2001 TDO 18 I/Os GS832472 Die Layout TDI Die B x18 16Mb Die B x36 32Mb TDO 36 I/Os 12/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Mode Pin Functions Mode Name Pin Name Burst Order Control LBO Output Register Control FT Power Down Control ZZ Single/Dual Cycle Deselect Control SCD FLXDrive Output Impedance Control ZQ State Function L Linear Burst H Interleaved Burst L Flow Through H or NC Pipeline L or NC Active H Standby, IDD = ISB L Dual Cycle Deselect H or NC Single Cycle Deselect L High Drive (Low Impedance) H or NC Low Drive (High Impedance) Note: There are pull-up devices on the ZQ, SCD and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Enable / Disable Parity I/O Pins This SRAM allows the user to configure the device to operate in Parity I/O active (x18, x36, or x72) or in Parity I/O inactive (x16, x32, or x64) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Grounding PE deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits generated and read into the ByteSafe parity circuits. Burst Counter Sequences Interleaved Burst Sequence Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 1st address 00 01 10 11 2nd address 01 10 11 00 2nd address 01 00 11 10 3rd address 10 11 00 01 3rd address 10 11 00 01 4th address 11 00 01 10 4th address 11 10 01 00 Note: The burst counter wraps to initial state on the 5th clock. Note: The burst counter wraps to initial state on the 5th clock. BPR 1999.05.18 Rev: 1.00 10/2001 13/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Byte Write Truth Table Function GW BW BA BB BC BD Notes Read H H X X X X 1 Read H L H H H H 1 Write byte a H L L H H H 2, 3 Write byte b H L H L H H 2, 3 Write byte c H L H H L H 2, 3, 4 Write byte d H L H H H L 2, 3, 4 Write all bytes H L L L L L 2, 3, 4 Write all bytes L X X X X X Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “C” and “D” are only available on the x36 version. Rev: 1.00 10/2001 14/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Synchronous Truth Table (x72 and x36 209-Bump BGA) Operation State Address Used Diagram Key5 E1 E2 ADSP ADSC ADV W3 DQ4 Deselect Cycle, Power Down None X H X X L X X High-Z Deselect Cycle, Power Down None X L F L X X X High-Z Deselect Cycle, Power Down None X L F H L X X High-Z Read Cycle, Begin Burst External R L T L X X X Q Read Cycle, Begin Burst External R L T H L X F Q Write Cycle, Begin Burst External W L T H L X T D Read Cycle, Continue Burst Next CR X X H H L F Q Read Cycle, Continue Burst Next CR H X X H L F Q Write Cycle, Continue Burst Next CW X X H H L T D Write Cycle, Continue Burst Next CW H X X H L T D Read Cycle, Suspend Burst Current X X H H H F Q Read Cycle, Suspend Burst Current H X X H H F Q Write Cycle, Suspend Burst Current X X H H H T D Write Cycle, Suspend Burst Current H X X H H T D Note: 1. X = Don’t Care, H = High, L = Low. 2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1. 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 5. 6. 7. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.00 10/2001 15/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Synchronous Truth Table (x18 209-Bump BGA and x36/x18 119-Bump BGA) State Operation Address Used Diagram E1 ADSP ADSC 5 Key ADV W3 DQ4 Deselect Cycle, Power Down None X H X L X X High-Z Read Cycle, Begin Burst External R L L X X X Q Read Cycle, Begin Burst External R L H L X F Q Write Cycle, Begin Burst External W L H L X T D Read Cycle, Continue Burst Next CR X H H L F Q Read Cycle, Continue Burst Next CR H X H L F Q Write Cycle, Continue Burst Next CW X H H L T D Write Cycle, Continue Burst Next CW H X H L T D Read Cycle, Suspend Burst Current X H H H F Q Read Cycle, Suspend Burst Current H X H H F Q Write Cycle, Suspend Burst Current X H H H T D Write Cycle, Suspend Burst Current H X H H T D Notes: 1. X = Don’t Care, H = High, L = Low 2. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding 3. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 4. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. 5. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 6. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.00 10/2001 16/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Simplified State Diagram X Deselect W R Simple Burst Synchronous Operation Simple Synchronous Operation W X R R First Write CW First Read CR W X CR R R X Burst Write Burst Read X CR CW CR Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and assumes ADSP is tied high and ADV is tied low. Rev: 1.00 10/2001 17/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Simplified State Diagram with G X Deselect W R W X R R First Write CR CW W CW W X First Read X CR R Burst Write R CR CW W Burst Read X CW CR Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles. 3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.00 10/2001 18/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Absolute Maximum Ratings (All voltages reference to VSS) Symbol Description Value Unit VDD Voltage on VDD Pins –0.5 to 4.6 V VDDQ Voltage in VDDQ Pins –0.5 to 4.6 V VCK Voltage on Clock Input Pin –0.5 to 6 V VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 (≤ 4.6 V max.) V VIN Voltage on Other Input Pins –0.5 to VDD +0.5 (≤ 4.6 V max.) V IIN Input Current on Any Pin +/–20 mA IOUT Output Current on Any I/O Pin +/–20 mA PD Package Power Dissipation 1.5 W TSTG Storage Temperature –55 to 125 o TBIAS Temperature Under Bias –55 to 125 oC C Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Rev: 1.00 10/2001 19/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Power Supply Voltage Ranges Parameter Symbol Min. Typ. Max. Unit 3.3 V Supply Voltage VDD3 3.0 3.3 3.6 V 2.5 V Supply Voltage VDD2 2.3 2.5 2.7 V 3.3 V VDDQ I/O Supply Voltage VDDQ3 3.0 3.3 3.6 V 2.5 V VDDQ I/O Supply Voltage VDDQ2 2.4 2.5 2.7 V Notes Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. VDDQ3 Range Logic Levels Parameter Symbol Min. Typ. Max. Unit Notes VDD Input High Voltage VIH 1.7 — VDD + 0.3 V 1 VDD Input Low Voltage VIL –0.3 — 0.8 V 1 VDDQ I/O Input High Voltage VIHQ 1.7 — VDDQ + 0.3 V 1,3 VDDQ I/O Input Low Voltage VILQ –0.3 — 0.8 V 1,3 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. VDDQ2 Range Logic Levels Parameter Symbol Min. Typ. Max. Unit Notes VDD Input High Voltage VIH 0.6*VDD — VDD + 0.3 V 1 VDD Input Low Voltage VIL –0.3 — 0.3*VDD V 1 VDDQ I/O Input High Voltage VIHQ 0.6*VDD — VDDQ + 0.3 V 1,3 VDDQ I/O Input Low Voltage VILQ –0.3 — 0.3*VDD V 1,3 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. Rev: 1.00 10/2001 20/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Recommended Operating Temperatures Parameter Symbol Min. Typ. Max. Unit Notes Ambient Temperature (Commercial Range Versions) TA 0 25 70 °C 2 Ambient Temperature (Industrial Range Versions) TA –40 25 85 °C 2 Note: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Undershoot Measurement and Timing Overshoot Measurement and Timing VIH 20% tKC VDD + 2.0 V VSS 50% 50% VDD VSS – 2.0 V 20% tKC VIL Capacitance (TA = 25oC, f = 1 MHZ, VDD = 2.5 V) Parameter Symbol Test conditions Typ. Max. Unit Input Capacitance CIN VIN = 0 V 6.5 7.5 pF Input/Output Capacitance (x36/x72) CI/O VOUT = 0 V 6 7 pF Input/Output Capacitance (x18) CI/O VOUT = 0 V 8.5 9.5 pF Note: These parameters are sample tested. Package Thermal Characteristics Rating Layer Board Symbol Max Unit Notes Junction to Ambient (at 200 lfm) single RΘJA 40 °C/W 1,2 Junction to Ambient (at 200 lfm) four RΘJA 24 °C/W 1,2 Junction to Case (TOP) — RΘJC 9 °C/W 3 Notes: 1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance. 2. SCMI G-38-87 3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1 Rev: 1.00 10/2001 21/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) AC Test Conditions Parameter Conditions Input high level 2.3 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level 1.25 V Output reference level 1.25 V Output load Fig. 1& 2 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ 4. Device is deselected as defined by the Truth Table. Output Load 2 Output Load 1 DQ 2.5 V 50Ω 225Ω DQ 30pF* 5pF* VT = 1.25 V 225Ω * Distributed Test Jig Capacitance DC Electrical Characteristics Parameter Symbol Test Conditions Min Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD –2 uA 2 uA ZZ and PE Input Current IIN1 VDD ≥ VIN ≥ VIH 0 V ≤ VIN ≤ VIH –1 uA –1 uA 1 uA 100 uA FT, SCD, ZQ, DP Input Current IIN2 VDD ≥ VIN ≥ VIL 0 V ≤ VIN ≤ VIL –100 uA –1 uA 1 uA 1 uA Output Leakage Current (x36/x72) IOL Output Disable, VOUT = 0 to VDD –1 uA 1 uA Output Leakage Current (x18) IOL Output Disable, VOUT = 0 to VDD –2 uA 2 uA Output High Voltage VOH2 IOH = –8 mA, VDDQ = 2.375 V 1.7 V — Output High Voltage VOH3 IOH = –8 mA, VDDQ = 3.135 V 2.4 V — Output Low Voltage VOL IOL = 8 mA — 0.4 V Rev: 1.00 10/2001 22/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Rev: 1.00 10/2001 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 23/46 — Device Deselected; All other inputs ≥ VIH or ≤ VIL Deselect Current 310 30 520 30 280 20 345 15 200 10 40 IDD IDDQ IDD IDDQ IDD IDDQ IDD IDDQ ISB Pipeline Flow Through Pipeline Flow Through Pipeline IDD 120 170 IDD Pipeline Flow Through 40 ISB Flow Through Flow Through IDD IDDQ 200 10 345 20 280 20 580 60 IDD IDDQ IDD IDDQ IDD IDDQ IDD IDDQ IDD 520 40 310 40 IDD IDDQ 580 80 0 to 70°C IDD IDDQ Symbol IDDQ Pipeline Flow Through Pipeline Flow Through Pipeline Flow Through Pipeline Mode 130 180 60 60 215 10 360 15 300 20 540 30 330 30 600 60 215 10 360 20 300 20 540 40 330 40 560 80 –40 to 85°C -250 120 160 40 40 200 10 315 15 280 20 470 30 310 30 530 60 200 10 315 20 280 20 470 40 340 40 530 70 130 170 60 60 215 10 330 15 300 20 490 30 330 30 550 60 215 10 330 20 300 20 490 40 330 40 550 70 –40 to 85°C -225 0 to 70°C Notes: 1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation. 2. All parameters listed are worst case scenario. — ZZ ≥ VDD – 0.2 V (x18) (x36) (x72) (x18) (x36) (x72) Standby Current 2.5 V Operating Current Device Selected; All other inputs ≥VIH or ≤ VIL Output open Device Selected; All other inputs ≥VIH or ≤ VIL Output open Operating Current 3.3 V Test Conditions Parameter Operating Currents 100 150 40 40 175 10 290 15 250 20 430 30 270 30 480 50 175 10 290 15 250 20 430 30 270 30 480 60 0 to 70°C 110 160 60 60 190 10 305 15 270 20 450 30 290 30 500 50 190 10 305 15 270 20 450 30 290 30 500 60 –40 to 85°C -200 100 130 40 40 175 10 250 10 250 20 370 20 270 30 410 40 175 10 250 15 350 20 370 30 270 30 410 50 0 to 70°C 110 140 60 60 190 10 265 10 270 20 390 20 290 30 430 40 190 10 265 15 270 20 390 30 290 30 430 50 –40 to 85°C -166 100 120 40 40 175 10 230 10 250 20 340 20 270 30 380 40 175 10 230 15 250 20 340 30 270 30 380 50 0 to 70°C 110 130 60 60 190 10 245 10 270 20 360 20 290 30 400 40 190 10 245 15 270 20 360 30 290 30 400 50 –40 to 85°C -150 90 100 40 40 135 5 205 10 180 10 310 20 200 20 340 30 135 10 205 10 180 20 310 20 200 20 340 40 0 to 70°C 100 110 60 60 150 5 220 10 200 10 330 20 220 20 360 30 150 10 220 10 200 20 330 20 220 20 360 40 –40 to 85°C -133 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Unit Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) AC Electrical Characteristics Pipeline Flow Through Parameter Symbol Clock Cycle Time -250 -225 -200 -166 -150 -133 Unit Min Max Min Max Min Max Min Max Min Max Min Max tKC 4.0 — 4.4 — 5.0 — 6.0 — 6.7 — 7.5 — ns Clock to Output Valid tKQ — 2.3 — 2.5 — 3.0 — 3.4 — 3.8 — 4.0 ns Clock to Output Invalid tKQX 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns Clock to Output in Low-Z tLZ 1 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns Clock Cycle Time tKC 7.0 — 7.5 — 8.5 — 10.0 — 10.0 — 15.0 — ns Clock to Output Valid tKQ — 6.0 — 6.0 — 7.5 — 8.5 — 10.0 — 10.0 ns Clock to Output Invalid tKQX 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns Clock to Output in Low-Z tLZ1 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns Clock HIGH Time tKH 1.3 — 1.3 — 1.3 — 1.3 — 1.5 — 1.7 — ns Clock LOW Time tKL 1.5 — 1.5 — 1.5 — 1.5 — 1.7 — 2 — ns Clock to Output in High-Z tHZ1 1.5 2.3 1.5 2.5 1.5 3.0 1.5 3.5 1.5 3.8 1.5 4.0 ns G to Output Valid tOE — 2.3 — 2.5 — 3.2 — 3.5 — 3.8 — 4.0 ns G to output in Low-Z tOLZ1 0 — 0 — 0 — 0 — 0 — 0 — ns G to output in High-Z tOHZ1 — 2.3 — 2.5 — 3.0 — 3.5 — 3.8 — 4.0 ns Setup time tS 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns Hold time tH 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns ZZ setup time tZZS2 5 — 5 — 5 — 5 — 5 — 5 — ns ZZ hold time tZZH2 1 — 1 — 1 — 1 — 1 — 1 — ns ZZ recovery tZZR 100 — 100 — 100 — 100 — 100 — 100 — ns Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.00 10/2001 24/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Write Cycle Timing Single Write Burst Write Deselected Write CK tS tH tKH tKL tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated write ADSC tS tH ADV tS tH A0–An ADV must be inactive for ADSP Write WR2 WR1 WR3 tS tH GW tS tH BW tS tH BA–BD WR2 WR1 WR1 tS tH WR3 WR3 E1 masks ADSP E1 E1 only sampled with ADSP or ADSC G tS tH DQA–DQD Rev: 1.00 10/2001 Hi-Z Write specified byte for 2A and all bytes for 2B, 2C& 2D D1A D2A D2B D2C D2D 25/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. D3A © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Flow Through Read Cycle Timing Single Read Burst Read tKL CK tKH tS tH tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated read ADSC tS tH Suspend Burst Suspend Burst ADV tS tH A0–An RD1 RD2 RD3 tS tH tS tH GW BW BA–BD tS tH E1 masks ADSP E1 tOE tOHZ G tKQX tOLZ DQA–DQD Q1A Hi-Z Q2A tKQX Q2B Q2c Q2D Q3A tLZ tHZ tKQ Rev: 1.00 10/2001 26/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Flow Through Read-Write Cycle Timing Single Write Single Read Burst Read CK tS tH tKH tKL tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated read ADSC tS tH ADV tS tH A0–An WR1 RD1 tS RD2 tH GW tH tS BW tS tH BA–BD WR1 tS tH E1 masks ADSP E1 tOE tOHZ G tS tKQ DQA–DQD Hi-Z Q1A tH D1A Q2A Q2B Q2c Q2D Q2A Burst wrap around to it’s initial state Rev: 1.00 10/2001 27/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Pipelined SCD Read Cycle Timing Single Read Burst Read CK tKH tS tH tKL tKC ADSP ADSP is blocked by E inactive tS tH ADSC initiated read ADSC tS tH Suspend Burst ADV tS tH A0–An RD2 RD1 RD3 tS tH tS tH GW BW BWA–BWD tS tH E1 masks ADSP E1 tOE G DQA–DQD tOHZ Hi-Z tKQX tKQX tOLZ Q1A Q2A Q2B Q2c Q2D Q3A tLZ tHZ tKQ Rev: 1.00 10/2001 28/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Pipelined SCD Read-Write Cycle Timing Single Write Single Read Burst Read tKL CK tS tH tKH tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated read ADSC tS tH ADV tS tH A0–An WR1 RD1 RD2 tS tH GW tS tH BW tS tH BWA– BWD WR1 tS tH E1 masks ADSP E1 tOE tOHZ G DQA–DQD Rev: 1.00 10/2001 Hi-Z tS tH tKQ Q1A D1A Q2A 29/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Q2B Q2c Q2D © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Pipelined DCD Read Cycle Timing Single Read tKL Burst Read CK tS tH tKH tKC ADSP is blocked by E1 inactive ADSP tS tH ADSC initiated read ADSC tS tH Suspend Burst ADV tS tH A0–An RD1 RD3 RD2 tS tH tS tH GW BW BA–BD tS tH E1 masks ADSP E1 tOE G tOHZ Hi-Z tOLZ Q1A DQA–DQD tKQX Q2A tKQX Q2B Q2c Q2D Q3A tLZ tHZ tKQ Rev: 1.00 10/2001 30/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Pipelined DCD Read-Write Cycle Timing Single Write Burst Read Single Read tKL CK tS tH tKH tKC ADSP is blocked by E1 inactive ADSP tS tH ADSC initiated read ADSC tS tH ADV tS tH A0–An RD1 WR1 RD2 tS tH GW tS tH BW tS tH BA–BD WR1 tS tH E1 masks ADSP E1 tOE tOHZ G DQA–DQD Rev: 1.00 10/2001 Hi-Z tS tH tKQ Q1A D1A Q2A 31/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Q2B Q2c Q2D © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after 2 cycles of wake up time. Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode. CK tS tH tKC tKH tKL ADSP ADSC tZZS ZZ ~ ~ ~ ~ ~ ~ ~~ ~ ~ ~ Sleep Mode Timing Diagram tZZH tZZR Snooze Application Tips Single and Dual Cycle Deselect SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention. JTAG Port Operation Due to the fact that this device is built from two die, the two JTAG parts are chained together internally. The following describes the behavior of each die. Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDDQ. Rev: 1.00 10/2001 32/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected. JTAG Pin Descriptions Pin Pin Name I/O Description TCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS Test Mode Select In The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. In The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level. TDI Test Data In TDO Test Data Out Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up. JTAG Port Registers Overview The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible. Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Rev: 1.00 10/2001 33/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. JTAG TAP Block Diagram 0 Bypass Register 2 1 0 Instruction Register TDI TDO ID Code Register 31 30 29 · · · · 2 1 0 Boundary Scan Register n · · · · · · · · · 2 1 0 TMS Test Access Port (TAP) Controller TCK Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. Die Revision Code GSI Technology JEDEC Vendor ID Code I/O Configuration Not Used Presence Register ID Register Contents Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x72 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 1 0 0 1 1 x36 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1 x32 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 1 1 0 0 1 1 x18 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 x16 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 0 1 1 0 0 1 1 Tap Controller Instruction Set Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be Rev: 1.00 10/2001 34/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. JTAG Tap Controller State Diagram 1 0 Test Logic Reset 0 Run Test Idle 1 Select DR 1 Select IR 0 0 1 1 Capture DR Capture IR 0 0 Shift DR 1 1 1 Shift IR 0 1 1 Exit1 DR 0 Exit1 IR 0 0 Pause DR 1 Exit2 DR 1 0 Pause IR 1 Exit2 IR 0 1 Update DR Update IR 1 1 0 0 0 0 Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Rev: 1.00 10/2001 35/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to ShiftDR state then places the boundary scan register between the TDI and TDO pins. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins. Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK when the controller is in the Update-IR state. Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Rev: 1.00 10/2001 36/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) JTAG TAP Instruction Set Summary Instruction Code Description Notes EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1 IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2 SAMPLE-Z 010 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. 1 RFU 011 Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1 SAMPLE/ PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. 1 GSI 101 GSI private instruction. 1 RFU 110 Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1 BYPASS 111 Places Bypass Register between TDI and TDO. 1 Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.00 10/2001 37/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) JTAG Port Recommended Operating Conditions and DC Characteristics Parameter Symbol Min. Max. Unit Notes 3.3 V Test Port Input High Voltage VIHJ3 2.0 VDD3 +0.3 V 1 3.3 V Test Port Input Low Voltage VILJ3 –0.3 0.8 V 1 2.5 V Test Port Input High Voltage VIHJ2 0.6 * VDD2 VDD2 +0.3 V 1 2.5 V Test Port Input Low Voltage VILJ2 –0.3 0.3 * VDD2 V 1 TMS, TCK and TDI Input Leakage Current IINHJ –300 1 uA 2 TMS, TCK and TDI Input Leakage Current IINLJ –1 100 uA 3 TDO Output Leakage Current IOLJ –1 1 uA 4 Test Port Output High Voltage VOHJ 1.7 — V 5, 6 Test Port Output Low Voltage VOLJ — 0.4 V 5, 7 Test Port Output CMOS High VOHJC VDDQ – 100 mV — V 5, 8 Test Port Output CMOS Low VOLJC — 100 mV V 5, 9 Notes: 1. Input Under/overshoot voltage must be –2 V > Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC. 2. VILJ ≤ VIN ≤ VDDn 3. 0 V ≤ VIN ≤ VILJn 4. Output Disable, VOUT = 0 to VDDn 5. The TDO output driver is served by the VDDQ supply. 6. IOHJ = –4 mA 7. IOLJ = + 4 mA 8. IOHJC = –100 uA 9. IOHJC = +100 uA JTAG Port AC Test Conditions Parameter Conditions Input high level 2.3 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level 1.25 V Output reference level 1.25 V 50Ω 30pF* VT = 1.25 V * Distributed Test Jig Capacitance Notes: 1. Include scope and jig capacitance. 2. Test conditions as as shown unless otherwise noted. Rev: 1.00 10/2001 JTAG Port AC Test Load DQ 38/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) JTAG Port Timing Diagram tTKH tTKL tTKC TCK tTS tTH TMS TDI TDO tTKQ JTAG Port AC Electrical Characteristics Parameter Symbol Min Max Unit TCK Cycle Time tTKC 50 — ns TCK Low to TDO Valid tTKQ — 20 ns TCK High Pulse Width tTKH 20 — ns TCK Low Pulse Width tTKL 20 — ns TDI & TMS Set Up Time tTS 10 — ns TDI & TMS Hold Time tTH 10 — ns Rev: 1.00 10/2001 39/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) GS832418/36/72 Boundary Scan Chain Order Order x72 x36 x18 Bump x72 x36 x18 1(TBD) Notes: 1. Depending on the package, some input pads of the scan chain may not be connected to any external pin. In such case: LBO = 1, ZQ = 1, PE = 0, SD = 0, ZZ = 0, FT = 1, DP = 1, and SCD = 1. 2. Every DQ pad consists of two scan registers—D is for input capture, and Q is for output capture. 3. A single register (#194) for controlling tristate of all the DQ pins is at the end of the scan chain (i.e., the last bit shifted in this tristate control is effective after JTAG EXTEST instruction is executed. 4. 1 = no connect, internally set to logic value 1 5. 0 = no connect, internally set to logic value 0 6. X = no connect, value is undefined Rev: 1.00 10/2001 40/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) 209 BGA Package Drawing 14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array C A1 A Side View D aaa D1 ∅b Symbol Min Typ A Max Units 1.70 mm 0.40 0.50 0.60 mm ∅b 0.50 0.60 0.70 mm c 0.31 0.36 0.38 mm D 21.9 22.0 22.1 mm 18.0 (BSC) E 13.9 14.0 Bottom View e A1 D1 E E1 e mm 14.1 mm E1 10.0 (BSC) mm e 1.00 (BSC) mm aaa 0.15 mm Rev 1.0 Rev: 1.00 10/2001 41/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Package Dimensions—119-Pin PBGA 119-Bump BGA Package A Pin 1 Corner 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U A B C D E F G H J K L M N P R T U G B S D R Bottom View Top View Symbol Description Min. Nom. Max A Width 13.9 14.0 14.1 B Length 21.9 22.0 22.1 C Package Height (including ball) 1.73 1.86 1.99 D Ball Size 0.60 0.75 0.90 E Ball Height 0.50 0.60 0.70 F Package Height (excluding balls) 1.16 1.26 1.36 G Width between Balls K Package Height above board R Width of package between balls 7.62 S Length of package between balls 20.32 T Variance of Ball Height 0.15 1.27 0.65 0.70 0.75 C F E K T Package Dimensions—119-Pin PBGA Unit: mm Side View Rev: 1.00 10/2001 42/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Ordering Information for GSI Synchronous Burst RAMs Org Part Number1 Type Package Speed2 (MHz/ns) TA3 2M x 18 GS832418B-250 DCD Pipeline/Flow Through 119 BGA 250/6 C 2M x 18 GS832418B-225 DCD Pipeline/Flow Through 119 BGA 225/6.5 C 2M x 18 GS832418B-200 DCD Pipeline/Flow Through 119 BGA 200/7.5 C 2M x 18 GS832418B-166 DCD Pipeline/Flow Through 119 BGA 166/8.5 C 2M x 18 GS832418B-150 DCD Pipeline/Flow Through 119 BGA 150/10 C 2M x 18 GS832418B-133 DCD Pipeline/Flow Through 119 BGA 133/11 C 2M x 18 GS832418C-250 DCD Pipeline/Flow Through 209 BGA 250/6 C 2M x 18 GS832418C-225 DCD Pipeline/Flow Through 209 BGA 225/6.5 C 2M x 18 GS832418C-200 DCD Pipeline/Flow Through 209 BGA 200/7.5 C 2M x 18 GS832418C-166 DCD Pipeline/Flow Through 209 BGA 166/8.5 C 2M x 18 GS832418C-150 DCD Pipeline/Flow Through 209 BGA 150/10 C 2M x 18 GS832418C-133 DCD Pipeline/Flow Through 209 BGA 133/11 C 1M x 36 GS832436B-250 SCD/DCD Pipeline/Flow Through 119 BGA 250/6 C 1M x 36 GS832436B-225 SCD/DCD Pipeline/Flow Through 119 BGA 225/6.5 C 1M x 36 GS832436B-200 SCD/DCD Pipeline/Flow Through 119 BGA 200/7.5 C 1M x 36 GS832436B-166 SCD/DCD Pipeline/Flow Through 119 BGA 166/8.5 C 1M x 36 GS832436B-150 SCD/DCD Pipeline/Flow Through 119 BGA 150/10 C 1M x 36 GS832436B-133 SCD/DCD Pipeline/Flow Through 119 BGA 133/11 C 1M x 36 GS832436C-250 SCD/DCD Pipeline/Flow Through 209 BGA 250/6 C 1M x 36 GS832436C-225 SCD/DCD Pipeline/Flow Through 209 BGA 225/6.5 C 1M x 36 GS832436C-200 SCD/DCD Pipeline/Flow Through 209 BGA 200/7.5 C 1M x 36 GS832436C-166 SCD/DCD Pipeline/Flow Through 209 BGA 166/8.5 C 1M x 36 GS832436C-150 SCD/DCD Pipeline/Flow Through 209 BGA 150/10 C 1M x 36 GS832436C-133 SCD/DCD Pipeline/Flow Through 209 BGA 133/11 C 512K x 72 GS832472C-250 SCD/DCD Pipeline/Flow Through 209 BGA 250/6 C 512K x 72 GS832472C-225 SCD/DCD Pipeline/Flow Through 209 BGA 225/6.5 C 512K x 72 GS832472C-200 SCD/DCD Pipeline/Flow Through 209 BGA 200/7.5 C 512K x 72 GS832472C-166 SCD/DCD Pipeline/Flow Through 209 BGA 166/8.5 C 512K x 72 GS832472C-150 SCD/DCD Pipeline/Flow Through 209 BGA 150/10 C Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832418B-150IB. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.00 10/2001 43/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Ordering Information for GSI Synchronous Burst RAMs (Continued) Org Part Number1 Type Package Speed2 (MHz/ns) TA3 512K x 72 GS832472C-133 SCD/DCD Pipeline/Flow Through 209 BGA 133/11 C 2M x 18 GS832418B-250I DCD Pipeline/Flow Through 119 BGA 250/6 I 2M x 18 GS832418B-225I DCD Pipeline/Flow Through 119 BGA 225/6.5 I 2M x 18 GS832418B-200I DCD Pipeline/Flow Through 119 BGA 200/7.5 I 2M x 18 GS832418B-166I DCD Pipeline/Flow Through 119 BGA 166/8.5 I 2M x 18 GS832418B-150I DCD Pipeline/Flow Through 119 BGA 150/10 I 2M x 18 GS832418B-133I DCD Pipeline/Flow Through 119 BGA 133/11 I 2M x 18 GS832418C-250I DCD Pipeline/Flow Through 209 BGA 250/6 I 2M x 18 GS832418C-225I DCD Pipeline/Flow Through 209 BGA 225/6.5 I 2M x 18 GS832418C-200I DCD Pipeline/Flow Through 209 BGA 200/7.5 I 2M x 18 GS832418C-166I DCD Pipeline/Flow Through 209 BGA 166/8.5 I 2M x 18 GS832418C-150I DCD Pipeline/Flow Through 209 BGA 150/10 I 2M x 18 GS832418C-133I DCD Pipeline/Flow Through 209 BGA 133/11 I 1M x 36 GS832436B-250I SCD/DCD Pipeline/Flow Through 119 BGA 250/6 I 1M x 36 GS832436B-225I SCD/DCD Pipeline/Flow Through 119 BGA 225/6.5 I 1M x 36 GS832436B-200I SCD/DCD Pipeline/Flow Through 119 BGA 200/7.5 I 1M x 36 GS832436B-166I SCD/DCD Pipeline/Flow Through 119 BGA 166/8.5 I 1M x 36 GS832436B-150I SCD/DCD Pipeline/Flow Through 119 BGA 150/10 I 1M x 36 GS832436B-133I SCD/DCD Pipeline/Flow Through 119 BGA 133/11 I 1M x 36 GS832436C-250I SCD/DCD Pipeline/Flow Through 209 BGA 250/6 I 1M x 36 GS832436C-225I SCD/DCD Pipeline/Flow Through 209 BGA 225/6.5 I 1M x 36 GS832436C-200I SCD/DCD Pipeline/Flow Through 209 BGA 200/7.5 I 1M x 36 GS832436C-166I SCD/DCD Pipeline/Flow Through 209 BGA 166/8.5 I 1M x 36 GS832436C-150I SCD/DCD Pipeline/Flow Through 209 BGA 150/10 I 1M x 36 GS832436C-133I SCD/DCD Pipeline/Flow Through 209 BGA 133/11 I 512K x 72 GS832472C-250I SCD/DCD Pipeline/Flow Through 209 BGA 250/6 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832418B-150IB. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.00 10/2001 44/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Ordering Information for GSI Synchronous Burst RAMs (Continued) Org Part Number1 Type Package Speed2 (MHz/ns) TA3 512K x 72 GS832472C-225I SCD/DCD Pipeline/Flow Through 209 BGA 225/6.5 I 512K x 72 GS832472C-200I SCD/DCD Pipeline/Flow Through 209 BGA 200/7.5 I 512K x 72 GS832472C-166I SCD/DCD Pipeline/Flow Through 209 BGA 166/8.5 I 512K x 72 GS832472C-150I SCD/DCD Pipeline/Flow Through 209 BGA 150/10 I 512K x 72 GS832472C-133I SCD/DCD Pipeline/Flow Through 209 BGA 133/11 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832418B-150IB. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.00 10/2001 45/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) 36Mb Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; New 832418_r1 Rev: 1.00 10/2001 Types of Changes Format or Content Page;Revisions;Reason • Creation of new datasheet 46/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc.