GSI GS84118T-150 256k x 18 sync cache tag Datasheet

GS84118T/B-166/150/133/100
166 MHz–100 MHz
8.5 ns–12 ns
3.3 V VDD
3.3 V and 2.5 V I/O
256K x 18 Sync
Cache Tag
TQFP, BGA
Commercial Temp
Industrial Temp
Features
• 3.3 V +10%/–5% core power supply, 2.5 V or 3.3 V I/O
supply
• Intergrated data comparator for Tag RAM application
• FT mode pin for flow through or pipeline operation
• LBO pin for Linear or Interleave (PentiumTM and X86) Burst
mode
• Synchronous address, data I/O, and control inputs
• Synchronous Data Enable (DE)
• Asynchronous Output Enable (OE)
• Asynchronous Match Output Enable (MOE)
• Byte Write (BWE) and Global Write (GW) operation
• Three chip enable signals for easy depth expansion
• Internal self-timed write cycle
• JTAG Test mode conforms to IEEE standard 1149.1
• JEDEC-standard 100-lead TQFP package and 119-BGA:
T:TQFP or B: BGA
-166
-150
-133
-100
Pipeline
3-1-1-1
tcycle
tKQ
IDD
6.0 ns
3.5 ns
310 mA
6.6 ns
3.8 ns
275 mA
7.5 ns
4.0 ns
250 mA
10 ns
4.5 ns
190 mA
Flow
Through
2-1-1-1
tKQ
tcycle
IDD
8.5 ns
10 ns
190 mA
10 ns
10 ns
190 mA
11 ns
15 ns
140 mA
12 ns
15 ns
140 mA
Functional Description
The GS84118 is a 256K x 18 high performance synchronous
SRAM with integrated Tag RAM comparator. A 2-bit burst
counter is included to provide burst interface with PentiumTM
and other high performance CPUs. It is designed to be used as
a Cache Tag SRAM, as well as data SRAM. Addresses, data
IOs, match output, chip enables (CE1, CE2, CE3), address
control inputs (ADSP, ADSC, ADV), and write control inputs
(BW1, BW2, BWE, GW, DE) are synchronous and are
controlled by a positive-edge-triggered clock (CLK).
Output registers and the Match output register are provided and
controlled by the FT mode pin (Pin 14). Through use of the FT
mode pin, I/O registers can be programmed to perform pipeline
or flow through operation. Flow Through mode reduces
latency.
Byte write operation is performed by using Byte Write Enable
(BWE) input combined with two individual byte write signals
BW1-2. In addition, Global Write (GW) is available for
writing all bytes at one time.
Compare cycles begin as a read cycle with output disabled so
that compare data can be loaded into the data input register.
The comparator compares the read data with the registered
input data and a match signal is generated. The match output
can be either in Pipeline or Flow Through modes controlled by
the FT signal.
Low power (Standby mode) is attained through the assertion of
the ZZ signal, or by stopping the clock (CLK). Memory data is
retained during Standby mode.
JTAG boundary scan interface is provided using IEEE
standard 1149.1 protocol. Four pins—Test Data In (TDI), Test
Data Out (TDO), Test Clock (TCK) and Test Mode Select
(TMS)—are used to perform JTAG function.
The GS84118 operates on a 3.3 V power supply and all inputs/
outputs are 3.3 V- or 2.5 V-LVTTL-compatible. Separate
output (VDDQ) pins are used to allow both 3.3 V or 2.5 V IO
interface.
* Pentium is a trademark of Intel Corp.
Output Enable (OE), Match Output Enable, and power down
control (ZZ) are asynchronous. Burst can be initiated with
either ADSP or ADSC inputs. Subsequent burst addresses are
generated internally and are controlled by ADV. The burst
sequence is either interleave order (PentiumTM or x86) or
linear order, and is controlled by LBO.
Rev: 1.05 7/2001
1/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Trademark Notice (if any) Trademark of Giga Semiconductor, Inc. (GSI Technology).
© 1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
A6
A7
CE1
CE2
NC
NC
BW2
BW1
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
Pin Configuration
VDDQ
LBO
A5
A4
VSS
NC
NC
DQ9
DQ10
VSS
VDDQ
DQ11
DQ12
FT
VDD
NC
VSS
DQ13
DQ14
VDDQ
VSS
DQ15
DQ16
DQP2
NC
VSS
VDDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
256K
x
18
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.05 7/2001
A10
NC
NC
VDDQ
VSS
NC
DQP1
DQ8
DQ7
VSS
VDDQ
DQ6
DQ5
VSS
NC
VDD
ZZ
DQ4
DQ3
VDDQ
VSS
DQ2
DQ1
NC
NC
VSS
VDDQ
MATCH
DE
MOE
A3
A2
A1
A0
TMS
TDI
VSS
VDD
TDO
TCK
A15
A14
A13
A12
A11
A16
A17
NC
NC
NC
2/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
84118 PadOut
119-Bump BGA—Top View
Rev: 1.05 7/2001
1
2
3
4
5
6
7
A
VDDQ
A6
A7
ADSP
A8
A9
VDDQ
B
NC
E2
A4
ADSC
A15
E3
NC
C
NC
A5
A3
VDD
A14
A16
NC
D
DQB1
NC
VSS
NC
VSS
DQP1
NC
E
NC
DQB2
VSS
E1
VSS
NC
DQA8
F
VDDQ
NC
VSS
G
VSS
DQA7
VDDQ
G
NC
DQB3
BB
ADV
NC
NC
DQA6
H
DQB4
NC
VSS
GW
VSS
DQA5
NC
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
NC
DQB5
VSS
CK
VSS
NC
DQA4
L
DQB6
NC
NC
NC
BA
DQA3
NC
M
VDDQ
DQB7
VSS
BW
VSS
MATCH
VDDQ
N
DQB8
NC
VSS
A1
VSS
DQA2
DE
P
NC
DQP2
VSS
A0
VSS
MOE
DQA1
R
NC
A2
LBO
VDD
FT
A13
NC
T
NC
A10
A11
NC
A12
A17
ZZ
U
VDDQ
TMS
TDI
NC
TDO
TCK
VDDQ
3/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
TQFP Pin Description
Pin Location
Symbol
Description
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 80, 48,
47, 46, 45, 44, 49, 50
A0–A17
Address Input Signals—Inputs are registered and must meet
setup and hold times, as specified on page 11.
89
CLK
Clock Input Signal
87
BWE
Byte Write Enable Signal—The byte write enable signal
needs to be combined with one of the four byte write signals
for a write operation to occur.
93
BW1
Byte Write signal for data outputs 1 thru 8
94
BW2
Byte Write signal for data outputs 9 thru 16
88
GW
Global Write Enable
92, 97, 98
CE1,CE2, CE3
Chip Enables
86
OE
Output Enable
83
ADV
Burst address advance
84, 85
ADSP, ADSC
Address status signals
58, 59, 62 ,63, 68, 69, 72, 73, 8, 9, 12, 13, 18,
19, 22, 23
DQ1–DQ16
Data Input and Output pins
74, 24
DQP1–DQP2
Parity Input and Output pins
53
MATCH
Match Output
51
MOE
Match Output Enable
52
DE
Data Enable—Data input registers are updated only when DE
is active.
64
ZZ
Power down control—Application of ZZ will result in a low
standby power consumption.
14
FT
Flow Through or Pipeline mode
31
LBO
Linear Order Burst mode
38
TMS
Test Mode Select
39
TDI
Test Data In
42
TDO
Test Data Out
43
TCK
Test Clock
15, 41, 65, 91
VDD
3.3 V power supply
5,10,17, 21, 26, 40, 55, 60, 67, 71,
76, 90
VSS
Ground
4, 11, 20, 27, 54, 61, 70, 77
VDDQ
2.5 V/3.3 V output power supply
1, 2, 3, 6, 7, 16, 25, 28, 29, 30,56, 57, 66, 75,
78, 79, 95, 96
NC
No Connect
Rev: 1.05 7/2001
4/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
PBGA Pin Description
Pin Location
Symbol
Description
P4, N4, R2, C3, B3, C2, A2, A3, A5, A6, T6, C5,
R6, T5, T2, T3, B5, C6
A0–A17
Address Input Signals—Inputs are registered and must meet
setup and hold times, as specified on page 11.
K4
CLK
Clock Input Signal
M4
BWE
Byte Write Enable Signal—The byte write enable signal needs to
be combined with one of the four byte write signals for a write
operation to occur.
L5
BW1
Byte Write signal for data outputs 1 thru 8
G3
BW2
Byte Write signal for data outputs 9 thru 16
H4
GW
Global Write Enable
E4, B2, B6
CE1,CE2, CE3
Chip Enables
F4
OE
Output Enable
G4
ADV
Burst address advance
A4, B4
ADSP, ADSC
Address status signals
P7, N6, L6, K7, H6, G7, F6, E7, D1, E2, G2, H1,
K2, L1, M2, N1
DQ1–DQ16
Data Input and Output pins
D6, P2
DQP1–DQP2
Parity Input and Output pins
M6
MATCH
Match Output
P6
MOE
Match Output Enable
N7
DE
Data Enable—Data input registers are updated only when DE is
active.
T7
ZZ
Power down control—Application of ZZ will result in a low
standby power consumption.
R5
FT
Flow Through or Pipeline mode
R3
LBO
Linear Order Burst mode
U2
TMS
Test Mode Select
U3
TDI
Test Data In
U5
TDO
Test Data Out
U4
TCK
Test Clock
C4, J2, J4, J6, R4
VDD
3.3 V power supply
D3, D5, E3, E5, F3, F5, H3, H5, K3, K5, M3, M5,
N3, N5, P3, P5
VSS
Ground
A1, A7, F1, F7, J1, J7, M1, M7, U1, U7
VDDQ
2.5 V/3.3 V output power supply
B1, B7, C1, C7, D2, D4, D7, E1, E6, F2, G1, G5,
G6, H2, H7, J3, J5, K1, K6, L2, L3, L4, L7, N2,
P1, RR1, R7, T1, T4, U6
NC
No Connect
Rev: 1.05 7/2001
5/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
Functional Block Diagram
18
A0-17
REGISTER
D
Q
A0
A1
A0
D0
D1
Q0
BINARY
COUNTER
A1
18
Q1
A
Load
LBO
ADV
256K X 18
Memory
Array
CLK
ADSC
ADSP
Q
D
GW
Register
D
Q
BWE
18
BW1
18
2
Register
D
Q
BW2
Q
Register
D
D
Register
Q
Q
Register
D
DE
Register
D
Q
Register
D
Q
CE1
CE2
CE3
Powerdown
ZZ
FT
OE
MOE
A, DQ,
Control
Control
Register
D
Q
18
54
TDI
Boundary Scan
Registers
Bypass Reg
DQ1-16
DQP1-2
Match
TDO
ID Reg.
Instruction Reg.
TMS
TCK
Rev: 1.05 7/2001
TAP
Controller
6/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
Mode Pin Function
LBO
Function
FT
Function
L
Linear Burst
L
Flow Through
H or NC
Interleaved Burst
H or NC
Pipeline
Power Down Control
ZZ
Function
L or NC
Active
H
Standby, IDD = ISB
Note:
There are pull up devices on LBO and FT pins and pull down device on ZZ pin, so those input pins can be unconnected
and the chip will operate in the default states as specified in the above tables.
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
1st address
00
01
10
11
2nd address
01
10
11
00
2nd address
01
00
11
10
3rd address
10
11
00
01
3rd address
10
11
00
01
4th address
11
00
01
10
4th address
11
10
01
00
Byte Write Function
Function
GW
BWE
BW1
BW2
Read
H
H
X
X
Read
H
L
H
H
Write all bytes
L
X
X
X
Write all bytes
H
L
L
L
Write byte 1
H
L
L
H
Write byte 2
H
L
H
L
Note: H = logic high, L = logic low, NC = no connect
Rev: 1.05 7/2001
7/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
Synchronous Truth Table
Operation
Address Used
CE1
CE2
CE3
ADSP
ADSC
ADV
Write
OE CLK
DQ
Deselect Cycle, Power Down
none
H
X
X
X
L
X
X
X
L-H
High-Z
Deselect Cycle, Power Down
none
L
L
X
L
X
X
X
X
L-H
High-Z
Deselect Cycle, Power Down
none
L
X
H
L
X
X
X
X
L-H
High-Z
Deselect Cycle, Power Down
none
L
L
X
H
L
X
X
X
L-H
High-Z
Deselect Cycle, Power Down
none
L
X
H
H
L
X
X
X
L-H
High-Z
Read Cycle, Begin Burst
external
L
H
L
L
X
X
X
L
L-H
Q
Read Cycle, Begin Burst
external
L
H
L
L
X
X
X
H
L-H
High-Z
Read Cycle, Begin Burst
external
L
H
L
H
L
X
H
L
L-H
Q
Read Cycle, Begin Burst
external
L
H
L
H
L
X
H
H
L-H
High-Z
Write Cycle, Begin Burst
external
L
H
L
H
L
X
L
X
L-H
D
Read Cycle, Continue Burst
next
X
X
X
H
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
next
X
X
X
H
H
L
H
H
L-H
High-Z
Read Cycle, Continue Burst
next
H
X
X
X
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
next
H
X
X
X
H
L
H
H
L-H
High-Z
Write Cycle, Continue Burst
next
X
X
X
H
H
L
L
X
L-H
D
Write Cycle, Continue Burst
next
H
X
X
X
H
L
L
X
L-H
D
Read Cycle, Suspend Burst
current
X
X
X
H
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
current
X
X
X
H
H
H
H
H
L-H
High-Z
Read Cycle, Suspend Burst
current
H
X
X
X
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
current
H
X
X
X
H
H
H
H
L-H
High-Z
Write Cycle, Suspend Burst
current
X
X
X
H
H
H
L
X
L-H
D
Write Cycle, Suspend Burst
current
H
X
X
X
H
H
L
X
L-H
D
Notes:
1. X means “don’t care,” H means “logic high,” L means “logic low.”
2.
3.
4.
5.
6.
Write is the logic function of GW, BWE, BW1, BW2. See Byte Write Function table for detail.
All inputs, except OE, must meet setup and hold on rising edge of CLK.
Suspending busrt generates a wait cycle.
ADSP LOW along with SRAM being selected always initiates a Read cycle at the L-H edge of the clock (CLK).
A Write cycle can only be performed by setting Write low for the clock L-H edge of the subsequent wait cycle.
Refer to page 12 for the Write timing diagram.
Rev: 1.05 7/2001
8/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
Truth Table For Read/Write/Compare/Fill Write Operation
CE
Write
DE
MOE
OE
Match
DQ
Read
L
H
X
X
L
—
Q
Write
L
L
L
X
H
—
D
Compare
L
H
L
L
H
Data Out
D
Fill Write
L
L
H
X
X
—
X
Match Deselect
H
X
X
L
X
High
High Z
Deselect
H
X
X
H
X
High Z
High Z
Notes:
1. X means “don’t care,” H means “logic high,” L means “logic low.”
2. Write is the logic function of GW, BWE, BW1, BW2. See Byte Write Function table for detail.
3. CE is defined as CE1=L, CE2=H and CE3=L
4. All signals are synchronous and are sampled by CLK except OE and MOE. OE and MOE are asynchronous and drive the bus immediately.
Absolute Maximum Ratings (Voltage reference to VSS = 0 V)
Symbol
Description
Commerical
Unit
VDD
Supply Voltage
–0.5 to 4.6
V
VDDQ
Output Supply Voltage
–0.5 to VDD
V
VCLK
CLK Input Voltage
–0.5 to 6
V
Vin
Input Voltage
–0.5 to VDD + 0.5
(≤ 4.6 V max. )
V
Vout
Output Voltage
–0.5 to VDD + 0.5
(≤ 4.6 V max. )
V
Iout
Output Current per I/O
+/–20
mA
PD
Power Dissipation
1.5
W
TOPR
Operating Temperature
0 to 70
oC
TSTG
Storage Temperature
–55 to 125
o
C
Note: Permanent damage to the device may occur if the Absolute Maximun Ratings are exceeded. Functional operation should be restricted to
the recommended operation conditions. Exposure to higher than recommended voltages, for an extended period of time, could effect the
performance and reliability of this component.
Rev: 1.05 7/2001
9/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
Package Thermal Characteristics
Rating
Layer Board
Symbol
TQFP max
PBGA max
Unit
Notes
Junction to Ambient (at 200 lfm)
single
RΘJA
32
28
°C/W
1,2
Junction to Ambient (at 200 lfm)
four
RΘJA
20
18
°C/W
1,2
Junction to Case (TOP)
—
RΘJC
7
4
°C/W
3
Notes:
1.
Junction temperature is a function of SRAM power dissapation, package thermal resistance, mounting board temperature, ambient.
Temperature air flow, board density, and PCB thermal resistance.
2.
3.
SCMI G-38-87.
Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1.
AC Test Conditions
Output load 1
(VDD = 3.135 V–3.6 V, TA = 0–70°C)
DQ
Parameter
Conditions
Input high level
VIH = 2.3 V
Input low level
VIL = 0.2 V
Input slew rate
TR = 1 V/ns
Input reference level
1.25 V
Output reference level
1.25 V
Output load
Fig. 1& 2
50W
VT = 1.25 V
FIG. 1
Output load 2
2.5 V
5pF1
Include scope and jig capacitance.
2.
Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
Output load 2 for tLZ, tHZ, tOLZ and tOHZ.
Device is deselected as defined by the Truth Table.
3.
4.
Rev: 1.05 7/2001
225W
DQ
Notes:
1.
30pF1
10/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
225W
FIG. 2
© 1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
DC Characteristics and Supply Currents (Voltage reference to VSS = 0 V)
(VDD = 3.135 V–3.6 V, Ta = 0–70°C for Commercial Temperature Offering)
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except ZZ, FT, LBO pins)
IIL
VIN = 0 to VDD
–1 uA
1 uA
ZZ Input Current
IinZZ
VDD ≥ VIN ≥ VIH
0 V ≤ VIN ≤ VIH
–1 uA
–1 uA
1 uA
300 uA
Mode Input Current
(FT & LBO pins)
IinM
VDD ≥ VIN ≥ VIL
0 V ≤ VIN ≤ VIL
–30 0uA
–1 uA
1 uA
1 uA
Output Leakage Current
Iol
Output Disable,
VOUT = 0 to VDD
–1 uA
1 uA
Output High Voltage
VOH
IOH = –4 mA, VDDQ = 2.375 V
1.7 V
Output High Voltage
VOH
IOH = –4 mA, VDDQ = 3.135 V
2.4 V
Output Low Voltage
VOL
IOL = +4 mA
Rev: 1.05 7/2001
0.4 V
11/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
Operating Currents
-166
0
to
70°°C
–40
to
+85°°C
0
to
70°°C
–40
to
+85°°C
0
to
70°°C
IDD
Pipeline
310
320
275
285
250
260
190
200
mA
IDD
Flow Through
190
200
190
200
140
150
140
150
mA
ISB
Pipeline
30
40
30
40
30
40
30
40
mA
ISB
Flow Through
30
40
30
40
30
40
30
40
mA
IDD
Pipeline
110
120
105
115
100
110
80
90
mA
IDD
Flow Through
80
90
80
90
65
75
65
75
mA
Symbol
Operating
Current
Device Selected;
All other inputs
≥ VIH Or ≤ VIL
Output open
Deselect Supply
Current
Rev: 1.05 7/2001
Device Deselected;
All other inputs
≥ VIH OR ≤ VIL
-100
–40
to
+85°°C
Test Conditions
ZZ ≥ VDD – 0.2 V
-133
0
to
70°°C
Parameter
Standby Current
-150
12/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
–40 Unit
to
+85°°C
© 1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
AC Electrical Characteristics
Pipeline
Flow-Thru
Rev: 1.05 7/2001
Parameter
Symbol
Clock Cycle Time
-166
-150
-133
-100
Unit
Min
Max
Min
Max
Min
Max
Min
Max
tKC
6.0
—
6.7
—
7.5
—
10
—
ns
Clock to Output Valid
tKQ
—
3.5
—
3.8
—
4
—
4.5
ns
Clock to Output Invalid
tKQX
1.5
—
1.5
—
1.5
—
1.5
—
ns
Clock to Output in Low-Z
tLZ1
1.5
—
1.5
—
1.5
—
1.5
—
ns
Clock to Match Valid
tKM
—
3.5
—
3.8
—
4
—
4.5
ns
Clock to Match Invalid
tKMX
1.5
—
1.5
—
1.5
—
1.5
—
ns
Clock to Match in Low-Z
tMLZ1
1.5
—
1.5
—
1.5
—
1.5
—
ns
Clock Cycle Time
tKC
10.0
—
10.0
—
15.0
—
15.0
—
ns
Clock to Output Valid
tKQ
—
8.5
—
10.0
—
11.0
—
12.0
ns
Clock to Output Invalid
tKQX
3.0
—
3.0
—
3.0
—
3.0
—
ns
Clock to Output in Low-Z
tLZ1
3.0
—
3.0
—
3.0
—
3.0
—
ns
Clock to Match Valid
tKM
—
8.5
—
10.0
—
11.0
—
12.0
ns
Clock to Match Invalid
tKMX
3.0
—
3.0
—
3.0
—
3.0
—
ns
Clock to Match in Low-Z
tMLZ1
3.0
—
3.0
—
3.0
—
3.0
—
ns
Clock HIGH Time
tKH
1.3
—
1.5
—
1.7
—
2
—
ns
Clock LOW Time
tKL
1.5
—
1.7
—
1.9
—
2.2
—
ns
Clock to Output in High-Z
tHZ1
1.5
3.5
1.5
3.8
1.5
4
1.5
5
ns
OE to Output Valid
tOE
—
3.5
—
3.8
—
4
—
5
ns
OE to output in Low-Z
tOLZ1
0
—
0
—
0
—
0
—
ns
OE to output in High-Z
tOHZ1
—
3.5
—
3.8
—
4
—
5
ns
MOE to Match Valid
tMOE
—
3.5
—
3.8
—
4
—
5
ns
MOE to Match in Low-Z
tMOLZ1
0
—
0
—
0
—
0
—
ns
MOE to Match in High-Z
tMOHZ1
—
3.5
—
3.8
—
4
—
5
ns
13/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
AC Electrical Characteristics
Parameter
Symbol
Setup time
-166
-150
-133
-100
Unit
Min
Max
Min
Max
Min
Max
Min
Max
tS
1.5
—
1.5
—
2.0
—
2.0
—
ns
Hold time
tH
0.5
—
0.5
—
0.5
—
0.5
—
ns
ZZ setup time
tZZS2
5
—
5
—
5
—
5
—
ns
ZZ hold time
tZZH2
1
—
1
—
1
—
1
—
ns
ZZ recovery
tZZR
20
—
20
—
20
—
20
—
ns
Notes:
1. These parameters are sampled and are not 100% tested
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.05 7/2001
14/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
Write Cycle Timing
Burst Write
Single Write
Deselected
Write
CLK
tS tH
tKH
tKC
tKL
ADSP is blocked by CE1 inactive
ADSP
tS tH
ADSC initiated write
ADSC
tS tH
ADV
tS tH
A0–A17
ADV must be inactive for ADSP Write
WR2
WR1
WR3
tS tH
GW
tS tH
BWE
tS tH
BW1–
BW2
WR1
WR1
WR2
WR2
tS tH
WR3
WR3
CE1 masks ADSP
CE1
tS tH
Deselected with CE2
CE2
tS tH
CE2 and CE3 only sampled with ADSP or ADSC
CE3
OE
DQ1–16
DQP1–2
DE
Rev: 1.05 7/2001
tS tH
Hi-Z
D1a
Write specified byte for 2a and all bytes for 2b, 2c& 2d
D2a
D2b
D2c
D2d
D3a
tS tH
15/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
Flow Through—Read Cycle Timing
Single Read
CLK
Single Read
tS tH
tKH
ADSP
tKC
tKL
ADSP is blocked by CE1 inactive
tS tH
ADSC
ADSC initiated read
tS tH
ADV
Suspend Burst
Suspend Burst
tS tH
A0–A17
RD1
RD2
RD3
tS
tH
GW
tS
tH
BWE
BW1–
BW2
tS tH
CE1 masks ADSP
CE1
tS tH
CE2 and CE3 only sampled with ADSP or ADSC
Deselected with CE2
CE2
tS tH
CE3
tOE
OE
DQ1–16
DQP1–2
tOHZ
Hi-Z
tOLZ
Q1a
tKQX
Q2a
tKQX
Q2b
Q2c
Q2d
tLZ
tHZ
tKQ
Rev: 1.05 7/2001
Q3a
16/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
Flow Through—Read/Write Cycle Timing
CLK
tS tH
Burst Read
Single Write
Single Read
tKC
tKH tKL
ADSP is blocked by CE1 inactive
ADSP
tS tH
ADSC initiated read
ADSC
tS tH
ADV
tS tH
A0–A17
RD2
WR1
RD1
tS tH
GW
tS
tH
BWE
tS tH
BW1–
BW2
WR1
tS tH
CE1 masks ADSP
CE1
tS tH
CE2 and CE3 only sampled with ADSP and ADSC
CE2
tS tH
Deselected with CE3
CE3
tOE
tOHZ
OE
DQ1–16
DQP1–2
Hi-Z
tKQ
tS tH
Q1a
D1a
Q2a
tS tH
Burst wrap around to its initial state
Q2b
Q2c
Q2d
Q2a
DE
Rev: 1.05 7/2001
17/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
Pipeline—Read Cycle Timing
Burst Read
Single Read
CLK
tS tH
tKH
ADSP
tKC
tKL
ADSP is blocked by CE1 inactive
tS tH
ADSC
ADSC initiated read
tS tH
ADV
Suspend Burst
tS tH
A0–A17
RD1
RD3
RD2
tS
tH
GW
tS
tH
BWE
BW1–
BW4
tS tH
CE1 masks ADSP
CE1
tS tH
CE2 and CE3 only sampled with ADSP or ADSC
Deselected with CE2
CE2
tS tH
CE3
tOE
OE
DQ1–16
DQP1–2
Hi-Z
tOHZ
tOLZ
tKQX
tKQX
Q1a
Q2a
tLZ
Q2b
Q2c
Q3a
tHZ
tKQ
Rev: 1.05 7/2001
Q2d
18/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
Pipeline—Read/Write Cycle Timing
Single Write
Single Read
CLK
tS tH
tKC
tKH tKL
Burst Read
ADSP is blocked by CE1 inactive
ADSP
tS tH
ADSC initiated read
ADSC
tS tH
ADV
tS tH
A0–A17
RD2
WR1
RD1
tS tH
GW
tS
tH
BWE
tS tH
BW1–
BW4
WR1
tS tH
CE1 masks ADSP
CE1
tS tH
CE2 and CE3 only sampled with ADSP and ADSC
CE2
tS tH
Deselected with CE3
CE3
tOE
tOHZ
OE
DQ1–16
DQP1–2
Hi-Z
tS tH
tKQ
D1a
Q1a
Q2a
Q2b
Q2c
Q2d
tS tH
DE
Rev: 1.05 7/2001
19/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
Flow Through—Compare/Fill Write Cycle Timing
CLK
CE
tS
tH
(1)
W(2)
OE
A0-A17
A
B
DQ1-16
DQP1-2
A
B
B
DE
MOE
MATCH
tKM
tKM
tMOE
tMLZ
tKMX
Hit
tKM
Match high when chip deselected
Miss
Fill Write
Notes:
1. CE = L is defined as CE1=L, CE2=H and CE3=L
2. W = L is the Asertive function of GW, BWE, BW1, BW2. See Byte Write Function table for detail.
Rev: 1.05 7/2001
20/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
Pipeline—Compare/Fill Write Cycle Timing
CLK
CE
tS
tH
(1)
W(2)
OE
A0-A17
A
B
DQ1-16
DQP1-2
A
B
B
DE
tKM
tKM
MOE
tMLZ
tMOE
tKMX
tKM
Match high when chip deselected
MATCH
Hit
Miss
Fill Write
Notes:
1. CE = L is defined as CE1=L, CE2=H and CE3=L
2. W = L is the Asertive function of GW, BWE, BW1, BW2. See Byte Write Function table for detail.
Rev: 1.05 7/2001
21/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
CLK
tS tH
tKC
tKH tKL
ADSP
ADSC
ZZ
tZZS
Rev: 1.05 7/2001
~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~
ZZ Timing
tZZR
Snooze tZZH
22/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
Test Mode Description
Functional Description
The GS84118 provides JTAG boundary scan interface using IEEE standard 1149.1 protocol. The Test mode is intended to provide
a mechanism for testing the interconnect between master (processor, controller, etc.), SRAM, other components and the Printed
Circuit Board.
Test Access Port (TAP)
Four pins (as defined in Pin Description Tables) are used to performed JTAG functions. TDI input is used to scan test data serially
into one of three registers (Instruction Register, Boundary Scan Register and Bypass Register). TDO is the output pin to serially
output scan test data. The TDI sends the data into the LSB of the selected register and the MSB of that register feeds the data to
TDO. TMS input pin controls the state transition of 16 state TAP controllers, as specified in IEEE standard 1149.1. Inputs on TDI
and TMS are registered on the rising edge of TCK clock, and the output data on TDO is presented on the falling edge of TCK. The
TDO driver is in active state only when TAP controller is in Shift-IR state or in Shift -DR state.
TAP Controller
Sixteen state controllers are implemented as specified in IEEE standard 1149.1.
The controller enters the Reset state either through
• Power up or
• Apply logic 1 on TMS input pin on 5 consecutive rising edges.
Tap Controller State Diagram
1
Test Logic Reset
0
0
Run Test Idle
1
Select DR
1
Select IR
0
0
1
1
Capture DR
0
Capture IR
0
0
0
Shift DR
1
1
Shift IR
1
1
Exit1 DR
Exit1 IR
0
0
0
Pause DR
0
Pause IR
1
1
Exit2 DR
1
1
Rev: 1.05 7/2001
Update DR
0
1
0
Exit2 IR
1
0
Update IR
1
0
23/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
Instruction Register (3 Bits)
The JTAG Instruction register is consisted of shift register stage and parallel output latch. The register is 3 bits wide and is encoded
as follow:
Octal
MSB
—
LSB
Instruction
0
0
0
0
Bypass
1
0
0
1
IDCODE—Read device ID
2
0
1
0
Sample-Z—Sample Inputs and tri-state DQs, Match
3
0
1
1
Bypass
4
1
0
0
Sample—Sample Inputs
5
1
0
1
Private—Manufacturer use only
6
1
1
0
Bypass
7
1
1
1
Bypass
Bypass Register (1 Bit)
The Bypass Register is one bit wide and is connected electrically between TDI and TDO and provides the minimum length serially
path between TDI and TDO.
ID Register (32 Bits)
The ID Register are 32 bits wide and are listed as follow:
Rev: 1.05 7/2001
Header
ID[0]
1
GSI ID
(89 decimal in bank 2)
ID[7:1]
101 1001
ID[11:8]
0001
Part Number
ID[27:12]
0000 0000 0000 0000
Revision Number
ID[31:28]
xxxx
24/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
Boundary Scan Register (54 Bits)
The Boundary Scan Register are 54 bits wide and are listed as follow:
DQx, Match
19
Address
18
GW, BWE, BW1-2, DE
5
CE1, CE2, CE3
3
OE, MOE
2
ADSP, ADSC, ADV
3
ZZ, FT, LBO
3
CLK
1
Total
54
Scan Order (Order by exit sequence)
Order
Signal
TQFP
BGA
Order
Signal
TQFP
BGA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
A15
A14
A13
A12
A11
A16
A17
MOE
DE
MATCH
DQ1
DQ2
DQ3
DQ4
ZZ
DQ5
DQ6
DQ7
DQ8
DQP1
A10
A9
A8
ADV
ADSP
ADSC
OE
44
45
46
47
48
49
50
51
52
53
58
59
62
63
64
68
69
72
73
74
80
81
82
83
84
85
86
3T
2T
5T
6R
5C
5B
6C
6P
7N
6M
7P
6N
6L
7K
7T
6H
7G
6F
7E
6D
6T
6A
5A
4G
4A
4B
4F
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
BWE
GW
CLK
CE3
BW1
BW2
CE2
CE1
A7
A6
DQ9
DQ10
DQ11
DQ12
FT
DQ13
DQ14
DQ15
DQ16
DQP2
LBO
A5
A4
A3
A2
A1
A0
87
88
89
92
93
94
97
98
99
100
8
9
12
13
14
18
19
22
23
24
31
32
33
34
35
36
37
4M
4H
4K
6B
5L
3G
2B
4E
3A
2A
1D
2E
2G
1H
5R
2K
1L
2M
1N
2P
3R
2C
3B
3C
2R
4N
4P
Rev: 1.05 7/2001
25/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
Test Mode AC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
TCK Cycle Time
tTKC
20
—
ns
TCK Low to TDO Valid
tTKQ
—
10
ns
TCK High Pulse Width
tTKH
10
—
ns
TCK Low Pulse Width
tTKL
10
—
ns
TDI & TMS Set Up Time
tTS
5
—
ns
TDI & TMS Hold Time
tTH
5
—
ns
Test Mode Timing Diagram
tTKH
tTKL
tTKC
TCK
tTS
tTH
TMS
TDI
TDO
tTKQ
Rev: 1.05 7/2001
26/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
Package Dimensions—100-Pin TQFP
L
θ
c
Pin 1
L1
D
D1
e
b
A1
A2
E1
Y
E
Symbol
Description
Min.
Nom.
Max
A1
Standoff
0.05
0.10
0.15
A2
Body Thickness
1.35
1.40
1.45
B
Lead Width
0.20
0.30
0.40
C
Lead Thickness
0.09
D
Terminal Dimension
21.9
22.0
22.1
D1
Package Body
19.9
20.0
20.1
E
Terminal Dimension
15.9
16.0
16.1
E1
Package Body
13.9
14.0
14.1
E
Lead Pitch
L
Foot Length
L1
Lead Length
Y
Coplanarity
Q
Lead Angle
0.20
0.65
0.45
0.60
0.75
1.00
0.10
0°
7°
Notes:
1.
2.
Rev: 1.05 7/2001
All dimesnions are in millimeters (mm).
Package wideth and length do not include mold protrusion.
27/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
Package Dimesions - 119 Pin PBGA
A
Pin 1
Corner
7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
G
B
P
S
D
N
R
Bottom View
Top View
Symbo
l
Description
A
Width
13.8
14.0
14.2
B
Length
21.8
22.0
22.2
C
Package Height (including ball)
-
D
Ball Size
0.60
0.75
0.90
E
Ball Height
0.50
0.60
0.70
F
Package Height (excluding balls)
1.46
1.70
G
Width between Balls
1.27
K
Package Height above board
N
Cut-out Package Width
12.00
P
Foot Length
19.50
R
Width of package between balls
7.62
S
Length of package between balls
20.32
T
Variance of Ball Height
0.15
C
F
E
K
T
Package Dimesions - 119 Pin PBGA
Min Nom Ma
.
.
x
0.80
2.40
0.90
1.00
Unit: mm
Side View
BPR 1999.05.18
Rev: 1.05 7/2001
28/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
Ordering Information
Org
Part Number1
Type
Package
Speed2
(MHz/ns)
TA
256K x 18
GS84118T-166
Pipeline/Flow Through
TQFP
166/8.5
C
256K x 18
GS84118T-150
Pipeline/Flow Through
TQFP
150/10
C
256K x 18
GS84118T-133
Pipeline/Flow Through
TQFP
133/11
C
256K x 18
GS84118T-100
Pipeline/Flow Through
TQFP
100/12
C
256K x 18
GS84118T-166I
Pipeline/Flow Through
TQFP
166/8.5
I
256K x 18
GS84118T-150I
Pipeline/Flow Through
TQFP
150/10
I
256K x 18
GS84118T-133I
Pipeline/Flow Through
TQFP
133/11
C
256K x 18
GS84118T-100I
Pipeline/Flow Through
TQFP
100/12
I
256K x 18
GS84118B-166
Pipeline/Flow Through
BGA
166/8.5
C
256K x 18
GS84118B-150
Pipeline/Flow Through
BGA
150/10
C
256K x 18
GS84118B-133
Pipeline/Flow Through
BGA
133/11
C
256K x 18
GS84118B-100
Pipeline/Flow Through
BGA
100/12
C
256K x 18
GS84118B-166I
Pipeline/Flow Through
BGA
166/8.5
I
256K x 18
GS84118B-150I
Pipeline/Flow Through
BGA
150/10
I
256K x 18
GS84118I-133I
Pipeline/Flow Through
BGA
133/11
C
256K x 18
GS84118B-100I
Pipeline/Flow Through
BGA
100/12
I
3
Status
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS84032T-7.5T.
2. The speed column indicates the cycle frequency (Mhz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each
device is Pipeline / Flow through mode selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site for a complete listing of current offerings.
Rev: 1.05 7/2001
29/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
4Mb Synchronous Tag RAM Datasheet Revision History
Rev. Code: Old;New
GS84118-2000207; 84118_r1_01
84118_r1_02; 84118_r1_03
84118_r1_03; 84118_r1_04
84118_r1_04; 84118_r1_05
Rev: 1.05 7/2001
Types of Changes
Page /Revisions;Reason
Format or Content
Content
• Updated BGA Pin Description to meet JEDEC standard
Content/Format
• Updated format to comply with Technical Publications
standards
• Corrected typo in TQFP Package Description table on page
27
Content
• Updated Pinout on page 3
• Updated Pin Description tables for TQFP and PBGA
• Added overbar to all references of BWE, BW1, BW2, GW,
CE1, CE3, OE, ADV, ADSP, ADSC, MOE, DE, FT, and LBO
• Removed VDD note from AC Electrical Characteristics table
• Imported up-to-date Package Drawing for 119 PBGA
Content
• Reordered pin location listings in pin description tables on
pages 4 and 5
• Removed Global Write reference from BWE description in pin
description tables
• Removed BWE reference from GW description in pin
description tables
• Placed overbars on Write references in Synchronous Truth
Table
30/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.