Preliminary GS880E18/32/36T-11/11.5/100/80/66 100-Pin TQFP Commercial Temp Industrial Temp 512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs Features 100 MHz–66 MHz 3.3 V VDD 3.3 V and 2.5 V I/O interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. • FT pin for user-configurable flow through or pipelined operation • Dual Cycle Deselect (DCD) operation • 3.3 V +10%/–5% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Common data inputs and data outputs • Clock Control, registered, address, data, and control • Internal self-timed write cycle • Automatic power-down for portable applications • 100-lead TQFP package Flow Through / Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register. DCD Pipelined Reads The GS880E18/32/36T is a DCD (Dual Cycle Deselect) pipelined synchronous SRAM. SCD (Single Cycle Deselect) versions are also available. DCD SRAMs pipeline disable commands to the same degree as read commands. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. -11 -11.5 -100 -80 -66 10 ns 10 ns 12.5 ns 15 ns Pipeline tCycle 10 ns 4.0 ns 4.0 ns 4.0 ns 4.5 ns 5.0 ns 3-1-1-1 tKQ 225 mA 225 mA 225 mA 200 mA 185 mA IDD Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write control inputs. 11 ns 11.5 ns 12 ns 14 ns 18 ns Flow tKQ 15 ns 15 ns 15 ns 20 ns Through tCycle 15 ns 2-1-1-1 IDD 180 mA 180 mA 180 mA 175 mA 165 mA Sleep Mode Functional Description Low power (Sleep mode) is attained through the assertion (high) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Applications The GS880E18/32/36T is a 9,437,184-bit (8,388,608-bit for x32 version) high performance synchronous SRAM with a 2bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Core and Interface Voltages The GS880E18/32/36T operates on a 3.3 V power supply, and all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuit. Controls Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or Rev: 1.11 11/2000 1/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS880E18/32/36T-11/11.5/100/80/66 A6 A7 E1 E2 NC NC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A8 A9 GS880E18 100-Pin TQFP Pinout LBO A5 A4 VSS NC NC DQB1 DQB2 VSS VDDQ DQB3 DQB4 FT VDD NC VSS DQB5 DQB6 VDDQ VSS DQB7 DQB8 DQB9 NC VSS VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev: 1.11 11/2000 A18 NC NC VDDQ VSS NC DQA9 DQA8 DQA7 VSS VDDQ DQA6 DQA5 VSS NC VDD ZZ DQA4 DQA3 VDDQ VSS DQA2 DQA1 NC NC VSS VDDQ NC NC NC A3 A2 A1 A0 NC NC VSS VDD NC A17 A10 A11 A12 A13 A14 A15 A16 NC NC NC VDDQ 2/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS880E18/32/36T-11/11.5/100/80/66 A6 A7 E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A8 A9 GS880E32 100-Pin TQFP Pinout LBO A5 A4 VSS DQC6 DQC5 DQC4 DQC3 VSS VDDQ DQC2 DQC1 FT VDD NC VSS DQD1 DQD2 VDDQ VSS DQD3 DQD4 DQD5 DQD6 VSS VDDQ DQD7 DQD8 NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 256K x 32 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev: 1.11 11/2000 NC DQB8 DQB7 VDDQ VSS DQB6 DQB5 DQB4 DQB3 VSS VDDQ DQB2 DQB1 VSS NC VDD ZZ DQA1 DQA2 VDDQ VSS DQA3 DQA4 DQA5 DQA6 VSS VDDQ DQA7 DQA8 NC A3 A2 A1 A0 NC NC VSS VDD NC A17 A10 A11 A12 A13 A14 A15 A16 NC DQC8 DQC7 VDDQ 3/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS880E18/32/36T-11/11.5/100/80/66 A6 A7 E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A8 A9 GS880E36 100-Pin TQFP Pinout LBO A5 A4 VSS DQC6 DQC5 DQC4 DQC3 VSS VDDQ DQC2 DQC1 FT VDD NC VSS DQD1 DQD2 VDDQ VSS DQD3 DQD4 DQD5 DQD6 VSS VDDQ DQD7 DQD8 DQD9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 256K x 36 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev: 1.11 11/2000 DQB9 DQB8 DQB7 VDDQ VSS DQB6 DQB5 DQB4 DQB3 VSS VDDQ DQB2 DQB1 VSS NC VDD ZZ DQA1 DQA2 VDDQ VSS DQA3 DQA4 DQA5 DQA6 VSS VDDQ DQA7 DQA8 DQA9 A3 A2 A1 A0 NC NC VSS VDD NC A17 A10 A11 A12 A13 A14 A15 A16 DQC9 DQC8 DQC7 VDDQ 4/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS880E18/32/36T-11/11.5/100/80/66 TQFP Pin Description Pin Location Symbol Typ e Description 37, 36 A0, A1 I Address field LSBs and Address Counter preset Inputs 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50, 43 A2–A17 I Address Inputs 80 A18 I Address Inputs 63, 62, 59, 58, 57, 56, 53, 52 68, 69, 72, 73, 74, 75, 78, 79 13, 12, 9, 8, 7, 6, 3, 2 18, 19, 22, 23, 24, 25, 28, 29 DQA1–DQA8 DQB1–DQB8 DQC1–DQC8 DQD1–DQD8 I/O Data Input and Output pins (x32, x36 Version) 51, 80, 1, 30 DQA9, DQB9, DQC9, DQD9 I/O Data Input and Output pins 51, 80, 1, 30 NC — No Connect (x32 Version) 58, 59, 62, 63, 68, 69, 72, 73, 74 8, 9, 12, 13, 18, 19, 22, 23, 24 DQA1–DQA9 DQB1–DQB9 I/O Data Input and Output pins 51, 52, 53, 56, 57 75, 78, 79, 1, 2, 3, 6, 7 25, 28, 29, 30 NC — No Connect 87 BW I Byte Write—Writes all enabled bytes; active low 93, 94 BA, BB I Byte Write Enable for DQA, DQB Data I/Os; active low 95, 96 BC, BD I Byte Write Enable for DQC, DQD Data I/Os; active low (x32, x36 Version) 95, 96 NC — No Connect (x18 Version) 89 CK I Clock Input Signal; active high 88 GW I Global Write Enable—Writes all bytes; active low 98, 92 E1, E3 I Chip Enable; active low 97 E2 I Chip Enable; active high 86 G I Output Enable; active low 83 ADV I Burst address counter advance enable; active low 84, 85 ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low 64 ZZ I Sleep mode control; active high 14 FT I Flow Through or Pipeline mode; active low 31 LBO I Linear Burst Order mode; active low 15, 41, 65, 91 VDD I Core power supply 5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90 VSS I I/O and Core Ground 4, 11, 20, 27, 54, 61, 70, 77 VDDQ I Output driver power supply 16, 38, 39, 42, 66 NC — No Connect. Rev: 1.11 11/2000 5/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS880E18/32/36T-11/11.5/100/80/66 GS880E32 Block Diagram Register A0–An D Q A0 A0 D0 Q0 A1 A1 D1 Q1 Counter Load A LBO ADV Memory Array CK ADSC ADSP Q D Register GW BW BA D Q 36 Register D 36 Q BB 4 Register D Q D Q Q D D Register Register Q Register BC BD Register D Q Register E1 E2 E3 D Q Register D Q FT G ZZ 0 Power Down DQx0–DQx9 Control Note: Only x36 version shown for simplicity. Rev: 1.11 11/2000 6/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Mode Pin Functions Mode Name Pin Name Burst Order Control LBO Output Register Control FT Power Down Control ZZ State Function L Linear Burst H or NC Interleaved Burst L Flow Through H or NC Pipeline L or NC Active H Standby, IDD = ISB Note: There are pull-up devices on the LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above table. Burst Counter Sequences Interleaved Burst Sequence Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 1st address 00 01 10 11 2nd address 01 10 11 00 2nd address 01 00 11 10 3rd address 10 11 00 01 3rd address 10 11 00 01 4th address 11 00 01 10 4th address 11 10 01 00 Note: The burst counter wraps to initial state on the 5th clock. Note: The burst counter wraps to initial state on the 5th clock. BPR 1999.05.18 Byte Write Truth Table Function GW BW BA BB BC BD Notes Read H H X X X X 1 Read H L H H H H 1 Write byte a H L L H H H 2, 3 Write byte b H L H L H H 2, 3 Write byte c H L H H L H 2, 3, 4 Write byte d H L H H H L 2, 3, 4 Write all bytes H L L L L L 2, 3, 4 Write all bytes L X X X X X Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “C” and “D” are only available on the x32 and x36 versions. Rev: 1.11 11/2000 7/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Synchronous Truth Table Operation Address Used State Diagram Key5 E1 Deselect Cycle, Power Down None X H X X Deselect Cycle, Power Down None X L F Deselect Cycle, Power Down None X L Read Cycle, Begin Burst External R Read Cycle, Begin Burst External Write Cycle, Begin Burst E22 ADV W3 DQ4 L X X High-Z L X X X High-Z F H L X X High-Z L T L X X X Q R L T H L X F Q External W L T H L X T D Read Cycle, Continue Burst Next CR X X H H L F Q Read Cycle, Continue Burst Next CR H X X H L F Q Write Cycle, Continue Burst Next CW X X H H L T D Write Cycle, Continue Burst Next CW H X X H L T D Read Cycle, Suspend Burst Current X X H H H F Q Read Cycle, Suspend Burst Current H X X H H F Q Write Cycle, Suspend Burst Current X X H H H T D Write Cycle, Suspend Burst Current H X X H H T D (x36only) ADSP ADSC Notes: 1. X = Don’t Care, H = High, L = Low. 2. For x36 Version, E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1. 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 5. 6. 7. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.11 11/2000 8/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Simplified State Diagram X Deselect W R Simple Burst Synchronous Operation Simple Synchronous Operation W X R R First Write CW First Read CR W X CR R R X Burst Write Burst Read X CR CW CR Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and assumes ADSP is tied high and ADV is tied low. Rev: 1.11 11/2000 9/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Simplified State Diagram with G X Deselect W R W X R R First Write CR CW W CW W X First Read X CR R Burst Write R CR CW W Burst Read X CW CR Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles. 3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.11 11/2000 10/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Absolute Maximum Ratings (All voltages reference to VSS) Symbol Description Value Unit VDD Voltage on VDD Pins –0.5 to 4.6 V VDDQ Voltage in VDDQ Pins –0.5 to VDD V VCK Voltage on Clock Input Pin –0.5 to 6 V VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 (≤ 4.6 V max.) V VIN Voltage on Other Input Pins –0.5 to VDD +0.5 (≤ 4.6 V max.) V IIN Input Current on Any Pin +/–20 mA IOUT Output Current on Any I/O Pin +/–20 mA PD Package Power Dissipation 1.5 W TSTG Storage Temperature –55 to 125 o TBIAS Temperature Under Bias –55 to 125 oC C Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Recommended Operating Conditions Parameter Symbol Min. Typ. Max. Unit Notes Supply Voltage VDD 3.135 3.3 3.6 V I/O Supply Voltage VDDQ 2.375 2.5 VDD V 1 Input High Voltage VIH 1.7 — VDD +0.3 V 2 Input Low Voltage VIL –0.3 — 0.8 V 2 Ambient Temperature (Commercial Range Versions) TA 0 25 70 °C 3 Ambient Temperature (Industrial Range Versions) TA –40 25 85 °C 3 Notes: 1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V ≤ VDDQ ≤ 2.375 V (i.e., 2.5 V I/O) and 3.6 V ≤ VDDQ ≤ 3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case. 2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers. 3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 4. Input Under/overshoot voltage must be –2 V > Vi < VDD +2 V with a pulse width not to exceed 20% tKC. Rev: 1.11 11/2000 11/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Undershoot Measurement and Timing Overshoot Measurement and Timing VIH 20% tKC VDD + 2.0 V VSS 50% 50% VDD VSS – 2.0 V 20% tKC VIL Capacitance (TA = 25oC, f = 1 MHZ, VDD = 3.3 V) Parameter Symbol Test conditions Typ. Max. Unit Input Capacitance CIN VIN = 0 V 4 5 pF Input/Output Capacitance CI/O VOUT = 0 V 6 7 pF Note: These parameters are sample tested. Package Thermal Characteristics Rating Layer Board Symbol Max Unit Notes Junction to Ambient (at 200 lfm) single RΘJA 40 °C/W 1,2 Junction to Ambient (at 200 lfm) four RΘJA 24 °C/W 1,2 Junction to Case (TOP) — RΘJC 9 °C/W 3 Notes: 1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance. 2. SCMI G-38-87 3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1 Rev: 1.11 11/2000 12/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS880E18/32/36T-11/11.5/100/80/66 AC Test Conditions Parameter Conditions Input high level 2.3 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level 1.25 V Output reference level 1.25 V Output load Fig. 1& 2 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ 4. Device is deselected as defined by the Truth Table. Output Load 2 Output Load 1 DQ 2.5 V 50Ω 30pF* 225Ω DQ 5pF* VT = 1.25 V 225Ω * Distributed Test Jig Capacitance DC Electrical Characteristics Parameter Symbol Test Conditions Min Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD –1 uA 1 uA ZZ Input Current IINZZ VDD ≥ VIN ≥ VIH 0 V ≤ VIN ≤ VIH –1 uA –1 uA 1 uA 300 uA Mode Pin Input Current IINM VDD ≥ VIN ≥ VIL 0 V ≤ VIN ≤ VIL –300 uA –1 uA 1 uA 1 uA Output Leakage Current IOL Output Disable, VOUT = 0 to VDD –1 uA 1 uA Output High Voltage VOH IOH = –8 mA, VDDQ = 2.375 V 1.7 V — Output High Voltage VOH IOH = –8 mA, VDDQ = 3.135 V 2.4 V — Output Low Voltage VOL IOL = 8 mA — 0.4 V Rev: 1.11 11/2000 13/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Operating Currents -11 –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C Unit IDD Pipeline 225 235 225 235 225 235 200 210 185 195 mA IDD Flow-Thru 180 190 180 190 180 190 175 185 165 175 mA ISB Pipeline 30 40 30 40 30 40 30 40 30 40 mA ISB Flow-Thru 30 40 30 40 30 40 30 40 30 40 mA IDD Pipeline 80 90 80 90 80 90 70 80 60 70 mA IDD Flow-Thru 65 75 65 75 65 75 55 65 50 60 mA Operating Current Device Selected; All other inputs ≥VIH or ≤ VIL Output open Deselect Current Rev: 1.11 11/2000 -66 0 to 70°C Symbol Device Deselected; All other inputs ≥ VIH or ≤ VIL -80 –40 to 85°C Test Conditions ZZ ≥ VDD - 0.2V -100 0 to 70°C Parameter Standby Current -11.5 14/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS880E18/32/36T-11/11.5/100/80/66 AC Electrical Characteristics Pipeline FlowThru Parameter Symbol Clock Cycle Time -11 -11.5 -100 -80 -66 Unit Min Max Min Max Min Max Min Max Min Max tKC 10 — 10 — 10 — 12.5 — 15 — ns Clock to Output Valid tKQ — 4.0 — 4.0 — 4.0 — 4.5 — 5 ns Clock to Output Invalid tKQX 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns Clock to Output in Low-Z tLZ 1 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns Clock Cycle Time tKC 15.0 — 15.0 — 15.0 — 15.0 — 20 — ns Clock to Output Valid tKQ — 11.0 — 11.5 — 12.0 — 14.0 — 18 ns Clock to Output Invalid tKQX 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns Clock to Output in Low-Z tLZ1 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns Clock HIGH Time tKH 1.7 — 1.7 — 2 — 2 — 2.3 — ns Clock LOW Time tKL 2 — 2 — 2.2 — 2.2 — 2.5 — ns Clock to Output in High-Z tHZ1 1.5 4.0 1.5 4.2 1.5 4.5 1.5 4.5 1.5 4.8 ns G to Output Valid tOE — 4.0 — 4.2 — 4.5 — 4.5 — 4.8 ns G to output in Low-Z tOLZ1 0 — 0 — 0 — 0 — 0 — ns G to output in High-Z tOHZ1 — 4.0 — 4.2 — 4.5 — 4.5 — 4.8 ns Setup time tS 1.5 — 2.0 — 2.0 — 2.0 — 2.0 — ns Hold time tH 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns ZZ setup time tZZS2 5 — 5 — 5 — 5 — 5 — ns ZZ hold time tZZH2 1 — 1 — 1 — 1 — 1 — ns ZZ recovery tZZR 20 — 20 — 20 — 20 — 20 — ns Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.11 11/2000 15/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Write Cycle Timing Single Write Burst Write Deselected Write CK tS tH tKH tKL tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated write ADSC tS tH ADV tS tH A0–An ADV must be inactive for ADSP Write WR2 WR1 WR3 tS tH GW tS tH BW tS tH BA–BD WR1 WR1 WR2 tS tH WR3 WR3 E1 masks ADSP E1 tS tH Deselected with E2 E2 tS tH E2 and E3 only sampled with ADSP or ADSC E3 G tS tH DQA–DQD Rev: 1.11 11/2000 Hi-Z D1A Write specified byte for 2A and all bytes for 2B, 2c& 2D D2A D2B D2C D2D D3A 16/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Flow Through Read-Write Cycle Timing Single Write Single Read Burst Read CK tS tH tKC tKH tKL ADSP is blocked by E inactive ADSP tS tH ADSC initiated read ADSC tS tH ADV tS tH A0–An RD2 WR1 RD1 tS tH GW tS tH tS BW tS BA–BD tH WR1 tS tH E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP and ADSC E2 tS tH Deselected with E3 E3 tOE tOHZ G tS tKQ DQA–DQD Hi-Z Q1A tH D1A Q2A Q2B Q2c Q2D Q2A Burst wrap around to it’s initial state Rev: 1.11 11/2000 17/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Flow Through Read Cycle Timing Single Read Burst Read tKL CK tKH tS tH tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated read ADSC tS tH Suspend Burst Suspend Burst ADV tS tH A0–An RD1 RD2 RD3 tS tH tS tH GW BW BA–BD tS tH E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP or ADSC Deselected with E2 E2 tS tH E3 tOE tOHZ G tKQX tOLZ DQA–DQD Q1A Hi-Z Q2A tKQX Q2B Q2C Q2D Q3A tLZ tHZ tKQ Rev: 1.11 11/2000 18/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Pipelined DCD Read Cycle Timing Single Read tKL Burst Read CK tS tH tKH tKC ADSP is blocked by E1 inactive ADSP tS tH ADSC initiated read ADSC tS tH Suspend Burst ADV tS tH A0–An RD1 RD3 RD2 tS tH tS tH GW BW BA–BD tS tH E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP or ADSC E2 tS tH Deselected with E2 E3 tOE G tOHZ Hi-Z tOLZ Q1A DQA–DQD tKQX Q2A tKQX Q2B Q2c Q2D Q3A tLZ tHZ tKQ Rev: 1.11 11/2000 19/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Pipelined DCD Read-Write Cycle Timing Single Write Burst Read Single Read tKL CK tS tH tKH tKC ADSP is blocked by E1 inactive ADSP tS tH ADSC initiated read ADSC tS tH ADV tS tH A0–An WR1 RD1 RD2 tS tH GW tS tH BW tS tH BA–BD WR1 tS tH E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP and ADSC E2 tS tH Deselected with E3 E3 tOE tOHZ G DQA–DQD Rev: 1.11 11/2000 Hi-Z tS tH tKQ Q1A D1A Q2A 20/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Q2B Q2c Q2D © 2000, Giga Semiconductor, Inc. Preliminary GS880E18/32/36T-11/11.5/100/80/66 CK tS tH tKC tKH tKL ADSP ADSC tZZS ZZ ~ ~ ~ ~ ~ ~ ~~ ~ ~ ~ Sleep Mode Timing Diagram tZZH tZZR Snooze Application Tips Single and Dual Cycle Deselect SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention. Rev: 1.11 11/2000 21/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Output Driver Characteristics 120.0 100.0 Pull Down Drivers 80.0 60.0 40.0 20.0 VD D Q I Out (mA) IOut 0.0 VOut -20.0 VS S -40.0 -60.0 Pull Up Drivers -80.0 -100.0 -120.0 -140.0 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 V Out (Pull Down) VDDQ - V Out (Pull Up) 3.6V PD HD Rev: 1.11 11/2000 3.3V PD HD 3.1V PD HD 3.1V PU HD 3.3V PU HD 22/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 3.6V PU HD © 2000, Giga Semiconductor, Inc. Preliminary GS880E18/32/36T-11/11.5/100/80/66 TQFP Package Drawing L Min. Nom. Max A1 Standoff 0.05 0.10 0.15 A2 Body Thickness 1.35 1.40 1.45 b Lead Width 0.20 0.30 0.40 c Lead Thickness 0.09 — 0.20 D Terminal Dimension 21.9 22.0 22.1 D1 Package Body 19.9 20.0 20.1 E Terminal Dimension 15.9 16.0 16.1 E1 Package Body 13.9 14.0 14.1 e Lead Pitch — 0.65 — L Foot Length 0.45 0.60 0.75 L1 Lead Length — 1.00 — Y Coplanarity — — 0.10 θ Lead Angle 0° — 7° L1 c D D1 Description Pin 1 Symbol θ e b A1 A2 Y E1 E Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. BPR 1999.05.18 Rev: 1.11 11/2000 23/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Ordering Information for GSI Synchronous Burst RAMs Org Part Number1 Type Package Speed2 (MHz/ns) TA3 514K x 18 GS880E18T-11 DCD Pipeline/Flow Through TQFP 100/11 C 514K x 18 GS880E18T-11.5 DCD Pipeline/Flow Through TQFP 100/11.5 C 514K x 18 GS880E18T-100 DCD Pipeline/Flow Through TQFP 100/12 C 514K x 18 GS880E18T-80 DCD Pipeline/Flow Through TQFP 80/14 C 514K x 18 GS880E18T-66 DCD Pipeline/Flow Through TQFP 66/18 C 256K x 32 GS880E32T-11 DCD Pipeline/Flow Through TQFP 100/11 C 256K x 32 GS880E32T-11.5 DCD Pipeline/Flow Through TQFP 100/11.5 C 256K x 32 GS880E32T-100 DCD Pipeline/Flow Through TQFP 100/12 C 256K x 32 GS880E32T-80 DCD Pipeline/Flow Through TQFP 80/14 C 256K x 32 GS880E32T-66 DCD Pipeline/Flow Through TQFP 66/18 C 256K x 36 GS880E36T-11 DCD Pipeline/Flow Through TQFP 100/11 C 256K x 36 GS880E36T-11.5 DCD Pipeline/Flow Through TQFP 100/11.5 C 256K x 36 GS880E36T-100 DCD Pipeline/Flow Through TQFP 100/12 C 256K x 36 GS880E36T-80 DCD Pipeline/Flow Through TQFP 80/14 C 256K x 36 GS880E36T-66 DCD Pipeline/Flow Through TQFP 66/18 C 514K x 18 GS880E18T-11I DCD Pipeline/Flow Through TQFP 100/11 I 514K x 18 GS880E18T-11.5I DCD Pipeline/Flow Through TQFP 100/11.5 I 514K x 18 GS880E18T-100I DCD Pipeline/Flow Through TQFP 100/12 I 514K x 18 GS880E18T-80I DCD Pipeline/Flow Through TQFP 80/14 I 514K x 18 GS880E18T-66I DCD Pipeline/Flow Through TQFP 66/18 I 256K x 32 GS880E32T-11I DCD Pipeline/Flow Through TQFP 100/11 I 256K x 32 GS880E32T-11.5I DCD Pipeline/Flow Through TQFP 100/11.5 I 256K x 32 GS880E32T-100I DCD Pipeline/Flow Through TQFP 100/12 I 256K x 32 GS880E32T-80I DCD Pipeline/Flow Through TQFP 80/14 I 256K x 32 GS880E32T-66I DCD Pipeline/Flow Through TQFP 66/18 I 256K x 36 GS880E36T-11I DCD Pipeline/Flow Through TQFP 100/11 I 256K x 36 GS880E36T-11.5I DCD Pipeline/Flow Through TQFP 100/11.5 I 256K x 36 GS880E36T-100I DCD Pipeline/Flow Through TQFP 100/12 I 256K x 36 GS880E36T-80I DCD Pipeline/Flow Through TQFP 80/14 I 256K x 36 GS880E36T-66I DCD Pipeline/Flow Through TQFP 66/18 I Status Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS880E18TT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.11 11/2000 24/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS880E18/32/36T-11/11.5/100/80/66 Revision History DS/DateRev. Code: Old; New Types of Changes Page;Revisions;Reason Format or Content Format/Typos • Last Page/Fixed “GSGS..” in Ordering Information Note. • Fromatted Pin Outs and Pin Description to new small caps. • Formatted Block diagrams to new small caps. • Formatted Timing Diagrams to new small caps. • Changed “Flow thru” to “Flow Through” in Timing Diagrams. • Package Diagram/Changed “Dimesion” to “Dimension”. Content • 5/Fixed pin description table to match pinouts. • Pin Description/Changed chip enables to match pins. • Pin Description/Changed pin 80 from NC to Address Input. • Pin Description/Rearranged Address Inputs to match order of Pinout • Package Diagram/Changed Dimension D Max from 20.1 to 22.1 Content • Changed Flow Through Read-Write Cycle Timing Diagram for accuracy. • Changed order of TQFP Address Inputs to match pinout. • Changed order of TQFP DATA Input and Output pins to match pinout. • New GSI Logo. GS880E18/32/36TRev1.04h 5/1999; 1.05 9/1999I GS880E18/32/36T1.05 11/ 1999K880E18/32/36T1.06 1/ 2000L GS880E18/32/36T1.06 1/ 2000L; GS880E18/32/36T1.07 3/ 2000N; GS880E18/32/36T1.07 3/ 2000N; GS880E18/32/36T1.08 3/ 2000O; Content • Corrections to AC Electrical Characteristics Table Content GS880E18/32/36T1.08 3/ 2000O; 880E183236_r1_09 Content/Format 880E18_r1_09; 880E18_r1_10 Content 880E18_r1_10; 880E18_r1_11 Content Rev: 1.11 11/2000 • Changed all speed bin information (headings, references, tables, ordering info..) to reflect 150 - 80Mhz • Removed 150 MHz speed bin • Changed 133 MHz and 117 MHz speed bins to 11 ns and 11.5 ns (100 MHz) numbers • Updated format to comply with Technical Publications standards • Updated Capitance table—removed Input row and changed Output row to I/O • Corrected typo in AC Electrical Characteristics table 25/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc.