Preliminary GS88418/36B-200/180/166/150/133 512K x 18, 256K x 36 8Mb S/DCD Sync Burst SRAMs 119-Bump BGA Commercial Temp Industrial Temp Features (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. • FT pin for user-configurable flow through or pipelined operation • Single/Dual Cycle Deselect Selectable • ZQ mode pin for user-selectable high/low output drive strength • 3.3 V +10%/–5% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to SCD x18/x36 Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Common data inputs and data outputs • Clock Control, registered, address, data, and control • Internal self-timed write cycle • Automatic power-down for portable applications • 119-bump BGA package Pipeline 3-1-1-1 tCycle tKQ IDD -200 5.0 3.0 450 -180 5. 5 3.2 410 -166 6.0 3.5 380 -150 6.7 3.8 350 -133 7.5 4.0 340 Unit ns ns mA Flow Through 2-1-1-1 tKQ tCycle IDD 7.5 10 270 8 10 270 8.5 10 250 9.0 10 240 9.5 10 220 ns ns mA 200 MHz–133 MHz 3.3 V VDD 3.3 V and 2.5 V I/O Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode bump (Bump 5R). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register. SCD and DCD Pipelined Reads The GS88436B is a SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input on Bump 4L. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Functional Description Applications The GS88418/36B is a 9,437,184-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. FLXDrive™ The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details. Controls Sleep Mode Addresses, data I/Os, chip enables (E1, in x18 version, E1 and E2 in x36 version), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power-down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Rev: 1.05 10/2001 Core and Interface Voltages The GS884B operates on a 3.3 V power supply and all inputs/ outputs are 3.3 V- and 2.5 V-compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuit. 1/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS88418/36B-200/180/166/150/133 GS88436 Pad Out 119-Bump BGA—Top View Rev: 1.05 10/2001 1 2 3 4 5 6 7 A VDDQ A6 A7 ADSP A8 A9 VDDQ B NC E2 A4 ADSC A15 A17 NC C NC A5 A3 VDD A14 A16 NC D DQC4 DQPC9 VSS ZQ VSS DQPB9 DQB4 E DQC3 DQC8 VSS E1 VSS DQB8 DQB3 F VDDQ DQC7 VSS G VSS DQB7 VDDQ G DQC2 DQC6 BC ADV BB DQB6 DQB2 H DQC1 DQC5 VSS GW VSS DQB5 DQB1 J VDDQ VDD NC VDD NC VDD VDDQ K DQD1 DQD5 VSS CK VSS DQA5 DQA1 L DQD2 DQD6 BD SCD BA DQA6 DQA2 M VDDQ DQD7 VSS BW VSS DQA7 VDDQ N DQD3 DQD8 VSS A1 VSS DQA8 DQA3 P DQD4 DQPD9 VSS A0 VSS DQPA9 DQA4 R NC A2 LBO VDD FT A13 NC T NC NC A10 A11 A12 NC ZZ U VDDQ NC NC NC NC NC VDDQ 2/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS88418/36B-200/180/166/150/133 GS88418 Pad Out 119-Bump BGA—Top View Rev: 1.05 10/2001 1 2 3 4 5 6 7 A VDDQ A6 A7 ADSP A8 A9 VDDQ B NC NC A4 ADSC A15 A17 NC C NC A5 A3 VDD A14 A16 NC D DQB1 NC VSS ZQ VSS DQA9 NC E NC DQB2 VSS E1 VSS NC DQA8 F VDDQ NC VSS G VSS DQA7 VDDQ G NC DQB3 BB ADV NC NC DQA6 H DQB4 NC VSS GW VSS DQA5 NC J VDDQ VDD NC VDD NC VDD VDDQ K NC DQB5 VSS CK VSS NC DQA4 L DQB6 NC NC SCD BA DQA3 NC M VDDQ DQB7 VSS BW VSS NC VDDQ N DQB8 NC VSS A1 VSS DQA2 NC P NC DQB9 VSS A0 VSS NC DQA1 R NC A2 LBO VDD FT A13 NC T NC A10 A11 NC A12 A18 ZZ U VDDQ NC NC NC NC NC VDDQ 3/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS88418/36B-200/180/166/150/133 GS88418/36 BGA Pin Description Pin Location Symbol Type Description P4, N4 A0, A1 I Address field LSBs and Address Counter Preset Inputs A2, A3, A5, A6, B3, B5, C2, C3, C5, C6, G4, R2, R6, T3, T5 An I Address Inputs T4 An I Address Inputs (x36 Version) T2, T6 NC — No Connect (x36 Version) T2, T6 An I Address Inputs (x18 Version) K7, L7, N7, P7, K6, L6, M6, N6, P6 H7, G7, E7, D7, H6, G6, F6, E6, D6 H1, G1, E1, D1, H2, G2, F2, E2, D2 K1, L1, N1, P1, K2, L2, M2, N2, P2 DQA1–DQPA9 DQB1–DQPB9 DQC1–DQPC9 DQD1–DQPD9 I/O Data Input and Output pins (x36 Version) L5, G5, G3, L3 BA, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low ( x36 Version) P7, N6, L6, K7, H6, G7, F6, E7, D6 D1, E2, G2, H1, K2, L1, M2, N1, P2 DQA1–DQA9 DQB1–DQB9 I/O Data Input and Output pins (x18 Version) L5, G3 BA, BB I Byte Write Enable for DQA, DQB Data I/Os; active low ( x18 Version) P6, N7, M6, L7, K6, H7, G6, E6, D7, D2, E1, F2, G1, H2, K1, L2, N2, P1, G5, L3, T4 NC — No Connect (x18 Version) K4 CK I Clock Input Signal; active high E4 E1 I Chip Enable; active low B2 E2 I Chip Enable; active high F4 G I Output Enable; active low T7 ZZ I Sleep Mode control; active high R5 FT I Flow Through or Pipeline mode; active low R3 LBO I Linear Burst Order mode; active low L4 SCD I Single Cycle Deselect/Dual Cycle Deselect Mode Control D4 ZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) B1, C1, R1, T1, L4, B7, C7, U6, R7, J3,J5, U2, U3, U4, U5 NC — No Connect J2, C4, J4, R4, J6 VDD I Core power supply D3, E3, F3, H3, K3, M3, N3, P3, D5, E5, F5, H5, K5, M5, N5, P5 VSS I I/O and Core Ground A1, F1, J1, M1, U1, A7, F7, J7, M7, U7 VDDQ I Output driver power supply BPR2000.002.14 Rev: 1.05 10/2001 4/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS88418/36B-200/180/166/150/133 GS88418/36 Block Diagram Register A0–An D Q A0 A0 D0 Q0 A1 A1 D1 Q1 Counter Load A LBO ADV Memory Array CK ADSC ADSP Q D Register GW BW BA D Q Register D 18 Q BB 18 4 Register D Q D Q Q D D Register Register Q Register BC BD Register D Q Register E1 D Q Register D Q FT G ZZ DCD=0 SCD=1 Power Down Control DQx0–DQx9 Note: Only x18 version shown for simplicity. Rev: 1.05 10/2001 5/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS88418/36B-200/180/166/150/133 Mode Pin Functions Mode Name Pin Name Burst Order Control LBO Output Register Control FT Power Down Control ZZ Single/Dual Cycle Deselect Control SCD FLXDrive Output Impedance Control ZQ State Function L Linear Burst H or NC Interleaved Burst L Flow Through H or NC Pipeline L or NC Active H Standby, IDD = ISB L Dual Cycle Deselect H or NC Single Cycle Deselect L High Drive (Low Impedance) H Low Drive (High Impedance) Note: There are pull-up devices on the LBO, ZQ, SCD, and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above table. Enable / Disable Parity I/O Pins This SRAM allows the user to configure the device to operate in Parity I/O active (x18 or x36) or in Parity I/O inactive (x16 or x32) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Tying PE high deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits generated and read into the ByteSafe parity circuits. Burst Counter Sequences Interleaved Burst Sequence Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 1st address 00 01 10 11 2nd address 01 10 11 00 2nd address 01 00 11 10 3rd address 10 11 00 01 3rd address 10 11 00 01 4th address 11 00 01 10 4th address 11 10 01 00 Note: The burst counter wraps to initial state on the 5th clock. Note: The burst counter wraps to initial state on the 5th clock. BPR 1999.05.18 Rev: 1.05 10/2001 6/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS88418/36B-200/180/166/150/133 Byte Write Truth Table Function GW BW BA BB BC BD Notes Read H H X X X X 1 Read H L H H H H 1 Write byte a H L L H H H 2, 3 Write byte b H L H L H H 2, 3 Write byte c H L H H L H 2, 3, 4 Write byte d H L H H H L 2, 3, 4 Write all bytes H L L L L L 2, 3, 4 Write all bytes L X X X X X Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “C” and “D” are only available on the x36 version. Rev: 1.05 10/2001 7/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS88418/36B-200/180/166/150/133 Synchronous Truth Table Operation Address Used State Diagram Key5 E1 Deselect Cycle, Power Down None X H X X Deselect Cycle, Power Down None X L F Deselect Cycle, Power Down None X L Read Cycle, Begin Burst External R Read Cycle, Begin Burst External Write Cycle, Begin Burst E22 ADV W3 DQ4 L X X High-Z L X X X High-Z F H L X X High-Z L T L X X X Q R L T H L X F Q External W L T H L X T D Read Cycle, Continue Burst Next CR X X H H L F Q Read Cycle, Continue Burst Next CR H X X H L F Q Write Cycle, Continue Burst Next CW X X H H L T D Write Cycle, Continue Burst Next CW H X X H L T D Read Cycle, Suspend Burst Current X X H H H F Q Read Cycle, Suspend Burst Current H X X H H F Q Write Cycle, Suspend Burst Current X X H H H T D Write Cycle, Suspend Burst Current H X X H H T D (x36only) ADSP ADSC Notes: 1. X = Don’t Care, H = High, L = Low. 2. For x36 Version, E = T (True) if E2 = 1; E = F (False) if E2 = 0. 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 5. 6. 7. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.05 10/2001 8/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS88418/36B-200/180/166/150/133 Simplified State Diagram X Deselect W R Simple Burst Synchronous Operation Simple Synchronous Operation W X R R First Write CW First Read CR W X CR R R X Burst Write Burst Read X CR CW CR Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1 and E2) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and assumes ADSP is tied high and ADV is tied low. Rev: 1.05 10/2001 9/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS88418/36B-200/180/166/150/133 Simplified State Diagram with G X Deselect W R W X R R First Write CR CW W CW W X First Read X CR R Burst Write R CR CW W Burst Read X CW CR Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles. 3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.05 10/2001 10/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS88418/36B-200/180/166/150/133 Absolute Maximum Ratings (All voltages reference to VSS) Symbol Description Value Unit VDD Voltage on VDD Pins –0.5 to 4.6 V VDDQ Voltage in VDDQ Pins –0.5 to VDD V VCK Voltage on Clock Input Pin –0.5 to 6 V VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 (≤ 4.6 V max.) V VIN Voltage on Other Input Pins –0.5 to VDD +0.5 (≤ 4.6 V max.) V IIN Input Current on Any Pin +/–20 mA IOUT Output Current on Any I/O Pin +/–20 mA PD Package Power Dissipation 1.5 W TSTG Storage Temperature –55 to 125 oC TBIAS Temperature Under Bias –55 to 125 o C Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Recommended Operating Conditions Parameter Symbol Min. Typ. Max. Unit Notes Supply Voltage VDD 3.135 3.3 3.6 V I/O Supply Voltage VDDQ 2.375 2.5 VDD V 1 Input High Voltage VIH 1.7 — VDD +0.3 V 2 Input Low Voltage VIL –0.3 — 0.8 V 2 Ambient Temperature (Commercial Range Versions) TA 0 25 70 °C 3 Ambient Temperature (Industrial Range Versions) TA –40 25 85 °C 3 Notes: 1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V ≤ VDDQ ≤ 2.375 V (i.e., 2.5 V I/O) and 3.6 V ≤ VDDQ ≤ 3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case. 2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers. 3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 4. Input Under/overshoot voltage must be –2 V > Vi < VDD +2 V with a pulse width not to exceed 20% tKC. Rev: 1.05 10/2001 11/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS88418/36B-200/180/166/150/133 Undershoot Measurement and Timing Overshoot Measurement and Timing VIH 20% tKC VDD + 2.0 V VSS 50% 50% VDD VSS – 2.0 V 20% tKC VIL Capacitance (TA = 25oC, f = 1 MHZ, VDD = 3.3 V) Parameter Symbol Test conditions Typ. Max. Unit Input Capacitance CIN VIN = 0 V 4 5 pF Input/Output Capacitance CI/O VOUT = 0 V 6 7 pF Note: These parameters are sample tested. Package Thermal Characteristics Rating Layer Board Symbol Max Unit Notes Junction to Ambient (at 200 lfm) single RΘJA 40 °C/W 1,2 Junction to Ambient (at 200 lfm) four RΘJA 24 °C/W 1,2 Junction to Case (TOP) — RΘJC 9 °C/W 3 Notes: 1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance. 2. SCMI G-38-87 3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1 Rev: 1.05 10/2001 12/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS88418/36B-200/180/166/150/133 AC Test Conditions Parameter Conditions Input high level 2.3 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level 1.25 V Output reference level 1.25 V Output load Fig. 1& 2 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ 4. Device is deselected as defined by the Truth Table. Output Load 2 Output Load 1 DQ 2.5 V 50Ω 30pF* 225Ω DQ 5pF* VT = 1.25 V 225Ω * Distributed Test Jig Capacitance DC Electrical Characteristics Parameter Symbol Test Conditions Min Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD –1 uA 1 uA ZZ Input Current IINZZ VDD ≥ VIN ≥ VIH 0 V ≤ VIN ≤ VIH –1 uA –1 uA 1 uA 300 uA Mode Pin Input Current IINM VDD ≥ VIN ≥ VIL 0 V ≤ VIN ≤ VIL –300 uA –1 uA 1 uA 1 uA Output Leakage Current IOL Output Disable, VOUT = 0 to VDD –1 uA 1 uA Output High Voltage VOH IOH = –4 mA, VDDQ = 2.375 V 1.7 V — Output High Voltage VOH IOH = –4 mA, VDDQ = 3.135 V 2.4 V — Output Low Voltage VOL IOL = 4 mA — 0.4 V Rev: 1.05 10/2001 13/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS88418/36B-200/180/166/150/133 Operating Currents -200 Parameter Operating Current Deselect Current Rev: 1.05 10/2001 -133 0 -40 0 -40 0 -40 0 -40 to to to to to to to to 70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C Unit IDD Pipeline 450 470 410 430 380 400 350 370 340 360 mA IDD Flow Through 270 290 270 290 250 270 240 250 220 240 mA ISB Pipeline 40 60 40 60 40 60 40 60 40 60 mA ISB Flow Through 40 60 40 60 40 60 40 60 40 60 mA IDD Pipeline 120 140 110 130 100 120 100 120 90 110 mA IDD Flow Through 90 110 80 100 80 100 70 90 70 90 mA Device Selected; All other inputs ≥VIH or ≤ VIL Output open Device Deselected; All other inputs ≥ VIH or ≤ VIL -150 -40 to 85°C Symbol ZZ ≥ VDD – 0.2 V -166 0 to 70°C Test Conditions Standby Current -180 14/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS88418/36B-200/180/166/150/133 AC Electrical Characteristics Pipeline Flow Through Parameter Symbol Clock Cycle Time -200 -180 -166 -150 -133 Unit Min Max Min Max Min Max Min Max Min Max tKC 5.0 — 5.5 — 6.0 — 6.7 — 7.5 — ns Clock to Output Valid tKQ — 3.0 — 3.2 — 3.5 — 3.8 — 4.0 ns Clock to Output Invalid tKQX 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns Clock to Output in Low-Z tLZ 1 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns Clock Cycle Time tKC 10.0 — 10.0 — 10.0 — 10.0 — 10.0 — ns Clock to Output Valid tKQ — 7.5 — 8.0 — 8.5 — 9.0 — 9.5 ns Clock to Output Invalid tKQX 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns Clock to Output in Low-Z tLZ1 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns Clock HIGH Time tKH 1.3 — 1.3 — 1.3 — 1.3 — 1.3 — ns Clock LOW Time tKL 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns Clock to Output in High-Z tHZ1 1.5 3.0 1.5 3.2 1.5 3.5 1.5 3.8 1.5 4.0 ns G to Output Valid tOE — 3.2 — 3.2 — 3.5 — 3.8 — 4.0 ns G to output in Low-Z tOLZ1 0 — 0 — 0 — 0 — 0 — ns G to output in High-Z tOHZ1 — 3.0 — 3.2 — 3.5 — 3.8 — 4.0 ns Setup time tS 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns Hold time tH 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns ZZ setup time tZZS2 5 — 5 — 5 — 5 — 5 — ns ZZ hold time tZZH2 1 — 1 — 1 — 1 — 1 — ns ZZ recovery tZZR 20 — 20 — 20 — 20 — 20 — ns Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.05 10/2001 15/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS88418/36B-200/180/166/150/133 Write Cycle Timing Single Write Burst Write Deselected Write CK tS tH tKH tKL tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated write ADSC tS tH ADV tS tH A0–An ADV must be inactive for ADSP Write WR2 WR1 WR3 tS tH GW tS tH BW tS tH BA–BD WR1 WR1 WR2 tS tH WR3 WR3 E1 masks ADSP E1 tS tH Deselected with E2 E2* E2 only sampled with ADSP or ADSC G tS tH DQA–DQD Hi-Z D1A Write specified byte for 2A and all bytes for 2B, 2C& 2D D2A D2B D2C D2D D3A * Only in 88436B Rev: 1.05 10/2001 16/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS88418/36B-200/180/166/150/133 Flow Through Read Cycle Timing Single Read Burst Read tKL CK tKH tS tH tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated read ADSC tS tH Suspend Burst Suspend Burst ADV tS tH A0–An RD1 RD2 RD3 tS tH tS tH GW BW BA–BD tS tH E1 masks ADSP E1 tS tH E2 only sampled with ADSP or ADSC Deselected with E2 E2* tOE tOHZ G tKQX tOLZ DQA–DQD Q1A Hi-Z Q2A tKQX Q2B Q2c Q2D Q3A tLZ tHZ tKQ Rev: 1.05 10/2001 17/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS88418/36B-200/180/166/150/133 Flow Through Read-Write Cycle Timing Single Write Single Read Burst Read CK tS tH tKC tKH tKL ADSP is blocked by E inactive ADSP tS tH ADSC ADSC initiated read tS tH ADV tS tH A0–An WR1 RD1 tS RD2 tH GW tH tS BW tS tH BA–BD WR1 tS tH E1 masks ADSP E1 tS tH E2 only sampled with ADSP and ADSC E2* tOE tOHZ G tS tKQ DQA–DQD Hi-Z Q1A tH D1A Q2A Q2B Q2c Q2D Q2A Burst wrap around to it’s initial state * Only in 88436B Rev: 1.05 10/2001 18/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS88418/36B-200/180/166/150/133 Pipelined SCD Read Cycle Timing Single Read Burst Read CK tKH tS tH tKL tKC ADSP ADSP is blocked by E inactive tS tH ADSC initiated read ADSC tS tH Suspend Burst ADV tS tH A0–An RD2 RD1 RD3 tS tH tS tH GW BW BWA–BWD tS tH E1 masks ADSP E1 tS tH E2 only sampled with ADSP or ADSC Deselected with E2 E2* tOE G DQA–DQD tOHZ Hi-Z tKQX tKQX tOLZ Q1A Q2A Q2B Q2c Q2D Q3A tLZ tHZ tKQ * Only in 88436B Rev: 1.05 10/2001 19/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS88418/36B-200/180/166/150/133 Pipelined DCD Read-Write Cycle Timing Single Write Burst Read Single Read tKL CK tS tH tKH tKC ADSP is blocked by E1 inactive ADSP tS tH ADSC initiated read ADSC tS tH ADV tS tH A0–An WR1 RD1 RD2 tS tH GW tS tH BW tH tS BA–BD WR1 tS tH E1 masks ADSP E1 tS tH E2 only sampled with ADSP and ADSC E2* tOE tOHZ G DQA–DQD Hi-Z tS tH tKQ Q1A D1a Q2A Q2B Q2c Q2D * Only in 88436B Rev: 1.05 10/2001 20/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS88418/36B-200/180/166/150/133 CK tS tH tKC tKH tKL ADSP ADSC tZZS ZZ ~ ~ ~ ~ ~ ~ ~~ ~ ~ ~ Sleep Mode Timing Diagram tZZH tZZR Snooze Application Tips Single and Dual Cycle Deselect SCD devices force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention. Rev: 1.05 10/2001 21/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS88418/36B-200/180/166/150/133 FLXDrive Output Driver Characteristics 120.0 100.0 Pull Down Drivers 80.0 60.0 40.0 20.0 VDD I Out (mA) I Out 0.0 VOut -20.0 VSS -40.0 -60.0 Pull Up Drivers -80.0 -100.0 -120.0 -140.0 -0.5 Rev: 1.05 10/2001 0 0.5 1 1.5 2 2.5 3.6V PD HD 3.3V PD HD V Out (Pull Down) VDDQ - V Out (Pull Up) 3.1V PD HD 3.6V PD LD 3.1V PU LD 3.3V PU LD 3.6V PU LD 3.1V PU HD 3 3.5 4 3.3V PD LD 3.1V PD LD 3.3V PU HD 3.6V PU HD 22/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS88418/36B-200/180/166/150/133 Package Dimensions—119-Pin BGA A Pin 1 Corner 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U G B P S D N R Bottom View Top View Symbol Description A Width 13.8 14.0 14.2 B Length 21.8 22.0 22.2 C Package Height (including ball) - D Ball Size 0.60 0.75 0.90 E Ball Height 0.50 0.60 0.70 F Package Height (excluding balls) 1.46 1.70 G Width between Balls 1.27 K Package Height above board N Cut-out Package Width 12.00 P Foot Length 19.50 R Width of package between balls 7.62 S Length of package between balls 20.32 T Variance of Ball Height 0.15 C F E K T Package Dimensions—119-Pin BGA Side View Rev: 1.05 10/2001 Min. Nom. Max 0.80 2.40 0.90 1.00 Unit: mm 23/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS88418/36B-200/180/166/150/133 Ordering Information for GSI Synchronous Burst RAMs Org Part Number1 Type Package Speed2 (MHz/ns) TA3 512K x 18 GS88418B-200 S/DCD Pipeline/Flow Through BGA 200/7.5 C 512K x 18 GS88418B-180 S/DCD Pipeline/Flow Through BGA 180/8 C 512K x 18 GS88418B-166 S/DCD Pipeline/Flow Through BGA 166/8.5 C 512K x 18 GS88418B-150 S/DCD Pipeline/Flow Through BGA 150/9 C 512K x 18 GS88418B-133 S/DCD Pipeline/Flow Through BGA 133/9.5 C 256K x 36 GS88436B-200 S/DCD Pipeline/Flow Through BGA 200/7.5 C 256K x 36 GS88436B-180 S/DCD Pipeline/Flow Through BGA 180/8 C 256K x 36 GS88436B-166 S/DCD Pipeline/Flow Through BGA 166/8.5 C 256K x 36 GS88436B-150 S/DCD Pipeline/Flow Through BGA 150/9 C 256K x 36 GS88436B-133 S/DCD Pipeline/Flow Through BGA 133/9.5 C 512K x 18 GS88418B-200I S/DCD Pipeline/Flow Through BGA 200/7.5 I 512K x 18 GS88418B-180I S/DCD Pipeline/Flow Through BGA 180/8 I 512K x 18 GS88418B-166I S/DCD Pipeline/Flow Through BGA 166/8.5 I 512K x 18 GS88418B-150I S/DCD Pipeline/Flow Through BGA 150/9 I 512K x 18 GS88418B-133I S/DCD Pipeline/Flow Through BGA 133/9.5 I 512K x 36 GS88418B-200I S/DCD Pipeline/Flow Through BGA 200/7.5 I 512K x 36 GS88418B-180I S/DCD Pipeline/Flow Through BGA 180/8 I 256K x 36 GS88436B-166I S/DCD Pipeline/Flow Through BGA 166/8.5 I 256K x 36 GS88436B-150I S/DCD Pipeline/Flow Through BGA 150/9 I 256K x 36 GS88436B-133I S/DCD Pipeline/Flow Through BGA 133/9.5 I Status Not Available Not Available Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS88418BT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.05 10/2001 24/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. Preliminary GS88418/36B-200/180/166/150/133 Revision History DS/DateRev. Code: Old; New Types of Changes Page;Revisions;Reason Format or Content • GS8841836B Rev 1.00 First Release 88418_r1; 88418_r1_01 Content • Updated BGA pinout to meet JEDEC standards 88418_r1_01; 88418_r1_02 Format • Updated format to comply with Technical Publications standards 88418_r1_02; 88418_r1_03 Content • Updated Capitance table—removed Input row and changed Output row to I/O 88418_r1_03; 88418_r1_04 Content • Updated speed bin table on page 1 (Added 150 MHz and 133 MHz) • Updated pinouts on pages 2 & 3 (U2–U5 should all be NC) • Removed PE, DP, and QE from Pin Description table on page 4; added R7, J3, J5, U2, U3, U4, U5 to NC row • Added 150 MHz and 133 MHz to Operating Currents table on page 14 • Added 150 MHz and 133 MHz to Electrical Characteristics table on page 15 • Deleted BSR table on page 22 88418_r1_04; 88418_r1_05 Content • Added references to 150 MHz and 133 MHz speed bins to headers and ordering information table Rev: 1.05 10/2001 25/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc.