GX434 Monolithic 4x1 Video Multiplexer DATA SHEET FEATURES CIRCUIT DESCRIPTION • low differential gain: 0.03% typ. at 4.43 MHz The GX434 is a high performance low cost monolithic 4x1 video multiplexer incorporating four bipolar switches with a common output, a 2 to 4 address decoder and fast chip select circuitry. The chip select input allows for multi-chip paralleled operation in routing matrix applications. The chip is selected by applying a logic 0 on the chip select input. • low differential phase: 0.012 deg. typ. at 4.43 MHz • low insertion loss: 0.05 dB max at 100 kHz • low disabled power consumption: 5.2 mW typ. • high off isolation: 110 dB at 10 MHz • all hostile crosstalk @ 5 MHz, 97 dB typ. • bandwidth (-3dB) with 30 pF load, 100 MHz typ. • fast make-before-break switching: 200 ns typ. • TTL and 5 volt CMOS compatible logic inputs Unlike devices using MOS bilateral switching elements, these bipolar circuits represent fully buffered, unilateral transmission paths when selected. This results in extremely high output to input isolation. They also feature fast make-before-break switching action. These features eliminate such problems as switching 'glitches' and output-to-input signal feedthrough. • low cost 14 pin DIP and16 pin SOIC packages • optimised performance for NTSC, PAL and SECAM applications APPLICATIONS Glitch free analog switching for... • High quality video routing The GX434 operates from ± 7 to ± 13.2 volt DC supplies. They are specifically designed for video signal switching which requires extremely low differential phase and gain. Logic inputs are TTL and 5 volt CMOS compatible providing address and chip select functions. When the chip is not selected, the output goes to a high impedance state. PIN CONNECTIONS • A/D input multiplexing TOP VIEW • Sample and hold circuits • TV/ CATV/ monitor switching IN 0 PIN 1 +8V 14 TOP VIEW GND AO IN 1 A1 GND NC CS IN 1 AO GND AVAILABLE PACKAGING IN 0 O/P IN 2 14 pin DIP and 16 pin SOIC (wide) GND IN 3 NC REXT 7 A1 IN 2 CS GND O/P NC R EXT 8 9 IN 1 IN 2 IN 3 A0 A1 -8V PIN CONNECTION 16 PIN SOIC PIN CONNECTION 14 PIN DIP (wide) GX434 IN 0 +8V GND NC FUNCTIONAL BLOCK DIAGRAM 16 IN 3 -8V 8 PIN 1 X TRUTH TABLE X OUTPUT X X 2 TO 4 DECODER LOGIC CHIP SELECT CS CS A1 A0 0 0 0 OUTPUT IN 0 0 0 1 IN 1 0 1 0 IN 2 0 1 1 IN 3 1 X X HI - Z X = DON'T CARE Document No. 510 - 34 - 2 GENNUM CORPORATION P.O. Box 489, Stn A, Burlington, Ontario, Canada L7R 3Y3 Japan Branch: A-302 M i yamae Vi l l age, 2–10–42 M i yamae, Suginami–ku, Tokyo 168, Japan tel. (905) 632-2996 fax: (905) 632-5946 tel. (03) 3334-7700 fax (03) 3247-8839 ABSOLUTE MAXIMUM RATINGS ORDERING INFORMATION Parameter Value & Units Package Type Temperature Range ±13.5V GX434 – – CDB 14 Pin DIP 0° to 70° C 0°C ≤ TA ≤ 70° C GX434 – – CKC 16 Pin SOIC 0° to 70° C -65°C ≤ T S ≤ 150° C GX434 – – CTC Tape 16 Pin SOIC 0° to 70° C Supply Voltage Operating Temperature Range Storage Temperature Range Part Number 260° C Lead Temperature (Soldering, 10 Sec) Analog Input Voltage -4V ≤ VIN ≤ +2.4V Analog Input Current 50µA AVG, 10 mA peak CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE DEVICES EXCEPT AT A STATIC-FREE WORKSTATION -4V ≤ VL ≤ +5.5V Logic Input Voltage +Vcc CS 0.7pF 0.7pF 0.7pF 0.7pF VOUT V IN IN OUT 0.65V 1.2k CS CS #2 3mA #3 #4 1.5pF + 2pF + 1.3 V Common COUT 16pF 600Ω 12pF -V Fig.1 Crosspoint Equivalent Circuit ELECTRICAL CHARACTERISTICS Fig. 2 Disabled Crosspoint Equivalent Circuit (VS = ±8V DC, 0°C < TA < 70°C, CL = 30 pF, RL = 10kΩ unless otherwise shown.) GX434 PARAMETER Supply Voltage SYMBOL SUPPLY Supply current Analog Output Analog Input Bias MIN TYP MAX UNITS 7 8 13.2 V Chip selected (CS=0) - 10.5 11.5 mA Chip not selected (CS=1) - 0.4 0.58 mA Chip selected (CS=0) - 10.2 11.2 mA Chip not selected (CS=1) - 0.25 0.38 mA Extremes before clipping - +2 - occurs. - -1.2 - 22 - µA 0 7 14 mV - +50 +200 ± VS I+ DC CONDITIONS I- VOUT IBIAS V Current STATIC Output Offset Voltage VOS T A = 25°C, 75 Ω resistor on each input to gnd Output Offset Voltage ∆ VOS/∆T Drift REXT = 33.2 kΩ, 1% 510 -34 -2 2 µV/°C ELECTRICAL CHARACTERISTICS continued (VS = ± 8V DC, 0°C < TA < 70°C,CL = 30pF, RL = 10kΩ unless otherwise shown.) GX434 PARAMETER LOGIC SYMBOL CONDITIONS TYP MAX UNITS Crosspoint Selection Turn-On Time tADR-ON Control input to appearance of signal at the output. 130 200 270 ns Crosspoint Selection Turn-Off Time tADR-OFF Control input to disappearance of signal at output. 390 600 800 ns Chip Selection Turn-On Time t CS-ON Control input to appearance of signal at output. 200 300 400 ns Chip Selection Turn-Off Time t CS-OFF Control input to disappearance of signal at output. 460 700 940 ns Logic Input Thresholds V IH 1 2.0 - - V VIL 0 - - 1.1 V Chip selected A0,A1 = 1 - - 5.0 µA Chip selected A0,A1 = 0 - - 0.1 nA Address Input I BIAS(ADR) Bias Current Chip Select Bias IBIAS(CS) CS = 1 - - 1.0 nA CS = 0 - - 30 µA 1V p-p sine or sq. wave at 100 kHz 0.025 0.03 0.04 dB 100 120 - MHz +0.06 dB Current Insertion Loss I.L. Bandwidth (-3 dB) B.W. Gain Spread at 8 MHz Input to Output Signal Delay Matching (chip to chip) DYNAMIC MIN -0.04 ∆tP Input Resistance RIN Input Capacitance CIN T = 25°C, R = 75Ω A S ƒ= 3.579545 MHz - - - ± 0.15 degrees 0°C < T < 70°C, R as A S above, ƒas above. - - ± 0.3 degrees Chip selected (CS = 0) 900 - - kΩ Chip selected (CS = 0) - 2.0 - pF Chip not selected (CS = 1) - 2.4 - pF Output Resistance ROUT Chip selected (CS = 0) - 14 - Ω Output Capacitance COUT Chip not selected (CS = 1) - 15 - pF Differential Gain dg - 0.03 0.05 % - 0.012 0.025 degrees 94 97 - dB 100 110 - dB 360 450 - V/µs 160 200 - V/µs Differential Phase dp All Hostile Crosstalk (see graph) X TALK (AH) Chip Disabled Crosstalk X TALK(CD) (see graph) at 3.579545 MHz VIN = 40 IRE, (Fig. 7) Sweep on 3 inputs 1V p-p 4th input has 10 Ω resistor to gnd. ƒ = 5 MHz (Fig. 6) ƒ = 10 MHz (Fig. 5) +SR Slew Rate VIN = 3V p-p (C L = 0 pF) -SR REXT = 33.2kΩ, 1% 3 510 -34 -2 TYPICAL PERFORMANCE CURVES OF THE GX434 14 0 15 pF -1 10 30 pF 8 50 pF PHASE (DEGREES) GAIN (dB) 12 70 pF 6 Load Capacitance 4 2 0 -2 Load Capacitance -3 0 pF -4 10 pF 27 pF -5 47 pF -6 -7 -2 -8 -4 -9 -6 1 10 100 -10 200 1 FREQUENCY (MHz) 10 100 FREQUENCY (MHz) Phase vs Frequency -40 40 -50 50 ALL HOSTILE CROSSTALK (dB) ALL HOSTILE CROSSTALK (dB) Gain vs Frequency -60 RIN = 75Ω R = 37.5Ω IN -70 RIN = 10Ω -80 -90 -100 -110 0.1 R IN = 75 Ω 60 R IN = 75 Ω RIN = 37.5 Ω 70 R IN = 10 Ω SW1 / SW2 80 SW0 - SW3 90 100 RL = 10 kΩ RL = 10 kΩ 110 1 10 100 0.1 FREQUENCY (MHz) 1 10 100 FREQUENCY (MHz) All Hostile Crosstalk (14 pin DIP) All Hostile Crosstalk (16 pin SOIC) For all graphs, VS = ± 8 V DC and TA = 25°C. The curves shown above represent typical batch sampled results. 510 -34 -2 4 100 CHIP DISABLED CROSSTALK (dB) CHIP DISABLED CROSSTALK (dB) 110 90 80 70 60 50 110 100 Analog signal IN is 40 IRE (286 mV p-p) at 10 MHz 90 80 100 10 +1 0 -1 +3 +2 FREQUENCY (MHz) INPUT BIAS (V) Chip Disabled Crosstalk vs Input Bias (V) DIFFERENTIAL PHASE & GAIN (DEGREES & %) DIFFERENTIAL PHASE & GAIN (DEGREES & %) Chip Disabled Crosstalk vs Frequency +0.05 +0.04 dg % +0.03 +0.02 +0.01 0 dp ° -0.01 -0.02 ƒ = 3.58 MHz Blanking level is -0.03 clamped to V BIAS -0.04 -0.05 -0.8 -0.6 -0.2 -0.4 0 +0.2 +0.4 +0.6 +0.8 INPUT BIAS (V) +0.05 Blanking level 0V DC +0.04 dg % +0.03 +0.02 dp ° +0.01 0 2 1 4 3 5 8 10 3.58 dg/dp vs Input Bias FREQUENCY (MHz) dg/ dp vs Frequency 30 MΩ +1.0 10 MΩ GAIN SPREAD (dB) +0.4 +0.2 0.1 -0.2 -0.4 RIN ON 1 MΩ 3 CIN OFF CIN ON 100 kΩ 2 -0.6 INPUT CAPACITANCE (pF) GAIN SPREAD (dB) +0.6 4 RIN OFF INPUT CAPACITANCE (pF) +0.8 -0.8 -1.0 0.1 1 10 1 10 kΩ 100 -1 FREQUENCY (MHz) 0 +1 +2 +3 INPUT BIAS (V) Input Impedance Normalized Gain Spread CL = 30pF 5 510 -34 -2 0.1 V/div 10 mV/div 1 µs/div 0.5 µs/div Fig. 4 Switching Envelope (crosspoint to crosspoint) Fig.3 Switching Transient (crosspoint to crosspoint) VIN Chip disabled crosstalk = 20 log All hostile crosstalk = 20 log VOUT V OUT VIN RIN V OUT V OUT ENABLED CROSSPOINT V IN RL ≥10 kΩ VIN 37.5 Ω Fig. 6 All Hostile Crosstalk Test Circuit Fig. 5 Chip Disabled Crosstalk Test Circuit 10 µH 10 µH LUMINANCE LEVEL BLANKING LEVEL 220 Ω 8V CONTROL BIT FROM I/O PORT RELAY SWITCH 3.9 kΩ 0.1µF AC COUPLING 150 Ω R.F. SIGNAL SOURCE BUFFER AMP 75 Ω x2 75 Ω 150 Ω RL DUT 75 Ω CL Fig. 7 Differential Phase and Gain Test Circuit DIFFERENTIAL GAIN AND PHASE TEST CIRCUIT The test circuit of Figure 7 allows two DC bias levels, set by the user, to be superimposed on a high frequency signal source. A computer controlled relay selects either the preset blanking or luminance level. One measurement is taken at each level and the change in gain or phase is calculated. This procedure is repeated one hundred times to provide a reasonably large sample. 510 -34 -2 The results are averaged to reduce the standard deviation and therefore improve the accuracy of the measurement. The output from the device under test is AC coupled to a buffer amplifier which allows the buffer to operate at a constant luminance level so that it does not contribute any dg or dp to the measurement. 6 OPTIMISING THE PERFORMANCE OF THE GX434 1. Power Supply Considerations Table 1 shows the effect on differential gain (dg) and differential phase (dp) of various power supply voltages that may be used. A nominal supply voltage of ± 8 volts result in parameter values as shown in the top row of the table. By using other power supply voltage combinations, improvements to these parameters are possible at the sacrifice of increased chip power dissipation. Maximum degradation of the differential gain and phase occurs for the last combination of +12 , -7 volts along with an increase in power dissipation; these voltages are not recommended. Supply Voltage Table 2 shows the general characteristic variations of the GX434 when different combinations of power supply voltages are used. These changes are relative to a circuit using ± 8 volts Vcc. Differential Gain % Differential Phase degrees (Typical) (Typical) ±8 0.030 0.012 +8/ -12 0.010 0.007 ±12 0.010 0.007 +12/ -7 0.084 0.080 Supply Voltage The GX434 does not require input DC biasing to optimise dg or dp nor does it need switching transient suppression at the output. Furthermore, both the analog signal and logic circuits within the chip use one common power supply, making power supply configurations relatively simple and straightforward. Several of the input characteristic graphs on pages 4-5 show that for best operation, the input bias should be 0 volts. The switching transient photographs on page 6 show how small the actual transients are and clearly show the make-beforebreak action of the GX434 video multiplexer switch. 7 Characteristic Changes ± 7 - lower logic thresholds - max logic I/P (≈ 4.5V) - loss of off isolation (≈20 dB) - poorer dg and dp +8/ -12 - slight increase in negative supply current - slight decrease in offset - very similar frequency response - better dg and dp ± 12 - increase in supply current (10%) - increase in offset (≈ 2-4 mV) - very similar frequency response - better dg and dp +12/ -7 - loss in off isolation (≈20 dB) - poorer dg and dp 510 -34 -2 2. Load Resistance Considerations 3. Multi-chip Considerations DIFFERENTIAL PHASE & GAIN (DEGREES & %) The GX434 crosspoint switch is optimised for load resistances equal to or greater than 3 kΩ. Figure 8 shows the effect on the differential gain and phase when the load resistance is varied from 100 Ω to 100 kΩ. Whenever multi-chip bus systems are to be used, the total input and output capacitance must be carefully considered. The input capacitance of an enabled crosspoint (chip selected), is typically only 2 pF and increases slightly to 2.4 pF when the chip is disabled. The total output capacitance when the chip is disabled is approximately 15 pF per chip. 10 Usually the GX434 multiplexer switch is used in a matrix configuration of (n x 1) crosspoints perhaps combined in an (n x m) total routing matrix. This means for example, that four ICs produce a 16 x 1 configuration and have a total output capacitance of 4 x15 pF or 60 pF if all four chips are disabled. For any one enabled crosspoint, the effective load capacitance will be 3 x15 pF or 45 pF. ƒ= 3.58 MHz, 20 IRE BLANKING LEVEL = 0V DC 1.0 0.1 dg dp 0.01 0.001 100 1K 10K In a multi-input/multi-output matrix, it is important to consider the total input bus capacitance. The higher the bus capacitance and the more it varies from the ON to OFF condition, the more difficult it is to maintain a wide frequency response and constant drive from the input buffer. A 16 x 16 matrix using 64 ICs (16 x 4), would have a total input bus capacitance of 16 x 2.4 pF or 40 pF. 100K RL (Ω) Fig. 8 dg/dp vs RL The negative slew rate is dependant upon the output current and load capacitance as shown below. -SR = I + 3 mA I ≤ 8 mA CL The current I is determined from the following equation: I = -VEE R ≥1kΩ R It is possible to increase the negative slew rate (-S.R.) and thus the large signal bandwidth, by adding a resistance from the output to - VEE. This resistor increases the output current above the 3 mA provided by the internal current generator and increases the negative slew rate. The additional slew rate improving resistance must not be less than 1kΩ in order to prevent excessive currents in the output of the device. An adverse effect of utilising this negative slew rate improving resistor, is the increase in differential phase from typically 0.009° to 0.014°. Under these same conditions, the differential gain drops from typically 0.033 % to 0.021 %. X G 4 41 X G 4 41 X G 4 41 X G 4 41 X G 4 41 X G 4 41 X G 4 41 X G 4 41 X G 4 41 X G 4 41 INPUT 5 6 7 8 BUFFERS 1 2 3 4 9 10 11 12 X G 4 41 X G 4 41 +8V IN 0 GND IN 1 GND IN 2 GND IN 3 1 14 2 13 3 12 4 11 5 10 6 9 7 8 n A0 A1 O U TP U T CS B U FF E R S OUTPUT NC 1 R ≥ 1kΩ 2 3 m -8V Fig.9 510 -34 -2 Negative Slew Rate (-SR) Improvement Fig.10 Multi-chip Connections 8 APPLICATIONS INFORMATION The GX434 multiplexer is a very high performance, wideband circuit requiring careful external circuit design. Good power supply regulation and decoupling are necessary to achieve optimum results. The circuit designer must use proper lead dress, component placement and PCB layout as in any high frequency circuit. A typical video routing application is shown in Figure 11. Four ICs are used in a 16 x 1 multiplexer switching circuit. An external address decoder is shown which generates the 16 address and chip enable codes from a binary number. The address inputs to each chip are active high while the chip select inputs are active low. Depending on the application and speed of the logic family used, latches may be required for synchronization where timing and delays are critical. Since the individual crosspoint switching circuits are unidirectional bipolar elements, low crosstalk and high isolation are inherent. The makebefore-break switching characteristics of the GX434 means virtually 'glitch' free switching. Functionally, the video switches are non-inverting, unity gain bipolar switches with buffered inputs requiring DC coupling and 75Ω line terminating resistors when directly driven from 75Ω cable. The output must be buffered to drive 75Ω lines. This is usually accomplished with the addition of an operational amplifier/ buffer which also allows adjustments to be made to the gain, offset and frequency response of the overall circuit. VIDEO INPUTS GX434 SWITCHES 1 2 3 4 5 6 7 V0 V1 V2 V3 75 IN 0 GND IN 1 GND IN 2 GND IN 3 +V 14 13 A0 A 1 12 CS 11 10 OUT REXT 9 -V 8 A0 A1 33K 1% 0.1 75 75 BINARY ADDRESS DECODER +8V 0.1 75 4 5 -8V A2 2 2 6 +8V 0.1 3 1 74HC139 A3 1 ENABLE 7 1 2 3 4 5 6 7 V4 V5 V6 V7 75 16 8 +5V 0.1 33K 1% 0.1 75 75 +V 14 A 0 13 A 1 12 11 CS GND 10 IN 2 OUT GND REXT 9 -V 8 IN 3 IN 0 GND IN 1 +5V 75 -8V 0.1 1 2 3 4 5 6 7 V8 V9 V 10 V 11 75 IN 1 GND IN 2 GND IN 3 V14 V15 75 75 4 Video Out 0.1 CLC 410 (comlinear) DOCUMENT IDENTIFICATION +8V PRODUCT PROPOSAL This data has been compiled for market investigation purposes only, and does not constitute an offer for sale. 14 13 12 11 10 9 8 ADVANCE INFORMATION NOTE This product is in development phase and specifications are subject to change without notice. Gennum reserves the right to remove the product at any time. Listing the product does not constitute an offer for sale. 33K 1% 75 -8V All resistors in ohms, all capacitors in microfarads unless otherwise stated. Fig.11 - 75 6 33K 1% 0.1 75 2 7 -5V 0.1 V 13 100 0.1 + 500 300 -8V 1 IN 0 +V 2 GND A 0 3 A1 IN 1 4 GND CS 5 IN 2 OUT 6 GND R EXT 7 -V IN 3 3 250 CS 11 10 OUT REXT 9 -V 8 75 V 12 330 2-10pF 0.1 75 75 IN 0 GND +8V 14 +V 13 A0 A 1 12 16 x 1 Video Multiplexer Circuit PRELIMINARY DATA SHEET The product is in a preproduction phase and specifications are subject to change without notice. DATA SHEET The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible. Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. ©Copyright August 1989 Gennum Corporation. Revision date: January 1993. All rights reserved. Printed in Canada. 9 510 -34 -2