To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
1.
2.
3.
4.
5.
6.
7.
All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights
of third parties by or arising from the use of Renesas Electronics products or technical information described in this document.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights
of Renesas Electronics or others.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by
you or third parties arising from the use of these circuits, software, or information.
When exporting the products or technology described in this document, you should comply with the applicable export control
laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas
Electronics products or the technology described in this document for any purpose relating to military applications or use by
the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and
technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited
under any applicable domestic or foreign laws or regulations.
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics
does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages
incurred by you resulting from errors in or omissions from the information included herein.
Renesas Electronics products are classified according to the following three quality grades: “Standard”, “High Quality”, and
“Specific”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as
indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular
application. You may not use any Renesas Electronics product for any application categorized as “Specific” without the prior
written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for
which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way
liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an
application categorized as “Specific” or for which the product is not intended where you have failed to obtain the prior written
consent of Renesas Electronics. The quality grade of each Renesas Electronics product is “Standard” unless otherwise
expressly specified in a Renesas Electronics data sheets or data books, etc.
“Standard”:
8.
9.
10.
11.
12.
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots.
“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support.
“Specific”:
Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or
systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare
intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or
damages arising out of the use of Renesas Electronics products beyond such specified ranges.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have
specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,
Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to
guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a
Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire
control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because
the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system
manufactured by you.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental
compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable
laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS
Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with
applicable laws and regulations.
This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas
Electronics.
Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this
document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
The revision list can be viewed directly by clicking the title page.
The revision list summarizes the locations of revisions and additions.
Details should always be checked by referring to the relevant text.
H8/38024, H8/38024S,
H8/38024R, H8/38124 Group
Hardware Manual
Renesas 8-Bit Single-Chip Microcomputer
H8 Family/H8/300L Super Low Power Series
H8/38024 Group
H8/38024
H8/38023
H8/38022
H8/38021
H8/38020
H8/38024S Group H8/38024S
H8/38022S
H8/38021S
H8/38020S
H8/38000S
H8/38024R Group H8/38024R
H8/38124 Group
H8/38124
H8/38123
H8/38122
H8/38121
H8/38120
Rev.8.00 2010.03
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
Rev. 8.00 Mar. 09, 2010 Page ii of xx
REJ09B0042-0800
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in
the manual.
⎯ The input pins of CMOS products are generally in the high-impedance state. In
operation with an unused pin in the open-circuit state, extra electromagnetic noise is
induced in the vicinity of LSI, an associated shoot-through current flows internally, and
malfunctions may occur due to the false recognition of the pin state as an input signal.
Unused pins should be handled as described under Handling of Unused Pins in the
manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
⎯ The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the
states of pins are not guaranteed from the moment when power is supplied until the
reset process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on
reset function are not guaranteed from the moment when power is supplied until the
power reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
⎯ The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has
become stable. When switching the clock signal during program execution, wait until the
target clock signal has stabilized.
⎯ When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization
of the clock signal. Moreover, when switching to a clock signal produced with an
external resonator (or by an external oscillator) while program execution is in progress,
wait until the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different type number,
confirm that the change will not lead to problems.
⎯ The characteristics of MPU/MCU in the same group but having different type numbers
may differ because of the differences in internal memory capacity and layout pattern.
When changing to products of different type numbers, implement a system-evaluation
test for each of the products.
Rev. 8.00 Mar. 09, 2010 Page iii of xx
REJ09B0042-0800
Configuration of This Manual
This manual comprises the following items:
1. General Precautions in the Handling of MPU/MCU Products
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
•
CPU and System-Control Modules
•
On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
•
Product Codes, Package Dimensions, etc.
10. Main Revisions for This Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
Rev. 8.00 Mar. 09, 2010 Page iv of xx
REJ09B0042-0800
Preface
The H8/38024 Group is a single-chip microcomputer built around the high-speed H8/300L CPU
and equipped with peripheral system functions on-chip. The H8/38024 Group incorporates
peripheral functions including ROM, RAM, timer, serial communications interface (SCI), 10-bit
PWM, A/D converter, LCD controller/driver, and I/O ports. It is a microcomputer allowing the
implementation of a sophisticated control system. Versions are available with types of internal
ROM: flash memory (F-ZTAT™*1) and PROM (ZTAT™*2). This makes it possible to design
application products with a great deal of specification fluidity, and allows for rapid and flexible
response to contingencies arising between the initial stages of production and full-scale
production.
Below is a table listing the product specifications for each group.
Notes: 1. F-ZTAT is a trademark of Renesas Technology Corp.
2. ZTAT is a trademark of Renesas Technology Corp.
Rev. 8.00 Mar. 09, 2010 Page v of xx
REJ09B0042-0800
Specifications
Memory
Operating
voltage and
operating
frequency
I/O ports
Timers
ZTAT
Mask
Flash
32 Kbytes
8 Kbytes
to
32 Kbytes
32 Kbytes
RAM
1 Kbyte
512 bytes
or
1 Kbyte
1 Kbyte
1 Kbyte
512 bytes
or
1 Kbyte
1 Kbyte
512 bytes
or
1 Kbyte
4.5 to 5.5 V
16 MHz
16 MHz
—
—
—
20 MHz
20 MHz
2.7 to 5.5 V
10 MHz
10 MHz
—
—
—
20 MHz
20 MHz
1.8 to 5.5 V
4 MHz
4 MHz
—
—
—
—
—
2.7 to 3.6 V
—
—
10 MHz
10 MHz
10 MHz
—
—
1.8 to 3.6 V
—
—
—
—
4 MHz
—
—
Input only
9
9
9
9
9
9
9
Output only
6
6
6
6
6
6
6
I/O
51
51
51
51
51
50
50
Clock (timer A)
1
1
1
1
1
1
1
Reload (timer C)
1
1
1
1
1
1
1
Compare (timer F)
1
1
1
1
1
1
1
Mask
Flash
Mask
32 Kbytes 8 Kbytes to 16 Kbytes/ 8 Kbytes
32 Kbytes 32 Kbytes
to
32 Kbytes
Capture (timer G)
1
1
1
1
1
1
1
AEC
1
1
1
1
1
1
1
WDT
1
1
1
1
1
1
1
UART/Synchronous
A-D (resolution × input channels)
LCD
Flash
H8/38124 Group
ROM
Please
use R
version.
WDT (discrete)
SCI
H8/38024R H8/38024S
Group
Group
H8/38024 Group
Item
seg
com
1
1
10 × 8
10 × 8
32
32
32
4
4
4
13(8)
13(8)
POR (power-on reset)
—
—
LVD (low-voltage detection circuit)
—
—
FP-80A
FP-80A
External interrupt (internal
wakeup)
Package
1
10 × 8
1
1
1
1
10 × 8
10 × 8
10 × 8
10 × 8
32
32
32
32
4
4
4
4
13(8)
13(8)
13(8)
13(8)
—
—
—
1
1
—
—
—
1
1
FP-80A
FP-80A
FP-80A
FP-80A
TFP-80C
TFP-80C
13(8)
FP-80A
FP-80B
FP-80B
FP-80B
FP-80B
TFP-80C
TFP-80C
TFP-80C
TFP-80C
TFP-80C
TLP85V
TLP85V
TLP85V
Chip
Chip
Chip
Chip
Operating temperature
Rev. 8.00 Mar. 09, 2010 Page vi of xx
REJ09B0042-0800
Standard specifications: –20 to 75°C, WTR: –40 to 85°C
Target Readers: This manual is designed for use by people who design application systems using
the H8/38024 Group, H8/38024S Group, H8/38024R Group, and H8/38124 Group.
To use this manual, basic knowledge of electric circuits, logic circuits and microcomputers is
required.
Purpose: This manual provides the information of the hardware functions and electrical
characteristics of the H8/38024 Group, H8/38024S Group, H8/38024R Group, and H8/38124
Group. The H8/300L Series Software Manual contains detailed information of executable
instructions. Please read the Software Manual together with this manual.
How to Use the Book:
• To understand general functions
→ Read the manual from the beginning.
The manual explains the CPU, system control functions, peripheral functions and electrical
characteristics in that order.
• To understanding CPU functions
→ Refer to the separate H8/300L Series Software Manual.
Explanatory Note: Bit sequence: upper bit at left, and lower bit at right
List of Related Documents: The latest documents are available on our Web site. Please make
sure that you have the latest version.
(http://www.renesas.com/)
• User Manual for H8/38024 Group, H8/38024S Group, H8/38024R Group, and H8/38124
Group
Name of Document
Document No.
H8/38024 Group, H8/38024S Group, H8/38024R Group,
H8/38124 Group Hardware Manual
This manual
H8/300L Series Software Manual
REJ09B0214
• User's Manual for Development Tools
Name of Document
Document No.
H8S, H8/300 Series, C/C++ Compiler, Assembler, Optimizing Linkage
Editor User’s Manual
REJ10B2039
H8S, H8/300 Series Simulator/Debugger User’s Manual
REJ10B0211
High-Performance Embedded Workshop User’s Manual
REJ10J2037
Rev. 8.00 Mar. 09, 2010 Page vii of xx
REJ09B0042-0800
• Application Note
Name of Document
Document No.
H8S, H8/300 Series C/C++ Compiler Package Application Note
REJ05B0464
Notes: The following limitations apply to H8/38024, H8/38024R, and H8/38124 programming
and debugging when the on-chip emulator is used.
1. Pin 95 is not available because it is used exclusively by the on-chip emulator.
2. Pins 33, 34, and 35 are unavailable for use. In order to use these pins additional
hardware must be mounted on the user board.
3. The address range H'7000 to H'7FFF is used by the on-chip emulator and is unavailable
to the user.
4. The address range H'F780 to H'FB7F must not be accessed under any circumstances.
5. When the on-chip emulator is being used, pin 95 is I/O, pins 33 and 34 are input, and
pin 35 is output.
6. When using the on-chip emulator, pins OSC1 and OSC2 should be connected to an
oscillator, or an external clock should be supplied to pin OSC1, even if the on-chip
oscillator of the H8/38124 Group is selected.
All trademarks and registered trademarks are the property of their respective owners.
Rev. 8.00 Mar. 09, 2010 Page viii of xx
REJ09B0042-0800
Contents
Section 1 Overview................................................................................................1
1.1
1.2
1.3
Overview................................................................................................................................ 1
Internal Block Diagram.......................................................................................................... 7
Pin Arrangement and Functions............................................................................................. 9
1.3.1 Pin Arrangement ....................................................................................................... 9
1.3.2 Pin Functions .......................................................................................................... 19
Section 2 CPU......................................................................................................25
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Overview.............................................................................................................................. 25
2.1.1 Features................................................................................................................... 25
2.1.2 Address Space......................................................................................................... 26
2.1.3 Register Configuration............................................................................................ 26
Register Descriptions ........................................................................................................... 27
2.2.1 General Registers .................................................................................................... 27
2.2.2 Control Registers .................................................................................................... 27
2.2.3 Initial Register Values............................................................................................. 29
Data Formats ........................................................................................................................ 29
2.3.1 Data Formats in General Registers ......................................................................... 30
2.3.2 Memory Data Formats ............................................................................................ 31
Addressing Modes................................................................................................................ 32
2.4.1 Addressing Modes .................................................................................................. 32
2.4.2 Effective Address Calculation ................................................................................ 34
Instruction Set ...................................................................................................................... 38
2.5.1 Data Transfer Instructions....................................................................................... 40
2.5.2 Arithmetic Operations............................................................................................. 42
2.5.3 Logic Operations..................................................................................................... 43
2.5.4 Shift Operations ...................................................................................................... 44
2.5.5 Bit Manipulations.................................................................................................... 46
2.5.6 Branching Instructions ............................................................................................ 50
2.5.7 System Control Instructions.................................................................................... 52
2.5.8 Block Data Transfer Instruction.............................................................................. 53
Basic Operational Timing .................................................................................................... 55
2.6.1 Access to On-Chip Memory (RAM, ROM)............................................................ 55
2.6.2 Access to On-Chip Peripheral Modules .................................................................. 56
CPU States ........................................................................................................................... 57
2.7.1 Overview................................................................................................................. 57
2.7.2 Program Execution State......................................................................................... 59
Rev. 8.00 Mar. 09, 2010 Page ix of xx
REJ09B0042-0800
2.8
2.9
2.7.3 Program Halt State.................................................................................................. 59
2.7.4 Exception-Handling State ....................................................................................... 59
Memory Map ....................................................................................................................... 60
2.8.1 Memory Map .......................................................................................................... 60
Application Notes ................................................................................................................ 66
2.9.1 Notes on Data Access ............................................................................................. 66
2.9.2 Notes on Bit Manipulation...................................................................................... 68
2.9.3 Notes on Use of the EEPMOV Instruction ............................................................. 74
Section 3 Exception Handling .............................................................................75
3.1
3.2
3.3
3.4
Overview.............................................................................................................................. 75
Reset..................................................................................................................................... 75
3.2.1 Overview................................................................................................................. 75
3.2.2 Reset Sequence ....................................................................................................... 75
3.2.3 Interrupt Immediately after Reset ........................................................................... 76
Interrupts .............................................................................................................................. 77
3.3.1 Overview................................................................................................................. 77
3.3.2 Interrupt Control Registers...................................................................................... 79
3.3.3 External Interrupts .................................................................................................. 90
3.3.4 Internal Interrupts.................................................................................................... 91
3.3.5 Interrupt Operations ................................................................................................ 92
3.3.6 Interrupt Response Time......................................................................................... 97
Application Notes ................................................................................................................ 98
3.4.1 Notes on Stack Area Use ........................................................................................ 98
3.4.2 Notes on Rewriting Port Mode Registers................................................................ 99
3.4.3 Method for Clearing Interrupt Request Flags ....................................................... 101
Section 4 Clock Pulse Generators .....................................................................103
4.1
4.2
4.3
4.4
4.5
Overview............................................................................................................................ 103
4.1.1 Block Diagram ...................................................................................................... 103
4.1.2 System Clock and Subclock.................................................................................. 104
4.1.3 Register Descriptions ............................................................................................ 105
System Clock Generator .................................................................................................... 106
Subclock Generator............................................................................................................ 111
Prescalers ........................................................................................................................... 113
Note on Oscillators............................................................................................................. 115
4.5.1 Definition of Oscillation Stabilization Wait Time ................................................ 116
4.5.2 Notes on Use of Crystal Oscillator Element (Excluding Ceramic Oscillator
Element)................................................................................................................ 118
4.5.3 Note on Use of HD64F38024 ............................................................................... 119
Rev. 8.00 Mar. 09, 2010 Page x of xx
REJ09B0042-0800
4.6
Notes on H8/38124 Group ................................................................................................. 119
Section 5 Power-Down Modes ..........................................................................121
5.1
Overview............................................................................................................................ 121
5.1.1 System Control Registers...................................................................................... 124
5.2 Sleep Mode ........................................................................................................................ 128
5.2.1 Transition to Sleep Mode...................................................................................... 128
5.2.2 Clearing Sleep Mode............................................................................................. 129
5.2.3 Clock Frequency in Sleep (Medium-Speed) Mode............................................... 129
5.3 Standby Mode .................................................................................................................... 130
5.3.1 Transition to Standby Mode.................................................................................. 130
5.3.2 Clearing Standby Mode ........................................................................................ 130
5.3.3 Oscillator Stabilization Time after Standby Mode Is Cleared............................... 130
5.3.4 Standby Mode Transition and Pin States .............................................................. 132
5.3.5 Notes on External Input Signal Changes before/after Standby Mode................... 133
5.4 Watch Mode....................................................................................................................... 134
5.4.1 Transition to Watch Mode .................................................................................... 134
5.4.2 Clearing Watch Mode ........................................................................................... 135
5.4.3 Oscillator StabilizationTime after Watch Mode Is Cleared .................................. 135
5.4.4 Notes on External Input Signal Changes before/after Watch Mode ..................... 135
5.5 Subsleep Mode................................................................................................................... 136
5.5.1 Transition to Subsleep Mode ................................................................................ 136
5.5.2 Clearing Subsleep Mode ....................................................................................... 136
5.6 Subactive Mode ................................................................................................................. 137
5.6.1 Transition to Subactive Mode ............................................................................... 137
5.6.2 Clearing Subactive Mode...................................................................................... 137
5.6.3 Operating Frequency in Subactive Mode.............................................................. 137
5.7 Active (Medium-Speed) Mode .......................................................................................... 138
5.7.1 Transition to Active (Medium-Speed) Mode ........................................................ 138
5.7.2 Clearing Active (Medium-Speed) Mode............................................................... 138
5.7.3 Operating Frequency in Active (Medium-Speed) Mode....................................... 138
5.8 Direct Transfer ................................................................................................................... 139
5.8.1 Overview of Direct Transfer ................................................................................. 139
5.8.2 Direct Transition Times ........................................................................................ 140
5.8.3 Notes on External Input Signal Changes before/after Direct Transition............... 142
5.9 Module Standby Mode....................................................................................................... 143
5.9.1 Setting Module Standby Mode ............................................................................. 143
5.9.2 Clearing Module Standby Mode ........................................................................... 143
5.10 Usage Note......................................................................................................................... 144
5.10.1 Contention Between Module Standby and Interrupts ........................................... 144
Rev. 8.00 Mar. 09, 2010 Page xi of xx
REJ09B0042-0800
Section 6 ROM ..................................................................................................145
6.1
Overview............................................................................................................................ 145
6.1.1 Block Diagram ...................................................................................................... 145
6.2 H8/38024 PROM Mode ..................................................................................................... 146
6.2.1 Setting to PROM Mode ........................................................................................ 146
6.2.2 Socket Adapter Pin Arrangement and Memory Map............................................ 146
6.3 H8/38024 Programming..................................................................................................... 149
6.3.1 Writing and Verifying........................................................................................... 149
6.3.2 Programming Precautions ..................................................................................... 154
6.4 Reliability of Programmed Data ........................................................................................ 155
6.5 Flash Memory Overview ................................................................................................... 156
6.5.1 Features................................................................................................................. 156
6.5.2 Block Diagram ...................................................................................................... 157
6.5.3 Block Configuration.............................................................................................. 158
6.5.4 Register Configuration.......................................................................................... 160
6.6 Descriptions of Registers of the Flash Memory................................................................. 160
6.6.1 Flash Memory Control Register 1 (FLMCR1)...................................................... 160
6.6.2 Flash Memory Control Register 2 (FLMCR2)...................................................... 163
6.6.3 Erase Block Register (EBR) ................................................................................. 164
6.6.4 Flash Memory Power Control Register (FLPWCR) ............................................. 164
6.6.5 Flash Memory Enable Register (FENR) ............................................................... 165
6.7 On-Board Programming Modes......................................................................................... 166
6.7.1 Boot Mode ............................................................................................................ 166
6.7.2 Programming/Erasing in User Program Mode...................................................... 169
6.7.3 Notes on On-Board Programming ........................................................................ 170
6.8 Flash Memory Programming/Erasing ................................................................................ 170
6.8.1 Program/Program-Verify ...................................................................................... 170
6.8.2 Erase/Erase-Verify................................................................................................ 174
6.8.3 Interrupt Handling when Programming/Erasing Flash Memory........................... 174
6.9 Program/Erase Protection .................................................................................................. 176
6.9.1 Hardware Protection ............................................................................................. 176
6.9.2 Software Protection............................................................................................... 176
6.9.3 Error Protection..................................................................................................... 177
6.10 Programmer Mode ............................................................................................................. 177
6.10.1 Socket Adapter...................................................................................................... 177
6.10.2 Programmer Mode Commands ............................................................................. 178
6.10.3 Memory Read Mode ............................................................................................. 181
6.10.4 Auto-Program Mode ............................................................................................. 184
6.10.5 Auto-Erase Mode .................................................................................................. 186
6.10.6 Status Read Mode ................................................................................................. 187
Rev. 8.00 Mar. 09, 2010 Page xii of xx
REJ09B0042-0800
6.10.7 Status Polling ........................................................................................................ 189
6.10.8 Programmer Mode Transition Time...................................................................... 190
6.10.9 Notes on Memory Programming........................................................................... 190
6.11 Power-Down States for Flash Memory.............................................................................. 191
Section 7 RAM ..................................................................................................193
7.1
Overview............................................................................................................................ 193
7.1.1 Block Diagram ...................................................................................................... 193
Section 8 I/O Ports .............................................................................................195
8.1
8.2
8.3
8.4
8.5
8.6
Overview............................................................................................................................ 195
Port 1.................................................................................................................................. 197
8.2.1 Overview............................................................................................................... 197
8.2.2 Register Configuration and Description................................................................ 197
8.2.3 Pin Functions ........................................................................................................ 202
8.2.4 Pin States............................................................................................................... 203
8.2.5 MOS Input Pull-Up............................................................................................... 203
Port 3.................................................................................................................................. 204
8.3.1 Overview............................................................................................................... 204
8.3.2 Register Configuration and Description................................................................ 204
8.3.3 Pin Functions ........................................................................................................ 209
8.3.4 Pin States............................................................................................................... 210
8.3.5 MOS Input Pull-Up............................................................................................... 210
Port 4.................................................................................................................................. 211
8.4.1 Overview............................................................................................................... 211
8.4.2 Register Configuration and Description................................................................ 211
8.4.3 Pin Functions ........................................................................................................ 213
8.4.4 Pin States............................................................................................................... 214
Port 5.................................................................................................................................. 215
8.5.1 Overview............................................................................................................... 215
8.5.2 Register Configuration and Description................................................................ 215
8.5.3 Pin Functions ........................................................................................................ 218
8.5.4 Pin States............................................................................................................... 219
8.5.5 MOS Input Pull-Up............................................................................................... 219
Port 6.................................................................................................................................. 220
8.6.1 Overview............................................................................................................... 220
8.6.2 Register Configuration and Description................................................................ 220
8.6.3 Pin Functions ........................................................................................................ 222
8.6.4 Pin States............................................................................................................... 223
8.6.5 MOS Input Pull-Up............................................................................................... 223
Rev. 8.00 Mar. 09, 2010 Page xiii of xx
REJ09B0042-0800
8.7
8.8
8.9
8.10
8.11
8.12
8.13
Port 7.................................................................................................................................. 224
8.7.1 Overview............................................................................................................... 224
8.7.2 Register Configuration and Description................................................................ 224
8.7.3 Pin Functions ........................................................................................................ 226
8.7.4 Pin States............................................................................................................... 226
Port 8.................................................................................................................................. 227
8.8.1 Overview............................................................................................................... 227
8.8.2 Register Configuration and Description................................................................ 227
8.8.3 Pin Functions ........................................................................................................ 229
8.8.4 Pin States............................................................................................................... 229
Port 9.................................................................................................................................. 230
8.9.1 Overview............................................................................................................... 230
8.9.2 Register Configuration and Description................................................................ 231
8.9.3 Pin Functions ........................................................................................................ 234
8.9.4 Pin States............................................................................................................... 234
Port A................................................................................................................................. 235
8.10.1 Overview............................................................................................................... 235
8.10.2 Register Configuration and Description................................................................ 235
8.10.3 Pin Functions ........................................................................................................ 237
8.10.4 Pin States............................................................................................................... 238
Port B ................................................................................................................................. 239
8.11.1 Overview............................................................................................................... 239
8.11.2 Register Configuration and Description................................................................ 239
8.11.3 Pin Functions ........................................................................................................ 241
Input/Output Data Inversion Function ............................................................................... 242
8.12.1 Overview............................................................................................................... 242
8.12.2 Register Configuration and Descriptions .............................................................. 243
8.12.3 Note on Modification of Serial Port Control Register .......................................... 244
Application Note ................................................................................................................ 245
8.13.1 The Management of the Un-Use Terminal ........................................................... 245
Section 9 Timers................................................................................................247
9.1
9.2
9.3
Overview............................................................................................................................ 247
Timer A.............................................................................................................................. 248
9.2.1 Overview............................................................................................................... 248
9.2.2 Register Descriptions ............................................................................................ 250
9.2.3 Timer Operation.................................................................................................... 253
9.2.4 Timer A Operation States ..................................................................................... 254
9.2.5 Application Note................................................................................................... 254
Timer C .............................................................................................................................. 255
Rev. 8.00 Mar. 09, 2010 Page xiv of xx
REJ09B0042-0800
9.4
9.5
9.6
9.7
9.3.1 Overview............................................................................................................... 255
9.3.2 Register Descriptions ............................................................................................ 257
9.3.3 Timer Operation.................................................................................................... 260
9.3.4 Timer C Operation States...................................................................................... 262
Timer F .............................................................................................................................. 263
9.4.1 Overview............................................................................................................... 263
9.4.2 Register Descriptions ............................................................................................ 266
9.4.3 CPU Interface ....................................................................................................... 273
9.4.4 Operation .............................................................................................................. 276
9.4.5 Application Notes ................................................................................................. 279
Timer G.............................................................................................................................. 283
9.5.1 Overview............................................................................................................... 283
9.5.2 Register Descriptions ............................................................................................ 285
9.5.3 Noise Canceler ...................................................................................................... 290
9.5.4 Operation .............................................................................................................. 292
9.5.5 Application Notes ................................................................................................. 297
9.5.6 Timer G Application Example .............................................................................. 301
Watchdog Timer ................................................................................................................ 302
9.6.1 Overview............................................................................................................... 302
9.6.2 Register Descriptions ............................................................................................ 305
9.6.3 Timer Operation.................................................................................................... 311
9.6.4 Watchdog Timer Operation States ........................................................................ 312
Asynchronous Event Counter (AEC) ................................................................................. 313
9.7.1 Overview............................................................................................................... 313
9.7.2 Register Configurations ........................................................................................ 316
9.7.3 Operation .............................................................................................................. 325
9.7.4 Asynchronous Event Counter Operation Modes................................................... 330
9.7.5 Application Notes ................................................................................................. 330
Section 10 Serial Communication Interface ......................................................333
10.1 Overview............................................................................................................................ 333
10.1.1 Features................................................................................................................. 333
10.1.2 Block Diagram ...................................................................................................... 335
10.1.3 Pin Configuration.................................................................................................. 336
10.1.4 Register Configuration.......................................................................................... 336
10.2 Register Descriptions ......................................................................................................... 337
10.2.1 Receive Shift Register (RSR) ............................................................................... 337
10.2.2 Receive Data Register (RDR) ............................................................................... 337
10.2.3 Transmit Shift Register (TSR) .............................................................................. 338
10.2.4 Transmit Data Register (TDR).............................................................................. 338
Rev. 8.00 Mar. 09, 2010 Page xv of xx
REJ09B0042-0800
10.2.5 Serial Mode Register (SMR)................................................................................. 339
10.2.6 Serial Control Register 3 (SCR3).......................................................................... 342
10.2.7 Serial Status Register (SSR) ................................................................................. 346
10.2.8 Bit Rate Register (BRR) ....................................................................................... 350
10.2.9 Clock stop register 1 (CKSTPR1)......................................................................... 356
10.2.10 Serial Port Control Register (SPCR)..................................................................... 356
10.3 Operation............................................................................................................................ 358
10.3.1 Overview............................................................................................................... 358
10.3.2 Operation in Asynchronous Mode ........................................................................ 362
10.3.3 Operation in Synchronous Mode .......................................................................... 371
10.4 Interrupts ............................................................................................................................ 379
10.5 Application Notes .............................................................................................................. 380
Section 11 10-Bit PWM ....................................................................................385
11.1 Overview............................................................................................................................ 385
11.1.1 Features................................................................................................................. 385
11.1.2 Block Diagram ...................................................................................................... 386
11.1.3 Pin Configuration.................................................................................................. 387
11.1.4 Register Configuration.......................................................................................... 388
11.2 Register Descriptions ......................................................................................................... 388
11.2.1 PWM Control Register (PWCRm)........................................................................ 388
11.2.2 PWM Data Registers U and L (PWDRUm, PWDRLm)....................................... 390
11.2.3 Clock Stop Register 2 (CKSTPR2)....................................................................... 391
11.3 Operation............................................................................................................................ 392
11.3.1 Operation .............................................................................................................. 392
11.3.2 PWM Operation Modes ........................................................................................ 393
Section 12 A/D Converter .................................................................................395
12.1 Overview............................................................................................................................ 395
12.1.1 Features................................................................................................................. 395
12.1.2 Block Diagram ...................................................................................................... 396
12.1.3 Pin Configuration.................................................................................................. 397
12.1.4 Register Configuration.......................................................................................... 397
12.2 Register Descriptions ......................................................................................................... 398
12.2.1 A/D Result Registers (ADRRH, ADRRL)............................................................ 398
12.2.2 A/D Mode Register (AMR) .................................................................................. 398
12.2.3 A/D Start Register (ADSR)................................................................................... 400
12.2.4 Clock Stop Register 1 (CKSTPR1)....................................................................... 401
12.3 Operation............................................................................................................................ 402
12.3.1 A/D Conversion Operation ................................................................................... 402
Rev. 8.00 Mar. 09, 2010 Page xvi of xx
REJ09B0042-0800
12.4
12.5
12.6
12.7
12.3.2 Start of A/D Conversion by External Trigger Input.............................................. 402
12.3.3 A/D Converter Operation Modes .......................................................................... 403
Interrupts ............................................................................................................................ 403
Typical Use ........................................................................................................................ 403
A/D Conversion Accuracy Definitions .............................................................................. 407
Application Notes .............................................................................................................. 409
12.7.1 Permissible Signal Source Impedance .................................................................. 409
12.7.2 Influences on Absolute Precision.......................................................................... 409
12.7.3 Additional Usage Notes ........................................................................................ 410
Section 13 LCD Controller/Driver.....................................................................411
13.1 Overview............................................................................................................................ 411
13.1.1 Features................................................................................................................. 411
13.1.2 Block Diagram ...................................................................................................... 412
13.1.3 Pin Configuration.................................................................................................. 414
13.1.4 Register Configuration.......................................................................................... 414
13.2 Register Descriptions ......................................................................................................... 415
13.2.1 LCD Port Control Register (LPCR)...................................................................... 415
13.2.2 LCD Control Register (LCR)................................................................................ 417
13.2.3 LCD Control Register 2 (LCR2)........................................................................... 419
13.2.4 Clock Stop Register 2 (CKSTPR2)....................................................................... 421
13.3 Operation............................................................................................................................ 422
13.3.1 Settings up to LCD Display .................................................................................. 422
13.3.2 Relationship between LCD RAM and Display ..................................................... 424
13.3.3 Operation in Power-Down Modes ........................................................................ 429
13.3.4 Boosting the LCD Drive Power Supply................................................................ 430
Section 14 Power-On Reset and Low-Voltage Detection Circuits
(H8/38124 Group Only)...................................................................431
14.1 Overview............................................................................................................................ 431
14.1.1 Features................................................................................................................. 431
14.1.2 Block Diagram ...................................................................................................... 432
14.1.3 Pin Description ..................................................................................................... 433
14.1.4 Register Descriptions ............................................................................................ 433
14.2 Individual Register Descriptions........................................................................................ 433
14.2.1 Low-Voltage Detection Control Register (LVDCR) ............................................ 433
14.2.2 Low-Voltage Detection Status Register (LVDSR) ............................................... 436
14.2.3 Low-Voltage Detection Counter (LVDCNT) ....................................................... 438
14.2.4 Clock Stop Register 2 (CKSTPR2)....................................................................... 438
14.3 Operation............................................................................................................................ 439
Rev. 8.00 Mar. 09, 2010 Page xvii of xx
REJ09B0042-0800
14.3.1 Power-On Reset Circuit ........................................................................................ 439
14.3.2 Low-Voltage Detection Circuit............................................................................. 440
Section 15 Power Supply Circuit (H8/38124 Group Only)...............................447
15.1 When Using Internal Power Supply Step-Down Circuit.................................................... 447
15.2 When Not Using Internal Power Supply Step-Down Circuit............................................. 448
Section 16 Electrical Characteristics .................................................................449
16.1 H8/38024 Group ZTAT Version and Mask ROM Version Absolute Maximum
Ratings ............................................................................................................................... 449
16.2 H8/38024 Group ZTAT Version and Mask ROM Version Electrical Characteristics....... 450
16.2.1 Power Supply Voltage and Operating Range........................................................ 450
16.2.2 DC Characteristics ................................................................................................ 453
16.2.3 AC Characteristics ................................................................................................ 459
16.2.4 A/D Converter Characteristics .............................................................................. 462
16.2.5 LCD Characteristics.............................................................................................. 464
16.3 H8/38024 Group F-ZTAT Version and H8/38024R Group F-ZTAT Version Absolute
Maximum Ratings.............................................................................................................. 465
16.4 H8/38024 Group F-ZTAT Version and H8/38024R Group F-ZTAT Version Electrical
Characteristics.................................................................................................................... 466
16.4.1 Power Supply Voltage and Operating Range........................................................ 466
16.4.2 DC Characteristics ................................................................................................ 469
16.4.3 AC Characteristics ................................................................................................ 476
16.4.4 A/D Converter Characteristics .............................................................................. 479
16.4.5 LCD Characteristics.............................................................................................. 480
16.4.6 Flash Memory Characteristics .............................................................................. 481
16.4.7 Power Supply Characteristics ............................................................................... 482
16.5 H8/38024S Group Mask ROM Version Absolute Maximum Ratings............................... 483
16.6 H8/38024S Group Mask ROM Version Electrical Characteristics .................................... 484
16.6.1 Power Supply Voltage and Operating Range........................................................ 484
16.6.2 DC Characteristics ................................................................................................ 487
16.6.3 AC Characteristics ................................................................................................ 495
16.6.4 A/D Converter Characteristics .............................................................................. 499
16.6.5 LCD Characteristics.............................................................................................. 500
16.7 Absolute Maximum Ratings of H8/38124 Group F-ZTAT Version and Mask ROM
Version............................................................................................................................... 501
16.8 Electrical Characteristics of H8/38124 Group F-ZTAT Version and Mask ROM
Version............................................................................................................................... 502
16.8.1 Power Supply Voltage and Operating Ranges ...................................................... 502
16.8.2 DC Characteristics ................................................................................................ 506
Rev. 8.00 Mar. 09, 2010 Page xviii of xx
REJ09B0042-0800
16.9
16.10
16.11
16.12
16.8.3 AC Characteristics ................................................................................................ 515
16.8.4 A/D Converter Characteristics .............................................................................. 517
16.8.5 LCD Characteristics.............................................................................................. 518
16.8.6 Flash Memory Characteristics .............................................................................. 519
16.8.7 Power Supply Voltage Detection Circuit Characteristics ..................................... 521
16.8.8 Power-On Reset Circuit Characteristics................................................................ 524
16.8.9 Watchdog Timer Characteristics........................................................................... 525
16.8.10 Power Supply Characteristics ............................................................................... 525
Operation Timing............................................................................................................... 526
Output Load Circuit ........................................................................................................... 528
Resonator Equivalent Circuit ............................................................................................. 529
Usage Note......................................................................................................................... 530
Appendix A CPU Instruction Set.......................................................................531
A.1
A.2
A.3
Instructions......................................................................................................................... 531
Operation Code Map.......................................................................................................... 539
Number of Execution States............................................................................................... 541
Appendix B Internal I/O Registers ....................................................................546
B.1
B.2
Addresses ........................................................................................................................... 546
Functions............................................................................................................................ 551
Appendix C I/O Port Block Diagrams ...............................................................612
C.1
C.2
C.3
C.4
C.5
C.6
C.7
C.8
C.9
C.10
Block Diagrams of Port 1................................................................................................... 612
Block Diagrams of Port 3................................................................................................... 615
Block Diagrams of Port 4................................................................................................... 620
Block Diagram of Port 5 .................................................................................................... 624
Block Diagram of Port 6 .................................................................................................... 625
Block Diagram of Port 7 .................................................................................................... 626
Block Diagram of Port 8 .................................................................................................... 627
Block Diagrams of Port 9................................................................................................... 628
Block Diagram of Port A ................................................................................................... 630
Block Diagrams of Port B .................................................................................................. 631
Appendix D Port States in the Different Processing States ...............................634
Appendix E List of Product Codes ....................................................................635
Appendix F Package Dimensions ......................................................................639
Rev. 8.00 Mar. 09, 2010 Page xix of xx
REJ09B0042-0800
Appendix G Specifications of Chip Form .........................................................643
Appendix H Form of Bonding Pads ..................................................................645
Appendix I Specifications of Chip Tray............................................................646
Main Revisions for This Edition .........................................................................649
Rev. 8.00 Mar. 09, 2010 Page xx of xx
REJ09B0042-0800
Section 1 Overview
Section 1 Overview
1.1
Overview
The H8/300L Series is a series of single-chip microcomputers (MCU: microcomputer unit), built
around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip.
Within the H8/300L Series, the H8/38024 Group, H8/38024S Group, and H8/38124 Group
comprise single-chip microcomputers equipped with a LCD (Liquid Crystal Display)
controller/driver. Other on-chip peripheral functions include six timers, a two-channel 10-bit
pulse width modulator (PWM), a serial communication interface, and an A/D converter.
Together, these functions make the H8/38024 Group, H8/38024S Group, and H8/38124 Group
ideally suited for embedded applications in systems requiring low power consumption and LCD
display. Models in the H8/38024 Group, H8/38024S Group, and H8/38124 Group are the
H8/38024, H8/38024S, and H8/38124 with on-chip 32-Kbyte ROM and 1-Kbyte RAM, the
H8/38023, H8/38023S, and H8/38123 with on-chip 24-Kbyte ROM and 1-Kbyte RAM, the
H8/38022, H8/38022S, and H8/38122 with on-chip 16-Kbyte ROM and 1-Kbyte RAM, the
H8/38021, H8/38021S, and H8/38121 with 12-Kbyte ROM and 512 byte RAM, and the
H8/38020, H8/38020S, and H8/38120 with 8-Kbyte ROM and 512 byte RAM.
The H8/38024 is also available in a ZTAT™*1 version with on-chip PROM which can be
programmed as required by the user. The H8/38024 is also available in F-ZTAT™*2 versions with
on-chip flash memory which can be reprogrammed on board.
The H8/38124 is also available in an F-ZTAT™ version with on-chip flash memory that can be
programmed on board.
Table 1.1 summarizes the features of the H8/38024 Group, H8/38024S Group, and H8/38124
Group.
Notes: 1. ZTAT (Zero Turn Around Time) is a trademark of Renesas Technology Corp.
2. F-ZTAT is a trademark of Renesas Technology Corp.
Rev. 8.00 Mar. 09, 2010 Page 1 of 658
REJ09B0042-0800
Section 1 Overview
Table 1.1
Features
Item
Specification
CPU
High-speed H8/300L CPU
•
General-register architecture
General registers: Sixteen 8-bit registers (can be used as eight 16-bit
registers)
•
Operating speed
⎯ Max. operating speed: 8 MHz (5 MHz for HD64F38024 and H8/38024S
Group)
⎯ Add/subtract: 0.25 µs (operating at 8 MHz), 0.4 μs (operating at φ =
5 MHz)
⎯ Multiply/divide: 1.75 µs (operating at 8 MHz), 2.8 μs (operating at φ =
5 MHz)
⎯ Can run on 32.768 kHz or 38.4 kHz subclock (32.768 kHz only for
H8/38124 Group)
•
Instruction set compatible with H8/300 CPU
⎯ Instruction length of 2 bytes or 4 bytes
⎯ Basic arithmetic operations between registers
⎯ MOV instruction for data transfer between memory and registers
•
Typical instructions
⎯ Multiply (8 bits × 8 bits)
⎯ Divide (16 bits ÷ 8 bits)
⎯ Bit accumulator
⎯ Register-indirect designation of bit position
Interrupts
22 interrupt sources
•
13 external interrupt sources (IRQ4, IRQ3, IRQ1, IRQ0, WKP7 to WKP0,
IRQAEC)
•
9 internal interrupt sources
Rev. 8.00 Mar. 09, 2010 Page 2 of 658
REJ09B0042-0800
Section 1 Overview
Item
Specification
Clock pulse
generators
Two on-chip clock pulse generators
Power-down
modes
Memory
I/O ports
•
System clock pulse generator:
1.0 to 16 MHz: H8/38024 Group
1.0 to 10 MHz: HD64F38024, HD64F38024R, and H8/38024S Group
2.0 to 20 MHz: H8/38124 Group
•
Subclock pulse generator:
32.768 kHz, 38.4 kHz* (* does not apply to H8/38124 Group)
H8/38124 Group equipped with on-chip oscillator
Seven power-down modes
•
Sleep (high-speed) mode
•
Sleep (medium-speed) mode
•
Standby mode
•
Watch mode
•
Subsleep mode
•
Subactive mode
•
Active (medium-speed) mode
Large on-chip memory
•
H8/38024, H8/38024S, and H8/38124: 32-Kbyte ROM, 1-Kbyte RAM
•
H8/38023, H8/38023S, and H8/38123: 24-Kbyte ROM, 1-Kbyte RAM
•
H8/38022, H8/38022S, and H8/38122: 16-Kbyte ROM, 1-Kbyte RAM
•
H8/38021, H8/38021S, and H8/38121: 12-Kbyte ROM, 512 byte RAM
•
H8/38020, H8/38020S, and H8/38120: 8-Kbyte ROM, 512 byte RAM
66 pins
•
51 I/O pins (50 pins on H8/38124 Group)
•
9 input pins
•
6 output pins
Rev. 8.00 Mar. 09, 2010 Page 3 of 658
REJ09B0042-0800
Section 1 Overview
Item
Specification
Timers
Six on-chip timers
•
Timer A: 8-bit timer
Count-up timer with selection of eight internal clock signals divided from the
system clock (φ)* and four clock signals divided from the watch clock (φw)*
•
Asynchronous event counter: 16-bit timer
⎯ Count-up timer able to count asynchronous external events
independently of the MCU's internal clocks
Asynchronous external events can be counted (both rising and falling edge
detection possible)
•
Timer C: 8-bit timer
⎯ Count-up/down timer with selection of seven internal clock signals or
event input from external pin
⎯ Auto-reloading
•
Timer F: 16-bit timer
⎯ Can be used as two independent 8-bit timers
⎯ Count-up timer with selection of four internal clock signals or event input
from external pin
⎯ Provision for toggle output by means of compare-match function
•
Timer G: 8-bit timer
⎯ Count-up timer with selection of four internal clock signals
⎯ Incorporates input capture function (built-in noise canceler)
•
Watchdog timer
⎯ Reset signal generated by overflow of 8-bit counter
Rev. 8.00 Mar. 09, 2010 Page 4 of 658
REJ09B0042-0800
Section 1 Overview
Item
Specification
Serial
communication
interface
•
10-bit PWM
Pulse-division PWM output for reduced ripple
•
A/D converter
LCD controller/
driver
SCI3: 8-bit synchronous/asynchronous serial interface
Can be used as a 10-bit D/A converter by connecting to an external lowpass filter.
Successive approximations using a resistance ladder
•
8-channel analog input pins
•
Conversion time: 31/φ or 62/φ per channel
LCD controller/driver equipped with a maximum of 32 segment pins and four
common pins
•
Choice of four duty cycles (static, 1/2, 1/3, or 1/4)
•
Segment pins can be switched to general-purpose port function in 4-bit units
Power-on reset
Power-on reset circuit
and low-voltage
• An internal reset signal can be issued at power-on by connecting an
detect circuits
external capacitor.
(H8/38124 Group
only)
Low-voltage detect circuit
•
Monitors the power supply voltage and issues an internal reset signal or
interrupt if the voltage goes below or above a specified range.
Rev. 8.00 Mar. 09, 2010 Page 5 of 658
REJ09B0042-0800
Section 1 Overview
Item
Specification
Product lineup
Product Code
ROM/RAM Size
(Byte)
Mask ROM Version
ZTAT Version
F-ZTAT Version
Package
HD64338024
HD64738024
HD64F38024R
HD64F38024
FP-80A
FP-80B
TFP-80C
TLP-85V (HD64F38024R only)
Die (mask ROM/F-ZTAT version
only)
32K/1K
HD64338023
—
—
FP-80A
FP-80B
TFP-80C
Die
24K/1K
HD64338022
—
—
FP-80A
FP-80B
TFP-80C
Die
16K/1K
HD64338021
—
—
FP-80A
FP-80B
TFP-80C
Die
12K/512
HD64338020
—
—
FP-80A
FP-80B
TFP-80C
Die
8K/512
HD64338024S
—
—
FP-80A
TFP-80C
TLP-85V
Die
32K/1K
HD64338023S
—
—
FP-80A
TFP-80C
TLP-85V
Die
24K/1K
HD64338022S
—
—
FP-80A
TFP-80C
TLP-85V
Die
16K/1K
HD64338021S
—
—
FP-80A
TFP-80C
TLP-85V
Die
12K/512
HD64338020S
—
—
FP-80A
TFP-80C
TLP-85V
Die
8K/512
HD64338124
—
HD64F38124
FP-80A
TFP-80C
32K/1K
HD64338123
—
—
FP-80A
TFP-80C
24K/1K
HD64338122
—
HD64F38122
FP-80A
TFP-80C
16K/1K
HD64338121
—
—
FP-80A
TFP-80C
12K/512
HD64338120
—
—
FP-80A
TFP-80C
8K/512
Refer to appendix E for information on product model numbers.
Note: * See section 4, Clock Pulse Generators, for the definition of φ and φw.
Rev. 8.00 Mar. 09, 2010 Page 6 of 658
REJ09B0042-0800
Section 1 Overview
1.2
Internal Block Diagram
Figure 1.1(1) shows a block diagram of the H8/38024 Group and H8/38024S Group.
Figure 1.1(2) shows a block diagram of the H8/38124 Group.
x1
x2
Sub clock
OSC
VSS
VSS = AVSS
VCC
RES
TEST
H8/300L
CPU
Timer C
P50/WKP0/SEG1
P51/WKP1/SEG2
P52/WKP2/SEG3
P53/WKP3/SEG4
P54/WKP4/SEG5
P55/WKP5/SEG6
P56/WKP6/SEG7
P57/WKP7/SEG8
Timer G
P60/SEG9
P61/SEG10
P62/SEG11
P63/SEG12
P64/SEG13
P65/SEG14
P66/SEG15
P67/SEG16
WDT
Port 9
P87/SEG32
P86/SEG31
P85/SEG30
P84/SEG29
P83/SEG28
P82/SEG27
P81/SEG26
P80/SEG25
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
A/D
(10 bits)
AVCC
Note: If the on-chip emulator is used, pins 95,
33, 34, and 35 are reserved for the
emulator and not available to the user.
LCD
controller
Port B
Port 6
RAM
(512 bytes to 1 Kbyte)
Serial
communication
interface
(SCI3)
P95
P94
P93
P92
P91/PWM2
P90/PWM1
Port 8
Timer F
P40/SCK32
P41/RXD32
P42/TXD32
P43/IRQ0
PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1
Port 7
10-bit PWM2
LCD power
supply
Timer A
P30/UD
P31/TMOFL
P32/TMOFH
P33
P34
P35
P36/AEVH
P37/AEVL
Port 3
10-bit PWM1
Port 4
ROM
(8 Kbytes to 32 Kbytes)
Port 5
Port 1
P13/TMIG
P14/IRQ4/ADTRG
P16
P17/IRQ3/TMIF
Asynchronous
counter
(16 bits)
Port A
IRQAEC
System clock
OSC
OSC1
OSC2
V1
V2
V3
PB7/AN7
PB6/AN6
PB5/AN5
PB4/AN4
PB3/AN3/IRQ1/TMIC
PB2/AN2
PB1/AN1
PB0/AN0
Large-current (25 mA/pin) high-voltage open-drain pin (7 V)
Large-current (10 mA/pin) (H8/38024S Group only)
Large-current (10 mA/pin) high-voltage open-drain pin (7 V)
Large-current (10 mA/pin) (H8/38024S Group only)
High-voltage (7 V) input pin (Except for H8/38024S Group)
Figure 1.1(1) Block Diagram (H8/38024 Group, H8/38024R Group, and H8/38024S Group)
Rev. 8.00 Mar. 09, 2010 Page 7 of 658
REJ09B0042-0800
Section 1 Overview
System clock
OSC
10-bit PWM1
Power-on reset and
low-voltage detect circuits
P50/WKP0/SEG1
P51/WKP1/SEG2
P52/WKP2/SEG3
P53/WKP3/SEG4
P54/WKP4/SEG5
P55/WKP5/SEG6
P56/WKP6/SEG7
P57/WKP7/SEG8
P60/SEG9
P61/SEG10
P62/SEG11
P63/SEG12
P64/SEG13
P65/SEG14
P66/SEG15
P67/SEG16
10-bit PWM2
Port 4
P40/SCK32
P41/RXD32
P42/TXD32
P43/IRQ0
Timer A
Timer C
Timer F
Port 5
P30/UD
P31/TMOFL
P32/TMOFH
P33
P34
P35
P36/AEVH
P37/AEVL
Port 3
P17/IRQ3/TMIF
Timer G
WDT
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
LCD
controller
Port B
A/D
(10 bits)
AVCC
Note: If the on-chip emulator is used, pins 95,
33, 34, and 35 are reserved for the
emulator and not available to the user.
Large-current (15 mA/pin)
Figure 1.1(2) Block Diagram (H8/38124 Group)
Rev. 8.00 Mar. 09, 2010 Page 8 of 658
REJ09B0042-0800
P95
P94
P93/Vref
P92
P91/PWM2
P90/PWM1
P87/SEG32
P86/SEG31
P85/SEG30
P84/SEG29
P83/SEG28
P82/SEG27
P81/SEG26
P80/SEG25
Port 6
RAM
(512 bytes to 1 Kbyte)
Serial
communication
interface
(SCI3)
Port 9
ROM
(8 Kbytes to 32 Kbytes)
IRQAEC
PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1
Port 8
Port 1
P13/TMIG
P14/IRQ4/ADTRG
Asynchronous
counter
(16 bits)
Port 7
OSC1
OSC2
H8/300L
CPU
Port A
Sub clock
OSC
LCD power
supply
x1
x2
CVCC
VSS
VSS = AVSS
VCC
RES
TEST
V1
V2
V3
PB7/AN7
PB6/AN6
PB5/AN5
PB4/AN4
PB3/AN3/IRQ1/TMIC
PB2/AN2
PB1/AN1/extU
PB0/AN0/extD
Section 1 Overview
1.3
Pin Arrangement and Functions
1.3.1
Pin Arrangement
FP-80A, TFP-80C
(Top view)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P83/SEG28
P82/SEG27
P81/SEG26
P80/SEG25
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
P67/SEG16
P66/SEG15
P65/SEG14
P64/SEG13
P63/SEG12
P62/SEG11
P61/SEG10
P60/SEG9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
AVCC
P13/TMIG
P14/IRQ4/ADTRG
P16
P17/IRQ3/TMIF
X1
X2
VSS=AVSS
OSC2
OSC1
TEST
RES
P50/WKP0/SEG1
P51/WKP1/SEG2
P52/WKP2/SEG3
P53/WKP3/SEG4
P54/WKP4/SEG5
P55/WKP5/SEG6
P56/WKP6/SEG7
P57/WKP7/SEG8
P30/UD
P31/TMOFL
P32/TMOFH
P33
P34
P35
P36/AEVH
P37/AEVL
P40/SCK32
P41/RXD32
P42/TXD32
P43/IRQ0
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3/IRQ1/TMIC
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
IRQAEC
P95
P94
P93
P92
P91/PWM2
P90/PWM1
VSS
VCC
V1
V2
V3
PA0/COM1
PA1/COM2
PA2/COM3
PA3/COM4
P87/SEG32
P86/SEG31
P85/SEG30
P84/SEG29
The H8/38024 Group, H8/38024R Group, H8/38024S Group, and H8/38124 Group pin
arrangements are shown in figures 1.2, 1.3, and 1.4. The bonding pad location diagram of the
HCD64338024, HCD64338023, HCD64338022, HCD64338021, and HCD64338020 is shown in
figure 1.5. The bonding pad coordinates of the HCD64338024, HCD64338023, HCD64338022,
HCD64338021, and HCD64338020 are given in table 1.2. The bonding pad location diagram of
the HCD64F38024, HCD64F38024R is shown in figure 1.6. The bonding pad coordinates of the
HCD64F38024 are given in table 1.3. The bonding pad location diagram of the HCD64338024S,
HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S is shown in figure 1.7.
The bonding pad coordinates of the HCD64338024S, HCD64338023S, HCD64338022S,
HCD64338021S, and HCD64338020S are given in table 1.4.
Note: If the on-chip emulator is used, pins 95, 33, 34, and 35 are reserved for the emulator and not available to the user.
Figure 1.2(1) Pin Arrangement (FP-80A, TFP-80C: Top View,
H8/38024 Group, H8/38024R Group, H8/38024S Group)
Rev. 8.00 Mar. 09, 2010 Page 9 of 658
REJ09B0042-0800
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
FP-80A,TFP-80C
(Top view)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P83/SEG28
P82/SEG27
P81/SEG26
P80/SEG25
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
P67/SEG16
P66/SEG15
P65/SEG14
P64/SEG13
P63/SEG12
P62/SEG11
P61/SEG10
P60/SEG9
AVCC
P13/TMIG
P14/IRQ4/ADTRG
CVCC
P17/IRQ3/TMIF
X1
X2
VSS=AVSS
OSC2
OSC1
TEST
RES
P50/WKP0/SEG1
P51/WKP1/SEG2
P52/WKP2/SEG3
P53/WKP3/SEG4
P54/WKP4/SEG5
P55/WKP5/SEG6
P56/WKP6/SEG7
P57/WKP7/SEG8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
P30/UD
P31/TMOFL
P32/TMOFH
P33
P34
P35
P36/AEVH
P37/AEVL
P40/SCK32
P41/RXD32
P42/TXD32
P43/IRQ0
PB0/AN0/extD
PB1/AN1/extU
PB2/AN2
PB3/AN3/IRQ1/TMIC
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
IRQAEC
P95
P94
P93/Vref
P92
P91/PWM2
P90/PWM1
VSS
VCC
V1
V2
V3
PA0/COM1
PA1/COM2
PA2/COM3
PA3/COM4
P87/SEG32
P86/SEG31
P85/SEG30
P84/SEG29
Section 1 Overview
Note: If the on-chip emulator is used, pins 95, 33, 34, and 35 are reserved for the emulator and not available to the user.
Figure 1.2(2) Pin Arrangement (FP-80A, TFP-80C: Top View, H8/38124 Group)
Rev. 8.00 Mar. 09, 2010 Page 10 of 658
REJ09B0042-0800
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P31/TMOFL
P30/UD
IRQAEC
P95
P94
P93
P92
P91/PWM2
P90/PWM1
VSS
VCC
V1
V2
V3
PA0/COM1
PA1/COM2
PA2/COM3
PA3/COM4
P87/SEG32
P86/SEG31
P85/SEG30
P84/SEG29
P83/SEG28
P82/SEG27
Section 1 Overview
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
FP-80B
(Top view)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
P81/SEG26
P80/SEG25
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
P67/SEG16
P66/SEG15
P65/SEG14
P64/SEG13
P63/SEG12
P62/SEG11
PB6/AN6
PB7/AN7
AVCC
P13/TMIG
P14/IRQ4/ADTRG
P16
P17/IRQ3/TMIF
X1
X2
VSS=AVSS
OSC2
OSC1
TEST
RES
P50/WKP0/SEG1
P51/WKP1/SEG2
P52/WKP2/SEG3
P53/WKP3/SEG4
P54/WKP4/SEG5
P55/WKP5/SEG6
P56/WKP6/SEG7
P57/WKP7/SEG8
P60/SEG9
P61/SEG10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
P32/TMOFH
P33
P34
P35
P36/AEVH
P37/AEVL
P40/SCK32
P41/RXD32
P42/TXD32
P43/IRQ0
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3/IRQ1/TMIC
PB4/AN4
PB5/AN5
Note: If the on-chip emulator is used, pins 95, 33, 34, and 35 are reserved for the emulator and not available to the user.
Figure 1.3 Pin Arrangement (FP-80B: Top View, H8/38024 Group, H8/38024R Group)
Rev. 8.00 Mar. 09, 2010 Page 11 of 658
REJ09B0042-0800
Section 1 Overview
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D1
D2
D3
D4
D8
D9
D10
E1
E2
E3
E8
E9
E10
F1
F2
F3
F8
F9
F10
G1
G2
G3
G8
G9
G10
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
TLP-85V
(Top view)
Note: Pins are shown in transparent view.
Figure 1.4 Pin Arrangement (TLP-85V, H8/38024R Group, H8/38024S Group)
Rev. 8.00 Mar. 09, 2010 Page 12 of 658
REJ09B0042-0800
Section 1 Overview
81
79
80
77
78
75
76
73
74
71
72
69
67
70
68
65
66
63
64
62
Type code
61
1
2
60
59
3
4
58
5
57
6
7
56
Y
8
55
9
54
53
10
(0, 0)
11
52
X
51
12
50
13
49
14
15
48
16
47
17
46
18
45
19
44
20
43
21
42
22
24
23
26
25
28
27
29
30
31
32
33
34
36
35
37
38
40
39
41
Chip size: 3.99 mm × 3.99 mm
Voltage level on the back of the chip: GND
Figure 1.5 Bonding Pad Location Diagram of HCD64338024, HCD64338023,
HCD64338022, HCD64338021, and HCD64338020 (Top View)
Rev. 8.00 Mar. 09, 2010 Page 13 of 658
REJ09B0042-0800
Section 1 Overview
Table 1.2
Bonding Pad Coordinates of HCD64338024, HCD64338023, HCD64338022,
HCD64338021, and HCD64338020
Coordinates
Coordinates
Pad No.
Pad Name
X (μm)
Y (μm)
Pad No.
Pad Name
X (μm)
Y (μm)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
AVCC
P13/TMIG
P14/IRQ4/ADTRG
P16
P17/IRQ3/TMIF
X1
X2
AVSS
VSS
OSC2
OSC1
TEST
RES
P50/WKP0/SEG1
P51/WKP1/SEG2
P52/WKP2/SEG3
P53/WKP3/SEG4
P54/WKP4/SEG5
P55/WKP5/SEG6
P56/WKP6/SEG7
P57/WKP7/SEG8
P60/SEG9
P61/SEG10
P62/SEG11
P63/SEG12
P64/SEG13
P65/SEG14
P66/SEG15
P67/SEG16
P70/SEG17
P71/SEG18
P72/SEG19
P73/SEG20
P74/SEG21
P75/SEG22
P76/SEG23
P77/SEG24
P80/SEG25
P81/SEG26
P82/SEG27
–1870
–1870
–1870
–1870
–1870
–1870
–1870
–1870
–1870
–1870
–1870
–1870
–1870
–1870
–1870
–1870
–1870
–1870
–1870
–1870
–1870
–1780
–1621
–1037
–896
–765
–635
–502
–371
–239
–108
23
156
287
419
550
682
833
1040
1621
1546
1274
1058
909
759
608
475
304
173
–10
–150
–290
–425
–560
–695
–831
–966
–1101
–1236
–1379
–1561
–1872
–1872
–1872
–1872
–1872
–1872
–1872
–1872
–1872
–1872
–1872
–1872
–1872
–1872
–1872
–1872
–1872
–1872
–1872
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
P84/SEG29
P85/SEG30
P86/SEG31
P87/SEG32
PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1
V3
V2
V1
VCC
VSS
P90/PWM1
P91/PWM2
P92
P93
P94
P95
IRQAEC
P30/UD
P31/TMOFL
P32/TMOFH
P33
P34
P35
P36/AEVH
P37/AEVL
P40/SCK32
P41/RXD32
P42/TXD32
P43/IRQ0
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3/IRQ1/TMIC
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
1870
1870
1870
1870
1870
1870
1870
1870
1870
1870
1870
1870
1870
1870
1870
1870
1870
1870
1870
1870
1782
1621
1084
948
810
673
536
311
176
38
–99
–234
–482
–614
–745
–878
–1008
–1148
–1621
–1782
–1571
–1395
–1251
–1111
–970
–831
–691
–550
–410
–270
–131
10
150
293
489
685
880
1076
1274
1546
1872
1872
1872
1872
1872
1872
1872
1872
1872
1872
1872
1872
1872
1872
1872
1872
1872
1872
1872
1872
P83/SEG28
1782
–1872
41
Note:
VSS Pads (No. 8 and 9) should be connected to power supply lines.
TEST Pad (No. 12) should be connected to VSS.
If the pad of these aren’t connected to the power supply line, the LSI will not operate correctly. These values show the
coordinates of the centers of pads. The accuracy is ±5 μm. The home-point position is the chip’s center and the center
is located at half the distance between the upper and lower pads and left and right pads.
Rev. 8.00 Mar. 09, 2010 Page 14 of 658
REJ09B0042-0800
Section 1 Overview
81
79
80
77
78
75
76
73
71
74
72
69
70
67
68
65
66
64
63
1
2
62
3
61
4
60
5
6
59
7
9
8
58
Y
10
11
13
15
57
12
56
14
(0, 0)
55
X
54
16
53
17
52
18
50
19
20
48
51
49
47
46
21
45
44
Type code
22
43
23
42
24
26
25
27
28
29
30
31
32
34 36 38
33
35 37
40
39
41
Chip size: 3.84 mm × 4.24 mm
Voltage level on the back of the chip: GND
: NC pad
Figure 1.6 Bonding Pad Location Diagram of HCD64F38024, HCD64F38024R (Top View)
Rev. 8.00 Mar. 09, 2010 Page 15 of 658
REJ09B0042-0800
Section 1 Overview
Table 1.3 Bonding Pad Coordinates of HCD64F38024, HCD64F38024R
Coordinates
Coordinates
Pad No.
Pad Name
X (μm)
Y (μm)
Pad No.
Pad Name
X (μm)
Y (μm)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PB7/AN7
AVCC
P13/TMIG
P14/IRQ4/ADTRG
P16
P17/IRQ3/TMIF
X1
X2
AVSS
VSS
OSC2
OSC1
TEST
RES
P50/WKP0/SEG1
P51/WKP1/SEG2
P52/WKP2/SEG3
P53/WKP3/SEG4
P54/WKP4/SEG5
P55/WKP5/SEG6
P56/WKP6/SEG7
P57/WKP7/SEG8
P60/SEG9
P61/SEG10
P62/SEG11
P63/SEG12
P64/SEG13
P65/SEG14
P66/SEG15
P67/SEG16
P70/SEG17
P71/SEG18
P72/SEG19
P73/SEG20
P74/SEG21
P75/SEG22
P76/SEG23
P77/SEG24
P80/SEG25
P81/SEG26
–1802
–1802
–1802
–1802
–1802
–1802
–1802
–1802
–1802
–1802
–1802
–1802
–1802
–1802
–1802
–1802
–1802
–1802
–1802
–1802
–1802
–1802
–1802
–1686
–1198
–1057
–916
–755
–625
–493
–352
–202
–69
72
213
330
459
583
730
937
1904
1717
1443
1292
1157
1022
887
753
638
473
318
202
69
–63
–195
–355
–514
–674
–844
–1008
–1348
–1709
–1904
–1999
–1999
–1999
–1999
–1999
–1999
–1999
–1999
–1999
–1999
–1999
–1999
–1999
–1999
–1999
–1999
–1999
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
P83/SEG28
P84/SEG29
P85/SEG30
P86/SEG31
P87/SEG32
PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1
V3
V2
V1
VCC
VSS
P90/PWM1
P91/PWM2
P92
P93
P94
P95
IRQAEC
P30/UD
P31/TMOFL
P32/TMOFH
P33
P34
P35
P36/AEVH
P37/AEVL
P40/SCK32
P41/RXD32
P42/TXD32
P43/IRQ0
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3/IRQ1/TMIC
PB4/AN4
PB5/AN5
PB6/AN6
1802
1802
1802
1802
1802
1802
1802
1802
1802
1802
1802
1802
1802
1802
1802
1802
1802
1802
1802
1802
1802
1802
1686
1222
1077
932
788
643
498
353
226
63
–82
–229
–404
–577
–751
–925
–1099
–1686
–1898
–1750
–1594
–1454
–1296
–1182
–1068
–954
–840
–726
–534
–402
–267
–126
206
457
707
958
1209
1460
1710
1904
1999
1999
1999
1999
1999
1999
1999
1999
1999
1999
1999
1999
1999
1999
1999
1999
1999
1999
P82/SEG27
1686
–1999
41
Note:
VSS Pads (No. 9 and 10) should be connected to power supply lines.
TEST Pad (No. 13) should be connected to VSS.
If the pad of these aren’t connected to the power supply line, the LSI will not operate correctly. These values show the
coordinates of the centers of pads. The accuracy is ±5 μm. The home-point position is the chip’s center and the center
is located at half the distance between the upper and lower pads and left and right pads.
Rev. 8.00 Mar. 09, 2010 Page 16 of 658
REJ09B0042-0800
Section 1 Overview
79
80
77
78
75
76
73
74
71
72
69
70
67
68
65
66
63
64
61
62
60
1
59
2
58
3
57
4
56
5
55
6
54
7
Y
8
53
52
9
51
10
(0.0)
11
50
X
49
12
48
13
47
14
46
15
45
16
44
17
43
18
42
19
41
20
22
21
24
23
26
25
28
27
30
29
32
31
34
33
36
35
38
37
40
39
Chip size: 2.91 mm × 2.91 mm
Voltage level on the back of the chip: GND
Figure 1.7 Bonding Pad Location Diagram of HCD64338024S, HCD64338023S,
HCD64338022S, HCD64338021S, and HCD64338020S (Top View)
Rev. 8.00 Mar. 09, 2010 Page 17 of 658
REJ09B0042-0800
Section 1 Overview
Table 1.4
Bonding Pad Coordinates of HCD64338024S, HCD64338023S, HCD64338022S,
HCD64338021S, and HCD64338020S
Coordinates
Coordinates
Pad No.
Pad Name
X (μm)
Y (μm)
Pad No.
Pad Name
X (μm)
Y (μm)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
AVCC
P13/TMIG
P14/IRQ4/ADTRG
P16
P17/IRQ3/TMIF
X1
X2
VSS = AVSS
OSC2
OSC1
TEST
RES
P50/WKP0/SEG1
P51/WKP1/SEG2
P52/WKP2/SEG3
P53/WKP3/SEG4
P54/WKP4/SEG5
P55/WKP5/SEG6
P56/WKP6/SEG7
P57/WKP7/SEG8
P60/SEG9
P61/SEG10
P62/SEG11
P63/SEG12
P64/SEG13
P65/SEG14
P66/SEG15
P67/SEG16
P70/SEG17
P71/SEG18
P72/SEG19
P73/SEG20
P74/SEG21
P75/SEG22
P76/SEG23
P77/SEG24
P80/SEG25
P81/SEG26
P82/SEG27
P83/SEG28
–1338
–1338
–1338
–1338
–1338
–1338
–1338
–1338
–1338
–1338
–1338
–1338
–1338
–1338
–1338
–1338
–1338
–1338
–1338
–1338
–1121
–927
–805
–703
–593
–483
–372
–263
–166
–47
55
166
277
388
499
610
701
790
885
1076
1053
823
737
649
556
460
363
229
100
13
–74
–168
–265
–373
–481
–590
–698
–806
–892
–1091
–1338
–1338
–1338
–1338
–1338
–1338
–1338
–1338
–1338
–1338
–1338
–1338
–1338
–1338
–1338
–1338
–1338
–1338
–1338
–1338
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P84/SEG29
P85/SEG30
P86/SEG31
P87/SEG32
PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1
V3
V2
V1
VCC
VSS
P90/PWM1
P91/PWM2
P92
P93
P94
P95
IRQAEC
P30/UD
P31/TMOFL
P32/TMOFH
P33
P34
P35
P36/AEVH
P37/AEVL
P40/SCK32
P41/RXD32
P42/TXD32
P43/IRQ0
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3/IRQ1/TMIC
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
1338
1338
1338
1338
1338
1338
1338
1338
1338
1338
1338
1338
1338
1338
1338
1338
1338
1338
1338
1338
1131
936
831
735
631
526
421
317
212
108
3
–101
–249
–362
–476
–589
–702
–791
–880
–1081
–1121
–929
–820
–721
–610
–499
–388
–277
–189
–91
6
156
362
528
614
699
785
871
957
1147
1338
1338
1338
1338
1338
1338
1338
1338
1338
1338
1338
1338
1338
1338
1338
1338
1338
1338
1338
1338
Note: Pad No. 11 (TEST) should be connected to VSS.
If it is not connected, the LSI will not operate correctly.
These values show the coordinates of the centers of pads. The accuracy is ±5 µm.
The home-point position is the chip’s center and the center is located at halfway between the upper and lower pads and
the left and right pads.
Rev. 8.00 Mar. 09, 2010 Page 18 of 658
REJ09B0042-0800
Section 1 Overview
1.3.2
Pin Functions
Table 1.5 outlines the pin functions of the H8/38024 Group.
Table 1.5
Pin Functions
Pin No.
Type
Symbol
FP-80A
TFP-80C FP-80B TLP-85V
Pad Pad Pad
No.*1 No.*2 No.*3 I/O
Power
source
pins
VCC
52
54
53
54
52
Input
Power supply: All VCC
pins should be connected
to the system power
supply.
VSS
8
(= AVSS)
53
10
D8
(= AVSS) E1
55
(= AVSS)
9
54
10
55
8
53
Input
Ground: All VSS pins
should be connected to
the system power supply
(0 V).
AVCC
1
3
B1
1
2
1
Input
Analog power supply:
This is the power supply
pin for the A/D converter.
When the A/D converter
is not used, connect this
pin to the system power
supply.
AVSS
8 (= VSS)
10
(= VSS)
E1
(= VSS)
8
9
8
Input
Analog ground: This is
the A/D converter ground
pin. It should be
connected to the system
power supply (0V).
V1
V2
V3
51
50
49
53
52
51
F9
E9
F8
52
51
50
53
52
51
51
50
49
Input
LCD power supply:
These are the power
supply pins for the LCD
controller/driver.
CVCC*4
4
—
—
—
—
—
Input
Power supply: This is
the internal step-down
power supply pin. To
ensure stability, a
capacitor with a rating of
about 0.1 µF should be
connected between this
pin and the VSS pin.
E8
Name and Functions
Rev. 8.00 Mar. 09, 2010 Page 19 of 658
REJ09B0042-0800
Section 1 Overview
Pin No.
Type
Clock
pins
System
control
Interrupt
pins
Symbol
FP-80A
TFP-80C FP-80B TLP-85V
Pad Pad Pad
No.*1 No.*2 No.*3 I/O
Name and Functions
These pins connect to a
crystal or ceramic
oscillator, or can be used
to input an external clock.
See section 4, Clock
Pulse Generators, for a
typical connection
diagram.
OSC1
10
12
F2
11
12
10
Input
OSC2
9
11
E3
10
11
9
Output
X1
6
8
D3
6
7
6
Input
X2
7
9
D2
7
8
7
RES
12
14
F3
13
14
12
Input
Reset: When this pin is
driven low, the chip is
reset
TEST
11
13
E2
12
13
11
Input
Test pin: This pin is
reserved and cannot be
used. It should be
connected to VSS.
IRQ0
IRQ1
IRQ3
IRQ4
72
76
5
3
74
78
7
5
C5
B3
D1
B2
73
77
5
3
74
78
6
4
72
76
5
3
Input
IRQ interrupt request 0,
1, 3, and 4: These are
input pins for edgesensitive external
interrupts, with a selection
of rising or falling edge
IRQAEC 60
62
C10
61
62
60
Input
Asynchronous event
counter event signal:
This is an interrupt input
pin for enabling
asynchronous event
input.
These pins connect to a
32.768-kHz or 38.4-kHz*5
Output
crystal oscillator.
See section 4, Clock
Pulse Generators, for a
typical connection
diagram.
On the H8/38124 Group,
this must be fixed at VCC
or GND because the
oscillator is selected by
the input level during
resets. Refer to section 4,
Clock Pulse Generators,
for information on the
selection method.
Rev. 8.00 Mar. 09, 2010 Page 20 of 658
REJ09B0042-0800
Section 1 Overview
Pin No.
FP-80A
TFP-80C FP-80B TLP-85V
Pad Pad Pad
No.*1 No.*2 No.*3 I/O
Name and Functions
Type
Symbol
Interrupt
pins
WKP7 to 20 to 13
WKP0
22 to 15 H1, J1,
H3, G1,
H2, G2,
F2, G3
21 to 22 to
14
15
20 to
13
Input
Wakeup interrupt
request 7 to 0: These are
input pins for rising or
falling-edge-sensitive
external interrupts.
Timer
pins
AEVL
AEVH
68
67
70
69
A6
B7
69
68
70
69
68
67
Input
Asynchronous event
counter event input:
This is an event input pin
for input to the
asynchronous event
counter.
TMIC
76
78
B3
77
78
76
Input
Timer C event input:
This is an event input pin
for input to the timer C
counter.
UD
61
63
A9
62
63
61
Input
Timer C up/down select:
This pin selects up- or
down-counting for the
timer C counter. The
counter operates as a
down-counter when this
pin is high, and as an upcounter when low.
TMIF
5
7
D1
5
6
5
Input
Timer F event input:
This is an event input pin
for input to the timer F
counter.
TMOFL
62
64
A8
63
64
62
Output Timer FL output: This is
an output pin for
waveforms generated by
the timer FL output
compare function.
TMOFH
63
65
B9
64
65
63
Output Timer FH output: This is
an output pin for
waveforms generated by
the timer FH output
compare function.
TMIG
2
4
C1
2
3
2
Input
Timer G capture input:
This is an input pin for
timer G input capture.
Rev. 8.00 Mar. 09, 2010 Page 21 of 658
REJ09B0042-0800
Section 1 Overview
Pin No.
FP-80A
TFP-80C FP-80B TLP-85V
Pad Pad Pad
No.*1 No.*2 No.*3 I/O
10-bit
PWM1
PWM pin PWM2
54
55
56
57
E10
D9
55
56
56
57
54
55
Output 10-bit PWM output:
These are output pins for
waveforms generated by
the channel 1 and 2 10-bit
PWMs.
I/O ports
5
4
3
2
7
6
5
4
D1
C2
B2
C1
5
4
3
2
6
5
4
3
5
4
3
2
I/O
Type
Symbol
P17
P16
P14
P13
Name and Functions
Port 1: This is a 4-bit I/O
port. Input or output can
be designated for each bit
by means of port control
register 1 (PCR1).
Note that the H8/38124
Group is not equipped
with a pin 16.
P37 to
P30
68 to 61
70 to 63 A6, B7
C7, A7
B8, B9
A8, A9
69 to 70 to
62
63
68 to
61
I/O
Port 3: This is an 8-bit I/O
port. Input or output can
be designated for each bit
by means of port control
register 3 (PCR3).
If the on-chip emulator is
used, pins 33, 34, and 35
are reserved for the
emulator and not
available to the user.
P43
72
74
C5
P42 to
P40
71 to 69
73 to 71 B6
B5
C6
P57 to
P50
20 to 13
P67 to
P60
28 to 21
72
Input
Port 4 (bit 3): This is a 1bit input port.
72 to 73 to
70
71
71 to
69
I/O
Port 4 (bits 2 to 0): This
is a 3-bit I/O port. Input or
output can be designated
for each bit by means of
port control register 4
(PCR4).
22 to 15 H1, J1
H3, G1
H2, G2
F1, G3
21 to 22 to
14
15
20 to
13
I/O
Port 5: This is an 8-bit I/O
port. Input or output can
be designated for each bit
by means of port control
register 5 (PCR5).
30 to 23 K5, J4
H4, K4
J3, J2
K3, K2
29 to 30 to
22
23
28 to
21
I/O
Port 6: This is an 8-bit I/O
port. Input or output can
be designated for each bit
by means of port control
register 6 (PCR6).
Rev. 8.00 Mar. 09, 2010 Page 22 of 658
REJ09B0042-0800
73
74
Section 1 Overview
Pin No.
FP-80A
TFP-80C FP-80B TLP-85V
Pad Pad Pad
No.*1 No.*2 No.*3 I/O
P77 to
P70
36 to 29
38 to 41 J8, J7
K6, H7
H6, J7
H6, J5
J6, H5
37 to 38 to
30
31
36 to
29
I/O
Port 7: This is an 8-bit I/O
port. Input or output can
be designated for each bit
by means of port control
register 7 (PCR7).
P87 to
P80
44 to 37
46 to 39 H9, J9
H10, J10
K8, K9
H8, K7
45 to 46 to
38
39
44 to
37
I/O
Port 8: This is an 8-bit I/O
port. Input or output can
be designated for each bit
by means of port control
register 8 (PCR8).
P95 to
P90
59 to 54
61 to 56 B10, C8
D10, C9
D9, E10
60 to 61 to
55
56
59 to
54
Output Port 9: This is a 6-bit
output port. If the on-chip
emulator is used, pin 95 is
reserved for the emulator
and not available to the
user. In the case of the
F-ZTAT version, pin 95
should not be left open in
the user mode, and
should instead be pulled
up to high level.
PA3 to
PA0
45 to 48
47 to 50 G10
G8
G9
F10
46 to 47 to
49
50
45 to
48
I/O
Port A: This is a 4-bit I/O
port. Input or output can
be designated for each bit
by means of port control
register A (PCRA).
PB7 to
PB0
80 to 73
2, 1,
A3, A2
80 to 75 C3, A4
B3, B4
A5, C4
81 to 1,
74
81 to
75
80 to
73
Input
Port B: This is an 8-bit
input port.
Serial
RXD32
communication
(SCI)
TXD32
70
72
B5
71
72
70
Input
SCI3 receive data input:
This is the SCI3 data
input pin.
71
73
B6
72
73
71
Output SCI3 transmit data
output: This is the SCI3
data output pin.
SCK32
69
71
C6
70
71
69
I/O
SCI3 clock I/O: This is
the SCI3 clock I/O pin.
80 to 73
2, 1,
A3, A2
80 to 75 C3, A4
B3, B4
A5, C4
80 to
73
Input
Analog input channels 7
to 0: These are analog
data input channels to the
A/D converte.
Type
Symbol
I/O ports
A/D
AN7 to
converter AN0
81 to 1,
74
81 to
75
Name and Functions
Rev. 8.00 Mar. 09, 2010 Page 23 of 658
REJ09B0042-0800
Section 1 Overview
Pin No.
Type
Symbol
A/D
ADTRG
converter
FP-80A
TFP-80C FP-80B TLP-85V
Pad Pad Pad
No.*1 No.*2 No.*3 I/O
3
3
3
Input
46 to 47 to
49
50
45 to
48
Output LCD common output:
These are the LCD
common output pins.
SEG32 to 44 to 13
SEG1
45 to 46 to
46 to 15 H9, J9,
15
H10, J10, 14
K8, K9, H8,
K7, J8, J7,
K6, H7, H6,
J5, J6, H5,
K5, J4, H4,
K4, J3, J2,
K3, K2, H1,
J1, H3, G1,
H2, G2, F1,
G3
44 to
13
Output LCD segment output:
These are the LCD
segment output pins.
NC
NC
—
—
A1, A10,
D4, K2,
K10
—
—
—
—
NC pin
Lowvoltage
detect
circuit
(LVD)*4
Vref
57
—
—
—
—
—
Input
LVD reference voltage
input: This is the LVD
reference voltage input
pin.
extD
73
—
—
—
—
—
Input
LVD power supply drop
detect voltage input:
This is the LVD power
supply drop detect
voltage input pin.
extD
74
—
—
—
—
—
Input
LVD power supply rise
detect voltage input:
This is the LVD power
supply rise detect voltage
input pin.
LCD
COM4 to 45 to 48
controller/ COM1
driver
5
B2
47 to 50 G10, G8
G9, F10
4
Name and Functions
A/D converter trigger
input: This is the external
trigger input pin to the A/D
converter.
Notes: 1. Pad number for HCD64338024, HCD64338023, HCD64338022, HCD64338021, and
HCD64338020.
2. Pad number for HCD64F38024 and HCD64F38024R.
3. Pad number for HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S,
and HCD64338020S.
4. H8/38124 Group only
5. Does not apply to H8/38124 Group.
Rev. 8.00 Mar. 09, 2010 Page 24 of 658
REJ09B0042-0800
Section 2 CPU
Section 2 CPU
2.1
Overview
The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit
registers. Its concise instruction set is designed for high-speed operation.
2.1.1
Features
Features of the H8/300L CPU are listed below.
• General-register architecture
Sixteen 8-bit general registers, also usable as eight 16-bit general registers
• Instruction set with 55 basic instructions, including:
⎯ Multiply and divide instructions
⎯ Powerful bit-manipulation instructions
• Eight addressing modes
⎯ Register direct
⎯ Register indirect
⎯ Register indirect with displacement
⎯ Register indirect with post-increment or pre-decrement
⎯ Absolute address
⎯ Immediate
⎯ Program-counter relative
⎯ Memory indirect
• 64-Kbyte address space
• High-speed operation
⎯ All frequently used instructions are executed in two to four states
⎯ High-speed arithmetic and logic operations
⎯ 8- or 16-bit register-register add or subtract: 0.25 µs*
⎯ 8 × 8-bit multiply:
1.75 µs*
⎯ 16 ÷ 8-bit divide:
1.75 µs*
Note: * These values are at φ = 8 MHz.
• Low-power operation modes
SLEEP instruction for transfer to low-power operation
Rev. 8.00 Mar. 09, 2010 Page 25 of 658
REJ09B0042-0800
Section 2 CPU
2.1.2
Address Space
The H8/300L CPU supports an address space of up to 64 Kbytes for storing program code and
data.
See section 2.8, Memory Map, for details of the memory map.
2.1.3
Register Configuration
Figure 2.1 shows the register structure of the H8/300L CPU. There are two groups of registers: the
general registers and control registers.
General registers (Rn)
7
0 7
R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H
0
R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L
(SP)
Control registers (CR)
15
0
PC
CCR
7
I
6
U
[Legend]
SP: Stack pointer
PC: Program counter
CCR: Condition code register
I:
Interrupt mask bit
U:
User bit
H:
Half-carry flag
N:
Negative flag
Z:
Zero flag
V:
Overflow flag
C:
Carry flag
Figure 2.1 CPU Registers
Rev. 8.00 Mar. 09, 2010 Page 26 of 658
REJ09B0042-0800
5
H
4
U
3
N
2
Z
1
V
0
C
Section 2 CPU
2.2
Register Descriptions
2.2.1
General Registers
All the general registers can be used as both data registers and address registers.
When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes
(R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers.
When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7).
R7 also functions as the stack pointer (SP), used implicitly by hardware in exception processing
and subroutine calls. When it functions as the stack pointer, as indicated in figure 2.2, SP (R7)
points to the top of the stack.
Lower address side [H'0000]
Unused area
SP (R7)
Stack area
Upper address side [H'FFFF]
Figure 2.2 Stack Pointer
2.2.2
Control Registers
The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code
register (CCR).
Program Counter (PC)
This 16-bit register indicates the address of the next instruction the CPU will execute. All
instructions are fetched 16 bits (1 word) at a time, so the least significant bit of the PC is ignored
(always regarded as 0).
Rev. 8.00 Mar. 09, 2010 Page 27 of 658
REJ09B0042-0800
Section 2 CPU
Condition Code Register (CCR)
This 8-bit register contains internal status information, including the interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. These bits can be read
and written by software (using the LDC, STC, ANDC, ORC, and XORC instructions). The N, Z,
V, and C flags are used as branching conditions for conditional branching (Bcc) instructions.
Bit 7—Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1
automatically at the start of exception handling. The interrupt mask bit may be read and written
by software. For further details, see section 3.3, Interrupts.
Bit 6—User Bit (U): Can be used freely by the user.
Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B
instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0
otherwise.
The H flag is used implicitly by the DAA and DAS instructions.
When the ADD.W, SUB.W, or CMP.W instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 11, and is cleared to 0 otherwise.
Bit 4—User Bit (U): Can be used freely by the user.
Bit 3—Negative Flag (N): Indicates the most significant bit (sign bit) of the result of an
instruction.
Bit 2—Zero Flag (Z): Set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero
result.
Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other
times.
Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift and rotate instructions, to store the value shifted out of the end bit
The carry flag is also used as a bit accumulator by bit manipulation instructions.
Some instructions leave some or all of the flag bits unchanged.
Refer to the H8/300L Series Software Manual for the action of each instruction on the flag bits.
Rev. 8.00 Mar. 09, 2010 Page 28 of 658
REJ09B0042-0800
Section 2 CPU
2.2.3
Initial Register Values
When the CPU is reset, the program counter (PC) is initialized to the value stored at address
H'0000 in the vector table, and the I bit in the CCR is set to 1. The other CCR bits and the general
registers are not initialized. In particular, the stack pointer (R7) is not initialized. The stack pointer
should be initialized by software, by the first instruction executed after a reset.
2.3
Data Formats
The H8/300L CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word)
data.
• Bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand
(n = 0, 1, 2, ..., 7).
• All arithmetic and logic instructions except ADDS and SUBS can operate on byte data.
• The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions operate on word data.
• The DAA and DAS instructions perform decimal arithmetic adjustments on byte data in
packed BCD form. Each nibble of the byte is treated as a decimal digit.
Rev. 8.00 Mar. 09, 2010 Page 29 of 658
REJ09B0042-0800
Section 2 CPU
2.3.1
Data Formats in General Registers
Data of all the sizes above can be stored in general registers as shown in figure 2.3.
Data Type
Register No.
Data Format
7
1-bit data
RnH
1-bit data
RnL
Byte data
RnH
Byte data
RnL
Word data
Rn
4-bit BCD data
RnH
4-bit BCD data
RnL
7
0
6
5
4
3
2
1
0
Don't care
7
Don't care
7
7
0
MSB
LSB
Don't care
0
6
5
4
3
2
1
0
Don't care
7
0
MSB
LSB
15
0
MSB
LSB
7
4
3
Upper digit
0
Lower digit
Don't care
7
Don't care
4
Upper digit
[Legend]
RnH: Upper byte of general register
RnL: Lower byte of general register
MSB: Most significant bit
LSB: Least significant bit
Figure 2.3 Register Data Formats
Rev. 8.00 Mar. 09, 2010 Page 30 of 658
REJ09B0042-0800
0
3
Lower digit
Section 2 CPU
2.3.2
Memory Data Formats
Figure 2.4 indicates the data formats in memory. The H8/300L CPU can access word data stored
in memory (MOV.W instruction), but the word data must always begin at an even address. If word
data starting at an odd address is accessed, the least significant bit of the address is regarded as 0,
and the word data starting at the preceding address is accessed. The same applies to instruction
codes.
Data Type
Address
Data Format
7
0
1-bit data
Address n
7
Byte data
Address n
MSB
Even address
MSB
Word data
6
Odd address
Byte data (CCR) on stack
Word data on stack
5
4
3
2
1
0
LSB
Upper 8 bits
Lower 8 bits
LSB
MSB
CCR
LSB
Odd address
MSB
CCR*
LSB
Even address
MSB
Even address
Odd address
LSB
Note: * Ignored on return
[Legend]
CCR: Condition code register
Figure 2.4 Memory Data Formats
When the stack is accessed using R7 as an address register, word access should always be
performed. When the CCR is pushed on the stack, two identical copies of the CCR are pushed to
make a complete word. When they are restored, the lower byte is ignored.
Rev. 8.00 Mar. 09, 2010 Page 31 of 658
REJ09B0042-0800
Section 2 CPU
2.4
Addressing Modes
2.4.1
Addressing Modes
The H8/300L CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a
subset of these addressing modes.
Table 2.1
Addressing Modes
No.
Address Modes
Symbol
1
Register direct
Rn
2
Register indirect
@Rn
3
Register indirect with displacement
@(d:16, Rn)
4
Register indirect with post-increment
Register indirect with pre-decrement
@Rn+
@–Rn
5
Absolute address
@aa:8 or @aa:16
6
Immediate
#xx:8 or #xx:16
7
Program-counter relative
@(d:8, PC)
8
Memory indirect
@@aa:8
Register Direct—Rn: The register field of the instruction specifies an 8- or 16-bit general register
containing the operand.
Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands.
Register Indirect—@Rn: The register field of the instruction specifies a 16-bit general register
containing the address of the operand in memory.
Register Indirect with Displacement—@(d:16, Rn): The instruction has a second word (bytes 3
and 4) containing a displacement which is added to the contents of the specified general register to
obtain the operand address in memory.
This mode is used only in MOV instructions. For the MOV.W instruction, the resulting address
must be even.
Rev. 8.00 Mar. 09, 2010 Page 32 of 658
REJ09B0042-0800
Section 2 CPU
Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn:
• Register indirect with post-increment—@Rn+
The @Rn+ mode is used with MOV instructions that load registers from memory.
The register field of the instruction specifies a 16-bit general register containing the address of
the operand. After the operand is accessed, the register is incremented by 1 for MOV.B or 2 for
MOV.W. For MOV.W, the original contents of the 16-bit general register must be even.
• Register indirect with pre-decrement—@–Rn
The @–Rn mode is used with MOV instructions that store register contents to memory.
The register field of the instruction specifies a 16-bit general register which is decremented by
1 or 2 to obtain the address of the operand in memory. The register retains the decremented
value. The size of the decrement is 1 for MOV.B or 2 for MOV.W. For MOV.W, the original
contents of the register must be even.
Absolute Address—@aa:8 or @aa:16: The instruction specifies the absolute address of the
operand in memory.
The absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). The MOV.B and bit
manipulation instructions can use 8-bit absolute addresses. The MOV.B, MOV.W, JMP, and JSR
instructions can use 16-bit absolute addresses.
For an 8-bit absolute address, the upper 8 bits are assumed to be 1 (H'FF). The address range is
H'FF00 to H'FFFF (65280 to 65535).
Immediate—#xx:8 or #xx:16: The instruction contains an 8-bit operand (#xx:8) in its second
byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. Only MOV.W instructions can
contain 16-bit immediate values.
The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit
manipulation instructions contain 3-bit immediate data in the second or fourth byte of the
instruction, specifying a bit number.
Program-Counter Relative—@(d:8, PC): This mode is used in the Bcc and BSR instructions.
An 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits and added to the
program counter contents to generate a branch destination address. The possible branching range
is –126 to +128 bytes (–63 to +64 words) from the current address. The displacement should be an
even number.
Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The
second byte of the instruction code specifies an 8-bit absolute address. The word located at this
address contains the branch destination address.
Rev. 8.00 Mar. 09, 2010 Page 33 of 658
REJ09B0042-0800
Section 2 CPU
The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is from
H'0000 to H'00FF (0 to 255). Note that with the H8/300L Series, the lower end of the address area
is also used as a vector area. See section 3.3, Interrupts, for details on the vector area.
If an odd address is specified as a branch destination or as the operand address of a MOV.W
instruction, the least significant bit is regarded as 0, causing word access to be performed at the
address preceding the specified address. See section 2.3.2, Memory Data Formats, for further
information.
2.4.2
Effective Address Calculation
Table 2.2 shows how effective addresses are calculated in each of the addressing modes.
Arithmetic and logic instructions use register direct addressing (1). The ADD.B, ADDX, SUBX,
CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6).
Data transfer instructions can use all addressing modes except program-counter relative (7) and
memory indirect (8).
Bit manipulation instructions can use register direct (1), register indirect (2), or 8-bit absolute
addressing (5) to specify the operand. Register indirect (1) (BSET, BCLR, BNOT, and BTST
instructions) or 3-bit immediate addressing (6) can be used independently to specify a bit position
in the operand.
Rev. 8.00 Mar. 09, 2010 Page 34 of 658
REJ09B0042-0800
4
3
rm
op
7 6
rm
4 3
4 3
rn
0
0
op
disp
7 6
rm
op
7 6
rm
4 3
4 3
0
0
15
op
7 6
rm
4 3
0
Register indirect with pre-decrement,
@−Rn
15
Register indirect with
post-increment, @Rn+
15
Register indirect with displacement,
@(d:16, Rn)
15
Register indirect, @Rn
8 7
0
0
0
Contents (16 bits) of register
indicated by rm
0
1 or 2
Contents (16 bits) of register
indicated by rm
disp
Contents (16 bits) of register
indicated by rm
Contents (16 bits) of register
indicated by rm
3
rm
0
3
rn
Effective Address (EA)
0
15
15
15
15
0
0
0
0
Operand is contents of registers indicated by rm/rn
Incremented or decremented
by 1 if operand is byte size,
1 or 2
and by 2 if word size
15
15
15
15
Effective Address Calculation Method
Table 2.2
2
op
Register direct, Rn
1
15
Addressing Mode and
Instruction Format
No.
Section 2 CPU
Effective Address Calculation
Rev. 8.00 Mar. 09, 2010 Page 35 of 658
REJ09B0042-0800
Rev. 8.00 Mar. 09, 2010 Page 36 of 658
REJ09B0042-0800
7
6
5
No.
op
op
IMM
op
8 7
abs
op
8 7
IMM
abs
15
op
8 7
disp
Program-counter relative
@(d:8, PC)
15
#xx:16
15
Immediate
#xx:8
15
@aa:16
15
Absolute address
@aa:8
Addressing Mode and
Instruction Format
0
0
0
0
0
PC contents
Sign extension
15
disp
0
Effective Address Calculation Method
H'FF
8 7
0
0
15
0
Operand is 1- or 2-byte immediate data
15
15
Effective Address (EA)
Section 2 CPU
8 7
[Legend]
rm, rn: Register field
Operation field
op:
disp: Displacement
IMM: Immediate data
abs: Absolute address
op
abs
Memory indirect, @@aa:8
8
15
Addressing Mode and
Instruction Format
No.
0
15
8 7
abs
Memory contents (16 bits)
H'00
0
Effective Address Calculation Method
15
Effective Address (EA)
0
Section 2 CPU
Rev. 8.00 Mar. 09, 2010 Page 37 of 658
REJ09B0042-0800
Section 2 CPU
2.5
Instruction Set
The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2.3.
Table 2.3
Instruction Set
Function
Instructions
*1
Number
*1
Data transfer
MOV, PUSH , POP
Arithmetic operations
ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA,
DAS, MULXU, DIVXU, CMP, NEG
14
Logic operations
AND, OR, XOR, NOT
4
Shift
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR
8
Bit manipulation
14
Branch
BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR,
BXOR, BIXOR, BLD, BILD, BST, BIST
2
Bcc* , JMP, BSR, JSR, RTS
System control
RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP
8
Block data transfer
EEPMOV
1
1
5
Total: 55
Notes: 1. PUSH Rn is equivalent to MOV.W Rn, @–SP.
POP Rn is equivalent to MOV.W @SP+, Rn. The same applies to the machine
language.
2. Bcc is a conditional branch instruction in which cc represents a condition code.
The following sections give a concise summary of the instructions in each category, and indicate
the bit patterns of their object code. The notation used is defined next.
Rev. 8.00 Mar. 09, 2010 Page 38 of 658
REJ09B0042-0800
Section 2 CPU
Notation
Rd
General register (destination)
Rs
General register (source)
Rn
General register
(EAd), <EAd>
Destination operand
(EAs), <EAs>
Source operand
CCR
Condition code register
N
N (negative) flag of CCR
Z
Z (zero) flag of CCR
V
V (overflow) flag of CCR
C
C (carry) flag of CCR
PC
Program counter
SP
Stack pointer
#IMM
Immediate data
disp
Displacement
+
Addition
–
Subtraction
×
Multiplication
÷
Division
∧
AND logical
∨
OR logical
⊕
Exclusive OR logical
→
Move
~
Logical negation (logical complement)
:3
3-bit length
:8
8-bit length
:16
16-bit length
( ), < >
Contents of operand indicated by effective address
Rev. 8.00 Mar. 09, 2010 Page 39 of 658
REJ09B0042-0800
Section 2 CPU
2.5.1
Data Transfer Instructions
Table 2.4 describes the data transfer instructions. Figure 2.5 shows their object code formats.
Table 2.4
Data Transfer Instructions
Instruction
Size*
Function
MOV
B/W
(EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general
register and memory, or moves immediate data to a general
register.
The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:16, @–Rn, and @Rn+
addressing modes are available for word data. The @aa:8
addressing mode is available for byte data only.
The @–R7 and @R7+ modes require word operands. Do not
specify byte size for these two modes.
POP
W
@SP+ → Rn
Pops a 16-bit general register from the stack. Equivalent to
MOV.W @SP+, Rn.
PUSH
W
Rn → @–SP
Pushes a 16-bit general register onto the stack. Equivalent to
MOV.W Rn, @–SP.
Note:
*
Size: Operand size
B:
Byte
W:
Word
Certain precautions are required in data access. See section 2.9.1, Notes on Data Access, for
details.
Figure 2.7 lists the format of the bit manipulation instructions.
Rev. 8.00 Mar. 09, 2010 Page 40 of 658
REJ09B0042-0800
Section 2 CPU
15
8
7
0
op
rm
15
8
rn
0
rm
8
Rm→Rn
7
op
15
MOV
rn
@Rm←→Rn
7
0
op
rm
rn
@(d:16, Rm)←→Rn
disp
15
8
7
0
op
rm
15
8
op
7
0
rn
15
@Rm+→Rn, or
Rn →@−Rm
rn
abs
8
@aa:8←→Rn
7
0
op
rn
@aa:16←→Rn
abs
15
8
op
7
0
rn
15
IMM
8
#xx:8→Rn
7
0
op
rn
#xx:16→Rn
IMM
15
8
op
7
0
1
1
1
rn
PUSH, POP
@SP+ → Rn, or
Rn → @−SP
[Legend]
op:
Operation field
rm, rn: Register field
disp: Displacement
abs:
Absolute address
IMM: Immediate data
Figure 2.5 Data Transfer Instruction Codes
Rev. 8.00 Mar. 09, 2010 Page 41 of 658
REJ09B0042-0800
Section 2 CPU
2.5.2
Arithmetic Operations
Table 2.5 describes the arithmetic instructions.
Table 2.5
Arithmetic Instructions
Instruction
Size*
Function
ADD
B/W
Rd ± Rs → Rd, Rd + #IMM → Rd
SUB
Performs addition or subtraction on data in two general registers,
or addition on immediate data and data in a general register.
Immediate data cannot be subtracted from data in a general
register. Word data can be added or subtracted only when both
words are in general registers.
ADDX
B
SUBX
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry or borrow on byte data
in two general registers, or addition or subtraction on immediate
data and data in a general register.
INC
B
DEC
Rd ± 1 → Rd
Increments or decrements a general register by 1.
ADDS
W
SUBS
Rd ± 1 → Rd, Rd ± 2 → Rd
Adds or subtracts 1 or 2 to or from a general register
DAA
B
DAS
Rd decimal adjust → Rd
Decimal-adjusts (adjusts to 4-bit BCD) an addition or subtraction
result in a general register by referring to the CCR
MULXU
B
Rd × Rs → Rd
Performs 8-bit × 8-bit unsigned multiplication on data in two
general registers, providing a 16-bit result
DIVXU
B
Rd ÷ Rs → Rd
Performs 16-bit ÷ 8-bit unsigned division on data in two general
registers, providing an 8-bit quotient and 8-bit remainder
CMP
B/W
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general
register or with immediate data, and indicates the result in the
CCR. Word data can be compared only between two general
registers.
NEG
B
0 – Rd → Rd
Obtains the two’s complement (arithmetic complement) of data in a
general register
Note:
*
Size: Operand size
B:
Byte
W:
Word
Rev. 8.00 Mar. 09, 2010 Page 42 of 658
REJ09B0042-0800
Section 2 CPU
2.5.3
Logic Operations
Table 2.6 describes the four instructions that perform logic operations.
Table 2.6
Logic Operation Instructions
Instruction
Size*
Function
AND
B
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and
another general register or immediate data
OR
B
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data
XOR
B
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register
and another general register or immediate data
NOT
B
~ Rd → Rd
Obtains the one’s complement (logical complement) of general
register contents
Note:
*
Size: Operand size
B:
Byte
Rev. 8.00 Mar. 09, 2010 Page 43 of 658
REJ09B0042-0800
Section 2 CPU
2.5.4
Shift Operations
Table 2.7 describes the eight shift instructions.
Table 2.7
Shift Instructions
Instruction
Size*
Function
SHAL
SHAR
B
Rd shift → Rd
SHLL
SHLR
B
ROTL
ROTR
B
ROTXL
ROTXR
B
Note:
Performs an arithmetic shift operation on general register contents
Rd shift → Rd
Performs a logical shift operation on general register contents
Rd rotate → Rd
Rotates general register contents
Rd rotate through carry → Rd
Rotates general register contents through the C (carry) bit
*
Size: Operand size
B:
Byte
Rev. 8.00 Mar. 09, 2010 Page 44 of 658
REJ09B0042-0800
Section 2 CPU
Figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions.
15
8
7
op
0
rm
15
8
7
0
op
15
8
7
0
rm
8
op
8
0
8
0
AND, OR, XOR (Rm)
0
IMM
8
op
rn
7
rn
15
ADD, ADDX, SUBX,
CMP (#XX:8)
7
rm
15
MULXU, DIVXU
IMM
op
op
rn
7
rn
15
ADDS, SUBS, INC, DEC,
DAA, DAS, NEG, NOT
rn
op
15
ADD, SUB, CMP,
ADDX, SUBX (Rm)
rn
AND, OR, XOR (#xx:8)
7
0
rn
SHAL, SHAR, SHLL, SHLR,
ROTL, ROTR, ROTXL, ROTXR
[Legend]
op:
Operation field
rm, rn: Register field
IMM: Immediate data
Figure 2.6 Arithmetic, Logic, and Shift Instruction Codes
Rev. 8.00 Mar. 09, 2010 Page 45 of 658
REJ09B0042-0800
Section 2 CPU
2.5.5
Bit Manipulations
Table 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code formats.
Table 2.8
Bit-Manipulation Instructions
Instruction
Size*
Function
BSET
B
1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory to 1. The bit
number is specified by 3-bit immediate data or the lower three bits
of a general register.
BCLR
B
0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory to 0. The bit
number is specified by 3-bit immediate data or the lower three bits
of a general register.
BNOT
B
~ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory. The bit
number is specified by 3-bit immediate data or the lower three bits
of a general register.
BTST
B
~ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory and sets or
clears the Z flag accordingly. The bit number is specified by 3-bit
immediate data or the lower three bits of a general register.
BAND
B
C ∧ (<bit-No.> of <EAd>) → C
ANDs the C flag with a specified bit in a general register or
memory, and stores the result in the C flag.
BIAND
B
C ∧ [~ (<bit-No.> of <EAd>)] → C
ANDs the C flag with the inverse of a specified bit in a general
register or memory, and stores the result in the C flag.
The bit number is specified by 3-bit immediate data.
BOR
B
C ∨ (<bit-No.> of <EAd>) → C
ORs the C flag with a specified bit in a general register or memory,
and stores the result in the C flag.
BIOR
B
C ∨ [~ (<bit-No.> of <EAd>)] → C
ORs the C flag with the inverse of a specified bit in a general
register or memory, and stores the result in the C flag.
The bit number is specified by 3-bit immediate data.
Note:
*
Size: Operand size
B:
Byte
Rev. 8.00 Mar. 09, 2010 Page 46 of 658
REJ09B0042-0800
Section 2 CPU
Instruction
Size*
Function
BXOR
B
C ⊕ (<bit-No.> of <EAd>) → C
XORs the C flag with a specified bit in a general register or
memory, and stores the result in the C flag.
BIXOR
B
C ⊕ [~(<bit-No.> of <EAd>)] → C
XORs the C flag with the inverse of a specified bit in a general
register or memory, and stores the result in the C flag.
The bit number is specified by 3-bit immediate data.
BLD
B
(<bit-No.> of <EAd>) → C
Copies a specified bit in a general register or memory to the C flag.
BILD
B
~ (<bit-No.> of <EAd>) → C
Copies the inverse of a specified bit in a general register or
memory to the C flag.
The bit number is specified by 3-bit immediate data.
BST
B
BIST
B
C → (<bit-No.> of <EAd>)
Copies the C flag to a specified bit in a general register or memory.
~ C → (<bit-No.> of <EAd>)
Copies the inverse of the C flag to a specified bit in a general
register or memory.
The bit number is specified by 3-bit immediate data.
Note:
*
Size: Operand size
B:
Byte
Certain precautions are required in bit manipulation. See section 2.9.2, Notes on Bit
Manipulation, for details.
Figure 2.7 lists the format of the bit manipulation instructions.
Rev. 8.00 Mar. 09, 2010 Page 47 of 658
REJ09B0042-0800
Section 2 CPU
BSET, BCLR, BNOT, BTST
15
8
7
op
0
IMM
15
8
7
op
0
rm
15
8
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
rn
Operand: register direct (Rn)
Bit No.: register direct (Rm)
rn
7
op
0
rn
0
0
0
0 Operand: register indirect (@Rn)
IMM
0
0
0
0 Bit No.:
op
rn
0
0
0
0 Operand: register indirect (@Rn)
op
rm
0
0
0
0 Bit No.:
op
15
8
15
8
7
0
7
abs
IMM
15
8
0
Operand: absolute (@aa:8)
0
0
7
0 Bit No.:
immediate (#xx:3)
0
op
abs
op
register direct (Rm)
0
op
op
immediate (#xx:3)
rm
0
Operand: absolute (@aa:8)
0
0
0 Bit No.:
register direct (Rm)
BAND, BOR, BXOR, BLD, BST
15
8
7
op
0
IMM
15
8
7
op
op
15
8
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
rn
0
rn
0
0
0
0 Operand: register indirect (@Rn)
IMM
0
0
0
0 Bit No.:
7
0
op
abs
op
immediate (#xx:3)
IMM
0
Operand: absolute (@aa:8)
0
0
0 Bit No.:
immediate (#xx:3)
[Legend]
op:
Operation field
rm, rn: Register field
abs:
Absolute address
IMM: Immediate data
Figure 2.7 Bit Manipulation Instruction Codes
Rev. 8.00 Mar. 09, 2010 Page 48 of 658
REJ09B0042-0800
Section 2 CPU
BIAND, BIOR, BIXOR, BILD, BIST
15
8
7
op
0
IMM
15
8
7
op
op
15
8
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
rn
0
rn
0
0
0
0 Operand: register indirect (@Rn)
IMM
0
0
0
0 Bit No.:
7
0
op
abs
op
immediate (#xx:3)
IMM
0
Operand: absolute (@aa:8)
0
0
0 Bit No.:
immediate (#xx:3)
[Legend]
op:
Operation field
rm, rn: Register field
abs:
Absolute address
IMM: Immediate data
Figure 2.7 Bit Manipulation Instruction Codes (cont)
Rev. 8.00 Mar. 09, 2010 Page 49 of 658
REJ09B0042-0800
Section 2 CPU
2.5.6
Branching Instructions
Table 2.9 describes the branching instructions. Figure 2.8 shows their object code formats.
Table 2.9
Branching Instructions
Instruction
Size
Function
Bcc
—
Branches to the designated address if condition cc is true. The
branching conditions are given below.
Mnemonic
Description
Condition
BRA (BT)
Always (true)
Always
BRN (BF)
Never (false)
Never
BHI
High
C∨Z=0
BLS
Low or same
C∨Z=1
BCC (BHS)
Carry clear (high or same)
C=0
BCS (BLO)
Carry set (low)
C=1
BNE
Not equal
Z=0
BEQ
Equal
Z=1
BVC
Overflow clear
V=0
BVS
Overflow set
V=1
BPL
Plus
N=0
BMI
Minus
N=1
BGE
Greater or equal
N⊕V=0
BLT
Less than
N⊕V=1
BGT
Greater than
Z ∨ (N ⊕ V) = 0
BLE
Less or equal
Z ∨ (N ⊕ V) = 1
JMP
—
Branches unconditionally to a specified address
BSR
—
Branches to a subroutine at a specified address
JSR
—
Branches to a subroutine at a specified address
RTS
—
Returns from a subroutine
Rev. 8.00 Mar. 09, 2010 Page 50 of 658
REJ09B0042-0800
Section 2 CPU
15
8
op
7
0
cc
15
disp
8
7
op
0
rm
15
Bcc
8
0
0
0
7
0
JMP (@Rm)
0
op
JMP (@aa:16)
abs
15
8
7
0
op
abs
15
8
JMP (@@aa:8)
7
0
op
disp
15
8
7
op
0
rm
15
BSR
8
0
0
0
7
0
JSR (@Rm)
0
op
JSR (@aa:16)
abs
15
8
7
op
0
abs
15
8
7
JSR (@@aa:8)
0
op
RTS
[Legend]
op: Operation field
cc: Condition field
rm: Register field
disp: Displacement
abs: Absolute address
Figure 2.8 Branching Instruction Codes
Rev. 8.00 Mar. 09, 2010 Page 51 of 658
REJ09B0042-0800
Section 2 CPU
2.5.7
System Control Instructions
Table 2.10 describes the system control instructions. Figure 2.9 shows their object code formats.
Table 2.10 System Control Instructions
Instruction
Size*
Function
RTE
—
Returns from an exception-handling routine
SLEEP
—
Causes a transition from active mode to a power-down mode. See
section 5, Power-Down Modes, for details.
LDC
B
Rs → CCR, #IMM → CCR
Moves immediate data or general register contents to the condition
code register
STC
B
CCR → Rd
Copies the condition code register to a specified general register
ANDC
B
CCR ∧ #IMM → CCR
Logically ANDs the condition code register with immediate data
ORC
B
CCR ∨ #IMM → CCR
Logically ORs the condition code register with immediate data
XORC
B
CCR ⊕ #IMM → CCR
Logically exclusive-ORs the condition code register with immediate
data
NOP
—
PC + 2 → PC
Only increments the program counter
Note:
*
Size: Operand size
B:
Byte
Rev. 8.00 Mar. 09, 2010 Page 52 of 658
REJ09B0042-0800
Section 2 CPU
15
8
7
0
op
15
8
RTE, SLEEP, NOP
7
0
op
15
rn
8
7
LDC, STC (Rn)
0
op
IMM
ANDC, ORC,
XORC, LDC (#xx:8)
[Legend]
op: Operation field
rn: Register field
IMM: Immediate data
Figure 2.9 System Control Instruction Codes
2.5.8
Block Data Transfer Instruction
Table 2.11 describes the block data transfer instruction. Figure 2.10 shows its object code format.
Table 2.11 Block Data Transfer Instruction
Instruction
Size
Function
EEPMOV
—
If R4L ≠ 0 then
repeat
until
@R5+ → @R6+
R4L – 1 → R4L
R4L = 0
else next;
Block transfer instruction. Transfers the number of data bytes
specified by R4L from locations starting at the address indicated by
R5 to locations starting at the address indicated by R6. After the
transfer, the next instruction is executed.
Certain precautions are required in using the EEPMOV instruction. See section 2.9.3, Notes on
Use of the EEPMOV Instruction, for details.
Rev. 8.00 Mar. 09, 2010 Page 53 of 658
REJ09B0042-0800
Section 2 CPU
15
8
7
op
op
[Legend]
op: Operation field
Figure 2.10 Block Data Transfer Instruction Code
Rev. 8.00 Mar. 09, 2010 Page 54 of 658
REJ09B0042-0800
0
Section 2 CPU
2.6
Basic Operational Timing
CPU operation is synchronized by a system clock (φ) or a subclock (φSUB). For details on these
clock signals see section 4, Clock Pulse Generators. The period from a rising edge of φ or φSUB to
the next rising edge is called one state. A bus cycle consists of two states or three states. The
cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules.
2.6.1
Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing
access in byte or word size. Figure 2.11 shows the on-chip memory access cycle.
Bus cycle
T1 state
T2 state
φ or φSUB
Internal address bus
Address
Internal read signal
Internal data bus
(read access)
Read data
Internal write signal
Internal data bus
(write access)
Write data
Figure 2.11 On-Chip Memory Access Cycle
Rev. 8.00 Mar. 09, 2010 Page 55 of 658
REJ09B0042-0800
Section 2 CPU
2.6.2
Access to On-Chip Peripheral Modules
On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits,
so access is by byte size only. This means that for accessing word data, two instructions must be
used. Figures 2.12 and 2.13 show the on-chip peripheral module access cycle.
Two-state access to on-chip peripheral modules
Bus cycle
T1 state
T2 state
φ or φSUB
Internal address bus
Address
Internal read signal
Internal data bus
(read access)
Read data
Internal write signal
Internal data bus
(write access)
Write data
Figure 2.12 On-Chip Peripheral Module Access Cycle (2-State Access)
Rev. 8.00 Mar. 09, 2010 Page 56 of 658
REJ09B0042-0800
Section 2 CPU
Three-state access to on-chip peripheral modules
Bus cycle
T1 state
T2 state
T3 state
φ or φSUB
Internal
address bus
Address
Internal
read signal
Internal
data bus
(read access)
Read data
Internal
write signal
Internal
data bus
(write access)
Write data
Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access)
2.7
CPU States
2.7.1
Overview
There are four CPU states: the reset state, program execution state, program halt state, and
exception-handling state. The program execution state includes active (high-speed or mediumspeed) mode and subactive mode. In the program halt state there are a sleep (high-speed or
medium-speed) mode, standby mode, watch mode, and sub-sleep mode. These states are shown in
figure 2.14. Figure 2.15 shows the state transitions.
Rev. 8.00 Mar. 09, 2010 Page 57 of 658
REJ09B0042-0800
Section 2 CPU
CPU state
Reset state
The CPU is initialized
Program
execution state
Active
(high speed) mode
The CPU executes successive program
instructions at high speed,
synchronized by the system clock
Active
(medium speed) mode
The CPU executes successive
program instructions at
reduced speed, synchronized
by the system clock
Subactive mode
The CPU executes
successive program
instructions at reduced
speed, synchronized
by the subclock
Program halt state
A state in which some
or all of the chip
functions are stopped
to conserve power
Low-power
modes
Sleep (high-speed)
mode
Sleep (medium-speed)
mode
Standby mode
Watch mode
Subsleep mode
Exceptionhandling state
A transient state in which the CPU changes
the processing flow due to a reset or an interrupt
Note: See section 5, Power-Down Modes, for details on the modes and their transitions.
Figure 2.14 CPU Operation States
Rev. 8.00 Mar. 09, 2010 Page 58 of 658
REJ09B0042-0800
Section 2 CPU
Reset cleared
Reset state
Exception-handling state
Reset occurs
Reset
occurs
Reset
occurs
Interrupt
source
occurs
Program halt state
Interrupt
source
occurs
Exceptionhandling
complete
Program execution state
SLEEP instruction executed
Figure 2.15 State Transitions
2.7.2
Program Execution State
In the program execution state the CPU executes program instructions in sequence.
There are three modes in this state, two active modes (high speed and medium speed) and one
subactive mode. Operation is synchronized with the system clock in active mode (high speed and
medium speed), and with the subclock in subactive mode. See section 5, Power-Down Modes for
details on these modes.
2.7.3
Program Halt State
In the program halt state there are five modes: two sleep modes (high speed and medium speed),
standby mode, watch mode, and subsleep mode. See section 5, Power-Down Modes for details on
these modes.
2.7.4
Exception-Handling State
The exception-handling state is a transient state occurring when exception handling is started by a
reset or interrupt and the CPU changes its normal processing flow. In exception handling caused
by an interrupt, SP (R7) is referenced and the PC and CCR values are saved on the stack.
For details on interrupt handling, see section 3.3, Interrupts.
Rev. 8.00 Mar. 09, 2010 Page 59 of 658
REJ09B0042-0800
Section 2 CPU
2.8
Memory Map
2.8.1
Memory Map
The memory map of the H8/38024, H8/38024S, and H8/38124 are shown in figure 2.16(1), that of
the H8/38023, H8/38023S, and H8/38123 in figure 2.16(2), that of the H8/38022, H8/38022S, and
H8/38122 in figure 2.16(3), that of the H8/38021, H8/38021S, and H8/38121 in figure 2.16(4),
and that of the H8/38020, H8/38020S, and H8/38120 in figure 2.16(5).
Rev. 8.00 Mar. 09, 2010 Page 60 of 658
REJ09B0042-0800
Section 2 CPU
HD64F38024, HD64F38024R, HD64F38124
(flash memory version)
H'0000
HD64338024 (mask ROM version)
HD64338024S (mask ROM version)
HD64338124 (mask ROM version)
HD64738024 (PROM version)
H'0000
Interrupt vector area
Interrupt vector area
H'0029
H'0029
H'002A
H'002A
On-chip ROM
32 Kbytes
(32768 bytes)
32 Kbytes
(32768 bytes)
On-chip ROM
H'7000
Firmware
for on-chip emulator*1
H'7FFF
H'7FFF
Not used
H'F020
H'F02B
Not used
Internal I/O register
Not used
H'F740
H'F740
H'F74F
LCD RAM (16 bytes)
H'F74F
LCD RAM (16 bytes)
Not used
H'F780
H'FB7F
H'FB80
Not used
(Workarea for reprogramming
flash memory: 1 Kbyte)*2
On-chip RAM
(2 Kbytes)
User area
(1 Kbyte)
H'FF7F
H'FB80
1024 bytes
On-chip RAM
H'FF7F
H'FF80
H'FF80
Internal I/O register
(128 bytes)
H'FFFF
1024 bytes
Internal I/O register
(128 bytes)
H'FFFF
Notes: 1. Not available to the user if the on-chip emulator is used.
2. Used by the programming control program when programming flash memory. Also, not available to the user
if the on-chip emulator is used.
Figure 2.16(1) H8/38024, H8/38024S, and H8/38124 Memory Map
Rev. 8.00 Mar. 09, 2010 Page 61 of 658
REJ09B0042-0800
Section 2 CPU
H'0000
Interrupt vector area
H'0029
H'002A
24 Kbytes
On-chip ROM
(24576 bytes)
H'5FFF
Not used
H'F740
LCD RAM
(16 bytes)
H'F74F
Not used
H'FB80
On-chip RAM
1024 bytes
H'FF7F
H'FF80
Internal I/O registers
(128 bytes)
H'FFFF
Figure 2.16(2) H8/38023, H8/38023S, and H8/38123 Memory Map
Rev. 8.00 Mar. 09, 2010 Page 62 of 658
REJ09B0042-0800
Section 2 CPU
Flash memory version
Mask ROM version
H'0000
H'0000
Interrupt vector area
Interrupt vector area
H'0029
H'0029
H'002A
H'002A
On-chip ROM
On-chip ROM
16 Kbytes
(16384 bytes)
H'3FFF
16 Kbytes
(16384 bytes)
H'3FFF
Not used
H'7000
Firmware
for on-chip emulator
H'7FFF
Not used
Not used
H'F020
H'F02B
Internal I/O register
Not used
H'F740
H'F740
H'F74F
LCD RAM (16 bytes)
H'F74F
LCD RAM (16 bytes)
Not used
H'F780
H'FB7F
H'FB80
Not used
(Workarea for reprogramming
flash memory: 1 Kbyte)*
On-chip RAM
(2 Kbytes)
User area
(1 Kbyte)
H'FB80
On-chip RAM
1024 bytes
H'FF7F
H'FF7F
H'FF80
H'FF80
Internal I/O register
(128 bytes)
Internal I/O register
(128 bytes)
H'FFFF
1024 bytes
H'FFFF
Note: * Used by the programming control program when programming flash memory. Also, not available to the user if
the on-chip emulator is used.
Figure 2.16(3) H8/38022, H8/38022S, and H8/38122 Memory Map
Rev. 8.00 Mar. 09, 2010 Page 63 of 658
REJ09B0042-0800
Section 2 CPU
H'0000
Interrupt vector area
H'0029
H'002A
12 Kbytes
On-chip ROM
(12288 bytes)
H'2FFF
Not used
H'F740
LCD RAM
(16 bytes)
H'F74F
Not used
H'FD80
On-chip RAM
512 bytes
H'FF7F
H'FF80
Internal I/O registers
(128 bytes)
H'FFFF
Figure 2.16(4) H8/38021, H8/38021S, and H8/38121 Memory Map
Rev. 8.00 Mar. 09, 2010 Page 64 of 658
REJ09B0042-0800
Section 2 CPU
H'0000
Interrupt vector area
H'0029
H'002A
8 Kbytes
On-chip ROM
(8192 bytes)
H'1FFF
Not used
H'F740
LCD RAM
(16 bytes)
H'F74F
Not used
H'FD80
On-chip RAM
512 bytes
H'FF7F
H'FF80
Internal I/O registers
(128 bytes)
H'FFFF
Figure 2.16(5) H8/38020, H8/38020S, and H8/38120 Memory Map
Rev. 8.00 Mar. 09, 2010 Page 65 of 658
REJ09B0042-0800
Section 2 CPU
2.9
Application Notes
2.9.1
Notes on Data Access
1. Access to Empty Areas:
The address space of the H8/300L CPU includes empty areas in addition to the RAM,
registers, and ROM areas available to the user. If these empty areas are mistakenly accessed
by an application program, the following results will occur.
Data transfer from CPU to empty area:
The transferred data will be lost. This action may also cause the CPU to misoperate.
Data transfer from empty area to CPU:
Unpredictable data is transferred.
2. Access to Internal I/O Registers:
Internal data transfer to or from on-chip modules other than the ROM and RAM areas makes
use of an 8-bit data width. If word access is attempted to these areas, the following results will
occur.
Word access from CPU to I/O register area:
Upper byte: Will be written to I/O register.
Lower byte: Transferred data will be lost.
Word access from I/O register to CPU:
Upper byte: Will be written to upper part of CPU register.
Lower byte: Unpredictable data will be written to lower part of CPU register.
Byte size instructions should therefore be used when transferring data to or from I/O registers
other than the on-chip ROM and RAM areas. Figure 2.17 shows the data size and number of
states in which on-chip peripheral modules can be accessed.
Rev. 8.00 Mar. 09, 2010 Page 66 of 658
REJ09B0042-0800
Section 2 CPU
Access
States
Word
Byte
H'0000
H'0029
Interrupt vector area
(42 bytes)
H'002A
2
32 Kbytes
On-chip ROM
*1
H'7FFF
⎯
Not used
H'F020
H'F02B
×
Internal I/O registers*3
⎯
Not used
H'F740
H'F74F
H'FB7F
*2
H'FB80
⎯
⎯
2
⎯
(1-Kbyte work area for flash
memory programming)*3
Internal RAM
User Area
⎯
2
LCD RAM
(16 bytes)
Not used
H'F780
⎯
⎯
⎯
2
2
1024 bytes
H'FF7F
H'FF80
Internal I/O registers
(128 bytes)
H'FF98 to H'FF9F
H'FFA8 to H'FFAF
H'FFFF
×
×
×
×
×
2
3
2
3
2
Notes: These examples apply to the H8/38024.
1. On the H8/38024, H8/38124, and H8/38024S, 32 Kbytes and the address is H'7FFF; on the
H8/38023, H8/38123, and H8/38023S, 24 Kbytes and the address is H'5FFF; on the
H8/38022, H8/38122, and H8/38022S, 16 Kbytes and the address is H'3FFF; on the
H8/38021, H8/38121, and H8/38021S, 12 Kbytes and the address is H'2FFF; on the
H8/38020, H8/38120, and H8/38020S, 8 Kbytes and the address is H'1FFF.
2. On the H8/38021, H8/38121, H8/38021S, H8/38020, H8/38120, and H8/38020S, 512 bytes
and the address is H'FD80.
3. Only the HD64F38024, HD64F38024R, HD64F38122, and HD64F38124 are equipped with
internal I/O registers from H'F020 to H'F02B and on-chip RAM from H'F780 to H'FB7F.
Attempting to access these areas on products other than the HD64F38024, HD64F38024R,
HD64F38122, and HD64F38124 will result in access to an empty area.
Figure 2.17 Data Size and Number of States for Access to and from
On-Chip Peripheral Modules
Rev. 8.00 Mar. 09, 2010 Page 67 of 658
REJ09B0042-0800
Section 2 CPU
2.9.2
Notes on Bit Manipulation
The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data,
then write the data byte again. Special care is required when using these instructions in cases
where two registers are assigned to the same address, in the case of registers that include writeonly bits, and when the instruction accesses an I/O port.
Order of Operation
Operation
1
Read
Read byte data at the designated address
2
Modify
Modify a designated bit in the read data
3
Write
Write the altered byte data to the designated address
1. Bit manipulation in two registers assigned to the same address
Example 1: timer load register and timer counter
Figure 2.18 shows an example in which two timer registers share the same address. When a bit
manipulation instruction accesses the timer load register and timer counter of a reloadable timer,
since these two registers share the same address, the following operations take place.
Order of Operation
Operation
1
Read
Timer counter data is read (one byte)
2
Modify
The CPU modifies (sets or resets) the bit designated in the instruction
3
Write
The altered byte data is written to the timer load register
The timer counter is counting, so the value read is not necessarily the same as the value in the
timer load register. As a result, bits other than the intended bit in the timer load register may be
modified to the timer counter value.
Read
Count clock
Timer counter
Reload
Write
Timer load register
Internal
data bus
Figure 2.18 Timer Configuration Example
Rev. 8.00 Mar. 09, 2010 Page 68 of 658
REJ09B0042-0800
Section 2 CPU
Example 2: BSET instruction executed designating port 3
P37 and P36 are designated as input pins, with a low-level signal input at P37 and a high-level
signal at P36. The remaining pins, P35 to P31, are output pins and output low-level signals. In this
example, the BSET instruction is used to change pin P30 to high-level output.
[A: Prior to executing BSET]
P37
Input/output Input
P36
P35
P34
P33
P32
P31
P30
Input
Output
Output
Output
Output
Output
Output
Pin state
Low level High level Low level Low level Low level Low level Low level Low level
PCR3
0
0
1
1
1
1
1
1
PDR3
1
0
0
0
0
0
0
0
[B: BSET instruction executed]
BSET
#0
,
The BSET instruction is executed designating port 3.
@PDR3
[C: After executing BSET]
P37
Input/output Input
P36
P35
P34
P33
P32
P31
P30
Input
Output
Output
Output
Output
Output
Output
Pin state
Low level High level Low level Low level Low level Low level Low level High level
PCR3
0
0
1
1
1
1
1
1
PDR3
0
1
0
0
0
0
0
1
[D: Explanation of how BSET operates]
When the BSET instruction is executed, first the CPU reads port 3.
Since P37 and P36 are input pins, the CPU reads the pin states (low-level and high-level input).
P35 to P30 are output pins, so the CPU reads the value in PDR3. In this example PDR3 has a value
of H'80, but the value read by the CPU is H'40.
Next, the CPU sets bit 0 of the read data to 1, changing the PDR3 data to H'41. Finally, the CPU
writes this value (H'41) to PDR3, completing execution of BSET.
As a result of this operation, bit 0 in PDR3 becomes 1, and P30 outputs a high-level signal.
However, bits 7 and 6 of PDR3 end up with different values.
Rev. 8.00 Mar. 09, 2010 Page 69 of 658
REJ09B0042-0800
Section 2 CPU
To avoid this problem, store a copy of the PDR3 data in a work area in memory. Perform the bit
manipulation on the data in the work area, then write this data to PDR3.
[A: Prior to executing BSET]
MOV. B
MOV. B
MOV. B
#80,
R0L,
R0L,
P37
Input/output Input
The PDR3 value (H'80) is written to a work area in memory
(RAM0) as well as to PDR3
R0L
@RAM0
@PDR3
P36
P35
P34
P33
P32
P31
P30
Input
Output
Output
Output
Output
Output
Output
Pin state
Low level High level Low level Low level Low level Low level Low level Low level
PCR3
0
0
1
1
1
1
1
1
PDR3
1
0
0
0
0
0
0
0
RAM0
1
0
0
0
0
0
0
0
[B: BSET instruction executed]
BSET
#0
,
The BSET instruction is executed designating the PDR3
work area (RAM0).
@RAM0
[C: After executing BSET]
MOV. B
MOV. B
The work area (RAM0) value is written to PDR3.
@RAM0, R0L
R0L, @PDR3
P37
Input/output Input
P36
P35
P34
P33
P32
P31
P30
Input
Output
Output
Output
Output
Output
Output
Pin state
Low level High level Low level Low level Low level Low level Low level High level
PCR3
0
0
1
1
1
1
1
1
PDR3
1
0
0
0
0
0
0
1
RAM0
1
0
0
0
0
0
0
1
Rev. 8.00 Mar. 09, 2010 Page 70 of 658
REJ09B0042-0800
Section 2 CPU
2. Bit manipulation in a register containing a write-only bit
Example 3: BCLR instruction executed designating port 3 control register PCR3
As in the examples above, P37 and P36 are input pins, with a low-level signal input at P37 and a
high-level signal at P36. The remaining pins, P35 to P30, are output pins that output low-level
signals. In this example, the BCLR instruction is used to change pin P30 to an input port. It is
assumed that a high-level signal will be input to this input pin.
[A: Prior to executing BCLR]
P37
Input/output Input
P36
P35
P34
P33
P32
P31
P30
Input
Output
Output
Output
Output
Output
Output
Pin state
Low level High level Low level Low level Low level Low level Low level Low level
PCR3
0
0
1
1
1
1
1
1
PDR3
1
0
0
0
0
0
0
0
[B: BCLR instruction executed]
BCLR
#0
,
The BCLR instruction is executed designating PCR3.
@PCR3
[C: After executing BCLR]
P37
Input/output Output
P36
P35
P34
P33
P32
P31
P30
Output
Output
Output
Output
Output
Output
Input
Pin state
Low level High level Low level Low level Low level Low level Low level High level
PCR3
1
1
1
1
1
1
1
0
PDR3
1
0
0
0
0
0
0
0
[D: Explanation of how BCLR operates]
When the BCLR instruction is executed, first the CPU reads PCR3. Since PCR3 is a write-only
register, the CPU reads a value of H'FF, even though the PCR3 value is actually H'3F.
Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE. Finally, this value
(H'FE) is written to PCR3 and BCLR instruction execution ends.
As a result of this operation, bit 0 in PCR3 becomes 0, making P30 an input port. However, bits 7
and 6 in PCR3 change to 1, so that P37 and P36 change from input pins to output pins.
Rev. 8.00 Mar. 09, 2010 Page 71 of 658
REJ09B0042-0800
Section 2 CPU
To avoid this problem, store a copy of the PCR3 data in a work area in memory. Perform the bit
manipulation on the data in the work area, then write this data to PCR3.
[A: Prior to executing BCLR]
MOV. B
MOV. B
MOV. B
#3F,
R0L,
R0L,
P37
Input/output Input
The PCR3 value (H'3F) is written to a work area in memory
(RAM0) as well as to PCR3.
R0L
@RAM0
@PCR3
P36
P35
P34
P33
P32
P31
P30
Input
Output
Output
Output
Output
Output
Output
Pin state
Low level High level Low level Low level Low level Low level Low level Low level
PCR3
0
0
1
1
1
1
1
1
PDR3
1
0
0
0
0
0
0
0
RAM0
0
0
1
1
1
1
1
1
[B: BCLR instruction executed]
BCLR
#0
,
The BCLR instruction is executed designating the PCR3
work area (RAM0).
@RAM0
[C: After executing BCLR]
MOV. B
MOV. B
The work area (RAM0) value is written to PCR3.
@RAM0, R0L
R0L, @PCR3
P37
Input/output Input
P36
P35
P34
P33
P32
P31
P30
Input
Output
Output
Output
Output
Output
Output
Pin state
Low level High level Low level Low level Low level Low level Low level High level
PCR3
0
0
1
1
1
1
1
0
PDR3
1
0
0
0
0
0
0
0
RAM0
0
0
1
1
1
1
1
0
Table 2.12 lists the pairs of registers that share identical addresses. Table 2.13 lists the registers
that contain write-only bits.
Rev. 8.00 Mar. 09, 2010 Page 72 of 658
REJ09B0042-0800
Section 2 CPU
Table 2.12 Registers with Shared Addresses
Register Name
Abbreviation
Address
Timer counter C/Timer load register C
Port data register 1*
TCC/TLC
H'FFB5
PDR1
H'FFD4
Port data register 3*
PDR3
H'FFD6
Port data register 4*
PDR4
H'FFD7
Port data register 5*
PDR5
H'FFD8
Port data register 6*
Port data register 7*
PDR6
H'FFD9
PDR7
H'FFDA
Port data register 8*
PDR8
H'FFDB
Port data register A*
PDRA
H'FFDD
Note: * Port data registers have the same addresses as input pins.
Table 2.13 Registers with Write-Only Bits
Register Name
Abbreviation
Address
Port control register 1
PCR1
H'FFE4
Port control register 3
PCR3
H'FFE6
Port control register 4
PCR4
H'FFE7
Port control register 5
PCR5
H'FFE8
Port control register 6
PCR6
H'FFE9
Port control register 7
PCR7
H'FFEA
Port control register 8
PCR8
H'FFEB
Port control register A
PCRA
H'FFED
Timer control register F
TCRF
H'FFB6
PWM1 control register
PWCR1
H'FFD0
PWM1 data register U
PWDRU1
H'FFD1
PWM1 data register L
PWDRL1
H'FFD2
PWM2 control register
PWCR2
H'FFCD
PWM2 data register U
PWDRU2
H'FFCE
PWM2 data register L
PWDRL2
H'FFCF
Event counter PWM data register H
ECPWDRH
H'FF8E
Event counter PWM data register L
ECPWDRL
H'FF8F
Rev. 8.00 Mar. 09, 2010 Page 73 of 658
REJ09B0042-0800
Section 2 CPU
2.9.3
Notes on Use of the EEPMOV Instruction
• The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes
specified by R4L from the address specified by R5 to the address specified by R6.
R5 →
← R6
R5 + R4L →
← R6 + R4L
• When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not
exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of
the instruction.
R5 →
R5 + R4L →
← R6
H'FFFF
Not allowed
Rev. 8.00 Mar. 09, 2010 Page 74 of 658
REJ09B0042-0800
← R6 + R4L
Section 3 Exception Handling
Section 3 Exception Handling
3.1
Overview
Exception handling is performed in the H8/38024 Group, H8/38024S Group, H8/38024F-ZTAT
Group, and H8/38124 Group when a reset or interrupt occurs. Table 3.1 shows the priorities of
these two types of exception handling.
Table 3.1
Exception Handling Types and Priorities
Priority
Exception Source
Time of Start of Exception Handling
High
Reset
Exception handling starts as soon as the reset state is cleared
Interrupt
When an interrupt is requested, exception handling starts after
execution of the present instruction or the exception handling in
progress is completed
Low
3.2
Reset
3.2.1
Overview
A reset is the highest-priority exception. The internal state of the CPU and the registers of the onchip peripheral modules are initialized.
3.2.2
Reset Sequence
As soon as the RES pin goes low, all processing is stopped and the chip enters the reset state.
To make sure the chip is reset properly, observe the following precautions.
• At power on: Hold the RES pin low until the clock pulse generator output stabilizes.
• Resetting during operation: Hold the RES pin low for at least 10 system clock cycles.
Reset exception handling takes place as follows.
• The CPU internal state and the registers of on-chip peripheral modules are initialized, with the
I bit of the condition code register (CCR) set to 1.
• The PC is loaded from the reset exception handling vector address (H'0000 to H'0001), after
which the program starts executing from the address indicated in PC.
Rev. 8.00 Mar. 09, 2010 Page 75 of 658
REJ09B0042-0800
Section 3 Exception Handling
When system power is turned on or off, the RES pin should be held low.
Figure 3.1 shows the reset sequence starting from RES input.
See section 14.3.1, Power-On Reset Circuit, for information on the reset sequence for the
H8/38124 Group, which is equipped with an on-chip power-on reset circuit.
Reset cleared
Program initial
instruction prefetch
Vector fetch Internal
processing
RES
φ
Internal
address bus
(1)
(2)
Internal read
signal
Internal write
signal
Internal data
bus (16-bit)
(2)
(3)
(1) Reset exception handling vector address (H'0000)
(2) Program start address
(3) First instruction of program
Figure 3.1 Reset Sequence
3.2.3
Interrupt Immediately after Reset
After a reset, if an interrupt were to be accepted before the stack pointer (SP: R7) was initialized,
PC and CCR would not be pushed onto the stack correctly, resulting in program runaway. To
prevent this, immediately after reset exception handling all interrupts are masked. For this reason,
the initial program instruction is always executed immediately after a reset. This instruction
should initialize the stack pointer (e.g. MOV.W #xx: 16, SP).
Rev. 8.00 Mar. 09, 2010 Page 76 of 658
REJ09B0042-0800
Section 3 Exception Handling
3.3
Interrupts
3.3.1
Overview
The interrupt sources include 13 external interrupts (WKP7 to WKP0, IRQ4, IRQ3, IRQ1, IRQ0,
IRQAEC) and 9 internal interrupts from on-chip peripheral modules. Table 3.2 shows the interrupt
sources, their priorities, and their vector addresses. When more than one interrupt is requested, the
interrupt with the highest priority is processed.
The interrupts have the following features:
• Internal and external interrupts can be masked by the I bit in CCR. When the I bit is set to 1,
interrupt request flags can be set but the interrupts are not accepted.
• IRQ4, IRQ3, IRQ1, IRQ0, and WKP7 to WKP0 can be set to either rising edge sensing or falling
edge sensing, and IRQAEC can be set to either rising edge sensing, falling edge sensing, or
both edge sensing.
Rev. 8.00 Mar. 09, 2010 Page 77 of 658
REJ09B0042-0800
Section 3 Exception Handling
Table 3.2
Interrupt Sources and Their Priorities
Interrupt Source
Interrupt
Vector Number Vector Address
Priority
RES
Reset
0
H'0000 to H'0001
High
IRQ0
LVDI*
IRQ0
Low-voltage detect interrupt*
4
H'0008 to H'0009
IRQ1
IRQ1
5
H'000A to H'000B
Watchdog timer
IRQAEC
IRQAEC
6
H'000C to H'000D
IRQ3
IRQ3
7
H'000E to H'000F
IRQ4
IRQ4
8
H'0010 to H'0011
WKP0
WKP1
WKP2
WKP3
WKP4
WKP5
WKP6
WKP7
WKP0
WKP1
WKP2
WKP3
WKP4
WKP5
WKP6
WKP7
9
H'0012 to H'0013
Timer A
Timer A overflow
11
H'0016 to H'0017
Asynchronous
event counter
Asynchronous event
counter overflow
12
H'0018 to H'0019
Timer C
Timer C overflow or underflow 13
H'001A to H'001B
Timer FL
Timer FL compare match
Timer FL overflow
14
H'001C to H'001D
Timer FH
Timer FH compare match
Timer FH overflow
15
H'001E to H'001F
Timer G
Timer G input capture
Timer G overflow
16
H'0020 to H'0021
SCI3
SCI3 transmit end
SCI3 transmit data empty
SCI3 receive data full
SCI3 overrun error
SCI3 framing error
SCI3 parity error
18
H'0024 to H'0025
A/D
A/D conversion end
19
H'0026 to H'0027
(SLEEP instruction
executed)
Direct transfer
20
H'0028 to H'0029
Low
Notes: Vector addresses H'0002 to H'0007, H'0014 to H'0015, and H'0022 to H'0023 are reserved
and cannot be used.
* The low-voltage detect interrupt triggered by the LVDI is only implemented on the
H8/38124 Group.
Rev. 8.00 Mar. 09, 2010 Page 78 of 658
REJ09B0042-0800
Section 3 Exception Handling
3.3.2
Interrupt Control Registers
Table 3.3 lists the registers that control interrupts.
Table 3.3
Interrupt Control Registers
Name
Abbreviation
R/W
Initial Value
Address
IRQ edge select register
IEGR
R/W
—
H'FFF2
Interrupt enable register 1
IENR1
R/W
—
H'FFF3
Interrupt enable register 2
IENR2
R/W
—
H'FFF4
IRR1
R/W *
—
H'FFF6
Interrupt request register 2
IRR2
R/W *
—
H'FFF7
Wakeup interrupt request register
IWPR
R/W *
H'00
H'FFF9
Wakeup edge select register
WEGR
R/W
H'00
H'FF90
Interrupt request register 1
Note: * Write is enabled only for writing of 0 to clear a flag.
IRQ Edge Select Register (IEGR)
Bit
7
6
5
4
3
2
1
0
⎯
⎯
⎯
IEG4
IEG3
⎯
IEG1
IEG0
Initial value
1
1
1
0
0
⎯
0
0
Read/Write
⎯
⎯
⎯
R/W
R/W
W
R/W
R/W
IEGR is an 8-bit read/write register used to designate whether pins IRQ4, IRQ3, IRQ1, and IRQ0
are set to rising edge sensing or falling edge sensing. For the IRQAEC pin edge sensing
specifications, see section 9.7, Asynchronous Event Counter (AEC).
Bits 7 to 5—Reserved
Bits 7 to 5 are reserved: they are always read as 1 and cannot be modified.
Rev. 8.00 Mar. 09, 2010 Page 79 of 658
REJ09B0042-0800
Section 3 Exception Handling
Bit 4—IRQ4 Edge Select (IEG4)
Bit 4 selects the input sensing of the IRQ4 pin and ADTRG pin.
Bit 4
IEG4
Description
0
Falling edge of IRQ4 and ADTRG pin input is detected
1
Rising edge of IRQ4 and ADTRG pin input is detected
(initial value)
Bit 3—IRQ3 Edge Select (IEG3)
Bit 3 selects the input sensing of the IRQ3 pin and TMIF pin.
Bit 3
IEG3
Description
0
Falling edge of IRQ3 and TMIF pin input is detected
1
Rising edge of IRQ3 and TMIF pin input is detected
(initial value)
Bit 2—Reserved
Bit 2 is reserved: it can only be written with 0.
Bit 1—IRQ1 Edge Select (IEG1)
Bit 1 selects the input sensing of the IRQ1 pin and TMIC pin.
Bit 1
IEG1
Description
0
Falling edge of IRQ1 and TMIC pin input is detected
1
Rising edge of IRQ1 and TMIC pin input is detected
(initial value)
Bit 0—IRQ0 Edge Select (IEG0)
Bit 0 selects the input sensing of pin IRQ0.
Bit 0
IEG0
Description
0
Falling edge of IRQ0 pin input is detected
1
Rising edge of IRQ0 pin input is detected
Rev. 8.00 Mar. 09, 2010 Page 80 of 658
REJ09B0042-0800
(initial value)
Section 3 Exception Handling
Interrupt Enable Register 1 (IENR1)
Bit
7
6
5
4
3
2
1
0
IENTA
⎯
IENWP
IEN4
IEN3
IENEC2
IEN1
IEN0
Initial value
0
⎯
0
0
0
0
0
0
Read/Write
R/W
W
R/W
R/W
R/W
R/W
R/W
R/W
IENR1 is an 8-bit read/write register that enables or disables interrupt requests.
Bit 7—Timer A Interrupt Enable (IENTA)
Bit 7 enables or disables timer A overflow interrupt requests.
Bit 7
IENTA
Description
0
Disables timer A interrupt requests
1
Enables timer A interrupt requests
(initial value)
Bit 6—Reserved
Bit 6 is reserved: it can only be written with 0.
Bit 5—Wakeup Interrupt Enable (IENWP)
Bit 5 enables or disables WKP7 to WKP0 interrupt requests.
Bit 5
IENWP
Description
0
Disables WKP7 to WKP0 interrupt requests
1
Enables WKP7 to WKP0 interrupt requests
(initial value)
Bits 4 and 3—IRQ4 and IRQ3 Interrupt Enable (IEN4 and IEN3)
Bits 4 and 3 enable or disable IRQ4 and IRQ3 interrupt requests.
Bit n
IENn
Description
0
Disables interrupt requests from pin IRQn
1
Enables interrupt requests from pin IRQn
(initial value)
(n = 4 or 3)
Rev. 8.00 Mar. 09, 2010 Page 81 of 658
REJ09B0042-0800
Section 3 Exception Handling
Bit 2—IRQAEC Interrupt Enable (IENEC2)
Bit 2 enables or disables IRQAEC interrupt requests.
Bit 2
IENEC2
Description
0
Disables IRQAEC interrupt requests
1
Enables IRQAEC interrupt requests
(initial value)
Bits 1 and 0—IRQ1 and IRQ0 Interrupt Enable (IEN1 and IEN0)
Bits 1 and 0 enable or disable IRQ1 and IRQ0 interrupt requests.
Bit n
IENn
Description
0
Disables interrupt requests from pin IRQn
1
Enables interrupt requests from pin IRQn
(initial value)
(n = 1 or 0)
Interrupt Enable Register 2 (IENR2)
Bit
7
6
5
4
IENDT
IENAD
—
IENTG
3
1
0
IENTC
IENEC
2
IENTFH IENTFL
Initial value
0
0
—
0
0
0
0
0
Read/Write
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
IENR2 is an 8-bit read/write register that enables or disables interrupt requests.
Bit 7—Direct Transfer Interrupt Enable (IENDT)
Bit 7 enables or disables direct transfer interrupt requests.
Bit 7
IENDT
Description
0
Disables direct transfer interrupt requests
1
Enables direct transfer interrupt requests
Rev. 8.00 Mar. 09, 2010 Page 82 of 658
REJ09B0042-0800
(initial value)
Section 3 Exception Handling
Bit 6—A/D Converter Interrupt Enable (IENAD)
Bit 6 enables or disables A/D converter interrupt requests.
Bit 6
IENAD
Description
0
Disables A/D converter interrupt requests
1
Enables A/D converter interrupt requests
(initial value)
Bit 5—Reserved
Bit 5 is reserved bit: it can only be written with 0.
Bit 4—Timer G Interrupt Enable (IENTG)
Bit 4 enables or disables timer G input capture or overflow interrupt requests.
Bit 4
IENTG
Description
0
Disables timer G interrupt requests
1
Enables timer G interrupt requests
(initial value)
Bit 3—Timer FH Interrupt Enable (IENTFH)
Bit 3 enables or disables timer FH compare match and overflow interrupt requests.
Bit 3
IENTFH
Description
0
Disables timer FH interrupt requests
1
Enables timer FH interrupt requests
(initial value)
Bit 2—Timer FL Interrupt Enable (IENTFL)
Bit 2 enables or disables timer FL compare match and overflow interrupt requests.
Bit 2
IENTFL
Description
0
Disables timer FL interrupt requests
1
Enables timer FL interrupt requests
(initial value)
Rev. 8.00 Mar. 09, 2010 Page 83 of 658
REJ09B0042-0800
Section 3 Exception Handling
Bit 1—Timer C Interrupt Enable (IENTC)
Bit 1 enables or disables timer C overflow and underflow interrupt requests.
Bit 1
IENTC
Description
0
Disables timer C interrupt requests
1
Enables timer C interrupt requests
(initial value)
Bit 0—Asynchronous Event Counter Interrupt Enable (IENEC)
Bit 0 enables or disables asynchronous event counter interrupt requests.
Bit 0
IENEC
Description
0
Disables asynchronous event counter interrupt requests
1
Enables asynchronous event counter interrupt requests
(initial value)
For details of SCI3 interrupt control, see section 10.2.6 Serial control register 3 (SCR3).
Interrupt Request Register 1 (IRR1)
Bit
7
6
5
4
3
2
1
0
IRRTA
⎯
⎯
IRRI4
IRRI3
IRREC2
IRRI1
IRRI0
Initial value
0
⎯
1
0
0
0
0
0
Read/Write
R/(W)*
⎯
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
W
Note: * Only a write of 0 for flag clearing is possible
IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer A,
IRQAEC, IRQ4, IRQ3, IRQ1, or IRQ0 interrupt is requested. The flags are not cleared
automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag.
Rev. 8.00 Mar. 09, 2010 Page 84 of 658
REJ09B0042-0800
Section 3 Exception Handling
Bit 7—Timer A Interrupt Request Flag (IRRTA)
Bit 7
IRRTA
Description
0
Clearing condition:
When IRRTA = 1, it is cleared by writing 0
1
Setting condition:
When the timer A counter value overflows
(initial value)
Bit 6—Reserved
Bit 6 is reserved; it can only be written with 0.
Bit 5—Reserved
Bit 5 is reserved; it is always read as 1 and cannot be modified.
Bits 4 and 3—IRQ4 and IRQ3 Interrupt Request Flags (IRRI4 and IRRI3)
Bit n
IRRIn
Description
0
Clearing condition:
When IRRIn = 1, it is cleared by writing 0
(initial value)
1
Setting condition:
When pin IRQn is designated for interrupt input and the designated signal edge is
input
(n = 4 or 3)
Bit 2—IRQAEC Interrupt Request Flag (IRREC2)
Bit 2
IRREC2
Description
0
Clearing condition:
When IRREC2 = 1, it is cleared by writing 0
(initial value)
1
Setting condition:
When pin IRQAEC is designated for interrupt input and the designated signal edge is
input
Rev. 8.00 Mar. 09, 2010 Page 85 of 658
REJ09B0042-0800
Section 3 Exception Handling
Bits 1 and 0—IRQ1 and IRQ0 Interrupt Request Flags (IRRI1 and IRRI0)
Bit n
IRRIn
Description
0
Clearing condition:
When IRRIn = 1, it is cleared by writing 0
(initial value)
1
Setting condition:
When pin IRQn is designated for interrupt input and the designated signal edge is
input
(n = 1 or 0)
Interrupt Request Register 2 (IRR2)
Bit
7
6
5
4
3
2
1
0
IRRDT
IRRAD
⎯
IRRTG
IRRTC
IRREC
Initial value
0
0
⎯
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
W
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
IRRTFH IRRTFL
Note: * Only a write of 0 for flag clearing is possible
IRR2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct
transfer, A/D converter, Timer G, Timer FH, Timer FL, Timer C, or asynchronous event counter
interrupt is requested. The flags are not cleared automatically when an interrupt is accepted. It is
necessary to write 0 to clear each flag.
Bit 7—Direct Transfer Interrupt Request Flag (IRRDT)
Bit 7
IRRDT
Description
0
Clearing condition:
When IRRDT = 1, it is cleared by writing 0
1
Setting condition:
When a direct transfer is made by executing a SLEEP instruction while DTON = 1 in
SYSCR2
Rev. 8.00 Mar. 09, 2010 Page 86 of 658
REJ09B0042-0800
(initial value)
Section 3 Exception Handling
Bit 6—A/D Converter Interrupt Request Flag (IRRAD)
Bit 6
IRRAD
Description
0
Clearing condition:
When IRRAD = 1, it is cleared by writing 0
(initial value)
1
Setting condition:
When A/D conversion is completed and ADSF is cleared to 0 in ADSR
Bit 5—Reserved
Bit 5 is reserved: it can only be written with 0.
Bit 4—Timer G Interrupt Request Flag (IRRTG)
Bit 4
IRRTG
Description
0
Clearing condition:
When IRRTG = 1, it is cleared by writing 0
(initial value)
1
Setting condition:
When the TMIG pin is designated for TMIG input and the designated signal edge is
input, and when TCG overflows while OVIE is set to 1 in TMG
Bit 3—Timer FH Interrupt Request Flag (IRRTFH)
Bit 3
IRRTFH
Description
0
Clearing condition:
When IRRTFH = 1, it is cleared by writing 0
(initial value)
1
Setting condition:
When TCFH and OCRFH match in 8-bit timer mode, or when TCF (TCFL, TCFH)
and OCRF (OCRFL, OCRFH) match in 16-bit timer mode
Rev. 8.00 Mar. 09, 2010 Page 87 of 658
REJ09B0042-0800
Section 3 Exception Handling
Bit 2—Timer FL Interrupt Request Flag (IRRTFL)
Bit 2
IRRTFL
Description
0
Clearing condition:
When IRRTFL = 1, it is cleared by writing 0
1
Setting condition:
When TCFL and OCRFL match in 8-bit timer mode
(initial value)
Bit 1—Timer C Interrupt Request Flag (IRRTC)
Bit 1
IRRTC
Description
0
Clearing condition:
When IRRTC = 1, it is cleared by writing 0
1
Setting condition:
When the timer C counter value overflows or underflows
(initial value)
Bit 0—Asynchronous Event Counter Interrupt Request Flag (IRREC)
Bit 0
IRREC
Description
0
Clearing condition:
When IRREC = 1, it is cleared by writing 0
1
Setting condition:
When ECH overflows in 16-bit counter mode, or ECH or ECL overflows in 8-bit
counter mode
Rev. 8.00 Mar. 09, 2010 Page 88 of 658
REJ09B0042-0800
(initial value)
Section 3 Exception Handling
Wakeup Interrupt Request Register (IWPR)
Bit
7
6
5
4
3
2
1
0
IWPF7
IWPF6
IWPF5
IWPF4
IWPF3
IWPF2
IWPF1
IWPF0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Note: * Only a write of 0 for flag clearing is possible
IWPR is an 8-bit read/write register containing wakeup interrupt request flags. When one of pins
WKP7 to WKP0 is designated for wakeup input and a rising or falling edge is input at that pin, the
corresponding flag in IWPR is set to 1. A flag is not cleared automatically when the
corresponding interrupt is accepted. Flags must be cleared by writing 0.
Bits 7 to 0—Wakeup Interrupt Request Flags (IWPF7 to IWPF0)
Bit n
IWPFn
Description
0
Clearing condition:
When IWPFn= 1, it is cleared by writing 0
(initial value)
1
Setting condition:
When pin WKPn is designated for wakeup input and a rising or falling edge is input at
that pin
(n = 7 to 0)
Rev. 8.00 Mar. 09, 2010 Page 89 of 658
REJ09B0042-0800
Section 3 Exception Handling
Wakeup Edge Select Register (WEGR)
Bit
7
6
5
4
3
2
1
0
WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WEGR is an 8-bit read/write register that specifies rising or falling edge sensing for pins WKPn.
WEGR is initialized to H'00 by a reset.
Bit n—WKPn Edge Select (WKEGSn)
Bit n selects WKPn pin input sensing.
Bit n
WKEGSn
Description
0
WKPn pin falling edge detected
1
WKPn pin rising edge detected
(initial value)
(n = 7 to 0)
3.3.3
External Interrupts
There are 13 external interrupts: WKP7 to WKP0, IRQ4, IRQ3, IRQ1, IRQ0, and IRQAEC.
Interrupts WKP7 to WKP0
Interrupts WKP7 to WKP0 are requested by either rising or falling edge input to pins WKP7 to
WKP0. When these pins are designated as pins WKP7 to WKP0 in port mode register 5 and a
rising or falling edge is input, the corresponding bit in IWPR is set to 1, requesting an interrupt.
Recognition of wakeup interrupt requests can be disabled by clearing the IENWP bit to 0 in
IENR1. These interrupts can all be masked by setting the I bit to 1 in CCR.
When WKP7 to WKP0 interrupt exception handling is initiated, the I bit is set to 1 in CCR.
Vector number 9 is assigned to interrupts WKP7 to WKP0. All eight interrupt sources have the
same vector number, so the interrupt-handling routine must discriminate the interrupt source.
Rev. 8.00 Mar. 09, 2010 Page 90 of 658
REJ09B0042-0800
Section 3 Exception Handling
Interrupts IRQ4, IRQ3, IRQ1 and IRQ0
Interrupts IRQ4, IRQ3, IRQ1, and IRQ0 are requested by input signals to pins IRQ4, IRQ3, IRQ1,
and IRQ0. These interrupts are detected by either rising edge sensing or falling edge sensing,
depending on the settings of bits IEG4, IEG3, IEG1, and IEG0 in IEGR.
When these pins are designated as pins IRQ4, IRQ3, IRQ1, and IRQ0 in port mode register B, 2,
and 1 and the designated edge is input, the corresponding bit in IRR1 is set to 1, requesting an
interrupt. Recognition of these interrupt requests can be disabled individually by clearing bits
IEN4, IEN3, IEN1, and IEN0 to 0 in IENR1. These interrupts can all be masked by setting the I
bit to 1 in CCR.
When IRQ4, IRQ3, IRQ1, and IRQ0 interrupt exception handling is initiated, the I bit is set to 1 in
CCR. Vector numbers 8, 7, 5, and 4 are assigned to interrupts IRQ4, IRQ3, IRQ1, and IRQ0. The
order of priority is from IRQ0 (high) to IRQ4 (low). Table 3.2 gives details.
IRQAEC Interrupt
The IRQAEC interrupt is requested by an input signal to pin IRQAEC and IECPWM (output of
PWM for AEC). When the IRQAEC input pin is to be used as an external interrupt, set ECPWME
in AEGSR to 0. This interrupt is detected by rising edge, falling edge, or both edge sensing,
depending on the settings of bits AIEGS1 and AIEGS0 in AEGSR.
When bit IENEC2 in IENR1 is 1 and the designated edge is input, the corresponding bit in IRR1 is
set to 1, requesting an interrupt.
When IRQAEC interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector
number 6 is assigned to the IRQAEC interrupt exception handling. Table 3.2 gives details.
3.3.4
Internal Interrupts
There are 9 internal interrupts that can be requested by the on-chip peripheral modules. When a
peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1.
Recognition of individual interrupt requests can be disabled by clearing the corresponding bit in
IENR1 or IENR2. All these interrupts can be masked by setting the I bit to 1 in CCR. When
internal interrupt handling is initiated, the I bit is set to 1 in CCR. Vector numbers from 20 to 18
and 16 to 11 are assigned to these interrupts. Table 3.2 shows the order of priority of interrupts
from on-chip peripheral modules.
Rev. 8.00 Mar. 09, 2010 Page 91 of 658
REJ09B0042-0800
Section 3 Exception Handling
3.3.5
Interrupt Operations
Interrupts are controlled by an interrupt controller. Figure 3.2 shows a block diagram of the
interrupt controller. Figure 3.3 shows the flow up to interrupt acceptance.
Priority decision logic
Interrupt controller
External or
internal
interrupts
Interrupt
request
External
interrupts or
internal
interrupt
enable
signals
I
CCR (CPU)
Figure 3.2 Block Diagram of Interrupt Controller
Interrupt operation is described as follows.
• When an interrupt condition is met while the interrupt enable register bit is set to 1, an
interrupt request signal is sent to the interrupt controller.
• When the interrupt controller receives an interrupt request, it sets the interrupt request flag.
• From among the interrupts with interrupt request flags set to 1, the interrupt controller selects
the interrupt request with the highest priority and holds the others pending. (Refer to table 3.2
for a list of interrupt priorities.)
• The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request
is accepted; if the I bit is 1, the interrupt request is held pending.
Rev. 8.00 Mar. 09, 2010 Page 92 of 658
REJ09B0042-0800
Section 3 Exception Handling
• If the interrupt request is accepted, after processing of the current instruction is completed,
both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in
figure 3.4. The PC value pushed onto the stack is the address of the first instruction to be
executed upon return from interrupt handling.
• The I bit of CCR is set to 1, masking further interrupts.
• The vector address corresponding to the accepted interrupt is generated, and the interrupt
handling routine located at the address indicated by the contents of the vector address is
executed.
Notes: 1. When disabling interrupts by clearing bits in an interrupt enable register, or when
clearing bits in an interrupt request register, always do so while interrupts are masked
(I = 1).
2. If the above clear operations are performed while I = 0, and as a result a conflict arises
between the clear instruction and an interrupt request, exception processing for the
interrupt will be executed after the clear instruction has been executed.
Rev. 8.00 Mar. 09, 2010 Page 93 of 658
REJ09B0042-0800
Section 3 Exception Handling
Program execution state
IRRI0 = 1
No
Yes
IEN0 = 1
No
Yes
IRRI1 = 1
No
Yes
IEN1 = 1
Yes
No
IRREC2 = 1
No
Yes
IENEC2 = 1
No
Yes
IRRDT = 1
No
Yes
IENDT = 1
Yes
No
I=0
Yes
PC contents saved
CCR contents saved
I←1
Branch to interrupt
handling routine
[Legend]
PC: Program counter
CCR: Condition code register
I bit of CCR
I:
Figure 3.3 Flow up to Interrupt Acceptance
Rev. 8.00 Mar. 09, 2010 Page 94 of 658
REJ09B0042-0800
No
Section 3 Exception Handling
SP − 4
SP (R7)
CCR
SP − 3
SP + 1
CCR*
SP − 2
SP + 2
PCH
SP − 1
SP + 3
PCL
SP (R7)
SP + 4
Even address
Stack area
Prior to start of interrupt
exception handling
PC and CCR
saved to stack
After completion of interrupt
exception handling
[Legend]
PCH: Upper 8 bits of program counter (PC)
Lower 8 bits of program counter (PC)
PCL:
CCR: Condition code register
Stack pointer
SP:
Notes: 1. PC shows the address of the first instruction to be executed upon
return from the interrupt handling routine.
2. Register contents must always be saved and restored by word access,
starting from an even-numbered address.
* Ignored on return.
Figure 3.4 Stack State after Completion of Interrupt Exception Handling
Figure 3.5 shows a typical interrupt sequence.
Rev. 8.00 Mar. 09, 2010 Page 95 of 658
REJ09B0042-0800
Rev. 8.00 Mar. 09, 2010 Page 96 of 658
REJ09B0042-0800
Internal data bus
(16 bits)
Internal write
signal
Internal read
signal
Internal
address bus
φ
Interrupt
request signal
Figure 3.5 Interrupt Sequence
(4)
Instruction
prefetch
(3)
Internal
processing
(5)
(1)
Stack access
(6)
(7)
(9)
Vector fetch
(8)
(10)
(9)
Prefetch instruction of
Internal
interrupt-handling routine
processing
(1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.)
(2)(4) Instruction code (not executed)
(3) Instruction prefetch address (Instruction is not executed.)
(5) SP − 2
(6) SP − 4
(7) CCR
(8) Vector address
(9) Starting address of interrupt-handling routine (contents of vector)
(10) First instruction of interrupt-handling routine
(2)
(1)
Interrupt level
decision and wait for
end of instruction
Interrupt is
accepted
Section 3 Exception Handling
Section 3 Exception Handling
3.3.6
Interrupt Response Time
Table 3.4 shows the number of wait states after an interrupt request flag is set until the first
instruction of the interrupt handler is executed.
Table 3.4
Interrupt Wait States
Item
States
Total
Waiting time for completion of executing instruction*
1 to 13
15 to 27
Saving of PC and CCR to stack
4
Vector fetch
2
Instruction fetch
4
Internal processing
4
Note: * Not including EEPMOV instruction.
Rev. 8.00 Mar. 09, 2010 Page 97 of 658
REJ09B0042-0800
Section 3 Exception Handling
3.4
Application Notes
3.4.1
Notes on Stack Area Use
When word data is accessed in the LSI, the least significant bit of the address is regarded as 0.
Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never
indicate an odd address. Use PUSH Rn (MOV.W Rn, @–SP) or POP Rn (MOV.W @SP+, Rn) to
save or restore register values.
Setting an odd address in SP may cause a program to crash. An example is shown in figure 3.6.
SP →
SP →
PCH
PC L
R1L
PC L
SP →
H'FEFC
H'FEFD
H'FEFF
BSR instruction
SP set to H'FEFF
MOV. B R1L, @−R7
Stack accessed beyond SP
Contents of PCH are lost
[Legend]
PCH: Upper byte of program counter
PCL: Lower byte of program counter
R1L: General register R1L
SP: Stack pointer
Figure 3.6 Operation when Odd Address is Set in SP
When CCR contents are saved to the stack during interrupt exception handling or restored when
RTE is executed, this also takes place in word size. Both the upper and lower bytes of word data
are saved to the stack; on return, the even address contents are restored to CCR while the odd
address contents are ignored.
Rev. 8.00 Mar. 09, 2010 Page 98 of 658
REJ09B0042-0800
Section 3 Exception Handling
3.4.2
Notes on Rewriting Port Mode Registers
When a port mode register is rewritten to switch the functions of external interrupt pins and when
the value of ECPWME in AEGSR is rewritten to switch between selection/non-selection of
IRQAEC, the following points should be observed.
When an external interrupt pin function is switched by rewriting the port mode register that
controls pins IRQ4, IRQ3, IRQ1, IRQ0, WKP7 to WKP0, the interrupt request flag may be set to 1 at
the time the pin function is switched, even if no valid interrupt is input at the pin. Be sure to clear
the interrupt request flag to 0 after switching pin functions. When the value of ECPWME in
AEGSR that sets selection/non-selection of IRQAEC is rewritten, the interrupt request flag may
be set to 1, even if a valid edge has not arrived on the selected IRQAEC or IECPWM (PWM
output for AEC). Therefore, be sure to clear the interrupt request flag to 0 after switching the pin
function. Table 3.5 shows the conditions under which interrupt request flags are set to 1 in this
way.
Table 3.5
Conditions under which Interrupt Request Flag is Set to 1
Interrupt Request
Flags Set to 1
IRR1
IRRI4
Conditions
When PMR1 bit IRQ4 is changed from 0 to 1 while pin IRQ4 is low and IEGR bit
IEG4 = 0.
When PMR1 bit IRQ4 is changed from 1 to 0 while pin IRQ4 is low and IEGR bit
IEG4 = 1.
IRRI3
When PMR1 bit IRQ3 is changed from 0 to 1 while pin IRQ3 is low and IEGR bit
IEG3 = 0.
When PMR1 bit IRQ3 is changed from 1 to 0 while pin IRQ3 is low and IEGR bit
IEG3 = 1.
IRREC2
When an edge as designated by AIEGS1 and AIEGS0 in AEGSR is detected
because the values on the IRQAEC pin and of IECPWM at switching are different
(e.g., when the rising edge has been selected and ECPWME in AEGSR is changed
from 1 to 0 while pin IRQAEC is low and IECPWM = 1).
IRRI1
When PMRB bit IRQ1 is changed from 0 to 1 while pin IRQ1 is low and IEGR bit
IEG1 = 0.
When PMRB bit IRQ1 is changed from 1 to 0 while pin IRQ1 is low and IEGR bit
IEG1 = 1.
IRRI0
When PMR2 bit IRQ0 is changed from 0 to 1 while pin IRQ0 is low and IEGR bit
IEG0 = 0.
When PMR2 bit IRQ0 is changed from 1 to 0 while pin IRQ0 is low and IEGR bit
IEG0 = 1.
Rev. 8.00 Mar. 09, 2010 Page 99 of 658
REJ09B0042-0800
Section 3 Exception Handling
Interrupt Request
Flags Set to 1
IWPR
IWPF7
Conditions
When PMR5 bit WKP7 is changed from 0 to 1 while pin WKP7 is low and WEGR bit
WKEGS7 = 0.
When PMR5 bit WKP7 is changed from 1 to 0 while pin WKP7 is low and WEGR bit
WKEGS7 = 1.
IWPF6
When PMR5 bit WKP6 is changed from 0 to 1 while pin WKP6 is low and WEGR bit
WKEGS6 = 0.
When PMR5 bit WKP6 is changed from 1 to 0 while pin WKP6 is low and WEGR bit
WKEGS6 = 1.
IWPF5
When PMR5 bit WKP5 is changed from 0 to 1 while pin WKP5 is low and WEGR bit
WKEGS5 = 0.
When PMR5 bit WKP5 is changed from 1 to 0 while pin WKP5 is low and WEGR bit
WKEGS5 = 1.
IWPF4
When PMR5 bit WKP4 is changed from 0 to 1 while pin WKP4 is low and WEGR bit
WKEGS4 = 0.
When PMR5 bit WKP4 is changed from 1 to 0 while pin WKP4 is low and WEGR bit
WKEGS4 = 1.
IWPF3
When PMR5 bit WKP3 is changed from 0 to 1 while pin WKP3 is low and WEGR bit
WKEGS3 = 0.
When PMR5 bit WKP3 is changed from 1 to 0 while pin WKP3 is low and WEGR bit
WKEGS3 = 1.
IWPF2
When PMR5 bit WKP2 is changed from 0 to 1 while pin WKP2 is low and WEGR bit
WKEGS2 = 0.
When PMR5 bit WKP2 is changed from 1 to 0 while pin WKP2 is low and WEGR bit
WKEGS2 = 1.
IWPF1
When PMR5 bit WKP1 is changed from 0 to 1 while pin WKP1 is low and WEGR bit
WKEGS1 = 0.
When PMR5 bit WKP1 is changed from 1 to 0 while pin WKP1 is low and WEGR bit
WKEGS1 = 1.
IWPF0
When PMR5 bit WKP0 is changed from 0 to 1 while pin WKP0 is low and WEGR bit
WKEGS0 = 0.
When PMR5 bit WKP0 is changed from 1 to 0 while pin WKP0 is low and WEGR bit
WKEGS0 = 1.
Figure 3.7 shows the procedure for setting a bit in a port mode register and clearing the interrupt
request flag.
When switching a pin function, mask the interrupt before setting the bit in the port mode register
(or AEGSR). After accessing the port mode register (or AEGSR), execute at least one instruction
(e.g., NOP), then clear the interrupt request flag from 1 to 0. If the instruction to clear the flag is
Rev. 8.00 Mar. 09, 2010 Page 100 of 658
REJ09B0042-0800
Section 3 Exception Handling
executed immediately after the port mode register (or AEGSR) access without executing an
intervening instruction, the flag will not be cleared.
An alternative method is to avoid the setting of interrupt request flags when pin functions are
switched by keeping the pins at the high level so that the conditions in table 3.5 do not occur.
However, the procedure in Figure 3.7 is recommended because IECPWM is an internal signal and
determining its value is complicated.
CCR I bit ← 1
Interrupts masked. (Another possibility
is to disable the relevant interrupt in
interrupt enable register 1.)
Set port mode register (or AEGSR) bit
Execute NOP instruction
After setting the port mode register
(or AEGSR) bit, first execute at least
one instruction (e.g., NOP), then clear
the interrupt request flag to 0
Clear interrupt request flag to 0
CCR I bit ← 0
Interrupt mask cleared
Figure 3.7 Port Mode Register (or AEGSR) Setting and Interrupt Request Flag
Clearing Procedure
3.4.3
Method for Clearing Interrupt Request Flags
Use the recommended method, given below when clearing the flags of interrupt request registers
(IRR1, IRR2, IWPR).
• Recommended method
Use a single instruction to clear flags. The bit control instruction and byte-size data transfer
instruction can be used. Two examples of program code for clearing IRRI1 (bit 1 of IRR1) are
given below.
BCLR
#1,
@IRR1:8
MOV.B R1L, @IRR1:8 (set the value of R1L to B'11111101)
Rev. 8.00 Mar. 09, 2010 Page 101 of 658
REJ09B0042-0800
Section 3 Exception Handling
• Example of a malfunction
When flags are cleared with multiple instructions, other flags might be cleared during
execution of the instructions, even though they are currently set, and this will cause a
malfunction.
Here is an example in which IRRI0 is cleared and disabled in the process of clearing IRRI1
(bit 1 of IRR1).
MOV.B @IRR1:8,R1L ......... IRRI0 = 0 at this time
AND.B #B'11111101,R1L ..... Here, IRRI0 = 1
MOV.B R1L,@IRR1:8 ......... IRRI0 is cleared to 0
In the above example, it is assumed that an IRQ0 interrupt is generated while the AND.B
instruction is executing.
The IRQ0 interrupt is disabled because, although the original objective is clearing IRRI1,
IRRI0 is also cleared.
Rev. 8.00 Mar. 09, 2010 Page 102 of 658
REJ09B0042-0800
Section 4 Clock Pulse Generators
Section 4 Clock Pulse Generators
4.1
Overview
Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a
system clock pulse generator and a subclock pulse generator. The system clock pulse generator
consists of a system clock oscillator and system clock dividers. The subclock pulse generator
consists of a subclock oscillator circuit and a subclock divider.
In the H8/38124 Group, the system clock pulse generator includes an on-chip oscillator.
4.1.1
Block Diagram
Figure 4.1 shows a block diagram of the clock pulse generators of the H8/38024, H8/38024S, and
H8/38024R Group. Figure 4.2 shows a block diagram of the clock pulse generators of the
H8/38124 Group.
OSC 1
OSC 2
System clock
oscillator
φOSC
(fOSC)
φOSC/2
System clock
divider (1/2)
System
clock
divider
φOSC/128
φOSC/64
φOSC/32
φOSC/16
φ
Prescaler S
(13 bits)
System clock pulse generator
X1
X2
Subclock
oscillator
φW
(fW)
Subclock
divider
(1/2, 1/4, 1/8)
Subclock pulse generator
φW /2
φW /4
φW /8
φ/2
to
φ/8192
φW
φ SUB
Prescaler W
(5 bits)
φW /2
φW /4
φW /8
to
φW /128
Figure 4.1(1) Block Diagram of Clock Pulse Generators
(H8/38024 Group, H8/38024S Group, H8/38024R Group)
Rev. 8.00 Mar. 09, 2010 Page 103 of 658
REJ09B0042-0800
Section 4 Clock Pulse Generators
Internal reset signal (other than watchdog timer or low-voltage detect
circuit reset)
C
IRQAEC
OSC1
OSC2
D
Latch
Q
System
clock
oscillator
On-chip
oscillator
φOSC
(fOSC)
φOSC/2
System
clock
divider
(1/2)
System
clock
divider
ROSC
φOSC/16
φOSC/32
φOSC/64
φOSC/128
φ
Prescaler S
(13 bits)
φ/2
to
φ/8192
System clock pulse generator
φW
φW/2
X1
X2
Subclock
oscillator
φW
(fW)
Subclock
divider
(1/2, 1/4, 1/8)
φW/4
φW/8
Subclock pulse generator
φSUB
φW/2
φW/4
Prescaler W
(5 bits)
φW/8
to
φW/128
Figure 4.2 Block Diagram of Clock Pulse Generators (H8/38124 Group)
4.1.2
System Clock and Subclock
The basic clock signals that drive the CPU and on-chip peripheral modules are φ and φSUB. Four
of the clock signals have names: φ is the system clock, φSUB is the subclock, φOSC is the oscillator
clock, and φW is the watch clock.
The clock signals available for use by peripheral modules are φ/2, φ/4, φ/8, φ/16, φ/32, φ/64,
φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096, φ/8192, φW, φW/2, φW/4, φW/8, φW/16, φW/32, φW/64,
and φW/128. The clock requirements differ from one module to another.
Rev. 8.00 Mar. 09, 2010 Page 104 of 658
REJ09B0042-0800
Section 4 Clock Pulse Generators
4.1.3
Register Descriptions
Table 4.1 lists the registers that control the clock pulse generators. The registers listed in table 4.1
are only implemented in the H8/38124 Group.
Table 4.1
Clock Pulse Generator Control Registers
Name
Abbreviation
R/W
Initial Value
Address
Clock pulse generator control
register
OSCCR
R/W
—
H'FFF5
Clock Pulse Generator Control Register (OSCCR)
Bit
7
6
5
4
3
2
1
0
SUBSTP
—
—
—
—
IRQAECF
OSCF
—
Initial value
0
0
0
0
0
—
—
0
Read/Write
R/W
R
R/W
R/W
R/W
R
R
R/W
OSCCR is an 8-bit read/write register that contains the flag indicating the selection of system
clock oscillator or on-chip oscillator, indicates the input level of the IRQAEC pin during resets,
and controls whether the subclock oscillator operates or not.
Bit 7—Subclock Oscillator Stop Control (SUBSTP)
Bit 7 controls whether the subclock oscillator operates or not. It can be set to 1 only in the active
mode (high-speed/medium-speed). Setting bit 7 to 1 in the subactive mode will cause the LSI to
stop operating.
Bit 7
SUBSTP
Description
0
Subclock oscillator operates
1
Subclock oscillator stopped
(initial value)
Bit 6—Reserved
This bit is reserved. It is always read as 0 and cannot be written to.
Bits 5 to 3—Reserved
These bits are read/write enabled reserved bits.
Rev. 8.00 Mar. 09, 2010 Page 105 of 658
REJ09B0042-0800
Section 4 Clock Pulse Generators
Bit 2—IRQAEC Flag (IRQAECF)
This bit indicates the IRQAEC pin input level set during resets.
Bit 2
IRQAECF
Description
0
IRQAEC pin set to GND during resets
1
IRQAEC pin set to VCC during resets
Bit 1—OSC Flag (OSCF)
This bit indicates the oscillator operating with the system clock pulse generator.
Bit 1
OSCF
Description
0
System clock oscillator operating (on-chip oscillator stopped)
1
On-chip oscillator operating (system clock oscillator stopped)
Bit 0—Reserved
This bit is reserved. Never write 1 to this bit, as it can cause the LSI to malfunction.
4.2
System Clock Generator
Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic
oscillator, or by providing external clock input. As shown in figure 4.2, the H8/38124 Group
supports selection between a system clock oscillator and an on-chip oscillator. See section 4.2,
On-Chip Oscillator Selection Method, for information on selecting the on-chip oscillator.
Connecting a Crystal Oscillator
Figure 4.3(1) shows a typical method of connecting a crystal oscillator to the H8/38024 or
H8/38024R Group, and figure 4.3(2) shows a typical method of connecting a crystal oscillator to
the H8/38024S and H8/38124 Group.
Rev. 8.00 Mar. 09, 2010 Page 106 of 658
REJ09B0042-0800
Section 4 Clock Pulse Generators
C1
R f = 1 MΩ ±20%
OSC1
Rf
OSC2
C2
Frequency
Crystal
oscillator
C1, C2
Recommendation
value
4.19 MHz
NDK
12 pF ±20%
Note: Circuit constants should be determined in
consultation with the resonator manufacturer.
Figure 4.3(1) Typical Connection to Crystal Oscillator
(H8/38024, H8/38024R Group)
C1
R f = 1 MΩ ±20%
OSC1
Rf
C2
OSC2
Frequency
Crystal
oscillator
4.0 MHz
NDK
C1, C2
Products
Recommendation
name
value
NR-18
12 pF ±20%
Note: Circuit constants should be determined in consultation
with the resonator manufacturer.
Figure 4.3(2) Typical Connection to Crystal Oscillator
(H8/38024S, H8/38124 Group)
Figure 4.3 shows the equivalent circuit of a crystal oscillator. An oscillator having the
characteristics given in table 4.2 should be used.
CS
LS
RS
OSC 1
OSC 2
C0
Figure 4.4 Equivalent Circuit of Crystal Oscillator
Rev. 8.00 Mar. 09, 2010 Page 107 of 658
REJ09B0042-0800
Section 4 Clock Pulse Generators
Table 4.2
Crystal Oscillator Parameters
Frequency (MHz)
4
4.193
RS max (Ω)
100
100
C0 max (pF)
16
16
Connecting a Ceramic Oscillator
Figure 4.5(1) shows a typical method of connecting a ceramic oscillator to the H8/38024 or
H8/38024R Group, and figure 4.5(2) shows a typical method of connecting a crystal oscillator to
the H8/38024S and H8/38124 Group.
OSC 2
R f = 1 MΩ ±20%
C1
OSC 1
Rf
Frequency
Ceramic
oscillator
C1, C2
Recommendation
value
4.0 MHz
Murata
30 pF ±10%
C2
Figure 4.5(1) Typical Connection to Ceramic Oscillator
(H8/38024, H8/38024R Group)
C1
OSC1
Rf
C2
OSC2
Ceramic oscillator
Rf = 1 MΩ ±20%
Frequency
2.0 MHz
10.0 MHz
16.0 MHz*1
20.0 MHz*2
Ceramic
oscillator
Murata
Products name
C1, C2
Recommendation
value
CSTCC2M00G53-B0
CSTCC2M00G56-B0
CSTLS10M0G53-B0
CSTLS10M0G56-B0
CSTLS16M0X53-B0
CSTLS20M0X53-B0
15 pF ±20%
47 pF ±20%
15 pF ±20%
47 pF ±20%
15 pF ±20%
15 pF ±20%
Notes: Circuit constants should be determined in consultation
with the resonator manufacturer.
1. This does not apply to the H8/38024S Group.
2. H8/38124 Group only
Figure 4.5(2) Typical Connection to Ceramic Oscillator
(H8/38024S, H8/38124 Group)
Rev. 8.00 Mar. 09, 2010 Page 108 of 658
REJ09B0042-0800
Section 4 Clock Pulse Generators
Notes on Board Design
When generating clock pulses by connecting a crystal or ceramic oscillator, pay careful attention
to the following points.
Avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely
affected by induction currents. (See figure 4.6.)
The board should be designed so that the oscillator and load capacitors are located as close as
possible to pins OSC1 and OSC2.
Signal A
To be avoided
C1
Signal B
× ×
OSC 1
OSC 2
C2
Figure 4.6 Board Design of Oscillator Circuit
Note: The circuit parameters above are recommended by the crystal or ceramic oscillator
manufacturer.
The circuit parameters are affected by the crystal or ceramic oscillator and floating
capacitance when designing the board. When using the oscillator, consult with the crystal
or ceramic oscillator manufacturer to determine the circuit parameters.
Rev. 8.00 Mar. 09, 2010 Page 109 of 658
REJ09B0042-0800
Section 4 Clock Pulse Generators
External Clock Input Method
Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 4.7 shows a
typical connection.
OSC1
External clock input
OSC2
Open
Figure 4.7 External Clock Input (Example)
Frequency
Oscillator Clock (φOSC)
Duty cycle
45% to 55%
On-Chip Oscillator Selection Method (H8/38124 Group Only)
The on-chip oscillator is selected by setting the IRQAEC pin input level during resets.* Table 4.3
lists the methods for selecting the system clock oscillator and the on-chip oscillator. The IRQAEC
pin input level set during resets must be fixed at VCC or GND, based on the oscillator to be
selected. It is not necessary to connect an oscillator to pins OSC1 and OSC2 if the on-chip
oscillator is selected. In this case, pin OSC1 should be fixed at VCC or GND.
Note: The system clock oscillator must be selected in order to program or erase flash memory as
part of operations such as on-board programming. Also, when using the on-chip emulator,
an oscillator should be connected, or an external clock input, even if the on-chip oscillator
is selected.
* Other than watchdog timer or low-voltage detect circuit reset.
Table 4.3
System Clock Oscillator and On-Chip Oscillator Selection Methods
IRQAEC pin input level (during resets)
0
1
System clock oscillator
Enabled
Disabled
On-chip oscillator
Disabled
Enabled
Rev. 8.00 Mar. 09, 2010 Page 110 of 658
REJ09B0042-0800
Section 4 Clock Pulse Generators
4.3
Subclock Generator
Connecting a 32.768 kHz/38.4 kHz Crystal Oscillator
Clock pulses can be supplied to the subclock divider by connecting a 32.768 kHz/38.4 kHz crystal
oscillator, as shown in figure 4.8. Follow the same precautions as noted under 3. notes on board
design for the system clock in section 4.2.
Note that only operation at 32.768 kHz is guaranteed on the H8/38124 Group.
C1
X1
X2
C2
C1 = C 2 = 15 pF (typ.)
Frequency
Crystal oscillator
38.4 kHz
Seiko Instruments Inc. VTC-200
Products Name
32.768 kHz Nihon Denpa Kogyo
MX73P
C1 = C 2 = 7 pF (typ.)
Frequency
Crystal oscillator
Products Name Motion Resistance
32.768 kHz* EPSON TOYOCOM. C-001R
35 kΩ max
Notes: Circuit constants should be detemined in consultation with the
resonator manufacture.
* H8/38124 Group only.
Figure 4.8 Typical Connection to 32.768 kHz/38.4 kHz Crystal Oscillator (Subclock)
Figure 4.9 shows the equivalent circuit of the 32.768 kHz/38.4 kHz crystal oscillator.
CS
LS
RS
X1
X2
C0
C0 = 1.5 pF typ
RS = 14 k Ω typ
f W = 32.768 kHz/38.4 kHz
Figure 4.9 Equivalent Circuit of 32.768 kHz/38.4 kHz Crystal Oscillator
Rev. 8.00 Mar. 09, 2010 Page 111 of 658
REJ09B0042-0800
Section 4 Clock Pulse Generators
Pin Connection when Not Using Subclock
When the subclock is not used, connect pin X1 to GND and leave pin X2 open, as shown in figure
4.10.
X1
GND
X2
Open
Figure 4.10 Pin Connection when not Using Subclock
External Clock Input
Connect the external clock to the X1 pin and leave the X2 pin open, as shown in figure 4.11.
Note that no external clock should be input to the H8/38124 Group.
X1
X2
External clock input
Open
Figure 4.11 Pin Connection when Inputting External Clock
Rev. 8.00 Mar. 09, 2010 Page 112 of 658
REJ09B0042-0800
Section 4 Clock Pulse Generators
Frequency
Subclock (φw)
Duty
45% to 55%
Method for Disabling Subclock Oscillator (H8/38124 Group Only)
The subclock oscillator can be disabled by programs by setting the SUBSTP bit in the OSCCR
register to 1. The register setting to disable the subclock oscillator should be made in the active
mode. When restoring operation of the subclock oscillator after it has been disabled using the
OSCCR register, it is necessary to wait for the oscillation stabilization time (typ: 8s) to elapse
before using the subclock.
4.4
Prescalers
The H8/38024 Group is equipped with two on-chip prescalers having different input clocks
(prescaler S and prescaler W). Prescaler S is a 13-bit counter using the system clock (φ) as its
input clock. Its prescaled outputs provide internal clock signals for on-chip peripheral modules.
Prescaler W is a 5-bit counter using a 32.768 kHz or 38.4 kHz signal divided by 4 (φW/4) as its
input clock. Its prescaled outputs are used by timer A as a time base for timekeeping.
Prescaler S (PSS)
Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. It is incremented once
per clock period.
Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state.
In standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse
generator stops. Prescaler S also stops and is initialized to H'0000.
The CPU cannot read or write prescaler S.
The output from prescaler S is shared by timer A, timer C, timer F, timer G, SCI3, the A/D
converter, the LCD controller, watchdog timer, and the 10-bit PWM. The divider ratio can be set
separately for each on-chip peripheral function.
In active (medium-speed) mode the clock input to prescaler S is φosc/16, φosc/32, φosc/64, or
φosc/128.
Rev. 8.00 Mar. 09, 2010 Page 113 of 658
REJ09B0042-0800
Section 4 Clock Pulse Generators
Prescaler W (PSW)
Prescaler W is a 5-bit counter using a 32.768 kHz/38.4 kHz signal divided by 4 (φW/4) as its input
clock.
Prescaler W is initialized to H'00 by a reset, and starts counting on exit from the reset state.
Even in standby mode, watch mode, subactive mode, or subsleep mode, prescaler W continues
functioning so long as clock signals are supplied to pins X1 and X2.
Prescaler W can be reset by setting 1s in bits TMA3 and TMA2 of timer mode register A (TMA).
Output from prescaler W can be used to drive timer A, in which case timer A functions as a time
base for timekeeping.
Rev. 8.00 Mar. 09, 2010 Page 114 of 658
REJ09B0042-0800
Section 4 Clock Pulse Generators
4.5
Note on Oscillators
Oscillator characteristics are closely related to board design and should be carefully evaluated by
the user in mask ROM and ZTAT versions, referring to the examples shown in this section.
Oscillator circuit constants will differ depending on the oscillator element, stray capacitance in its
interconnecting circuit, and other factors. Suitable constants should be determined in consultation
with the oscillator element manufacturer. Design the circuit so that the oscillator element never
receives voltages exceeding its maximum rating.
P17
X1
X2
Vss
OSC2
OSC1
TEST
(Vss)
Figure 4.12 Example of Crystal and Ceramic Oscillator Element Arrangement
Figure 4.13 (1) shows an example measuring circuit with the negative resistance suggested by the
resonator manufacturer. Note that if the negative resistance of the circuit is less than that suggested
by the resonator manufacturer, it may be difficult to start the main oscillator.
If it is determined that oscillation is not occurring because the negative resistance is lower than the
level suggested by the resonator manufacturer, the circuit may be modified as shown in figure 4.13
(2) through (4). Which of the modification suggestions to use and the capacitor capacitance should
be decided based upon an evaluation of factors such as the negative resistance and the frequency
deviation.
Rev. 8.00 Mar. 09, 2010 Page 115 of 658
REJ09B0042-0800
Section 4 Clock Pulse Generators
Modification
point
OSC1
OSC1
C1
C1
Rf
Rf
OSC2
OSC2
C2
C2
Negative resistance,
addition of −R
(1) Negative Resistance Measuring Circuit
(2) Oscillator Circuit Modification Suggestion 1
Modification
point
Modification
point
C3
OSC1
C1
OSC1
C1
Rf
C2
Rf
OSC2
OSC2
(3) Oscillator Circuit Modification Suggestion 2
C2
(4) Oscillator Circuit Modification Suggestion 3
Figure 4.13 Negative Resistance Measurement and Circuit Modification Suggestions
4.5.1
Definition of Oscillation Stabilization Wait Time
Figure 4.14 shows the oscillation waveform (OSC2), system clock (φ), and microcomputer
operating mode when a transition is made from standby mode, watch mode, or subactive mode, to
active (high-speed/medium-speed) mode, with an oscillator element connected to the system clock
oscillator.
As shown in figure 4.13, as the system clock oscillator is halted in standby mode, watch mode,
and subactive mode, when a transition is made to active (high-speed/medium-speed) mode, the
sum of the following two times (oscillation stabilization time and wait time) is required.
Rev. 8.00 Mar. 09, 2010 Page 116 of 658
REJ09B0042-0800
Section 4 Clock Pulse Generators
1. Oscillation stabilization time (trc)
The time from the point at which the system clock oscillator oscillation waveform starts to change
when an interrupt is generated, until the amplitude of the oscillation waveform increases and the
oscillation frequency stabilizes.
2. Wait time
The time required for the CPU and peripheral functions to begin operating after the oscillation
waveform frequency and system clock have stabilized.
The wait time setting is selected with standby timer select bits 2 to 0 (STS2 to STS0) (bits 6 to 4 in
system control register 1 (SYSCR1)).
Oscillation
waveform
(OSC2)
System clock
(φ)
Oscillation
stabilization
time
Wait time
Operating
mode
Standby mode,
watch mode,
or subactive
mode
Oscillation stabilization wait time
Active (high-speed) mode or
active (medium-speed) mode
Interrupt accepted
Figure 4.14 Oscillation Stabilization Wait Time
When standby mode, watch mode, or subactive mode is cleared by an interrupt or reset, and a
transition is made to active (high-speed/medium-speed) mode, the oscillation waveform begins to
change at the point at which the interrupt is accepted. Therefore, when an oscillator element is
connected in standby mode, watch mode, or subactive mode, since the system clock oscillator is
halted, the time from the point at which this oscillation waveform starts to change until the
Rev. 8.00 Mar. 09, 2010 Page 117 of 658
REJ09B0042-0800
Section 4 Clock Pulse Generators
amplitude of the oscillation waveform increases and the oscillation frequency stabilizes—that is,
the oscillation stabilization time—is required.
The oscillation stabilization time in the case of these state transitions is the same as the oscillation
stabilization time at power-on (the time from the point at which the power supply voltage reaches
the prescribed level until the oscillation stabilizes), specified by "oscillation stabilization time trc"
in the AC characteristics.
Meanwhile, once the system clock has halted, a wait time of at least 8 states is necessary in order
for the CPU and peripheral functions to operate normally.
Thus, the time required from interrupt generation until operation of the CPU and peripheral
functions is the sum of the above described oscillation stabilization time and wait time. This total
time is called the oscillation stabilization wait time, and is expressed by equation (1) below.
Oscillation stabilization wait time = oscillation stabilization time + wait time
= trc + (8 to 16,384 states)*1 ................. (1)
(up to 131,072 states)*2
Notes: 1. H8/38024 Group
2. H8/38124 Group
Therefore, when a transition is made from standby mode, watch mode, or subactive mode, to
active (high-speed/medium-speed) mode, with an oscillator element connected to the system clock
oscillator, careful evaluation must be carried out on the installation circuit before deciding on the
oscillation stabilization wait time. In particular, since the oscillation stabilization time is affected
by installation circuit constants, stray capacitance, and so forth, suitable constants should be
determined in consultation with the oscillator element manufacturer.
4.5.2
Notes on Use of Crystal Oscillator Element (Excluding Ceramic Oscillator
Element)
When a microcomputer operates, the internal power supply potential fluctuates slightly in
synchronization with the system clock. Depending on the individual crystal oscillator element
characteristics, the oscillation waveform amplitude may not be sufficiently large immediately after
the oscillation stabilization wait time, making the oscillation waveform susceptible to influence by
fluctuations in the power supply potential. In this state, the oscillation waveform may be
disrupted, leading to an unstable system clock and erroneous operation of the microcomputer.
If erroneous operation occurs, change the setting of standby timer select bits 2 to 0 (STS2 to
STS0) (bits 6 to 4 in system control register 1 (SYSCR1)) to give a longer wait time.
Rev. 8.00 Mar. 09, 2010 Page 118 of 658
REJ09B0042-0800
Section 4 Clock Pulse Generators
For example, if erroneous operation occurs with a wait time setting of 16 states, check the
operation with a wait time setting of 1,024* states or more.
If the same kind of erroneous operation occurs after a reset as after a state transition, hold the RES
pin low for a longer period.
Note: * This figure applies to the H8/38024, H8/38024S, and H8/38024R Groups. The number of
states on the H8/38124 Group is 8,192 or more.
4.5.3
Note on Use of HD64F38024
When using the HD64F38024, the oscillators may not operate if an initial voltage of 10 mV is
applied to the VCC pin during power-on. This problem is caused by uncertainty about the state of
the oscillation control signals. It can be corrected by cutting off power and allowing the VCC pin
voltage to drop to ground potential before powering-on once again.
4.6
Notes on H8/38124 Group
When using the on-chip emulator, system clock precision is necessary for programming or erasing
the flash memory. However, the on-chip oscillator frequency can vary due to changes in
conditions such as voltage or temperature. Consequently, even if the on-chip oscillator is selected
when using the on-chip emulator, pins OSC1 and OSC2 should be connected to an oscillator, or an
external clock should be supplied. In this case, the LSI uses the on-chip oscillator when user
programs are being executed and the system clock oscillator when programming or erasing flash
memory. The process is controlled by the on-chip emulator.
Rev. 8.00 Mar. 09, 2010 Page 119 of 658
REJ09B0042-0800
Section 4 Clock Pulse Generators
Rev. 8.00 Mar. 09, 2010 Page 120 of 658
REJ09B0042-0800
Section 5 Power-Down Modes
Section 5 Power-Down Modes
5.1
Overview
The LSI has nine modes of operation after a reset. These include eight power-down modes, in
which power dissipation is significantly reduced. Table 5.1 gives a summary of the nine operating
modes.
Table 5.1
Operating Modes
Operating Mode
Description
Active (high-speed) mode
The CPU and all on-chip peripheral functions are operable on
the system clock in high-speed operation
Active (medium-speed) mode
The CPU and all on-chip peripheral functions are operable on
the system clock in low-speed operation
Subactive mode
The CPU and all on-chip peripheral functions are operable on
the subclock in low-speed operation
Sleep (high-speed) mode
The CPU halts. On-chip peripheral functions are operable on
the system clock
Sleep (medium-speed) mode
The CPU halts. On-chip peripheral functions operate at a
frequency of 1/128, 1/64, 1/32, or 1/16 of the system clock
frequency
Subsleep mode
The CPU halts. The time-base function of timer A, timer C,
timer F, timer G, SCI3, AEC, and LCD controller/driver are
operable on the subclock
Watch mode
The CPU halts. The time-base function of timer A, timer F,
timer G, AEC and LCD controller/driver are operable on the
subclock
Standby mode
The CPU and all on-chip peripheral functions halt
Module standby mode
Individual on-chip peripheral functions specified by software
enter standby mode and halt
Of these nine operating modes, all but the active (high-speed) mode are power-down modes. In
this section the two active modes (high-speed and medium speed) will be referred to collectively
as active mode.
Figure 5.1 shows the transitions among these operation modes. Table 5.2 indicates the internal
states in each mode.
Rev. 8.00 Mar. 09, 2010 Page 121 of 658
REJ09B0042-0800
Section 5 Power-Down Modes
Program
execution state
Reset state
SLEEP
instruction*a
Active
(high-speed)
mode
P
EE n
SL uctio
r
t
s
in
*d
Program
halt state
Program
halt state
a
SLEEP
instruction*f
SL
instr EEP
uctio *d
n
*1
SLEEP
instruction*e
Watch
mode
*1
SLEEP
instruction*i
*e
P
EE tion
SL ruc
st
in
Subactive
mode
P *
EE tion
SL ruc
st
inin SL
st E
ru EP
ct
io
n *b
SLEEP
instruction*b
*3
Sleep
(medium-speed)
mode
ins SLEE
tru P
cti
on *j
S
ins LE
tru EP
ctio
n *i
Active
(medium-speed)
mode
SLEEP
instruction*h
ins SLEE
tru
ctio P
n *e
*4
*1
SLEEP
instruction*g
*4
Standby
mode
Sleep
(high-speed)
mode
*3
SLEEP
instruction*c
*2
Subsleep
mode
Power-down modes
Mode Transition Conditions (2)
Mode Transition Conditions (1)
LSON MSON SSBY TMA3 DTON
*a
*b
*c
*d
*e
*f
*g
*h
*i
*j
0
0
1
0
*
0
0
0
1
0
0
1
*
*
*
0
1
1
*
0
0
0
0
1
1
0
0
1
1
1
*
*
1
0
1
*
*
1
1
1
0
0
0
0
0
1
1
1
1
1
Interrupt Sources
*1
*3
Timer A, Timer F, Timer G interrupt, IRQ0 interrupt,
WKP7 to WKP0 interrupts
Timer A, Timer C, Timer F, Timer G, SCI3 interrupt,
IRQ4, IRQ3, IRQ1 and IRQ0 interrupts, IRQAEC,
WKP7 to WKP0 interrupts, AEC
All interrupts
*4
IRQ1 or IRQ0 interrupt, WKP7 to WKP0 interrupts
*2
*: Don't care
Notes: 1. A transition between different modes cannot be made to occur simply because an interrupt
request is generated. Make sure that interrupts are enabled.
2. Details on the mode transition conditions are given in the explanations of each mode,
in sections 5.2 to 5.8.
Figure 5.1 Mode Transition Diagram
Rev. 8.00 Mar. 09, 2010 Page 122 of 658
REJ09B0042-0800
Section 5 Power-Down Modes
Table 5.2
Internal State in Each Operating Mode
Active Mode
HighSpeed
Function
System clock oscillator
Subclock oscillator
CPU
Instructions
operations RAM
Registers
I/O ports
External
IRQ0
interrupts IRQ1
IRQAEC
IRQ3
IRQ4
WKP0
WKP1
WKP2
WKP3
WKP4
WKP5
WKP6
WKP7
Peripheral Timer A
functions
Asynchronous
event counter
Timer C
WDT
Timer F
Timer G
SCI3
PWM
A/D converter
LCD
LVD
MediumSpeed
Sleep Mode
HighSpeed
MediumSpeed
Functions Functions Functions Functions
Functions Functions Functions Functions
Functions Functions Halted
Halted
Retained Retained
Watch
Mode
Subactive
Mode
Subsleep
Mode
Standby
Mode
Halted
Functions
Halted
Retained
Halted
Functions
Functions
Halted
Functions
Halted
Retained
Halted
Functions
Halted
Retained
Functions
Functions
Retained*
Functions
1
Functions Functions Functions Functions Functions
6
Retained*
Retained*6
Functions Functions Functions Functions Functions
Functions
Functions
Functions
Functions Functions Functions Functions Functions*5 Functions*5 Functions*5 Retained
8
Functions
Functions*8
Functions* Functions
Retained
Functions/
Retained*10
Functions/
Retained*9
Reset
Retained
Retained
Functions/
Retained*4
Functions Functions Functions Functions Functions
Functions/
Retained*2
Functions/
Retained*7
Functions/
Retained*9
Functions/
Retained*3
Functions/
Retained*2
Functions/
Retained*10
Functions/
Retained*9
Functions/
Retained*3
Retained
Retained
Functions/
Retained*4
Retained
Retained
Functions/
Retained*4
Retained
Retained
Retained
Functions
Functions
Functions
Retained
Functions/
Retained*11
Retained
Reset
Notes: 1.
Register contents are retained, but output is high-impedance state. Port 5 of the HD64F38024 retains the previous
pin state.
2. Functions if an external clock or the φW /4 internal clock is selected; otherwise halted and retained.
3. Functions if φW /2 is selected as the internal clock; otherwise halted and retained.
4. Functions if φW , φW /2 or φW /4 is selected as the operating clock; otherwise halted and retained.
5. Functions if the timekeeping time-base function is selected.
6. External interrupt requests are ignored. Interrupt request register contents are not altered.
7. On the H8/38124 Group, operates when φW /32 is selected as the internal clock or the on-chip oscillator is selected;
otherwise stops and stands by. On the H8/38024, H8/38024S, and H8/38024R Group, operates when φW /32 is
selected as the internal clock; otherwise stops and stands by.
8. Incrementing is possible, but interrupt generation is not.
9. Functions if φW /4 is selected as the internal clock; otherwise halted and retained.
10. On the H8/38124 Group, operates when φW /32 is selected as the internal clock or the on-chip oscillator is selected;
otherwise stops and stands by. On the H8/38024, H8/38024S, and H8/38024R Group, stops and stands by.
Rev. 8.00 Mar. 09, 2010 Page 123 of 658
REJ09B0042-0800
Section 5 Power-Down Modes
11. On the H8/38124 Group, operates only when the on-chip oscillator is selected; otherwise stops and stands by. On
the H8/38024, H8/38024S, and H8/38024R Group, stops and stands by.
5.1.1
System Control Registers
The operation mode is selected using the system control registers described in table 5.3.
Table 5.3
System Control Registers
Name
Abbreviation
R/W
Initial Value
Address
System control register 1
SYSCR1
R/W
H'07
H'FFF0
System control register 2
SYSCR2
R/W
H'F0
H'FFF1
System Control Register 1 (SYSCR1)
Bit
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
LSON
⎯
MA1
MA0
Initial value
0
0
0
0
0
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
⎯
R/W
R/W
SYSCR1 is an 8-bit read/write register for control of the power-down modes.
Upon reset, SYSCR1 is initialized to H'07.
Bit 7—Software Standby (SSBY)
This bit designates transition to standby mode or watch mode.
Bit 7
SSBY
Description
0
•
When a SLEEP instruction is executed in active mode,
a transition is made to sleep mode
•
When a SLEEP instruction is executed in subactive mode, a transition is made to
subsleep mode
•
When a SLEEP instruction is executed in active mode, a transition is made to
standby mode or watch mode
•
When a SLEEP instruction is executed in subactive mode, a transition is made to
watch mode
1
Rev. 8.00 Mar. 09, 2010 Page 124 of 658
REJ09B0042-0800
(initial value)
Section 5 Power-Down Modes
Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0)
These bits designate the time the CPU and peripheral modules wait for stable clock operation after
exiting from standby mode or watch mode to active mode due to an interrupt. The designation
should be made according to the operating frequency so that the waiting time is at least equal to
the oscillation stabilization time. Note that stabilization times for the H8/38024, H8/38024S, and
H8/38024R Group and for the H8/38124 Group are different.
• H8/38024, H8/38024S, H8/38024R Group
Bit 6
STS2
Bit 5
STS1
Bit 4
STS0
Description
0
0
0
Wait time = 8,192 states
0
0
1
Wait time = 16,384 states
0
1
0
Wait time = 1,024 states
0
1
1
Wait time = 2,048 states
1
0
0
Wait time = 4,096 states
1
0
1
Wait time = 2 states
1
1
0
Wait time = 8 states
1
1
1
Wait time = 16 states
(initial value)
(External clock input mode)
• H8/38124 Group
Bit 6
STS2
Bit 5
STS1
Bit 4
STS0
Description
0
0
0
Wait time = 8,192 states
0
0
1
Wait time = 16,384 states
0
1
0
Wait time = 32,768 states
0
1
1
Wait time = 65,536 states
1
0
0
Wait time = 131,072 states
1
0
1
Wait time = 2 states
1
1
0
Wait time = 8 states
1
1
1
Wait time = 16 states
(initial value)
(External clock input mode)
Note: If an external clock is being input, set standby timer select to external clock mode before
mode transition. Also, do not set standby timer select to external clock mode if no external
clock is used. 8,192 states (STS2 = STS1 = STS0 = 0) is recommended if the on-chip
oscillator is used on the H8/38124 Group.
Rev. 8.00 Mar. 09, 2010 Page 125 of 658
REJ09B0042-0800
Section 5 Power-Down Modes
Bit 3—Low Speed on Flag (LSON)
This bit chooses the system clock (φ) or subclock (φSUB) as the CPU operating clock when watch
mode is cleared. The resulting operation mode depends on the combination of other control bits
and interrupt input.
Bit 3
LSON
Description
0
The CPU operates on the system clock (φ)
1
The CPU operates on the subclock (φSUB)
(initial value)
Bit 2—Reserved
Bit 2 is reserved: it is always read as 1 and cannot be modified.
Bits 1 and 0—Active (Medium-Speed) Mode Clock Select (MA1, MA0)
Bits 1 and 0 choose φosc/128, φosc/64, φosc/32, or φosc/16 as the operating clock in active (mediumspeed) mode and sleep (medium-speed) mode. MA1 and MA0 should be written in active (highspeed) mode or subactive mode.
Bit 1
MA1
Bit 0
MA0
Description
0
0
φosc/16
0
1
φosc/32
1
0
φosc/64
1
1
φosc/128
(initial value)
System Control Register 2 (SYSCR2)
Bit
7
6
5
4
3
2
1
0
⎯
⎯
⎯
NESEL
DTON
MSON
SA1
SA0
Initial value
1
1
1
1
0
0
0
0
Read/Write
⎯
⎯
⎯
R/W
R/W
R/W
R/W
R/W
SYSCR2 is an 8-bit read/write register for power-down mode control.
Bits 7 to 5—Reserved
These bits are reserved; they are always read as 1, and cannot be modified.
Rev. 8.00 Mar. 09, 2010 Page 126 of 658
REJ09B0042-0800
Section 5 Power-Down Modes
Bit 4—Noise Elimination Sampling Frequency Select (NESEL)
This bit selects the frequency at which the watch clock signal (φW) generated by the subclock
pulse generator is sampled, in relation to the oscillator clock (φOSC) generated by the system clock
pulse generator. When φOSC = 2 to 20 MHz, clear NESEL to 0.
Bit 4
NESEL
Description
0
Sampling rate is φOSC/16
1
Sampling rate is φOSC/4
(initial value)
Bit 3—Direct Transfer on Flag (DTON)
This bit designates whether or not to make direct transitions among active (high-speed), active
(medium-speed) and subactive mode when a SLEEP instruction is executed. The mode to which
the transition is made after the SLEEP instruction is executed depends on a combination of other
control bits.
Bit 3
DTON
Description
0
•
When a SLEEP instruction is executed in active mode,
a transition is made to standby mode, watch mode, or sleep mode
•
When a SLEEP instruction is executed in subactive mode, a transition is made to
watch mode or subsleep mode
•
When a SLEEP instruction is executed in active (high-speed) mode, a direct
transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1
•
When a SLEEP instruction is executed in active (medium-speed) mode, a direct
transition is made to active (high-speed) mode if SSBY = 0, MSON = 0, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1
•
When a SLEEP instruction is executed in subactive mode, a direct transition is
made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON
= 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and
MSON = 1
1
(initial value)
Bit 2—Medium Speed on Flag (MSON)
After standby, watch, or sleep mode is cleared, this bit selects active (high-speed) or active
(medium-speed) mode.
Rev. 8.00 Mar. 09, 2010 Page 127 of 658
REJ09B0042-0800
Section 5 Power-Down Modes
Bit 2
MSON
Description
0
Operation in active (high-speed) mode
1
Operation in active (medium-speed) mode
(initial value)
Bits 1 and 0—Subactive Mode Clock Select (SA1, SA0)
These bits select the CPU clock rate (φW/2, φW/4, or φW/8) in subactive mode. SA1 and SA0
cannot be modified in subactive mode.
Bit 1
SA1
Bit 0
SA0
Description
0
0
φW /8
0
1
φW /4
1
*
φW /2
(initial value)
*: Don’t care
5.2
Sleep Mode
5.2.1
Transition to Sleep Mode
1. Transition to sleep (high-speed) mode
The system goes from active mode to sleep (high-speed) mode when a SLEEP instruction is
executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON and DTON
bits in SYSCR2 are cleared to 0. In sleep mode CPU operation is halted but the on-chip
peripheral functions. CPU register contents are retained.
2. Transition to sleep (medium-speed) mode
The system goes from active mode to sleep (medium-speed) mode when a SLEEP instruction
is executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in
SYSCR2 is set to 1, and the DTON bit in SYSCR2 is cleared to 0. In sleep (medium-speed)
mode, as in sleep (high-speed) mode, CPU operation is halted but the on-chip peripheral
functions are operational. The clock frequency in sleep (medium-speed) mode is determined
by the MA1 and MA0 bits in SYSCR1. CPU register contents are retained.
Furthermore, it sometimes acts with half state early timing at the time of transition to sleep
(medium-speed) mode.
Rev. 8.00 Mar. 09, 2010 Page 128 of 658
REJ09B0042-0800
Section 5 Power-Down Modes
5.2.2
Clearing Sleep Mode
Sleep mode is cleared by any interrupt (timer A, timer C, timer F, timer G, asynchronous event
counter, IRQAEC, IRQ4, IRQ3, IRQ1, IRQ0, WKP7 to WKP0, SCI3, A/D converter), or by input at
the RES pin.
• Clearing by interrupt
When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts.
A transition is made from sleep (high-speed) mode to active (high-speed) mode, or from sleep
(medium-speed) mode to active (medium-speed) mode. Sleep mode is not cleared if the I bit of
the condition code register (CCR) is set to 1 or the particular interrupt is disabled in the
interrupt enable register.
To synchronize the interrupt request signal with the system clock, up to 2/φ(s) delay may occur
after the interrupt request signal occurrence, before the interrupt exception handling start.
•
Clearing by RES input
When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared.
5.2.3
Clock Frequency in Sleep (Medium-Speed) Mode
Operation in sleep (medium-speed) mode is clocked at the frequency designated by the MA1 and
MA0 bits in SYSCR1.
Rev. 8.00 Mar. 09, 2010 Page 129 of 658
REJ09B0042-0800
Section 5 Power-Down Modes
5.3
Standby Mode
5.3.1
Transition to Standby Mode
The system goes from active mode to standby mode when a SLEEP instruction is executed while
the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and bit TMA3 in
TMA is cleared to 0. In standby mode the clock pulse generator stops, so the CPU and on-chip
peripheral modules stop functioning, but as long as the rated voltage is supplied, the contents of
CPU registers, on-chip RAM, and some on-chip peripheral module registers are retained. On-chip
RAM contents will be further retained down to a minimum RAM data retention voltage. The I/O
ports go to the high-impedance state. Port 5 of the HD64F38024 retains the previous pin state.
5.3.2
Clearing Standby Mode
Standby mode is cleared by an interrupt (IRQ1 or IRQ0), WKP7 to WKP0 or by input at the RES
pin.
• Clearing by interrupt
When an interrupt is requested, the system clock pulse generator starts. After the time set in
bits STS2 to STS0 in SYSCR1 has elapsed, a stable system clock signal is supplied to the
entire chip, standby mode is cleared, and interrupt exception handling starts. Operation
resumes in active (high-speed) mode if MSON = 0 in SYSCR2, or active (medium-speed)
mode if MSON = 1. Standby mode is not cleared if the I bit of CCR is set to 1 or the particular
interrupt is disabled in the interrupt enable register.
• Clearing by RES input
When the RES pin goes low, the system clock pulse generator starts. After the pulse generator
output has stabilized, if the RES pin is driven high, the CPU starts reset exception handling.
Since system clock signals are supplied to the entire chip as soon as the system clock pulse
generator starts functioning, the RES pin should be kept at the low level until the pulse
generator output stabilizes.
5.3.3
Oscillator Stabilization Time after Standby Mode Is Cleared
Bits STS2 to STS0 in SYSCR1 should be set as follows.
Note that stabilization times for the H8/38024, H8/38024S, and H8/38024R Group and for the
H8/38124 Group are different.
Rev. 8.00 Mar. 09, 2010 Page 130 of 658
REJ09B0042-0800
Section 5 Power-Down Modes
• When a oscillator is used
The table below gives settings for various operating frequencies. Set bits STS2 to STS0 for a
wait time at least as long as the oscillation stabilization time.
Table 5.4(1) Clock Frequency and Stabilization Time (H8/38024, H8/38024S,
H8/38024R Group)
(Unit: ms)
STS2
STS1
STS0
Wait Time
5 MHz
2 MHz
0
0
0
8,192 states
1.638
4.1
1
16,384 states
3.277
8.2
1
0
1,024 states
0.205
0.512
1
2,048 states
0.410
1.024
0
4,096 states
0.819
2.048
1
2 states
(Use prohibited with other than
external clock)
0.0004
0.001
0
8 states
0.002
0.004
1
16 states
0.003
0.008
1
0
1
Table 5.4(2) Clock Frequency and Stabilization Time (H8/38124 Group)
(Unit: ms)
STS2
STS1
STS0
Wait Time
5 MHz
2 MHz
0
0
0
8,192 states
1.638
4.1
1
16,384 states
3.277
8.2
0
32,768 states
6.554
16.4
1
65,536 states
13.108
32.8
0
131,072 states
26.216
65.5
1
2 states
(Use prohibited with other than
external clock)
0.0004
0.001
0
8 states
0.002
0.004
1
16 states
0.003
0.008
1
1
0
1
• When an external clock is used
STS2 = 1, STS1 = 0, and STS0 = 1 should be set. Other values possible use, but CPU
sometimes will start operation before wait time completion.
Rev. 8.00 Mar. 09, 2010 Page 131 of 658
REJ09B0042-0800
Section 5 Power-Down Modes
• When the on-chip oscillator is used
8,192 states (STS2 = STS1 = STS0 = 0) is recommended if the on-chip oscillator is used on
the H8/38124 Group.
5.3.4
Standby Mode Transition and Pin States
When a SLEEP instruction is executed in active (high-speed) mode or active (medium-speed)
mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in SYSCR1, and bit TMA3 is
cleared to 0 in TMA, a transition is made to standby mode. At the same time, pins go to the highimpedance state (except pins for which the pull-up MOS is designated as on). Port 5 of the
HD64F38024 retains the previous pin state. Figure 5.2 shows the timing in this case.
φ
Internal data bus
SLEEP instruction fetch
Fetch of next instruction
SLEEP instruction execution
Pins
Internal processing
Port output
Active (high-speed) mode or active (medium-speed) mode
Figure 5.2 Standby Mode Transition and Pin States
Rev. 8.00 Mar. 09, 2010 Page 132 of 658
REJ09B0042-0800
High-impedance
Standby mode
Section 5 Power-Down Modes
5.3.5
Notes on External Input Signal Changes before/after Standby Mode
1. When external input signal changes before/after standby mode or watch mode
When an external input signal such as IRQ, WKP, or IRQAEC is input, both the high- and
low-level widths of the signal must be at least two cycles of system clock φ or subclock φSUB
(referred to together in this section as the internal clock). As the internal clock stops in
standby mode and watch mode, the width of external input signals requires careful attention
when a transition is made via these operating modes. Ensure that external input signals
conform to the conditions stated in 3, Recommended timing of external input signals, below
2. When external input signals cannot be captured because internal clock stops
The case of falling edge capture is illustrated in figure 5.3.
As shown in the case marked "Capture not possible," when an external input signal falls
immediately after a transition to active (high-speed or medium-speed) mode or subactive
mode, after oscillation is started by an interrupt via a different signal, the external input signal
cannot be captured if the high-level width at that point is less than 2 tcyc or 2 tsubcyc.
3. Recommended timing of external input signals
To ensure dependable capture of an external input signal, high- and low-level signal widths of
at least 2 tcyc or 2 tsubcyc are necessary before a transition is made to standby mode or watch
mode, as shown in “Capture possible: case 1” in figure 5.3.
External input signal capture is also possible with the timing shown in “Capture possible: case
2” and “Capture possible: case 3” in figure 5.3, in which a 2 tcyc or 2 tsubcyc level width is
secured.
Rev. 8.00 Mar. 09, 2010 Page 133 of 658
REJ09B0042-0800
Section 5 Power-Down Modes
Operating
mode
Active (high-speed,
medium-speed) mode
or subactive mode
tcyc
tsubcyc
tcyc
tsubcyc
Wait for Active (high-speed,
Standby mode oscillation medium-speed) mode
or watch mode to settle or subactive mode
tcyc
tsubcyc
tcyc
tsubcyc
φ or φSUB
External input signal
Capture possible:
case 1
Capture possible:
case 2
Capture possible:
case 3
Capture not
possible
Interrupt by different
signal
Figure 5.3 External Input Signal Capture when Signal Changes before/after
Standby Mode or Watch Mode
4. Input pins to which these notes apply:
IRQ4, IRQ3, IRQ1, IRQ0, WKP7 to WKP0, IRQAEC, TMIC, TMIF, TMIG, ADTRG.
5.4
Watch Mode
5.4.1
Transition to Watch Mode
The system goes from active or subactive mode to watch mode when a SLEEP instruction is
executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1.
In watch mode, operation of on-chip peripheral modules is halted except for timer A, timer F,
timer G, AEC and the LCD controller/driver (for which operation or halting can be set) is halted.
As long as a minimum required voltage is applied, the contents of CPU registers, the on-chip
RAM and some registers of the on-chip peripheral modules, are retained. I/O ports keep the same
states as before the transition.
Rev. 8.00 Mar. 09, 2010 Page 134 of 658
REJ09B0042-0800
Section 5 Power-Down Modes
5.4.2
Clearing Watch Mode
Watch mode is cleared by an interrupt (timer A, timer F, timer G, IRQ0, or WKP7 to WKP0) or
by input at the RES pin.
• Clearing by interrupt
When watch mode is cleared by interrupt, the mode to which a transition is made depends on
the settings of LSON in SYSCR1 and MSON in SYSCR2. If both LSON and MSON are
cleared to 0, transition is to active (high-speed) mode; if LSON = 0 and MSON = 1, transition
is to active (medium-speed) mode; if LSON = 1, transition is to subactive mode. When the
transition is to active mode, after the time set in SYSCR1 bits STS2 to STS0 has elapsed, a
stable clock signal is supplied to the entire chip, watch mode is cleared, and interrupt exception
handling starts. Watch mode is not cleared if the I bit of CCR is set to 1 or the particular
interrupt is disabled in the interrupt enable register.
• Clearing by RES input
Clearing by RES pin is the same as for standby mode; see 2. Clearing by RES pin in section
5.3.2, Clearing Standby Mode.
5.4.3
Oscillator StabilizationTime after Watch Mode Is Cleared
The wait time is the same as for standby mode; see section 5.3.3, Oscillator Stabilization Time
after Standby Mode is Cleared.
5.4.4
Notes on External Input Signal Changes before/after Watch Mode
See section 5.3.5, Notes on External Input Signal Changes before/after Standby Mode.
Rev. 8.00 Mar. 09, 2010 Page 135 of 658
REJ09B0042-0800
Section 5 Power-Down Modes
5.5
Subsleep Mode
5.5.1
Transition to Subsleep Mode
The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed
while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in
TMA is set to 1. In subsleep mode, operation of on-chip peripheral modules other than the A/D
converter and PWM is in active state. As long as a minimum required voltage is applied, the
contents of CPU registers, the on-chip RAM and some registers of the on-chip peripheral modules
are retained. I/O ports keep the same states as before the transition.
5.5.2
Clearing Subsleep Mode
Subsleep mode is cleared by an interrupt (timer A, timer C, timer F, timer G, asynchronous event
counter, SCI3, IRQAEC, IRQ4, IRQ3, IRQ1, IRQ0, WKP7 to WKP0) or by a low input at the RES
pin.
• Clearing by interrupt
When an interrupt is requested, subsleep mode is cleared and interrupt exception handling
starts. Subsleep mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is
disabled in the interrupt enable register.
To synchronize the interrupt request signal with the system clock, up to 2/φSUB(s) delay may
occur after the interrupt request signal occurrence, before the interrupt exception handling
start.
• Clearing by RES input
Clearing by RES pin is the same as for standby mode; see Clearing by RES pin in section
5.3.2, Clearing Standby Mode.
Rev. 8.00 Mar. 09, 2010 Page 136 of 658
REJ09B0042-0800
Section 5 Power-Down Modes
5.6
Subactive Mode
5.6.1
Transition to Subactive Mode
Subactive mode is entered from watch mode if a timer A, timer F, timer G, IRQ0, or WKP7 to
WKP0 interrupt is requested while the LSON bit in SYSCR1 is set to 1. From subsleep mode,
subactive mode is entered if a timer A, timer C, timer F, timer G, asynchronous event counter,
SCI3, IRQAEC, IRQ4, IRQ3, IRQ1, IRQ0, or WKP7 to WKP0 interrupt is requested. A transition
to subactive mode does not take place if the I bit of CCR is set to 1 or the particular interrupt is
disabled in the interrupt enable register.
5.6.2
Clearing Subactive Mode
Subactive mode is cleared by a SLEEP instruction or by a low input at the RES pin.
• Clearing by SLEEP instruction
If a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and TMA3 bit in
TMA is set to 1, subactive mode is cleared and watch mode is entered. If a SLEEP instruction
is executed while SSBY = 0 and LSON = 1 in SYSCR1 and TMA3 = 1 in TMA, subsleep
mode is entered. Direct transfer to active mode is also possible; see section 5.8, Direct
Transfer, below.
• Clearing by RES pin
Clearing by RES pin is the same as for standby mode; see Clearing by RES pin in section
5.3.2, Clearing Standby Mode.
5.6.3
Operating Frequency in Subactive Mode
The operating frequency in subactive mode is set in bits SA1 and SA0 in SYSCR2. The choices
are φW/2, φW/4, and φW/8.
Rev. 8.00 Mar. 09, 2010 Page 137 of 658
REJ09B0042-0800
Section 5 Power-Down Modes
5.7
Active (Medium-Speed) Mode
5.7.1
Transition to Active (Medium-Speed) Mode
If the MSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition
to active (medium-speed) mode results from IRQ0, IRQ1 or WKP7 to WKP0 interrupts in standby
mode, timer A, timer F, timer G, IRQ0, or WKP7 to WKP0 interrupts in watch mode, or any
interrupt in sleep mode. A transition to active (medium-speed) mode does not take place if the I
bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register.
Furthermore, it sometimes acts with half state early timing at the time of transition to active
(medium-speed) mode.
5.7.2
Clearing Active (Medium-Speed) Mode
Active (medium-speed) mode is cleared by a SLEEP instruction.
• Clearing by SLEEP instruction
A transition to standby mode takes place if the SLEEP instruction is executed while the SSBY
bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and the TMA3 bit in TMA
is cleared to 0. The system goes to watch mode if the SSBY bit in SYSCR1 is set to 1 and bit
TMA3 in TMA is set to 1 when a SLEEP instruction is executed.
When both SSBY and LSON are cleared to 0 in SYSCR1 and a SLEEP instruction is executed,
sleep mode is entered. Direct transfer to active (high-speed) mode or to subactive mode is also
possible. See section 5.8, Direct Transfer, below for details.
• Clearing by RES pin
When the RES pin is driven low, a transition is made to the reset state and active (mediumspeed) mode is cleared.
5.7.3
Operating Frequency in Active (Medium-Speed) Mode
Operation in active (medium-speed) mode is clocked at the frequency designated by the MA1 and
MA0 bits in SYSCR1.
Rev. 8.00 Mar. 09, 2010 Page 138 of 658
REJ09B0042-0800
Section 5 Power-Down Modes
5.8
Direct Transfer
5.8.1
Overview of Direct Transfer
The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed)
mode, and subactive mode. A direct transfer is a transition among these three modes without the
stopping of program execution. A direct transfer can be made by executing a SLEEP instruction
while the DTON bit in SYSCR2 is set to 1. After the mode transition, direct transfer interrupt
exception handling starts.
If the direct transfer interrupt is disabled in interrupt enable register 2 (IENR2), a transition is
made instead to sleep mode or watch mode. Note that if a direct transition is attempted while the I
bit in CCR is set to 1, sleep mode or watch mode will be entered, and it will be impossible to clear
the resulting mode by means of an interrupt.
• Direct transfer from active (high-speed) mode to active (medium-speed) mode
When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and
LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is set to 1, and the DTON
bit in SYSCR2 is set to 1, a transition is made to active (medium-speed) mode via sleep mode.
• Direct transfer from active (medium-speed) mode to active (high-speed) mode
When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and
LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the
DTON bit in SYSCR2 is set to 1, a transition is made to active (high-speed) mode via sleep
mode.
• Direct transfer from active (high-speed) mode to subactive mode
When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and
LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in
TMA is set to 1, a transition is made to subactive mode via watch mode.
• Direct transfer from subactive mode to active (high-speed) mode
When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is
set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0,
the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made
directly to active (high-speed) mode via watch mode after the waiting time set in SYSCR1 bits
STS2 to STS0 has elapsed.
Rev. 8.00 Mar. 09, 2010 Page 139 of 658
REJ09B0042-0800
Section 5 Power-Down Modes
• Direct transfer from active (medium-speed) mode to subactive mode
When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and
LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in
TMA is set to 1, a transition is made to subactive mode via watch mode.
• Direct transfer from subactive mode to active (medium-speed) mode
When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is
set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is set to 1, the
DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made
directly to active (medium-speed) mode via watch mode after the waiting time set in SYSCR1
bits STS2 to STS0 has elapsed.
5.8.2
Direct Transition Times
1. Time for direct transition from active (high-speed) mode to active (medium-speed) mode
A direct transition from active (high-speed) mode to active (medium-speed) mode is performed by
executing a SLEEP instruction in active (high-speed) mode while bits SSBY and LSON are both
cleared to 0 in SYSCR1, and bits MSON and DTON are both set to 1 in SYSCR2. The time from
execution of the SLEEP instruction to the end of interrupt exception handling (the direct transition
time) is given by equation (1) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
processing states) } × (tcyc before transition) + (number of interrupt
exception handling execution states) × (tcyc after transition)
.................................. (1)
Example: Direct transition time = (2 + 1) × 2tosc + 14 × 16tosc = 230tosc (when φ/8 is selected
as the CPU operating clock)
[Legend]
tosc: OSC clock cycle time
tcyc: System clock (φ) cycle time
Rev. 8.00 Mar. 09, 2010 Page 140 of 658
REJ09B0042-0800
Section 5 Power-Down Modes
2. Time for direct transition from active (medium-speed) mode to active (high-speed) mode
A direct transition from active (medium-speed) mode to active (high-speed) mode is performed by
executing a SLEEP instruction in active (medium-speed) mode while bits SSBY and LSON are
both cleared to 0 in SYSCR1, and bit MSON is cleared to 0 and bit DTON is set to 1 in SYSCR2.
The time from execution of the SLEEP instruction to the end of interrupt exception handling (the
direct transition time) is given by equation (2) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
processing states) } × (tcyc before transition) + (number of interrupt
exception handling execution states) × (tcyc after transition)
.................................. (2)
Example: Direct transition time = (2 + 1) × 16tosc + 14 × 2tosc = 76tosc (when φ/8 is selected as
the CPU operating clock)
[Legend]
tosc: OSC clock cycle time
tcyc: System clock (φ) cycle time
3. Time for direct transition from subactive mode to active (high-speed) mode
A direct transition from subactive mode to active (high-speed) mode is performed by executing a
SLEEP instruction in subactive mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in
SYSCR1, bit MSON is cleared to 0 and bit DTON is set to 1 in SYSCR2, and bit TMA3 is set to 1
in TMA. The time from execution of the SLEEP instruction to the end of interrupt exception
handling (the direct transition time) is given by equation (3) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
processing states) } × (tsubcyc before transition) + { (wait time set in
STS2 to STS0) + (number of interrupt exception handling execution
states) } × (tcyc after transition)
........................ (3)
Example: Direct transition time = (2 + 1) × 8tw + (8192 + 14) × 2tosc = 24tw + 16412tosc (when
φw/8 is selected as the CPU operating clock, and wait time = 8192 states)
[Legend]
tosc:
tw:
tcyc:
tsubcyc:
OSC clock cycle time
Watch clock cycle time
System clock (φ) cycle time
Subclock (φSUB) cycle time
Rev. 8.00 Mar. 09, 2010 Page 141 of 658
REJ09B0042-0800
Section 5 Power-Down Modes
4. Time for direct transition from subactive mode to active (medium-speed) mode
A direct transition from subactive mode to active (medium-speed) mode is performed by
executing a SLEEP instruction in subactive mode while bit SSBY is set to 1 and bit LSON is
cleared to 0 in SYSCR1, bits MSON and DTON are both set to 1 in SYSCR2, and bit TMA3 is set
to 1 in TMA. The time from execution of the SLEEP instruction to the end of interrupt exception
handling (the direct transition time) is given by equation (4) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
processing states) } × (tsubcyc before transition) + { (wait time set in
STS2 to STS0) + (number of interrupt exception handling execution
states) } × (tcyc after transition)
........................ (4)
Example: Direct transition time = (2 + 1) × 8tw + (8192 + 14) × 16tosc = 24tw + 131296tosc
(when φw/8 or φ/8 is selected as the CPU operating clock, and wait time = 8192 states)
[Legend]
tosc:
tw:
tcyc:
tsubcyc:
OSC clock cycle time
Watch clock cycle time
System clock (φ) cycle time
Subclock (φSUB) cycle time
5.8.3
Notes on External Input Signal Changes before/after Direct Transition
1. Direct transition from active (high-speed) mode to subactive mode
Since the mode transition is performed via watch mode, see section 5.3.5, Notes on External
Input Signal Changes before/after Standby Mode.
2. Direct transition from active (medium-speed) mode to subactive mode
Since the mode transition is performed via watch mode, see section 5.3.5, Notes on External
Input Signal Changes before/after Standby Mode.
3. Direct transition from subactive mode to active (high-speed) mode
Since the mode transition is performed via watch mode, see section 5.3.5, Notes on External
Input Signal Changes before/after Standby Mode.
4. Direct transition from subactive mode to active (medium-speed) mode
Since the mode transition is performed via watch mode, see section 5.3.5, Notes on External
Input Signal Changes before/after Standby Mode.
Rev. 8.00 Mar. 09, 2010 Page 142 of 658
REJ09B0042-0800
Section 5 Power-Down Modes
5.9
Module Standby Mode
5.9.1
Setting Module Standby Mode
Module standby mode is set for individual peripheral functions. All the on-chip peripheral
modules can be placed in module standby mode. When a module enters module standby mode,
the system clock supply to the module is stopped and operation of the module halts. This state is
identical to standby mode.
Module standby mode is set for a particular module by setting the corresponding bit to 0 in clock
stop register 1 (CKSTPR1) or clock stop register 2 (CKSTPR2). (See table 5.5.)
5.9.2
Clearing Module Standby Mode
Module standby mode is cleared for a particular module by setting the corresponding bit to 1 in
clock stop register 1 (CKSTPR1) or clock stop register 2 (CKSTPR2). (See table 5.5.)
Following a reset, clock stop register 1 (CKSTPR1) and clock stop register 2 (CKSTPR2) are both
initialized to H'FF.
Table 5.5
Setting and Clearing Module Standby Mode by Clock Stop Register
Register Name
Bit Name
CKSTPR1
TACKSTP
TCCKSTP
TFCKSTP
TGCKSTP
ADCKSTP
S32CKSTP
Operation
1
Timer A module standby mode is cleared
0
Timer A is set to module standby mode
1
Timer C module standby mode is cleared
0
Timer C is set to module standby mode
1
Timer F module standby mode is cleared
0
Timer F is set to module standby mode
1
Timer G module standby mode is cleared
0
Timer G is set to module standby mode
1
A/D converter module standby mode is cleared
0
A/D converter is set to module standby mode
1
SCI3 module standby mode is cleared
0
SCI3 is set to module standby mode
Rev. 8.00 Mar. 09, 2010 Page 143 of 658
REJ09B0042-0800
Section 5 Power-Down Modes
Register Name
Bit Name
CKSTPR2
LDCKSTP
PW1CKSTP
WDCKSTP
AECKSTP
PW2CKSTP
LVDCKSTP*
Operation
1
LCD module standby mode is cleared
0
LCD is set to module standby mode
1
PWM1 module standby mode is cleared
0
PWM1 is set to module standby mode
1
Watchdog timer module standby mode is cleared
0
Watchdog timer is set to module standby mode
1
Asynchronous event counter module standby mode
is cleared
0
Asynchronous event counter is set to module standby
mode
1
PWM2 module standby mode is cleared
0
PWM2 is set to module standby mode
1
LVD module standby mode is cleared
0
LVD is set to module standby mode
Notes: For details of module operation, see the sections on the individual modules.
* LVDCKSTP is implemented on the H8/38124 group only.
5.10
Usage Note
5.10.1
Contention Between Module Standby and Interrupts
If, due to timing with which a peripheral module issues interrupt requests, the module in question
is set to module standby mode before an interrupt is processed, the module will stop with the
interrupt request still pending. In this situation, interrupt processing will be repeated indefinitely
unless interrupts are prohibited.
It is therefore necessary to ensure that no interrupts are generated when a module is set to module
standby mode. The surest way to do this is to specify the module standby mode setting only when
interrupts are prohibited (interrupts prohibited using the interrupt enable register or interrupts
masked using bit CCR-1).
Rev. 8.00 Mar. 09, 2010 Page 144 of 658
REJ09B0042-0800
Section 6 ROM
Section 6 ROM
6.1
Overview
The H8/38024, H8/38024S, and H8/38124 have 32 Kbytes of on-chip mask ROM, the H8/38023,
H8/38023S, and H8/38123 have 24 Kbytes, the H8/38022, H8/38022S, and H8/38122 have 16
Kbytes, the H8/38021, H8/38021S, and H8/38121 have 12 Kbytes, and the H8/38020, H8/38020S,
and H8/38120 have 8 Kbytes. The ROM is connected to the CPU by a 16-bit data bus, allowing
high-speed two-state access for both byte data and word data. The H8/38024 has a ZTAT version
and F-ZTAT version with 32-Kbyte PROM and flash memory. F-ZTAT™ versions of the
H8/38124 and H8/38122 are available. The former has 32 Kbytes, and the latter 16 Kbytes, of
flash memory.
6.1.1
Block Diagram
Figure 6.1 shows a block diagram of the on-chip ROM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'0000
H'0000
H'0001
H'0002
H'0002
H'0003
On-chip ROM
H'7FFE
H'7FFE
H'7FFF
Even-numbered
address
Odd-numbered
address
Figure 6.1 ROM Block Diagram (H8/38024)
Rev. 8.00 Mar. 09, 2010 Page 145 of 658
REJ09B0042-0800
Section 6 ROM
6.2
H8/38024 PROM Mode
6.2.1
Setting to PROM Mode
If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a
microcontroller and allows the PROM to be programmed in the same way as the standard
HN27C101 EPROM. However, page programming is not supported. Table 6.1 shows how to set
the chip to PROM mode.
Table 6.1
Setting to PROM Mode
Pin Name
Setting
TEST
High level
PB0/AN0
Low level
PB1/AN1
PB2/AN2
6.2.2
High level
Socket Adapter Pin Arrangement and Memory Map
A standard PROM programmer can be used to program the PROM. A socket adapter is required
for conversion to 32 pins.
Figure 6.2 shows the pin-to-pin wiring of the socket adapter. Figure 6.3 shows a memory map.
Rev. 8.00 Mar. 09, 2010 Page 146 of 658
REJ09B0042-0800
Section 6 ROM
H8/38024
EPROM socket
FP-80A, TFP-80C
FP-80B
12
14
RES
Pin
VPP
1
21
23
P60
EO0
13
22
24
P61
EO1
14
23
25
P62
EO2
15
24
26
P63
EO3
17
25
27
P64
EO4
18
26
28
P65
EO5
19
27
29
P66
EO6
20
28
30
P67
EO7
21
69
71
P40
EA0
12
70
72
P41
EA1
11
63
65
P32
EA2
10
64
66
P33
EA3
9
65
67
P34
EA4
8
66
68
P35
EA5
7
67
69
P36
EA6
6
68
70
P37
EA7
5
29
31
P70
EA8
27
72
74
P43
EA9
26
31
33
P72
EA10
23
32
34
P73
EA11
25
33
35
P74
EA12
4
34
36
P75
EA13
28
35
37
P76
EA14
29
57
59
P93
EA15
3
58
60
P94
EA16
36
38
P77
CE
22
30
32
P71
OE
24
56
58
P92
PGM
31
52
54
VCC
VCC
32
1
3
AVCC
11
13
TEST
75
77
PB2
54
56
P90
55
57
P91
59
61
P95
53
55
VSS
8
10
VSS = AVSS
VSS
16
6
8
73
75
PB0
74
76
PB1
Pin
HN27C101 (32-pin)
2
X1
Note: Pins not indicated in the figure should be left open.
Figure 6.2 Socket Adapter Pin Correspondence (with HN27C101)
Rev. 8.00 Mar. 09, 2010 Page 147 of 658
REJ09B0042-0800
Section 6 ROM
Address in
MCU mode
Address in
PROM mode
H'0000
H'0000
On-chip PROM
H'7FFF
H'7FFF
Uninstalled area*
H'1FFFF
Note: * The output data is not guaranteed if this address area is read in PROM mode.
Therefore, when programming with a PROM programmer, be sure to specify
addresses from H'0000 to H'7FFF. If programming is inadvertently performed from
H'8000 onward, it may not be possible to continue PROM programming and
verification.
When programming, H'FF should be set as the data in this address area (H'8000 to
H'1FFFF).
Figure 6.3 H8/38024 Memory Map in PROM Mode
Rev. 8.00 Mar. 09, 2010 Page 148 of 658
REJ09B0042-0800
Section 6 ROM
6.3
H8/38024 Programming
The write, verify, and other modes are selected as shown in table 6.2 in H8/38024 PROM mode.
Table 6.2
Mode Selection in PROM Mode (H8/38024)
Pins
Mode
CE
OE
PGM
VPP
VCC
EO7 to EO0
EA16 to EA0
Write
L
H
L
VPP
VCC
Data input
Address input
Verify
L
L
H
VPP
VCC
Data output
Address input
Programming
L
L
L
VPP
VCC
High impedance
Address input
disabled
L
H
H
H
L
L
H
H
H
[Legend]
L:
Low level
H:
High level
VPP:
VPP level
VCC: VCC level
The specifications for writing and reading are identical to those for the standard HN27C101
EPROM. However, page programming is not supported, and so page programming mode must not
be set. A PROM programmer that only supports page programming mode cannot be used. When
selecting a PROM programmer, ensure that it supports high-speed, high-reliability byte-by-byte
programming. Also, be sure to specify addresses from H'0000 to H'7FFF.
6.3.1
Writing and Verifying
An efficient, high-speed, high-reliability method is available for writing and verifying the PROM
data. This method achieves high speed without voltage stress on the device and without lowering
the reliability of written data. The basic flow of this high-speed, high-reliability programming
method is shown in figure 6.4.
Rev. 8.00 Mar. 09, 2010 Page 149 of 658
REJ09B0042-0800
Section 6 ROM
Start
Set write/verify mode
VCC = 6.0 V ± 0.25 V, VPP = 12.5 V ± 0.3 V
Address = 0
n=0
n+1 →n
No
Yes
n < 25
Write time t PW = 0.2 ms ± 5%
No
Address + 1 → address
Verify
Yes
Write time t OPW = 0.2n ms
Last address?
No
Yes
Set read mode
VCC = 5.0 V ± 0.25 V, VPP = VCC
No
Error
Read all
addresses?
Yes
End
Figure 6.4 High-Speed, High-Reliability Programming Flowchart
Rev. 8.00 Mar. 09, 2010 Page 150 of 658
REJ09B0042-0800
Section 6 ROM
Tables 6.3 and 6.4 give the electrical characteristics in programming mode.
Table 6.3
DC Characteristics
Conditions: VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol Min
Typ
Max
Unit
Test
Condition
Input high-level
voltage
EO7 to EO0,
EA16 to EA0,
OE, CE, PGM
VIH
2.4
—
VCC + 0.3
V
Input lowlevel voltage
EO7 to EO0,
EA16 to EA0,
OE, CE, PGM
VIL
–0.3
—
0.8
V
Output high-level
voltage
EO7 to EO0
VOH
2.4
—
—
V
IOH = –200 µA
Output low-level
voltage
EO7 to EO0
VOL
—
—
0.45
V
IOL = 0.8 mA
Input leakage
current
EO7 to EO0,
EA16 to EA0,
OE, CE, PGM
|ILI|
—
—
2
µA
Vin = 5.25 V/
0.5 V
VCC current
ICC
—
—
40
mA
VPP current
IPP
—
—
40
mA
Rev. 8.00 Mar. 09, 2010 Page 151 of 658
REJ09B0042-0800
Section 6 ROM
Table 6.4
AC Characteristics
Conditions: VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V, Ta = 25°C ±5°C
Item
Symbol
Min
Typ
Max
Unit
Test Condition
Address setup time
tAS
2
—
—
µs
Figure 6.5*
OE setup time
tOES
2
—
—
µs
Data setup time
tDS
2
—
—
µs
Address hold time
tAH
0
—
—
µs
Data hold time
2
—
—
µs
Data output disable time
tDH
2
tDF*
—
—
130
ns
VPP setup time
tVPS
2
—
—
µs
Programming pulse width
tPW
0.19
0.20
0.21
ms
PGM pulse width for overwrite
programming
3
tOPW *
0.19
—
5.25
ms
CE setup time
tCES
2
—
—
µs
VCC setup time
tVCS
2
—
—
µs
Data output delay time
tOE
0
—
200
ns
1
Notes: 1. Input pulse level: 0.45 V to 2.4 V
Input rise time/fall time ≤ 20 ns
Timing reference levels Input: 0.8 V, 2.0 V
Output: 0.8 V, 2.0 V
2. tDF is defined at the point at which the output is floating and the output level cannot be
read.
3. tOPW is defined by the value given in figure 6.4, High-Speed, High-Reliability
Programming Flow Chart.
Rev. 8.00 Mar. 09, 2010 Page 152 of 658
REJ09B0042-0800
Section 6 ROM
Figure 6.5 shows a PROM write/verify timing diagram.
Write
Verify
Address
tAS
Data
tAH
Input data
tDS
VPP
tDH
tDF
VPP
VCC
VCC
Output data
tVPS
VCC+1
VCC
tVCS
CE
tCES
PGM
tPW
OE
tOES
tOE
tOPW*
Note: * tOPW is defined by the value shown in figure 6.4, High-Speed, High-Reliability Programming Flowchart.
Figure 6.5 PROM Write/Verify Timing
Rev. 8.00 Mar. 09, 2010 Page 153 of 658
REJ09B0042-0800
Section 6 ROM
6.3.2
Programming Precautions
• Use the specified programming voltage and timing.
The programming voltage in PROM mode (VPP) is 12.5 V. Use of a higher voltage can
permanently damage the chip. Be especially careful with respect to PROM programmer
overshoot.
Setting the PROM programmer to Renesas specifications for the HN27C101 will result in
correct VPP of 12.5 V.
• Make sure the index marks on the PROM programmer socket, socket adapter, and chip are
properly aligned. If they are not, the chip may be destroyed by excessive current flow. Before
programming, be sure that the chip is properly mounted in the PROM programmer.
• Avoid touching the socket adapter or chip while programming, since this may cause contact
faults and write errors.
• Take care when setting the programming mode, as page programming is not supported.
• When programming with a PROM programmer, be sure to specify addresses from H'0000 to
H'7FFF. If programming is inadvertently performed from H'8000 onward, it may not be
possible to continue PROM programming and verification. When programming, H'FF should
be set as the data in address area H'8000 to H'1FFFF.
Rev. 8.00 Mar. 09, 2010 Page 154 of 658
REJ09B0042-0800
Section 6 ROM
6.4
Reliability of Programmed Data
A highly effective way to improve data retention characteristics is to bake the programmed chips
at 150°C, then screen them for data errors. This procedure quickly eliminates chips with PROM
memory cells prone to early failure.
Figure 6.6 shows the recommended screening procedure.
Program chip and verify
programmed data
Bake chip for 24 to 48 hours at
125°C to 150°C with power off
Read and check program
Install
Figure 6.6 Recommended Screening Procedure
If a series of programming errors occurs while the same PROM programmer is in use, stop
programming and check the PROM programmer and socket adapter for defects. Please inform
Renesas Technology of any abnormal conditions noted during or after programming or in
screening of program data after high-temperature baking.
Rev. 8.00 Mar. 09, 2010 Page 155 of 658
REJ09B0042-0800
Section 6 ROM
6.5
Flash Memory Overview
6.5.1
Features
The features of the 32-Kbyte or 16-Kbyte flash memory built into the flash memory versions are
summarized below.
• Programming/erase methods
⎯ The flash memory is programmed 128 bytes at a time. Erase is performed in single-block
units. On the HD64F38024, HD64F38024R, and HD64F38124 the flash memory is
configured as follows: 1 Kbyte × 4 blocks, 28 Kbytes × 1 block. On the HD64F38122 the
flash memory is configured as follows: 1 Kbyte × 4 blocks, 12 Kbytes × 1 block. To erase
the entire flash memory, each block must be erased in turn.
• Reprogramming capability
⎯ The HD64F38024R, HD64F38124, and HD64F38122 can be reprogrammed up to 1,000
times and the HD64F38024 up to 100 times.
• On-board programming
⎯ On-board programming/erasing can be done in boot mode, in which the boot program built
into the chip is started to erase or program of the entire flash memory. In normal user
program mode, individual blocks can be erased or programmed.
• Programmer mode
⎯ Flash memory can be programmed/erased in programmer mode using a PROM
programmer, as well as in on-board programming mode.
• Automatic bit rate adjustment
⎯ For data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match
the transfer bit rate of the host.
• Programming/erasing protection
⎯ Sets software protection against flash memory programming/erasing.
• Power-down mode
⎯ The power supply circuit is partly halted in the subactive mode and can be read in the
power-down mode.
Note: The system clock oscillator must be used when programming or erasing the flash memory
of the HD64F38124 and HD64F38122.
Rev. 8.00 Mar. 09, 2010 Page 156 of 658
REJ09B0042-0800
Section 6 ROM
Block Diagram
Internal address bus
Internal data bus (16 bits)
FLMCR1
Module bus
6.5.2
FLMCR2
Bus interface/controller
EBR
Operating
mode
TES pin
P95 pin
P34 pin
FLPWCR
FENR
Flash memory
[Legend]
FLMCR1:
FLMCR2:
EBR:
FLPWCR:
FENR:
Flash memory control register 1
Flash memory control register 2
Erase block register
Flash memory power control register
Flash memory enable register
Figure 6.7 Block Diagram of Flash Memory
Rev. 8.00 Mar. 09, 2010 Page 157 of 658
REJ09B0042-0800
Section 6 ROM
6.5.3
Block Configuration
Figure 6.8 shows the block configuration of the flash memory. The thick lines indicate erasing
units, the narrow lines indicate programming units, and the values are addresses. In versions with
32 Kbytes of flash memory, the flash memory is divided into 1 Kbyte × 4 blocks and 28 Kbytes ×
1 block. In versions with 16 Kbytes of flash memory, the flash memory is divided into 1 Kbyte × 4
blocks and 12 Kbytes × 1 block. Erasing is performed in these units. Programming is performed in
128-byte units starting from an address with lower eight bits H'00 or H'80.
Erase unit
H'0000
H'0001
H'0002
H'0080
H'0081
H'0082
H'00FF
H'0380
H'0381
H'0382
H'03FF
H'0400
H'0401
H'0402
H'0480
H'0481
H'0482
H'04FF
H'0780
H'0781
H'0782
H'07FF
H'0800
H'0801
H'0802
H'0880
H'0881
H'0882
H'0B80
H'0B81
H'0B82
H'0C00
H'0C01
H'0C02
H'0C80
H'0C81
H'0C82
Programming unit: 128 bytes
H'007F
1 Kbyte
Erase unit
Programming unit: 128 bytes
H'047F
1 Kbyte
Erase unit
Programming unit: 128 bytes
H'087F
H'08FF
1 Kbyte
Erase unit
H'0BFF
Programming unit: 128 bytes
H'0C7F
H'0CFF
1 Kbyte
Erase unit
H'0F80
H'0F81
H'0F82
H'1000
H'1001
H'1002
H'1080
H'1081
H'1082
H'10FF
H'7F80
H'7F81
H'7F82
H'7FFF
H'0FFF
Programming unit: 128 bytes
H'107F
28 Kbytes
Figure 6.8(1) Block Configuration of 32-Kbyte Flash Memory
Rev. 8.00 Mar. 09, 2010 Page 158 of 658
REJ09B0042-0800
Section 6 ROM
Erase unit
H'0000
H'0001
H'0002
H'0080
H'0081
H'0082
H'00FF
H'0380
H'0381
H'0382
H'03FF
H'0400
H'0401
H'0402
H'0480
H'0481
H'0482
H'04FF
H'0780
H'0781
H'0782
H'07FF
H'0800
H'0801
H'0802
H'0880
H'0881
H'0882
H'08FF
H'0B80
H'0B81
H'0B82
H'0BFF
H'0C00
H'0C01
H'0C02
H'0C80
H'0C81
H'0C82
H'0F80
H'0F81
H'0F82
H'1000
H'1001
H'1002
H'1080
H'1081
H'1082
H'10FF
H'3F80
H'3F81
H'3F82
H'3FFF
Programming unit: 128 bytes
H'007F
1 Kbyte
Erase unit
Programming unit: 128 bytes
H'047F
1 Kbyte
Erase unit
Programming unit: 128 bytes
H'087F
1 Kbyte
Erase unit
Programming unit: 128 bytes
H'0C7F
H'0CFF
1 Kbyte
Erase unit
H'0FFF
Programming unit: 128 bytes
H'107F
12 Kbytes
Figure 6.8(2) Block Configuration of 16-Kbyte Flash Memory
Rev. 8.00 Mar. 09, 2010 Page 159 of 658
REJ09B0042-0800
Section 6 ROM
6.5.4
Register Configuration
Table 6.5 lists the register configuration to control the flash memory when the built in flash
memory is effective.
Table 6.5
Register Configuration
Register Name
Abbreviation
R/W
Initial Value
Address
Flash memory control register 1
FLMCR1
R/W
H'00
H'F020
Flash memory control register 2
FLMCR2
R
H'00
H'F021
Flash memory power control register
FLPWCR
R/W
H'00
H'F022
Erase block register
EBR
R/W
H'00
H'F023
Flash memory enable register
FENR
R/W
H'00
H'F02B
Note: FLMCR1, FLMCR2, FLPWCR, EBR, and FENR are 8 bit registers. Only byte access is
enabled which are two-state access. These registers are dedicated to the product in which
flash memory is included. The product in which PROM or ROM is included does not have
these registers. When the corresponding address is read in these products, the value is
undefined. A write is disabled.
6.6
Descriptions of Registers of the Flash Memory
6.6.1
Flash Memory Control Register 1 (FLMCR1)
Bit
7
6
5
4
3
2
1
0
—
SWE
ESU
PSU
EV
PV
E
P
Initial value
0
0
0
0
0
0
0
0
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FLMCR1 is a register that makes the flash memory change to program mode, program-verify
mode, erase mode, or erase-verify mode. For details on register setting, refer to section 6.8, Flash
Memory Programming/Erasing. By setting this register, the flash memory enters program mode,
erase mode, program-verify mode, or erase-verify mode. Read the data in the state that bits 6 to 0
of this register are cleared when using flash memory as normal built-in ROM.
Bit 7—Reserved
This bit is always read as 0 and cannot be modified.
Rev. 8.00 Mar. 09, 2010 Page 160 of 658
REJ09B0042-0800
Section 6 ROM
Bit 6—Software Write Enable (SWE)
This bit is to set enabling/disabling of programming/enabling of flash memory (set when bits 5 to
0 and the EBR register are to be set).
Bit 6
SWE
Description
0
Programming/erasing is disabled. Other FLMCR1 register bits and all EBR bits
cannot be set.
(initial value)
1
Flash memory programming/erasing is enabled.
Bit 5—Erase Setup (ESU)
This bit is to prepare for changing to erase mode. Set this bit to 1 before setting the E bit to 1 in
FLMCR1 (do not set SWE, PSU, EV, PV, E, and P bits at the same time).
Bit 5
ESU
Description
0
The erase setup state is cancelled
1
The flash memory changes to the erase setup state. Set this bit to 1 before setting
the E bit to 1 in FLMCR1.
(initial value)
Bit 4—Program Setup (PSU)
This bit is to prepare for changing to program mode. Set this bit to 1 before setting the P bit to 1
in FLMCR1 (do not set SWE, ESU, EV, PV, E, and P bits at the same time).
Bit 4
PSU
Description
0
The program setup state is cancelled
1
The flash memory changes to the program setup state. Set this bit to 1 before
setting the P bit to 1 in FLMCR1.
(initial value)
Bit 3—Erase-Verify (EV)
This bit is to set changing to or cancelling erase-verify mode (do not set SWE, ESU, PSU, PV, E,
and P bits at the same time).
Rev. 8.00 Mar. 09, 2010 Page 161 of 658
REJ09B0042-0800
Section 6 ROM
Bit 3
EV
Description
0
Erase-verify mode is cancelled
1
The flash memory changes to erase-verify mode
(initial value)
Bit 2—Program-Verify (PV)
This bit is to set changing to or cancelling program-verify mode (do not set SWE, ESU, PSU, EV,
E, and P bits at the same time).
Bit 2
PV
Description
0
Program-verify mode is cancelled
1
The flash memory changes to program-verify mode
(initial value)
Bit 1—Erase (E)
This bit is to set changing to or cancelling erase mode (do not set SWE, ESU, PSU, EV, PV, and P
bits at the same time).
Bit 1
E
Description
0
Erase mode is cancelled
1
When this bit is set to 1, while the SWE = 1 and ESU = 1, the flash memory
changes to erase mode.
(initial value)
Bit 0—Program (P)
This bit is to set changing to or cancelling program mode (do not set SWE, ESU, PSU, EV, PV,
and E bits at the same time).
Bit 0
P
Description
0
Program mode is cancelled
1
When this bit is set to 1, while the SWE = 1 and PSU = 1, the flash memory
changes to program mode.
Rev. 8.00 Mar. 09, 2010 Page 162 of 658
REJ09B0042-0800
(initial value)
Section 6 ROM
6.6.2
Flash Memory Control Register 2 (FLMCR2)
Bit
7
6
5
4
3
2
1
0
FLER
—
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
—
—
—
—
—
—
—
FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a
read-only register, and should not be written to.
Bit 7—Flash Memory Error (FLER)
This bit is set when the flash memory detects an error and goes to the error-protection state during
programming or erasing to the flash memory. See section 6.9.3, Error Protection, for details.
Bit 7
FLER
Description
0
The flash memory operates normally.
1
Indicates that an error has occurred during an operation on flash memory
(programming or erasing).
(initial value)
Bits 6 to 0—Reserved
These bits are always read as 0 and cannot be modified.
Rev. 8.00 Mar. 09, 2010 Page 163 of 658
REJ09B0042-0800
Section 6 ROM
6.6.3
Erase Block Register (EBR)
Bit
7
6
5
4
3
2
1
0
—
—
—
EB4
EB3
EB2
EB1
EB0
Initial value
0
0
0
0
0
0
0
0
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
EBR specifies the flash memory erase area block. EBR is initialized to H'00 when the SWE bit in
FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR to be
automatically cleared to 0. When each bit is set to 1 in EBR, the corresponding block can be
erased. Other blocks change to the erase-protection state. See table 6.6 for the method of dividing
blocks of the flash memory. When the whole bits are to be erased, erase them in turn in unit of a
block.
Table 6.6
Division of Blocks to Be Erased
EBR
Bit Name
Block (Size)
Address
0
EB0
EB0 (1 Kbyte)
H'0000 to H'03FF
1
EB1
EB1 (1 Kbyte)
H'0400 to H'07FF
2
EB2
EB2 (1 Kbyte)
H'0800 to H'0BFF
3
EB3
EB3 (1 Kbyte)
H'0C00 to H'0FFF
4
EB4
EB4 (12 Kbytes)
H'1000 to H'3FFF (HD64F38122)
EB4 (28 Kbytes)
H'1000 to H'7FFF (HD64F38124,
HD64F38024, HD64F38024R)
6.6.4
Flash Memory Power Control Register (FLPWCR)
Bit
7
6
5
4
3
2
1
0
PDWND
—
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
—
—
—
—
—
—
—
FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI
switches to subactive mode. The power supply circuit can be read in the subactive mode, although
it is partly halted in the power-down mode.
Rev. 8.00 Mar. 09, 2010 Page 164 of 658
REJ09B0042-0800
Section 6 ROM
Bit 7—Power-down Disable (PDWND)
This bit selects the power-down mode of the flash memory when a transition to the subactive
mode is made.
Bit 7
PDWND
Description
0
When this bit is 0 and a transition is made to the subactive mode, the flash memory
enters the power-down mode.
(initial value)
1
When this bit is 1, the flash memory remains in the normal mode even after a
transition is made to the subactive mode.
Bits 6 to 0—Reserved
These bits are always read as 0 and cannot be modified.
6.6.5
Flash Memory Enable Register (FENR)
Bit
7
6
5
4
3
2
1
0
FLSHE
—
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
—
—
—
—
—
—
—
FENR controls CPU access to the flash memory control registers, FLMCR1, FLMCR2, EBR, and
FLPWCR.
Bit 7—Flash Memory Control Register Enable (FLSHE)
This bit controls access to the flash memory control registers.
Bit 7
FLSHE
Description
0
Flash memory control registers cannot be accessed
1
Flash memory control registers can be accessed
(initial value)
Bits 6 to 0—Reserved
These bits are always read as 0 and cannot be modified.
Rev. 8.00 Mar. 09, 2010 Page 165 of 658
REJ09B0042-0800
Section 6 ROM
6.7
On-Board Programming Modes
There are two modes for programming/erasing of the flash memory; boot mode, which enables onboard programming/erasing, and programmer mode, in which programming/erasing is performed
with a PROM programmer. On-board programming/erasing can also be performed in user
program mode. At reset-start in reset mode, the series of HD64F38024, HD64F38024R,
HD64F38124, and HD64F38122 changes to a mode depending on the TEST pin settings, P95 pin
settings, and input level of each port, as shown in table 6.7. The input level of each pin must be
defined four states before the reset ends.
When changing to boot mode, the boot program built into this LSI is initiated. The boot program
transfers the programming control program from the externally-connected host to on-chip RAM
via SCI3. After erasing the entire flash memory, the programming control program is executed.
This can be used for programming initial values in the on-board state or for a forcible return when
programming/erasing can no longer be done in user program mode. In user program mode,
individual blocks can be erased and programmed by branching to the user program/erase control
program prepared by the user.
Table 6.7
Setting Programming Modes
TEST
P95
P34
PB0
PB1
PB2
LSI State after Reset End
0
1
X
X
X
X
User Mode
0
0
1
X
X
X
Boot Mode
1
X
X
0
0
0
Programmer Mode
X: Don’t care
6.7.1
Boot Mode
Table 6.8 shows the boot mode operations between reset end and branching to the programming
control program.
1. When boot mode is used, the flash memory programming control program must be prepared in
the host beforehand. Prepare a programming control program in accordance with the
description in section 6.8, Flash Memory Programming/Erasing.
2. SCI3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop
bit, and no parity. The inversion function of TXD and RXD pins by the SPCR register is set to
“Not to be inverted,” so do not put the circuit for inverting a value between the host and this
LSI.
Rev. 8.00 Mar. 09, 2010 Page 166 of 658
REJ09B0042-0800
Section 6 ROM
3. When the boot program is initiated, the chip measures the low-level period of asynchronous
SCI communication data (H'00) transmitted continuously from the host. The chip then
calculates the bit rate of transmission from the host, and adjusts the SCI3 bit rate to match that
of the host. The reset should end with the RXD pin high. The RXD and TXD pins should be
pulled up on the board if necessary. After the reset is complete, it takes approximately 100
states before the chip is ready to measure the low-level period.
4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the
completion of bit rate adjustment. The host should confirm that this adjustment end indication
(H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could
not be performed normally, initiate boot mode again by a reset. Depending on the host's
transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between
the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit
rate and system clock frequency of this LSI within the ranges listed in table 6.9.
5. In boot mode, a part of the on-chip RAM area is used by the boot program. The area H'F780 to
H'FEEF is the area to which the programming control program is transferred from the host.
The boot program area cannot be used until the execution state in boot mode switches to the
programming control program.
6. Before branching to the programming control program, the chip terminates transfer operations
by SCI3 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value
remains set in BRR. Therefore, the programming control program can still use it for transfer
of write data or verify data with the host. The TXD pin is high (PCR42 = 1, P42 = 1). The
contents of the CPU general registers are undefined immediately after branching to the
programming control program. These registers must be initialized at the beginning of the
programming control program, as the stack pointer (SP), in particular, is used implicitly in
subroutine calls, etc.
7. Boot mode can be cleared by a reset. End the reset after driving the reset pin low, waiting at
least 20 states, and then setting the TEST pin and P95 pin. Boot mode is also cleared when a
WDT overflow occurs.
8. Do not change the TEST pin and P95 pin input levels in boot mode.
Rev. 8.00 Mar. 09, 2010 Page 167 of 658
REJ09B0042-0800
Section 6 ROM
Table 6.8
Boot Mode Operation
Item
Host Operation
LSI Operation
Processing Contents
Processing Contents
Branches to boot program at reset-start.
Bit rate
adjustment
Continuously transmits data H'00 at
specified bit rate.
Flash memory erase
Transmits data H'55 when data H'00
is received and no error occurs.
· Measures low-level period of receive data H'00.
· Calculates bit rate and sets it in BRR of SCI3.
· Transmits data H'00 to the host to indicate that the
adjustment has ended.
Checks flash memory data, erases all flash memory
blocks in case of written data existing, and transmits
data H'AA to host. (If erase could not be done,
transmits data H'FF to host and aborts operation.)
Transfer of
programming control
program
Transmits number of bytes (N) of
programming control program to be
transferred as 2-byte data (low-order
byte following high-order byte)
Transfer of
programming control
program (repeated for
N times)
Transmits 1-byte of programming
control program
Echobacks received data to host and also
transfers it to RAM.
Transmits 1-byte data H'AA to host.
Execution of
Programming
control program
Table 6.9
Echobacks the 2-byte received data to host.
Branches to programming control program
transferred to on-chip RAM and starts execution.
Oscillating Frequencies (fOSC) for which Automatic Adjustment of LSI Bit Rate
Is Possible
Product Group
Host Bit Rate
Oscillating Frequencies (fOSC) Range of LSI
F-ZTAT version of
H8/38024 Group and
F-ZTAT version of
H8/38024R Group
4,800 bps
8 to 10 MHz
2,400 bps
4 to 10 MHz
1,200 bps
2 to 10 MHz
F-ZTAT version of
H8/38124 Group
19,200 bps
16 to 20 MHz
9,600 bps
8 to 20 MHz
4,800 bps
6 to 20 MHz
2,400 bps
2 to 20 MHz
1,200 bps
2 to 20 MHz
Rev. 8.00 Mar. 09, 2010 Page 168 of 658
REJ09B0042-0800
Section 6 ROM
6.7.2
Programming/Erasing in User Program Mode
The term user mode refers to the status when a user program is being executed. On-board
programming/erasing of an individual flash memory block can also be performed in user program
mode by branching to a user program/erase control program. The user must set branching
conditions and provide on-board means of supplying programming data. The flash memory must
contain the user program/erase control program or a program that provides the user program/erase
control program from external memory. As the flash memory itself cannot be read during
programming/erasing, transfer the user program/erase control program to on-chip RAM, as in boot
mode. Figure 6.9 shows a sample procedure for programming/erasing in user program mode.
Prepare a user program/erase control program in accordance with the description in section 6.8,
Flash Memory Programming/Erasing.
Reset-start
No
Program/erase?
Yes
Transfer user program/erase control
program to RAM
Branch to flash memory application
program
Branch to user program/erase control
program in RAM
Execute user program/erase control
program (flash memory rewrite)
Branch to flash memory application
program
Figure 6.9 Programming/Erasing Flowchart Example in User Program Mode
Rev. 8.00 Mar. 09, 2010 Page 169 of 658
REJ09B0042-0800
Section 6 ROM
6.7.3
Notes on On-Board Programming
1. You must use the system clock oscillator when programming or erasing flash memory on the
H8/38124 Group. The on-chip oscillator should not be used for programming or erasing flash
memory. See section 4.2, On-Chip Oscillator Selection Method, for information on switching
between the system clock oscillator and the on-chip oscillator.
2. On the H8/38124 Group the watchdog timer operates after a reset is canceled. When executing
a program prepared by the user that performs programming and erasing in the user mode, the
watchdog timer’s overflow cycle should be set to an appropriate value. Refer to section 6.8.1,
Program/Program-Verify, for information on the appropriate watchdog timer overflow cycle
for programming, and refer to section 6.8.2, Erase/Erase-Verify, for information on the
appropriate watchdog timer overflow cycle for erasing.
6.8
Flash Memory Programming/Erasing
A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one
of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify
mode. The programming control program in boot mode and the user program/erase control
program in user program mode use these operating modes in combination to perform
programming/erasing. Flash memory programming and erasing should be performed in
accordance with the descriptions in section 6.8.1, Program/Program-Verify and section 6.8.2,
Erase/Erase-Verify, respectively.
6.8.1
Program/Program-Verify
When writing data or programs to the flash memory, the program/program-verify flowchart shown
in figure 6.10 should be followed. Performing programming operations according to this
flowchart will enable data or programs to be written to the flash memory without subjecting the
chip to voltage stress or sacrificing program data reliability.
1. Programming must be done to an empty address. Do not reprogram an address to which
programming has already been performed.
2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be
performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the
extra addresses.
3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128byte reprogramming data area, and a 128-byte additional-programming data area. Perform
Rev. 8.00 Mar. 09, 2010 Page 170 of 658
REJ09B0042-0800
Section 6 ROM
reprogramming data computation according to table 6.10, and additional programming data
computation according to table 6.11.
4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or
additional-programming data area to the flash memory. The program address and 128-byte
data are latched in the flash memory. The lower 8 bits of the start address in the flash memory
destination area must be H'00 or H'80.
Do not use RTS instruction from data transfer to setting P bit to 1. (This does not apply to the
HD64F38124 and HD64F38122.)
5. The time during which the P bit is set to 1 is the programming time. Figure 6.12 shows the
allowable programming times.
6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
An overflow cycle of approximately 6.6 ms is allowed.
7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 1 bit
is b'0. Verify data can be read in word size from the address to which a dummy write was
performed.
Do not use RTS instruction from dummy write to verify data read. (This does not apply to the
HD64F38124 and HD64F38122.)
8. The maximum number of repetitions of the program/program-verify sequence of the same bit
is 1,000.
Rev. 8.00 Mar. 09, 2010 Page 171 of 658
REJ09B0042-0800
Section 6 ROM
Write pulse application subroutine
Apply Write Pulse
START
Set SWE bit in FLMCR1
WDT enable
Wait 1 μs
Set PSU bit in FLMCR1
Store 128-byte program data in program
data area and reprogram data area
Wait 50 μs
n=1
Set P bit in FLMCR1
m=0
Wait (Wait time = programming time)
Write 128-byte data in RAM reprogram
data area consecutively to flash memory
Clear P bit in FLMCR1
Apply Write pulse
Wait 5 μs
Set PV bit in FLMCR1
Clear PSU bit in FLMCR1
Wait 4 μs
Wait 5 μs
Set block start address as
verify address
Disable WDT
n←n+1
H'FF dummy write to verify address
End Sub
Wait 2 μs
Read verify data
Verify data =
write data?
Increment address
No
m=1
Yes
n≤6?
No
Yes
Additional-programming data
computation
Reprogram data computation
No
128-byte
data verification
completed?
Yes
Clear PV bit in FLMCR1
Wait 2 μs
n ≤ 6?
No
Yes
Successively write 128-byte data from
additional-programming data area
in RAM to flash memory
Sub-Routine-Call
Apply Write Pulse
m=0?
No
n ≤ 1000 ?
Yes
No
Clear SWE bit in FLMCR1
Clear SWE bit in FLMCR1
Wait 100 μs
Wait 100 μs
End of programming
Programming failure
Figure 6.10 Program/Program-Verify Flowchart
Rev. 8.00 Mar. 09, 2010 Page 172 of 658
REJ09B0042-0800
Yes
Section 6 ROM
Table 6.10 Reprogram Data Computation Table
Program Data
Verify Data
Reprogram Data
Comments
0
0
1
Programming completed
0
1
0
Reprogram bit
1
0
1
—
1
1
1
Remains in erased state
Table 6.11 Additional-Program Data Computation Table
Reprogram Data
Verify Data
Additional-Program
Data
Comments
0
0
0
Additional-program bit
0
1
1
No additional programming
1
0
1
No additional programming
1
1
1
No additional programming
In Additional
Programming
Comments
Table 6.12 Programming Time
n
Programming
(Number of Writes) Time
1 to 6
30
10
7 to 1,000
200
—
Note: Time shown in μs.
Rev. 8.00 Mar. 09, 2010 Page 173 of 658
REJ09B0042-0800
Section 6 ROM
6.8.2
Erase/Erase-Verify
When erasing flash memory, the erase/erase-verify flowchart shown in figure 6.11 should be
followed.
1. Prewriting (setting erase block data to all 0s) is not necessary.
2. Erasing is performed in block units. Make only a single-bit specification in the erase block
register (EBR). To erase multiple blocks, each block must be erased in turn.
3. The time during which the E bit is set to 1 is the flash memory erase time.
4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. An
overflow cycle of approximately 19.8 ms is allowed.
5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 1 bit
is b'0. Verify data can be read in word size from the address to which a dummy write was
performed.
Do not use RTS instruction from dummy write to verify data read. (This does not apply to the
HD64F38124 and HD64F38122.)
6. If the read data is not erased successfully, set erase mode again, and repeat the erase/eraseverify sequence as before. The maximum number of repetitions of the erase/erase-verify
sequence is 100.
6.8.3
Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, are disabled while flash memory is being programmed or erased, or while the boot
program is executing, for the following three reasons:
1. Interrupt during programming/erasing may cause a violation of the programming or erasing
algorithm, with the result that normal operation cannot be assured.
2. If interrupt exception handling starts before the vector address is written or during
programming/erasing, a correct vector cannot be fetched and the CPU malfunctions.
3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be
carried out.
Rev. 8.00 Mar. 09, 2010 Page 174 of 658
REJ09B0042-0800
Section 6 ROM
Erase start
SWE bit ← 1
Wait 1 μs
n←1
Set EBR
Enable WDT
ESU bit ← 1
Wait 100 μs
E bit ← 1
Wait 10 ms
E bit ← 0
Wait 10 μs
ESU bit ← 0
Wait 10 μs
Disable WDT
EV bit ← 1
Wait 20 μs
Set block start address as verify address
H'FF dummy write to verify address
Wait 2 μs
n←n+1
Read verify data
No
Verify data = all 1s ?
Increment address
Yes
No
Last address of block ?
Yes
No
EV bit ← 0
EV bit ← 0
Wait 4 μs
Wait 4μs
All erase block erased ?
n ≤100 ?
Yes
No
Yes
SWE bit ← 0
SWE bit ← 0
Wait 100 μs
Wait 100 μs
End of erasing
Erase failure
Figure 6.11 Erase/Erase-Verify Flowchart
Rev. 8.00 Mar. 09, 2010 Page 175 of 658
REJ09B0042-0800
Section 6 ROM
6.9
Program/Erase Protection
There are three kinds of flash memory program/erase protection; hardware protection, software
protection, and error protection.
6.9.1
Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted because of a transition to reset, subactive mode, subsleep mode, watch mode,
or standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2
(FLMCR2), and erase block register (EBR) are initialized. In a reset via the RES pin, the reset
state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In
the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the
AC Characteristics section.
6.9.2
Software Protection
Software protection can be implemented against programming/erasing of all flash memory blocks
by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P or E bit
in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase
block register (EBR), erase protection can be set for individual blocks. When EBR is set to H'00,
erase protection is set for all blocks.
Rev. 8.00 Mar. 09, 2010 Page 176 of 658
REJ09B0042-0800
Section 6 ROM
6.9.3
Error Protection
In error protection, an error is detected when CPU runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
When the following errors are detected during programming/erasing of flash memory, the FLER
bit in FLMCR2 is set to 1, and the error protection state is entered.
• When the flash memory of the relevant address area is read during programming/erasing
(including vector read and instruction fetch)
• Immediately after exception handling excluding a reset during programming/erasing
• When a SLEEP instruction is executed during programming/erasing
The FLMCR1, FLMCR2, and EBR settings are retained, however program mode or erase mode is
aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered
by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be
made to verify mode. Error protection can be cleared only by a power-on reset.
6.10
Programmer Mode
In programmer mode, a PROM programmer can be used to perform programming/erasing via a
socket adapter, just as a discrete flash memory. Use a PROM programmer that supports the MCU
device type with the on-chip Renesas Technology 64-Kbyte flash memory (F-ZTAT64V3). A 10MHz input clock is required. For the conditions for transition to programmer mode, see table 6.7.
6.10.1
Socket Adapter
The socket adapter converts the pin allocation of the HD64F38024, HD64F38024R,
HD64F38124, and HD64F38122 to that of the discrete flash memory HN28F101. The address of
the on-chip flash memory is H'0000 to H'7FFF. Figure 6.12(1) shows a socket-adapter-pin
correspondence diagram of the HD64F38024 and HD64F38024R. Figure 6.12(2) shows a socketadapter-pin correspondence diagram of the HD64F38124 and HD64F38122.
Rev. 8.00 Mar. 09, 2010 Page 177 of 658
REJ09B0042-0800
Section 6 ROM
6.10.2
Programmer Mode Commands
The following commands are supported in programmer mode.
• Memory Read Mode
• Auto-Program Mode
• Auto-Erase Mode
• Status Read Mode
Status polling is used for auto-programming, auto-erasing, and status read modes. In status read
mode, detailed internal information is output after the execution of auto-programming or autoerasing. Table 6.13 shows the sequence of each command. In auto-programming mode, 129 cycles
are required since 128 bytes are written at the same time. In memory read mode, the number of
cycles depends on the number of address write cycles (n).
Table 6.13 Command Sequence in Programmer Mode
1st Cycle
2nd Cycle
Command Name
Number
of Cycles
Mode
Address
Data
Mode
Address
Data
Memory read
1+n
Write
X
H'00
Read
RA
Dout
Auto-program
129
Write
X
H'40
Write
WA
Din
Auto-erase
2
Write
X
H'20
Write
X
H'20
Status read
2
Write
X
H'71
Write
X
H'71
n: the number of address write cycles
Rev. 8.00 Mar. 09, 2010 Page 178 of 658
REJ09B0042-0800
Section 6 ROM
HD64F38024, HD64F38024R
Pin No.
FP-80A
TFP-80C
30
Pin Name
FP-80B
32
36
38
56
58
21
23
22
24
23
25
24
26
25
27
26
28
27
29
28
30
69
71
70
72
63
65
64
66
65
67
66
68
67
69
68
70
29
31
71
73
31
33
32
34
33
35
34
36
35
37
72
74
52
54
1
3
6
8
11
13
51
53
52
54
58
60
59
61
8
10
53
55
73
75
74
76
75
77
10, 9
12, 11
12
14
Other than the above
Socket Adapter
(Conversion to
32-Pin
Arrangement)
P71
P77
P92
P60
P61
P62
P63
P64
P65
P66
P67
P40
P41
P32
P33
P34
P35
P36
P37
P70
P42
P72
P73
P74
P75
P76
P43
Vcc
AVcc
X1
TEST
V1
Vcc
P94
P95
Vss
Vss
PB0
PB1
PB2
OSC1, OSC2
RES
(OPEN)
HN28F101 (32 Pins)
Pin Name
Pin No.
FWE
A9
A16
A15
WE
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
A0
A1
A2
A3
A4
A5
A6
A7
A8
OE
A10
A11
A12
A13
A14
CE
Vcc
Vss
1
26
2
3
31
13
14
15
17
18
19
20
21
12
11
10
9
8
7
6
5
27
24
23
25
4
28
29
22
32
16
[Legend]
FWE:
I/O7 to I/O0:
A16 to A0:
CE:
OE:
WE:
Oscillator circuit
Power-on
reset circuit
Flash-write enable
Data input/output
Address input
Chip enable
Output enable
Write enable
Note: The oscillation frequency
of the oscillator circuit
should be 10 MHz.
Figure 6.12(1) Socket Adapter Pin Correspondence Diagram
(HD64F38024, HD64F38024R)
Rev. 8.00 Mar. 09, 2010 Page 179 of 658
REJ09B0042-0800
Section 6 ROM
HD64F38124, HD64F38122
Pin No.
Socket Adapter
(Conversion to
32-Pin
Arrangement)
HN28F101 (32 Pins)
FP-80A
TFP-80C
Pin Name
30
P71
36
P77
A15
3
56
P92
WE
31
21
P60
I/O0
13
22
P61
I/O1
14
23
P62
I/O2
15
24
P63
I/O3
17
25
P64
I/O4
18
26
P65
I/O5
19
27
P66
I/O6
20
28
P67
I/O7
21
69
P40
A0
12
70
P41
A1
11
63
P32
A2
10
64
P33
A3
9
65
P34
A4
8
66
P35
A5
7
67
P36
A6
6
68
P37
A7
5
29
P70
A8
27
71
P42
OE
24
31
P72
A10
23
32
P73
A11
25
33
P74
A12
4
34
P75
A13
28
35
P76
A14
29
72
P43
CE
22
52
Vcc
Vcc
32
1
AVcc
Vss
16
6
X1
11
TEST
51
V1
52
Vcc
58
P94
4, 59
CVcc, P95
8
Vss
53
Vss
73
PB0
74
PB1
Pin Name
Pin No.
FWE
1
A9
26
A16
2
[Legend]
FWE:
I/O7 to I/O0:
A16 to A0:
CE:
OE:
WE:
Flash-write enable
Data input/output
Address input
Chip enable
Output enable
Write enable
Note: The oscillation frequency
of the oscillator circuit
should be 10 MHz.
75
PB2
10,9
OSC1,OSC2
Oscillator circuit
12
RES
Other than the above
(OPEN)
Power-on
reset circuit
Figure 6.12(2) Socket Adapter Pin Correspondence Diagram
(HD64F38124, HD64F38122)
Rev. 8.00 Mar. 09, 2010 Page 180 of 658
REJ09B0042-0800
Section 6 ROM
6.10.3
Memory Read Mode
1. After completion of auto-program/auto-erase/status read operations, a transition is made to the
command wait state. When reading memory contents, a transition to memory read mode must
first be made with a command write, after which the memory contents are read. Once memory
read mode has been entered, consecutive reads can be performed.
2. In memory read mode, command writes can be performed in the same way as in the command
wait state.
3. After powering on, memory read mode is entered.
4. Tables 6.14 to 6.16 show the AC characteristics.
Table 6.14 AC Characteristics in Transition to Memory Read Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Max
Unit
Notes
Command write cycle
tnxtc
20
—
µs
Figure 6.13
CE hold time
tceh
0
—
ns
CE setup time
tces
0
—
ns
Data hold time
tdh
50
—
ns
Data setup time
tds
50
—
ns
Write pulse width
twep
70
—
ns
WE rise time
tr
—
30
ns
WE fall time
tf
—
30
ns
Command write
Memory read mode
Address stable
A15−A0
tces
tceh
tnxtc
CE
OE
twep
tf
tr
WE
tds
tdh
I/O7−I/O0
Note: Data is latched on the rising edge of WE.
Figure 6.13 Timing Waveforms for Memory Read after Memory Write
Rev. 8.00 Mar. 09, 2010 Page 181 of 658
REJ09B0042-0800
Section 6 ROM
Table 6.15 AC Characteristics in Transition from Memory Read Mode to Another Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Max
Unit
Notes
Command write cycle
tnxtc
20
—
µs
Figure 6.14
CE hold time
tceh
0
—
ns
CE setup time
tces
0
—
ns
Data hold time
tdh
50
—
ns
Data setup time
tds
50
—
ns
Write pulse width
twep
70
—
ns
WE rise time
tr
—
30
ns
WE fall time
tf
—
30
ns
Memory read mode
A15−A0
Other mode command write
Address stable
tnxtc
tces
tceh
CE
OE
twep
tf
tr
WE
tds
tdh
I/O7−I/O0
Note: Do not enable WE and OE at the same time.
Figure 6.14 Timing Waveforms in Transition from Memory Read Mode to Another Mode
Rev. 8.00 Mar. 09, 2010 Page 182 of 658
REJ09B0042-0800
Section 6 ROM
Table 6.16 AC Characteristics in Memory Read Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Max
Unit
Notes
Access time
tacc
—
20
µs
Figure 6.15
CE output delay time
tce
—
150
ns
Figure 6.16
OE output delay time
toe
—
150
ns
Output disable delay time
tdf
—
100
ns
Data output hold time
toh
5
—
ns
A15−A0
Address stable
Address stable
CE
OE
WE
tacc
tacc
toh
toh
I/O7−I/O0
Figure 6.15 CE and OE Enable State Read Timing Waveforms
A15−A0
Address stable
Address stable
tce
tce
CE
toe
toe
OE
WE
tacc
tacc
toh
tdf
toh
tdf
I/O7−I/O0
Figure 6.16 CE and OE Clock System Read Timing Waveforms
Rev. 8.00 Mar. 09, 2010 Page 183 of 658
REJ09B0042-0800
Section 6 ROM
6.10.4
Auto-Program Mode
1. When reprogramming previously programmed addresses, perform auto-erasing before autoprogramming.
2. Perform auto-programming once only on the same address block. It is not possible to program
an address block that has already been programmed.
3. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out
by executing 128 consecutive byte transfers. A 128-byte data transfer is necessary even when
programming fewer than 128 bytes. In this case, H'FF data must be written to the extra
addresses.
4. The lower 7 bits of the transfer address must be low. If a value other than an effective address
is input, processing will switch to a memory write operation but a write error will be flagged.
5. Memory address transfer is performed in the second cycle (figure 6.17). Do not perform
transfer after the third cycle.
6. Do not perform a command write during a programming operation.
7. Perform one auto-program operation for a 128-byte block for each address. Two or more
additional programming operations cannot be performed on a previously programmed address
block.
8. Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode
can also be used for this purpose (I/O7 status polling uses the auto-program operation end
decision pin).
9. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long
as the next command write has not been performed, reading is possible by enabling CE and
OE.
10. Table 6.17 shows the AC characteristics.
Rev. 8.00 Mar. 09, 2010 Page 184 of 658
REJ09B0042-0800
Section 6 ROM
Table 6.17 AC Characteristics in Auto-Program Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Max
Unit
Notes
Command write cycle
tnxtc
20
—
µs
Figure 6.17
CE hold time
tceh
0
—
ns
CE setup time
tces
0
—
ns
Data hold time
tdh
50
—
ns
Data setup time
tds
50
—
ns
Write pulse width
twep
70
—
ns
Status polling start time
twsts
1
—
ms
Status polling access time
tspa
—
150
ns
Address setup time
tas
0
—
ns
Address hold time
tah
60
—
ns
Memory write time
twrite
1
3000
ms
WE rise time
tr
—
30
ns
WE fall time
tf
—
30
ns
Address
stable
A15−A0
tces
tceh
tnxtc
tnxtc
CE
OE
tf
twep
tr
tas
tah
twsts
tspa
WE
tds
tdh
I/O7
twrite
Write operation end decision signal
I/O6
I/O5−I/O0
Data transfer
1 to 128 bytes
Write normal end decision signal
H'40
H'00
Figure 6.17 Auto-Program Mode Timing Waveforms
Rev. 8.00 Mar. 09, 2010 Page 185 of 658
REJ09B0042-0800
Section 6 ROM
6.10.5
Auto-Erase Mode
1. Auto-erase mode supports only entire memory erasing.
2. Do not perform a command write during auto-erasing.
3. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also
be used for this purpose (I/O7 status polling uses the auto-erase operation end decision pin).
4. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long
as the next command write has not been performed, reading is possible by enabling CE and
OE.
5. Table 6.18 shows the AC characteristics.
Table 6.18 AC Characteristics in Auto-Erase Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Max
Unit
Notes
Command write cycle
tnxtc
20
—
µs
Figure 6.18
CE hold time
tceh
0
—
ns
CE setup time
tces
0
—
ns
Data hold time
tdh
50
—
ns
Data setup time
tds
50
—
ns
Write pulse width
twep
70
—
ns
Status polling start time
tests
1
—
ms
Status polling access time
tspa
—
150
ns
Memory erase time
terase
100
40000
ms
WE rise time
tr
—
30
ns
WE fall time
tf
—
30
ns
Rev. 8.00 Mar. 09, 2010 Page 186 of 658
REJ09B0042-0800
Section 6 ROM
A15−A0
tces
tceh
tnxtc
tnxtc
CE
OE
tf
twep
tr
tests
tspa
WE
tds
terase
tdh
I/O7
Erase end
decision signal
I/O6
Erase normal
end
decision signal
I/O5−I/O0
H'20
H'20
H'00
Figure 6.18 Auto-Erase Mode Timing Waveforms
6.10.6
Status Read Mode
1. Status read mode is provided to identify the kind of abnormal end. Use this mode when an
abnormal end occurs in auto-program mode or auto-erase mode.
2. The return code is retained until a command write other than a status read mode command
write is executed.
3. Table 6.19 shows the AC characteristics and 6.20 shows the return codes.
Rev. 8.00 Mar. 09, 2010 Page 187 of 658
REJ09B0042-0800
Section 6 ROM
Table 6.19 AC Characteristics in Status Read Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Max
Unit
Notes
Read time after command write
tnxtc
20
—
µs
Figure 6.19
CE hold time
tceh
0
—
ns
CE setup time
tces
0
—
ns
Data hold time
tdh
50
—
ns
Data setup time
tds
50
—
ns
Write pulse width
twep
70
—
ns
OE output delay time
toe
—
150
ns
Disable delay time
tdf
—
100
ns
CE output delay time
tce
—
150
ns
WE rise time
tr
—
30
ns
WE fall time
tf
—
30
ns
A15−A0
tces
tceh
tnxtc tces
tceh
tnxtc
tnxtc
CE
tce
OE
twep
tf
tr
twep
tf
tr
toe
WE
tds
I/O7−I/O0
tdh
H'71
tds
tdh
H'71
Note: I/O2 and I/O3 are undefined.
Figure 6.19 Status Read Mode Timing Waveforms
Rev. 8.00 Mar. 09, 2010 Page 188 of 658
REJ09B0042-0800
tdf
Section 6 ROM
Table 6.20 Status Read Mode Return Codes
Pin Name
Initial Value
Indications
I/O7
0
1: Abnormal end
0: Normal end
I/O6
0
1: Command error
I/O5
0
1: Programming error
0: Otherwise
0: Otherwise
I/O4
0
1: Erasing error
0: Otherwise
I/O3
0
⎯
I/O2
0
⎯
I/O1
0
1: Over counting of writing or erasing
0: Otherwise
I/O0
0
1: Effective address error
0: Otherwise
6.10.7
Status Polling
1. The I/O7 status polling flag indicates the operating status in auto-program/auto-erase mode.
2. The I/O6 status polling flag indicates a normal or abnormal end in auto-program/auto-erase
mode.
Table 6.21 Status Polling Output Truth Table
I/O7
I/O6
I/O0 to 5
Status
0
0
0
During internal operation
1
0
0
Abnormal end
1
1
0
Normal end
0
1
0
—
Rev. 8.00 Mar. 09, 2010 Page 189 of 658
REJ09B0042-0800
Section 6 ROM
6.10.8
Programmer Mode Transition Time
Commands cannot be accepted during the oscillation stabilization period or the programmer mode
setup period. After the programmer mode setup time, a transition is made to memory read mode.
Table 6.22 Stipulated Transition Times to Command Wait State
Item
Symbol
Min
Oscillation stabilization time(crystal oscillator)
Tosc1
10
Oscillation stabilization time(ceramic oscillator)
Tosc1
5
Programmer mode setup time
Tbmv
10
—
ms
Vcc hold time
Tdwn
0
—
ms
tosc1
tbmv
Auto-program mode
Auto-erase mode
Max
Unit
Notes
—
ms
Figure 6.20
—
ms
tdwn
Vcc
RES
Figure 6.20 Oscillation Stabilization Time, Boot Program Transfer Time,
and Power-Down Sequence
6.10.9
Notes on Memory Programming
1. When performing programming using programmer mode on a chip that has been
programmed/erased in an on-board programming mode, auto-erasing is recommended before
carrying out auto-programming.
2. The flash memory is initially in the erased state when the device is shipped by Renesas
Technology. For other chips for which the erasure history is unknown, it is recommended that
auto-erasing be executed to check and supplement the initialization (erase) level.
Rev. 8.00 Mar. 09, 2010 Page 190 of 658
REJ09B0042-0800
Section 6 ROM
6.11
Power-Down States for Flash Memory
In user mode, the flash memory will operate in either of the following states:
• Normal operating mode
The flash memory can be read and written to at high speed.
• Power-down operating mode
The power supply circuit of the flash memory is partly halted and can be read under low power
consumption.
• Standby mode
All flash memory circuits are halted.
Table 6.23 shows the correspondence between the operating modes of this LSI and the flash
memory. In subactive mode, the flash memory can be set to operate in power-down mode with the
PDWND bit in FLPWCR. When the flash memory returns to its normal operating state from
power-down mode or standby mode, a period to stabilize the power supply circuits that were
stopped is needed. When the flash memory returns to its normal operating state, bits STS2 to
STS0 in SYSCR1 must be set to provide a wait time of at least 20 µs, even when the external
clock is being used.
Table 6.23 Flash Memory Operating States
Flash Memory Operating State
LSI Operating State
PDWND = 0 (Initial value)
PDWND = 1
Active mode
Normal operating mode
Normal operating mode
Subactive mode
Power-down mode
Normal operating mode
Sleep mode
Normal operating mode
Normal operating mode
Subsleep mode
Standby mode
Standby mode
Standby mode
Standby mode
Standby mode
Watch mode
Standby mode
Standby mode
Rev. 8.00 Mar. 09, 2010 Page 191 of 658
REJ09B0042-0800
Section 6 ROM
Rev. 8.00 Mar. 09, 2010 Page 192 of 658
REJ09B0042-0800
Section 7 RAM
Section 7 RAM
7.1
Overview
The H8/38024, H8/38023, H8/38022, H8/38124, H8/38123, H8/38122, H8/38024S, H8/38023S,
and H8/38022S have 1 Kbyte of high-speed static RAM on-chip, and the H8/38021, H8/38020,
H8/38121, H8/38120, H8/38021S, and H8/38020S have 512 bytes. The RAM is connected to the
CPU by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data.
7.1.1
Block Diagram
Figure 7.1 shows a block diagram of the on-chip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'FB80
H'FB80
H'FB81
H'FB82
H'FB82
H'FB83
On-chip RAM
H'FF7E
H'FF7E
H'FF7F
Even-numbered
address
Odd-numbered
address
Figure 7.1 RAM Block Diagram (H8/38024)
Rev. 8.00 Mar. 09, 2010 Page 193 of 658
REJ09B0042-0800
Section 7 RAM
Rev. 8.00 Mar. 09, 2010 Page 194 of 658
REJ09B0042-0800
Section 8 I/O Ports
Section 8 I/O Ports
8.1
Overview
The LSI is provided with five 8-bit I/O ports, two 4-bit I/O ports, one 3-bit I/O port, one 8-bit
input-only port, one 1-bit input-only port, and one 6-bit output-only port. Table 8.1 indicates the
functions of each port.
Each port has of a port control register (PCR) that controls input and output, and a port data
register (PDR) for storing output data. Input or output can be assigned to individual bits.
See section 2.9.2, Notes on Bit Manipulation, for information on executing bit-manipulation
instructions to write data in PCR or PDR.
Ports 5, 6, 7, 8, and A are also used as liquid crystal display segment and common pins, selectable
in 4-bit units.
Block diagrams of each port are given in Appendix C, I/O Port Block Diagrams.
Table 8.1
Port Functions
Port
Description
Pins
Other Functions
Function
Switching
Registers
Port 1
•
4-bit I/O port
P17/IRQ3/TMIF
•
MOS input pull-up
option
External interrupt 3, timer
event input pin TMIF
PMR1
TCRF
P16*
None
P14/IRQ4/ADTRG
External interrupt 4, A/D
converter external trigger
PMR1
AMR
P13/TMIG
Timer G input capture
PMR1
PMR2
P37/AEVL
P36/AEVH
Asynchronous counter event
input pins AEVL, AEVH
PMR3
ECCR
P35 to P33
None
PMR2
Timer F output compare
output
PMR3
Timer C count up/down
selection input
PMR3
Port 3
•
8-bit I/O port
•
MOS input pull-up
option
1
•
Large-current
2
port*
P32, TMOFH
P31, TMOFL
•
MOS open drain
output selectable
(only P35)
P30/UD
Rev. 8.00 Mar. 09, 2010 Page 195 of 658
REJ09B0042-0800
Section 8 I/O Ports
Other Functions
Function
Switching
Registers
P43/IRQ0
External interrupt 0
PMR2
P42/TXD32
P41/RXD32
P40/SCK32
SCI3 data output (TXD32),
data input (RXD32), clock
input/output (SCK32)
SCR3
SMR3
SPCR
P57 to P50/
WKP7 to WKP0/
SEG8 to SEG1
Wakeup input (WKP7 to
WKP0), segment output
(SEG8 to SEG1)
PMR5
LPCR
P67 to P60/
SEG16 to SEG9
Segment output (SEG16 to
SEG9)
LPCR
8-bit I/O port
P77 to P70/
SEG24 to SEG17
Segment output (SEG24 to
SEG17)
LPCR
•
8-bit I/O port
P87 to P80/
SEG32 to SEG25
Segment output (SEG32 to
SEG25)
LPCR
•
Dedicated 6-bit
output port
P95 to P92
(P95, P94, P92,
4
P93/Vref)*
None
(LVD reference voltage
4
external input pin)*
(LVDSR)*
10-bit PWM output
PMR9
Port
Description
Pins
Port 4
•
1-bit input port
•
3-bit I/O port
•
8-bit I/O port
•
MOS input pull-up
option
•
8-bit I/O port
•
MOS input pull-up
option
Port 7
•
Port 8
Port 9
Port 5
Port 6
•
High-voltage, large3
P91, P90/
current port*
PWM2, PWM1
4
•
High-voltage port*
IRQAEC
None
Port A
•
4-bit I/O port
PA3 to PA0/
COM4 to COM1
Common output
(COM4 to COM1)
LPCR
Port B
•
Dedicated 8-bit
input port
PB7 to PB4/
AN7 to AN4
A/D converter analog input
(AN7 to AN4)
AMR
PB3/AN3/IRQ1
A/D converter analog input
(AN3), external interrupt 1,
timer event input (TMIC)
AMR
PMRB
TMC
PB2/AN2
A/D converter analog input
AMR
4
PB1/AN1/(extU)*
4
*
PB0/AN0/(extD)
A/D converter analog input
(LVD detect voltage external
4
input pin)*
AMR
4
(LVDCR)*
3
Notes: 1. Pin 16 and the associated function are not implemented on the H8/38124 Group.
2. Applies to the HD64338024, HD64338023, HD64338022, HD64338021, HD64338020,
and H8/38124 Group only.
3. Standard voltage on H8/38024S Group and H8/38124 Group.
4. Applies to H8/38124 Group only.
Rev. 8.00 Mar. 09, 2010 Page 196 of 658
REJ09B0042-0800
Section 8 I/O Ports
8.2
Port 1
8.2.1
Overview
Port 1 is a 4-bit I/O port. Figure 8.1 shows its pin configuration.
P17/IRQ3/TMIF
P16*
Port 1
P14/IRQ4/ADTRG
P13/TMIG
Note: * Pin 16 and the associated function are not implemented on the H8/38124 Group.
Figure 8.1 Port 1 Pin Configuration
8.2.2
Register Configuration and Description
Table 8.2 shows the port 1 register configuration.
Table 8.2
Port 1 Registers
Name
Abbr.
R/W
Initial Value
Address
Port data register 1
PDR1
R/W
—
H'FFD4
Port control register 1
PCR1
W
—
H'FFE4
Port pull-up control register 1
PUCR1
R/W
—
H'FFE0
Port mode register 1
PMR1
R/W
—
H'FFC8
Port mode register 2
PMR2
R/W
H'D8
H'FFC9
Rev. 8.00 Mar. 09, 2010 Page 197 of 658
REJ09B0042-0800
Section 8 I/O Ports
Port Data Register 1 (PDR1)
Bit
7
6
5
4
3
2
1
0
P17
P16*
—
P14
P13
—
—
—
Initial value
0
0
—
0
0
—
—
—
Read/Write
R/W
R/W
—
R/W
R/W
—
—
—
PDR1 is an 8-bit register that stores data for port 1 pins P17, P16*, P14, and P13. If port 1 is read
while PCR1 bits are set to 1, the values stored in PDR1 are read, regardless of the actual pin states.
If port 1 is read while PCR1 bits are cleared to 0, the pin states are read.
Note: * Pin 16 and the associated function are not implemented on the H8/38124 Group.
The register is both readable and writeable.
Port Control Register 1 (PCR1)
Bit
7
6
5
4
3
2
1
0
PCR17
PCR16*
—
PCR14
PCR13
—
—
—
Initial value
0
0
—
0
0
—
—
—
Read/Write
W
W
W
W
W
W
W
W
PCR1 is an 8-bit register for controlling whether each of the port 1 pins P17, P16*, P14, and P13
functions as an input pin or output pin. Setting a PCR1 bit to 1 makes the corresponding pin an
output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR1 and in
PDR1 are valid only when the corresponding pin is designated in PMR1 as a general I/O pin.
PCR1 is a write-only register, which is always read as all 1s.
Note: * Pin 16 and the associated function are not implemented on the H8/38124 Group.
Rev. 8.00 Mar. 09, 2010 Page 198 of 658
REJ09B0042-0800
Section 8 I/O Ports
Port Pull-Up Control Register 1 (PUCR1)
Bit
7
6
PUCR17 PUCR16*
5
—
4
3
PUCR14 PUCR13
2
1
0
—
—
—
Initial value
0
0
—
0
0
—
—
—
Read/Write
R/W
R/W
W
R/W
R/W
W
W
W
PUCR1 controls whether the MOS pull-up of each of the port 1 pins P17, P16*, P14, and P13 is on
or off. When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the
MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Note: * Pin 16 and the associated function are not implemented on the H8/38124 Group.
The register is both readable and writeable.
Port Mode Register 1 (PMR1)
Bit
7
6
5
4
3
2
1
0
IRQ3
—
—
IRQ4
TMIG
—
—
—
Initial value
0
1
—
0
0
—
1
—
Read/Write
R/W
—
W
R/W
R/W
W
—
W
PMR1 is an 8-bit read/write register, controlling the selection of pin functions for port 1 pins.
Bit 7—P17/IRQ3/TMIF Pin Function Switch (IRQ3)
This bit selects whether pin P17/IRQ3/TMIF is used as P17 or as IRQ3/TMIF.
Bit 7
IRQ3
Description
0
Functions as P17 I/O pin
1
Functions as IRQ3/TMIF input pin
(initial value)
Note: Rising or falling edge sensing can be designated for IRQ3, TMIF. For details on TMIF
settings, see 3. Timer Control Register F (TCRF) in section 9.4.2, Register Descriptions.
Bit 6—Reserved
This bit is reserved; it is always read as 1 and cannot be modified.
Bit 5—Reserved
This bit is reserved; it can only be written with 0.
Rev. 8.00 Mar. 09, 2010 Page 199 of 658
REJ09B0042-0800
Section 8 I/O Ports
Bit 4—P14/IRQ4/ADTRG Pin Function Switch (IRQ4)
This bit selects whether pin P14/IRQ4/ADTRG is used as P14 or as IRQ4/ADTRG.
Bit 4
IRQ4
Description
0
Functions as P14 I/O pin
1
Functions as IRQ4/ADTRG input pin
(initial value)
Note: For details of ADTRG pin setting, see section 12.3.2, Start of A/D Conversion by External
Trigger Input.
Bit 3—P13/TMIG Pin Function Switch (TMIG)
This bit selects whether pin P13/TMIG is used as P13 or as TMIG.
Bit 3
TMIG
Description
0
Functions as P13 I/O pin
1
Functions as TMIG input pin
(initial value)
Bits 2 and 0—Reserved
These bits are reserved; they can only be written with 0.
Bit 1—Reserved
This bit is reserved; it is always read as 1 and cannot be modified.
Port Mode Register 2 (PMR2)
Bit
7
6
5
4
3
2
1
0
—
—
POF1
—
—
WDCKS
NCS
IRQ0
Initial value
1
1
0
1
1
0
0
0
Read/Write
—
—
R/W
—
—
R/W
R/W
R/W
PMR2 is an 8-bit read/write register. It controls whether the PMOS transistor internal to P35 is on
or off, the selection of the watchdog timer clock, the selection of TMIG noise cancellation, and
switching of the P43/IRQ0 pin functions.
Upon reset, PMR2 is initialized to H'D8.
Rev. 8.00 Mar. 09, 2010 Page 200 of 658
REJ09B0042-0800
Section 8 I/O Ports
This section only deals with the bits related to timer G and the watchdog timer. For the functions
of the bits, see the descriptions of port 3 (POF1) and port 4 (IRQ0).
Bit 2—Watchdog Timer Source Clock (WDCKS)
This bit selects the watchdog timer source clock. Note that stabilization times for the H8/38024,
H8/38024S, and H8/38024R Group and for the H8/38124 Group are different.
• H8/38024, H8/38024S, H8/38024R Group
Bit 2
WDCKS
Description
0
Selects φ/8192
1
Selects φW /32
(initial value)
• H8/38124 Group
Bit 2
WDCKS
Description
0
Selects clock based on timer mode register W (TMW) setting*
1
Selects φW /32
(initial value)
Note: * See section 9.6, Watchdog Timer, for details.
Bit 1—TMIG Noise Canceller Select (NCS)
This bit selects controls the noise cancellation circuit of the input capture input signal (TMIG).
Bit 1
NCS
Description
0
No noise cancellation circuit
1
Noise cancellation circuit
(initial value)
Rev. 8.00 Mar. 09, 2010 Page 201 of 658
REJ09B0042-0800
Section 8 I/O Ports
8.2.3
Pin Functions
Table 8.3 shows the port 1 pin functions.
Table 8.3
Port 1 Pin Functions
Pin
Pin Functions and Selection Method
P17/IRQ3/TMIF
The pin function depends on bit IRQ3 in PMR1, bits CKSL2 to CKSL0 in TCRF,
and bit PCR17 in PCR1.
IRQ3
0
PCR17
0
CKSL2 to CKSL0
Pin function
1
1
*
Not 0**
*
0**
P17 input pin P17 output pin IRQ3 input pin
IRQ3/TMIF
input pin
Note: When this pin is used as the TMIF input pin, clear bit IEN3 to 0 in IENR1
to disable the IRQ3 interrupt.
P16
The pin function depends on bit PCR16 in PCR1.
PCR16
0
1
Pin function
P16 input pin
P16 output pin
Note: Pin 16 and the associated function are not implemented on the H8/38124
Group.
P14/IRQ4
ADTRG
The pin function depends on bit IRQ4 in PMR1, bit TRGE in AMR, and bit PCR14
in PCR1.
IRQ4
0
PCR14
0
TRGE
Pin function
1
1
*
0
*
1
P14 input pin P14 output pin IRQ4 input pin IRQ4/ADTRG
input pin
Note: When this pin is used as the ADTRG input pin, clear bit IEN4 to 0 in
IENR1 to disable the IRQ4 interrupt.
P13/TMIG
The pin function depends on bit TMIG in PMR1 and bit PCR13 in PCR1.
TMIG
0
PCR13
Pin function
0
1
1
P13 input pin P13 output pin
*
TMIG input pin
*: Don’t care
Rev. 8.00 Mar. 09, 2010 Page 202 of 658
REJ09B0042-0800
Section 8 I/O Ports
8.2.4
Pin States
Table 8.4 shows the port 1 pin states in each operating mode.
Table 8.4
Port 1 Pin States
Pins
Reset
Sleep
Subsleep Standby
P17/IRQ3/TMIF
HighRetains Retains
1
P16*
impedance previous previous
state
P14/IRQ4/ADTRG
state
P13/TMIG
Watch
Subactive Active
HighRetains Functional Functional
2
impedance* previous
state
Notes: 1. Pin 16 and the associated function are not implemented on the H8/38124 Group.
2. A high-level signal is output when the MOS pull-up is in the on state.
8.2.5
MOS Input Pull-Up
Port 1 has a built-in MOS input pull-up function that can be controlled by software. When a
PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS input pull-up
for that pin. The MOS input pull-up function is in the off state after a reset.
PCR1n
0
0
1
PUCR1n
0
1
*
MOS input pull-up
Off
On
Off
(n = 7, 6, 4, 3)
*: Don’t care
Rev. 8.00 Mar. 09, 2010 Page 203 of 658
REJ09B0042-0800
Section 8 I/O Ports
8.3
Port 3
8.3.1
Overview
Port 3 is an 8-bit I/O port, configured as shown in figure 8.2.
P3 7 /AEVL
P3 6 /AEVH
P3 5
P3 4
Port 3
P3 3
P3 2 /TMOFH
P3 1 /TMOFL
P3 0 /UD
Figure 8.2 Port 3 Pin Configuration
8.3.2
Register Configuration and Description
Table 8.5 shows the port 3 register configuration.
Table 8.5
Port 3 Registers
Name
Abbr.
R/W
Initial Value
Address
Port data register 3
PDR3
R/W
H'00
H'FFD6
Port control register 3
PCR3
W
H'00
H'FFE6
Port pull-up control register 3
PUCR3
R/W
H'00
H'FFE1
Port mode register 2
PMR2
R/W
H'D8
H'FFC9
Port mode register 3
PMR3
R/W
—
H'FFCA
Rev. 8.00 Mar. 09, 2010 Page 204 of 658
REJ09B0042-0800
Section 8 I/O Ports
Port Data Register 3 (PDR3)
Bit
7
6
5
4
3
2
1
0
P3 7
P36
P35
P34
P3 3
P32
P31
P30
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR3 is an 8-bit register that stores data for port 3 pins P37 to P30. If port 3 is read while PCR3
bits are set to 1, the values stored in PDR3 are read, regardless of the actual pin states. If port 3 is
read while PCR3 bits are cleared to 0, the pin states are read.
Upon reset, PDR3 is initialized to H'00.
Port Control Register 3 (PCR3)
Bit
7
6
5
4
3
2
1
0
PCR3 7
PCR3 6
PCR3 5
PCR34
PCR3 3
PCR3 2
PCR31
PCR30
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PCR3 is an 8-bit register for controlling whether each of the port 3 pins P37 to P30 functions as an
input pin or output pin. Setting a PCR3 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. The settings in PCR3 and in PDR3 are valid only
when the corresponding pin is designated in PMR3 as a general I/O pin.
Upon reset, PCR3 is initialized to H'00.
PCR3 is a write-only register, which is always read as all 1s.
Rev. 8.00 Mar. 09, 2010 Page 205 of 658
REJ09B0042-0800
Section 8 I/O Ports
Port Pull-Up Control Register 3 (PUCR3)
Bit
7
6
5
4
3
2
1
0
PUCR37 PUCR36 PUCR3 5 PUCR34 PUCR3 3 PUCR3 2 PUCR31 PUCR30
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PUCR3 controls whether the MOS pull-up of each of the port 3 pins P37 to P30 is on or off. When
a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for
the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Upon reset, PUCR3 is initialized to H'00.
Port Mode Register 2 (PMR2)
Bit
7
6
5
4
3
2
1
0
—
—
POF1
—
—
WDCKS
NCS
IRQ0
Initial value
1
1
0
1
1
0
0
0
Read/Write
—
—
R/W
—
—
R/W
R/W
R/W
PMR2 is an 8-bit read/write register. It controls whether the PMOS transistor internal to P35 is on
or off, the selection of the watchdog timer clock, the selection of TMIG noise cancellation, and
switching of the P43/IRQ0 pin functions.
Upon reset, PMR2 is initialized to H'D8.
This section only deals with the bit that controls whether the PMOS transistor internal to pin P35 is
on or off. For the functions of the other bits, see the descriptions of port 1 (WDCKS and NCS) and
port 4 (IRQ0).
Bit 5—Pin P35 PMOS Transistor Control (POF1)
This bit selects whether the PMOS transistor of the output buffer for pin P35 is on or off.
Bit 5
POF1
Description
0
CMOS output
1
NMOS open-drain output
(initial value)
Note: The pin is an NMOS open-drain output when this bit is set to 1 and P35 is an output.
Rev. 8.00 Mar. 09, 2010 Page 206 of 658
REJ09B0042-0800
Section 8 I/O Ports
Port Mode Register 3 (PMR3)
Bit
7
6
5
4
3
2
1
0
AEVL
AEVH
⎯
⎯
⎯
TMOFH
TMOFL
UD
Initial value
0
0
⎯
⎯
⎯
0
0
0
Read/Write
R/W
R/W
W
W
W
R/W
R/W
R/W
PMR3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins.
Bit 7—P37/AEVL Pin Function Switch (AEVL)
This bit selects whether pin P37/AEVL is used as P37 or as AEVL.
Bit 7
AEVL
Description
0
Functions as P37 I/O pin
1
Functions as AEVL input pin
(initial value)
Bit 6—P36/AEVH Pin Function Switch (AEVH)
This bit selects whether pin P36/AEVH is used as P36 or as AEVH.
Bit 6
AEVH
Description
0
Functions as P36 I/O pin
1
Functions as AEVH input pin
(initial value)
Bits 5 to 3—Reserved
These bits are reserved; they can only be written with 0.
Bit 2—P32/TMOFH Pin Function Switch (TMOFH)
This bit selects whether pin P32/TMOFH is used as P32 or as TMOFH.
Bit 2
TMOFH
Description
0
Functions as P32 I/O pin
1
Functions as TMOFH output pin
(initial value)
Rev. 8.00 Mar. 09, 2010 Page 207 of 658
REJ09B0042-0800
Section 8 I/O Ports
Bit 1—P31/TMOFL Pin Function Switch (TMOFL)
This bit selects whether pin P31/TMOFL is used as P31 or as TMOFL.
Bit 1
TMOFL
Description
0
Functions as P31 I/O pin
1
Functions as TMOFL output pin
(initial value)
Bit 0—P30/UD Pin Function Switch (UD)
This bit selects whether pin P30/UD is used as P30 or as UD.
Bit 0
UD
Description
0
Functions as P30 I/O pin
1
Functions as UD input pin
Rev. 8.00 Mar. 09, 2010 Page 208 of 658
REJ09B0042-0800
(initial value)
Section 8 I/O Ports
8.3.3
Pin Functions
Table 8.6 shows the port 3 pin functions.
Table 8.6
Port 3 Pin Functions
Pin
Pin Functions and Selection Method
P37/AEVL
The pin function depends on bit AEVL in PMR3 and bit PCR37 in PCR3.
AEVL
P36/AEVH
0
PCR37
0
1
*
Pin function
P37 input pin
P37 output pin
AEVL input pin
The pin function depends on bit AEVH in PMR3 and bit PCR36 in PCR3.
AEVH
P35 to P33
1
0
1
PCR36
0
1
*
Pin function
P36 input pin
P36 output pin
AEVH input pin
The pin function depends on the corresponding bit in PCR3.
PCR3n
0
1
Pin function
P3n input pin
P3n output pin
(n = 5 to 3)
P32/TMOFH
The pin function depends on bit TMOFH in PMR3 and bit PCR32 in PCR3.
TMOFH
P31/TMOFL
0
PCR32
0
1
*
Pin function
P32 input pin
P32 output pin
TMOFH output pin
The pin function depends on bit TMOFL in PMR3 and bit PCR31 in PCR3.
TMOFL
P30/UD
1
0
1
PCR31
0
1
*
Pin function
P31 input pin
P31 output pin
THOFL output pin
The pin function depends on bit UD in PMR3 and bit PCR30 in PCR3.
UD
0
1
PCR30
0
1
*
Pin function
P30 input pin
P30 output pin
UD input pin
*: Don’t care
Rev. 8.00 Mar. 09, 2010 Page 209 of 658
REJ09B0042-0800
Section 8 I/O Ports
8.3.4
Pin States
Table 8.7 shows the port 3 pin states in each operating mode.
Table 8.7
Port 3 Pin States
Pins
Reset
Sleep
Subsleep Standby
P37/AEVL
P36/AEVH
P35
P34
P33
P32/TMOFH
P31/TMOFL
P30/UD
Highimpedance
Retains Retains
previous previous
state
state
Watch
Subactive Active
Retains Functional Functional
Highimpedance* previous
state
Note: * A high-level signal is output when the MOS pull-up is in the on state.
8.3.5
MOS Input Pull-Up
Port 3 has a built-in MOS input pull-up function that can be controlled by software. When a
PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for
that pin. The MOS pull-up function is in the off state after a reset.
PCR3n
0
0
1
PUCR3n
0
1
*
MOS input pull-up
Off
On
Off
(n = 7 to 0)
*: Don’t care
Rev. 8.00 Mar. 09, 2010 Page 210 of 658
REJ09B0042-0800
Section 8 I/O Ports
8.4
Port 4
8.4.1
Overview
Port 4 is a 3-bit I/O port and 1-bit input port, configured as shown in figure 8.3.
P4 3 /IRQ0
P4 2 /TXD32
Port 4
P4 1 /RXD32
P4 0 /SCK32
Figure 8.3 Port 4 Pin Configuration
8.4.2
Register Configuration and Description
Table 8.8 shows the port 4 register configuration.
Table 8.8
Port 4 Registers
Name
Abbr.
R/W
Initial Value
Address
Port data register 4
PDR4
R/W
H'F8
H'FFD7
Port control register 4
PCR4
W
H'F8
H'FFE7
Port mode register 2
PMR2
R/W
H'D8
H'FFC9
Port Data Register 4 (PDR4)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
P43
P4 2
P4 1
P4
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
R
R/W
R/W
R/W
0
PDR4 is an 8-bit register that stores data for port 4 pins P42 to P40. If port 4 is read while PCR4
bits are set to 1, the values stored in PDR4 are read, regardless of the actual pin states. If port 4 is
read while PCR4 bits are cleared to 0, the pin states are read.
Upon reset, PDR4 is initialized to H'F8.
Rev. 8.00 Mar. 09, 2010 Page 211 of 658
REJ09B0042-0800
Section 8 I/O Ports
Port Control Register 4 (PCR4)
Bit
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
PCR42
PCR4 1
PCR4 0
Initial value
1
1
1
1
1
0
0
0
Read/Write
⎯
⎯
⎯
⎯
⎯
W
W
W
PCR4 is an 8-bit register for controlling whether each of port 4 pins P42 to P40 functions as an
input pin or output pin. Setting a PCR4 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. PCR4 and PDR4 settings are valid when the
corresponding pins are designated for general-purpose input/output by SCR3.
Upon reset, PCR4 is initialized to H'F8.
PCR4 is a write-only register, which is always read as all 1s.
Port Mode Register 2 (PMR2)
Bit
7
6
5
4
3
2
1
0
⎯
⎯
POF1
⎯
⎯
WDCKS
NCS
IRQ0
Initial value
1
1
0
1
1
0
0
0
Read/Write
⎯
⎯
R/W
⎯
⎯
R/W
R/W
R/W
PMR2 is an 8-bit read/write register. It controls whether the PMOS transistor internal to P35 is on
or off, the selection of the watchdog timer clock, the selection of TMIG noise cancellation, and
switching of the P43/IRQ0 pin functions.
Upon reset, PMR2 is initialized to H'D8.
This section only deals with the bit that controls switching of the P43/IRQ0 pin functions. For the
functions of the other bits, see the descriptions of port 1 (WDCKS and NCS) and port 3 (POF1).
Bit 0—P43/IRQ0 Pin Function Switch (IRQ0)
This bit selects whether pin P43/IRQ0 is used as P43 or as IRQ0.
Bit 0
IRQ0
Description
0
Functions as P43 input pin
1
Functions as IRQ0 input pin
Rev. 8.00 Mar. 09, 2010 Page 212 of 658
REJ09B0042-0800
(initial value)
Section 8 I/O Ports
8.4.3
Pin Functions
Table 8.9 shows the port 4 pin functions.
Table 8.9
Port 4 Pin Functions
Pin
Pin Functions and Selection Method
P43/IRQ0
The pin function depends on bit IRQ0 in PMR2.
P42/TXD32
P41/RXD32
IRQ0
0
1
Pin function
P43 input pin
IRQ0 input pin
The pin function depends on bit TE in SCR3, bit SPC32 in SPCR, and bit PCR42
in PCR4.
SPC32
0
1
TE
0
1
PCR42
0
1
*
Pin function
P42 input pin
P42 output pin
TXD32 output pin
The pin function depends on bit RE in SCR3 and bit PCR41 in PCR4.
RE
P40/SCK32
0
1
PCR41
0
1
*
Pin function
P41 input pin
P41 output pin
RXD32 input pin
The pin function depends on bit CKE1 and CKE0 in SCR3, bit COM in SMR3,
and bit PCR40 in PCR4.
CKE1
0
CKE0
COM
PCR40
Pin function
1
0
0
0
1
1
1
*
*
*
*
P40 input pin P40 output pin SCK32 output
pin
*
SCK32 input
pin
*: Don’t care
Rev. 8.00 Mar. 09, 2010 Page 213 of 658
REJ09B0042-0800
Section 8 I/O Ports
8.4.4
Pin States
Table 8.10 shows the port 4 pin states in each operating mode.
Table 8.10 Port 4 Pin States
Pins
Reset
Sleep
Subsleep Standby
P43/IRQ0
P42/TXD32
P41/RXD32
P40/SCK32
HighRetains Retains
impedance previous previous
state
state
Rev. 8.00 Mar. 09, 2010 Page 214 of 658
REJ09B0042-0800
Watch
Subactive Active
HighRetains Functional Functional
impedance previous
state
Section 8 I/O Ports
8.5
Port 5
8.5.1
Overview
Port 5 is an 8-bit I/O port, configured as shown in figure 8.4.
P57/WKP7/SEG8
P56/WKP6/SEG7
P55/WKP5/SEG6
P54/WKP4/SEG5
Port 5
P53/WKP3/SEG4
P52/WKP2/SEG3
P51/WKP1/SEG2
P50/WKP0/SEG1
Figure 8.4 Port 5 Pin Configuration
8.5.2
Register Configuration and Description
Table 8.11 shows the port 5 register configuration.
Table 8.11 Port 5 Registers
Name
Abbr.
R/W
Initial Value
Address
Port data register 5
PDR5
R/W
H'00
H'FFD8
Port control register 5
PCR5
W
H'00
H'FFE8
Port pull-up control register 5
PUCR5
R/W
H'00
H'FFE2
Port mode register 5
PMR5
R/W
H'00
H'FFCC
Rev. 8.00 Mar. 09, 2010 Page 215 of 658
REJ09B0042-0800
Section 8 I/O Ports
Port Data Register 5 (PDR5)
Bit
7
6
5
4
3
2
1
0
P57
P56
P55
P54
P53
P52
P51
P50
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR5 is an 8-bit register that stores data for port 5 pins P57 to P50. If port 5 is read while PCR5
bits are set to 1, the values stored in PDR5 are read, regardless of the actual pin states. If port 5 is
read while PCR5 bits are cleared to 0, the pin states are read.
Upon reset, PDR5 is initialized to H'00.
Port Control Register 5 (PCR5)
Bit
7
6
5
4
3
2
1
0
PCR57
PCR56
PCR55
PCR54
PCR53
PCR52
PCR51
PCR50
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PCR5 is an 8-bit register for controlling whether each of the port 5 pins P57 to P50 functions as an
input pin or output pin. Setting a PCR5 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. PCR5 and PDR5 settings are valid when the
corresponding pins are designated for general-purpose input/output by PMR5 and bits SGS3 to
SGS0 in LPCR.
Upon reset, PCR5 is initialized to H'00.
PCR5 is a write-only register, which is always read as all 1s.
Rev. 8.00 Mar. 09, 2010 Page 216 of 658
REJ09B0042-0800
Section 8 I/O Ports
Port Pull-Up Control Register 5 (PUCR5)
Bit
7
6
5
4
3
2
0
1
PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PUCR5 controls whether the MOS pull-up of each of port 5 pins P57 to P50 is on or off. When a
PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for
the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Upon reset, PUCR5 is initialized to H'00.
Port Mode Register 5 (PMR5)
Bit
7
6
5
4
3
2
1
0
WKP7
WKP6
WKP5
WKP4
WKP3
WKP2
WKP1
WKP0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PMR5 is an 8-bit read/write register, controlling the selection of pin functions for port 5 pins.
Upon reset, PMR5 is initialized to H'00.
Bit n—P5n/WKPn/SEGn+1 Pin Function Switch (WKPn)
When pin P5n/WKPn/SEGn+1 is not used as SEGn+1, these bits select whether the pin is used as
P5n or WKPn.
Bit n
WKPn
Description
0
Functions as P5n I/O pin
1
Functions as WKPn input pin
(initial value)
(n = 7 to 0)
Note: For use as SEGn+1, see section 13.2.1, LCD Port Control Register (LPCR).
Rev. 8.00 Mar. 09, 2010 Page 217 of 658
REJ09B0042-0800
Section 8 I/O Ports
8.5.3
Pin Functions
Table 8.12 shows the port 5 pin functions.
Table 8.12 Port 5 Pin Functions
Pin
Pin Functions and Selection Method
P57/WKP7/
SEG8 to
The pin function depends on bits WKP7 to WKP0 in PMR5, bits PCR57 to PCR50
in PCR5, and bits SGS3 to SGS0 in LPCR.
P50/WKP0/
SEG1
P57 to P54
SGS3 to SGS0
(n = 7 to 4)
Other than 0010, 0011, 0100, 0101, 0110,
0111, 1000, 1001
WKPn
0
PCR5n
Pin function
0
1
P5n input pin P5n output pin
1
*
*
*
WKPn input
pin
SEGn+1
output pin
P53 to P50
SGS3 to SGS0
0010, 0011,
0100, 0101,
0110, 0111,
1000, 1001
(m= 3 to 0)
Other than 0001, 0010, 0011, 0100, 0101,
0110, 0111, 1000
WKPm
0
0001, 0010,
0011, 0100,
0101, 0110,
0111, 1000
1
*
PCR5m
0
1
*
*
Pin function
P5m input pin
P5m output
pin
WKPm output
pin
SEGm+1
output pin
*: Don’t care
Rev. 8.00 Mar. 09, 2010 Page 218 of 658
REJ09B0042-0800
Section 8 I/O Ports
8.5.4
Pin States
Table 8.13 shows the port 5 pin states in each operating mode.
Table 8.13 Port 5 Pin States
Pins
Reset
Sleep
Subsleep Standby
P57/WKP7/
SEG8 to P50/
WKP0/SEG1
HighRetains Retains
impedance previous previous
state
state
Watch
Subactive Active
Retains Functional Functional
Highimpedance* previous
state
Note: * A high-level signal is output when the MOS pull-up is in the on state.
In the HD64F38024 the previous pin state is retained.
8.5.5
MOS Input Pull-Up
Port 5 has a built-in MOS input pull-up function that can be controlled by software. When a
PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for
that pin. The MOS pull-up function is in the off state after a reset.
PCR5n
0
0
1
PUCR5n
0
1
*
MOS input pull-up
Off
On
Off
(n = 7 to 0)
*: Don’t care
Rev. 8.00 Mar. 09, 2010 Page 219 of 658
REJ09B0042-0800
Section 8 I/O Ports
8.6
Port 6
8.6.1
Overview
Port 6 is an 8-bit I/O port. The port 6 pin configuration is shown in figure 8.5.
P67/SEG16
P66/SEG15
P65/SEG14
P64/SEG13
Port 6
P63/SEG12
P62/SEG11
P61/SEG10
P60/SEG9
Figure 8.5 Port 6 Pin Configuration
8.6.2
Register Configuration and Description
Table 8.14 shows the port 6 register configuration.
Table 8.14 Port 6 Registers
Name
Abbr.
R/W
Initial Value
Address
Port data register 6
PDR6
R/W
H'00
H'FFD9
Port control register 6
PCR6
W
H'00
H'FFE9
Port pull-up control register 6
PUCR6
R/W
H'00
H'FFE3
Rev. 8.00 Mar. 09, 2010 Page 220 of 658
REJ09B0042-0800
Section 8 I/O Ports
Port Data Register 6 (PDR6)
Bit
7
6
5
4
3
2
1
0
P6 7
P66
P65
P64
P6 3
P62
P61
P6 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR6 is an 8-bit register that stores data for port 6 pins P67 to P60.
If port 6 is read while PCR6 bits are set to 1, the values stored in PDR6 are read, regardless of the
actual pin states. If port 6 is read while PCR6 bits are cleared to 0, the pin states are read.
Upon reset, PDR6 is initialized to H'00.
Port Control Register 6 (PCR6)
Bit
7
6
5
4
3
2
1
0
PCR67
PCR66
PCR65
PCR64
PCR63
PCR62
PCR61
PCR60
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PCR6 is an 8-bit register for controlling whether each of the port 6 pins P67 to P60 functions as an
input pin or output pin.
Setting a PCR6 bit to 1 makes the corresponding pin (P67 to P60) an output pin, while clearing the
bit to 0 makes the pin an input pin. PCR6 and PDR6 settings are valid when the corresponding
pins are designated for general-purpose input/output by bits SGS3 to SGS0 in LPCR.
Upon reset, PCR6 is initialized to H'00.
PCR6 is a write-only register, which is always read as all 1s.
Rev. 8.00 Mar. 09, 2010 Page 221 of 658
REJ09B0042-0800
Section 8 I/O Ports
Port Pull-Up Control Register 6 (PUCR6)
Bit
7
6
5
4
3
2
0
1
PUCR67 PUCR66 PUCR6 5 PUCR64 PUCR6 3 PUCR6 2 PUCR61 PUCR60
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PUCR6 controls whether the MOS pull-up of each of the port 6 pins P67 to P60 is on or off. When
a PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the MOS pull-up for
the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Upon reset, PUCR6 is initialized to H'00.
8.6.3
Pin Functions
Table 8.15 shows the port 6 pin functions.
Table 8.15 Port 6 Pin Functions
Pin
Pin Functions and Selection Method
P67/SEG16 to
P60/SEG9
The pin function depends on bits PCR67 to PCR60 in PCR6 and bits SGS3 to
SGS0 in LPCR.
P67 to P64
SGS3 to SGS0
(n = 7 to 4)
Other than 0100, 0101, 0110, 0111,
1000, 1001, 1010, 1011
0100, 0101, 0110,
0111, 1000, 1001,
1010, 1011
PCR6n
0
1
*
Pin function
P6n input pin
P6n output pin
SEGn+9 output pin
P63 to P60
SGS3 to SGS0
(m = 3 to 0)
Other than 0011, 0100, 0101, 0110,
0111, 1000, 1001, 1010
0011, 0100, 0101,
0110, 0111, 1000,
1001, 1010
PCR6m
0
1
*
Pin function
P6m input pin
P6m output pin
SEGm+9 output pin
*: Don’t care
Rev. 8.00 Mar. 09, 2010 Page 222 of 658
REJ09B0042-0800
Section 8 I/O Ports
8.6.4
Pin States
Table 8.16 shows the port 6 pin states in each operating mode.
Table 8.16 Port 6 Pin States
Pin
Reset
Sleep
Subsleep Standby
P67/SEG16 to
P60/SEG9
HighRetains Retains
impedance previous previous
state
state
Watch
Subactive Active
Retains Functional Functional
Highimpedance* previous
state
Note: * A high-level signal is output when the MOS pull-up is in the on state.
8.6.5
MOS Input Pull-Up
Port 6 has a built-in MOS pull-up function that can be controlled by software. When a PCR6 bit is
cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the MOS pull-up for that pin. The
MOS pull-up function is in the off state after a reset.
PCR6n
0
0
1
PUCR6n
0
1
*
MOS input pull-up
Off
On
Off
(n = 7 to 0)
*: Don’t care
Rev. 8.00 Mar. 09, 2010 Page 223 of 658
REJ09B0042-0800
Section 8 I/O Ports
8.7
Port 7
8.7.1
Overview
Port 7 is an 8-bit I/O port, configured as shown in figure 8.6.
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
Port 7
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
Figure 8.6 Port 7 Pin Configuration
8.7.2
Register Configuration and Description
Table 8.17 shows the port 7 register configuration.
Table 8.17 Port 7 Registers
Name
Abbr.
R/W
Initial Value
Address
Port data register 7
PDR7
R/W
H'00
H'FFDA
Port control register 7
PCR7
W
H'00
H'FFEA
Rev. 8.00 Mar. 09, 2010 Page 224 of 658
REJ09B0042-0800
Section 8 I/O Ports
Port Data Register 7 (PDR7)
Bit
7
6
5
4
3
2
1
0
P7 7
P7 6
P75
P7 4
P73
P72
P71
P70
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR7 is an 8-bit register that stores data for port 7 pins P77 to P70. If port 7 is read while PCR7
bits are set to 1, the values stored in PDR7 are read, regardless of the actual pin states. If port 7 is
read while PCR7 bits are cleared to 0, the pin states are read.
Upon reset, PDR7 is initialized to H'00.
Port Control Register 7 (PCR7)
Bit
7
6
5
4
3
2
1
0
PCR77
PCR76
PCR75
PCR74
PCR73
PCR72
PCR71
PCR70
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PCR7 is an 8-bit register for controlling whether each of the port 7 pins P77 to P70 functions as an
input pin or output pin. Setting a PCR7 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. PCR7 and PDR7 settings are valid when the
corresponding pins are designated for general-purpose input/output by bits SGS3 to SGS0 in
LPCR.
Upon reset, PCR7 is initialized to H'00.
PCR7 is a write-only register, which is always read as all 1s.
Rev. 8.00 Mar. 09, 2010 Page 225 of 658
REJ09B0042-0800
Section 8 I/O Ports
8.7.3
Pin Functions
Table 8.18 shows the port 7 pin functions.
Table 8.18 Port 7 Pin Functions
Pin
Pin Functions and Selection Method
P77/SEG24 to
P70/SEG17
The pin function depends on bits PCR77 to PCR70 in PCR7 and bits SGS3 to
SGS0 in LPCR.
P77 to P74
(n = 7 to 4)
SGS3 to SGS0
Other than 0110, 0111, 1000, 1001,
1010, 1011, 1100, 1101
0110, 0111, 1000,
1001, 1010, 1011,
1100, 1101
PCR7n
0
1
*
Pin function
P7n input pin
P7n output pin
SEGn+17 output pin
P73 to P70
(m = 3 to 0)
SGS3 to SGS0
Other than 0101, 0110, 0111, 1000,
1001, 1010, 1011, 1100
0101, 0110, 0111,
1000, 1001, 1010,
1011, 1100
PCR7m
0
1
*
Pin function
P7m input pin
P7m output pin
SEGm+17 output pin
*: Don’t care
8.7.4
Pin States
Table 8.19 shows the port 7 pin states in each operating mode.
Table 8.19 Port 7 Pin States
Pins
Reset
Sleep
Subsleep Standby
P77/SEG24 to
P70/SEG17
HighRetains Retains
impedance previous previous
state
state
Rev. 8.00 Mar. 09, 2010 Page 226 of 658
REJ09B0042-0800
Watch
Subactive Active
HighRetains Functional Functional
impedance previous
state
Section 8 I/O Ports
8.8
Port 8
8.8.1
Overview
Port 8 is an 8-bit I/O port configured as shown in figure 8.7.
P87/SEG32
P86/SEG31
P85/SEG30
P84/SEG29
Port 8
P83/SEG28
P82/SEG27
P81/SEG26
P80/SEG25
Figure 8.7 Port 8 Pin Configuration
8.8.2
Register Configuration and Description
Table 8.20 shows the port 8 register configuration.
Table 8.20 Port 8 Registers
Name
Abbr.
R/W
Initial Value
Address
Port data register 8
PDR8
R/W
H'00
H'FFDB
Port control register 8
PCR8
W
H'00
H'FFEB
Rev. 8.00 Mar. 09, 2010 Page 227 of 658
REJ09B0042-0800
Section 8 I/O Ports
Port Data Register 8 (PDR8)
Bit
7
6
5
4
3
2
1
0
P87
P86
P85
P84
P83
P82
P81
P8 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR8 is an 8-bit register that stores data for port 8 pins P87 to P80. If port 8 is read while PCR8
bits are set to 1, the values stored in PDR8 are read, regardless of the actual pin states. If port 8 is
read while PCR8 bits are cleared to 0, the pin states are read.
Upon reset, PDR8 is initialized to H'00.
Port Control Register 8 (PCR8)
Bit
7
6
5
4
3
2
1
0
PCR87
PCR86
PCR85
PCR84
PCR83
PCR82
PCR81
PCR80
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PCR8 is an 8-bit register for controlling whether the port 8 pins P87 to P80 functions as an input or
output pin. Setting a PCR8 bit to 1 makes the corresponding pin an output pin, while clearing the
bit to 0 makes the pin an input pin. PCR8 and PDR8 settings are valid when the corresponding
pins are designated for general-purpose input/output by bits SGS3 to SGS0 in LPCR.
Upon reset, PCR8 is initialized to H'00.
PCR8 is a write-only register, which is always read as all 1s.
Rev. 8.00 Mar. 09, 2010 Page 228 of 658
REJ09B0042-0800
Section 8 I/O Ports
8.8.3
Pin Functions
Table 8.21 shows the port 8 pin functions.
Table 8.21 Port 8 Pin Functions
Pin
Pin Functions and Selection Method
P87/SEG32
to
P80/SEG25
The pin function depends on bits PCR87 to PCR80 in PCR8 and bits SGS3 to SGS0
in LPCR.
P87 to P84
(n = 7 to 4)
SGS3 to SGS0
Other than 1000, 1001, 1010, 1011, 1100,
1101, 1110, 1111
1000, 1001, 1010,
1011, 1100, 1101,
1110, 1111
PCR8n
0
1
*
Pin function
P8n input pin
P8n output pin
SEGn+25 output pin
P83 to P80
(m = 3 to 0)
SGS3 to SGS0
Other than 0111, 1000, 1001, 1010, 1011,
1100, 1101, 1110
0111, 1000, 1001,
1010, 1011, 1100,
1101, 1110
PCR8m
0
1
*
Pin function
P8m input pin
P8m output pin
SEGm+25 output pin
*: Don’t care
8.8.4
Pin States
Table 8.22 shows the port 8 pin states in each operating mode.
Table 8.22 Port 8 Pin States
Pins
Reset
Sleep
Subsleep Standby
P87/SEG32 to
P80/SEG25
HighRetains Retains
impedance previous previous
state
state
Watch
Subactive Active
HighRetains Functional Functional
impedance previous
state
Rev. 8.00 Mar. 09, 2010 Page 229 of 658
REJ09B0042-0800
Section 8 I/O Ports
8.9
Port 9
8.9.1
Overview
Port 9 is a 6-bit output port, configured as shown in figure 8.8.
P95
P94
Port 9
P93/Vref*
P92
P91/PWM2
P90/PWM1
Note: * The Vref pin is implemented on the H8/38124 Group only.
Figure 8.8 Port 9 Pin Configuration
Rev. 8.00 Mar. 09, 2010 Page 230 of 658
REJ09B0042-0800
Section 8 I/O Ports
8.9.2
Register Configuration and Description
Table 8.23 shows the port 9 register configuration.
Table 8.23 Port 9 Registers
Name
Abbr.
R/W
Initial Value
Address
Port data register 9
PDR9
R/W
H'FF
H'FFDC
Port mode register 9
PMR9
R/W
—
H'FFEC
Port Data Register 9 (PDR9)
Bit
7
6
5
4
3
2
1
0
—
—
P95
P9 4
P93
P92
P91
P9 0
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
R/W
R/W
R/W
R/W
R/W
R/W
PDR9 is an 8-bit register that stores data for port 9 pins P95 to P90.
Upon reset, PDR9 is initialized to H'FF.
Port Mode Register 9 (PMR9)
Bit
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
PIOFF/⎯*
⎯
PWM2
PWM1
Initial value
1
1
1
1
0
⎯
0
0
Read/Write
⎯
⎯
⎯
⎯
R/W
W
R/W
R/W
Note: * Readable/writable reserved bit in the H8/38024S Group and H8/38124 Group.
PMR9 is an 8-bit read/write register controlling the selection of the P90 and P91 pin functions.
Rev. 8.00 Mar. 09, 2010 Page 231 of 658
REJ09B0042-0800
Section 8 I/O Ports
Bit 3— P92 to P90 Step-Up Circuit Control (PIOFF)
Bit 3 turns the P92 to P90 step-up circuit on and off. This bit is reserved in the H8/38024S Group
and H8/38124 Group.
Bit 3
PIOFF
Description
0
Large-current port step-up circuit is turned on
1
Large-current port step-up circuit is turned off
(initial value)
Note: In the H8/38024 ZTAT version and mask ROM version, and the HD64F38024R, the
following precautions should be followed when accessing the PIOFF bit.
When turning the voltage boost circuit on or off, always write to the register when the buffer
NMOS is off (port data set to 1). Also, when turning on the voltage boost circuit, first clear
PIOFF to 0 and then after waiting 30 system clock cycles turn on the buffer NMOS (port
data cleared to 0). If 30 system clock cycles have not elapsed the voltage boost circuit will
not start operating and it will not be possible to produce a large current flow, resulting in
unstable operation.
In the HD64F38024, the following precautions should be followed when accessing the
PIOFF bit.
In the HD64F38024, if port data bits are cleared from 1 to 0 while the PIOFF bit is set to 1,
repeated charge-discharge cycles will occur in the voltage boost circuit, causing the current
consumption to rise and fall cyclically. The amount of rise in the current consumption in this
case is between several tens of µA and 100 µA above the normal level. Therefore, the
following points should be kept in mind.
(1) Not Using Subclock
Regardless of whether or not port 9 is used, the PIOFF bit should be left at its initial
value (0) and not changed.
(2) Not Using Port 9
Port data should be used unchanged with the PIOFF bit either at its initial value (0) or
set to 1. In the latter case the current consumption will vary, due to the intermittent
operation of the voltage boost circuit, by about 1 µA (standby mode or watch mode, VCC
= 3.0 V, Ta = 25°C).
(3) Using Port 9 with PIOFF Always Cleared to 0
This case applies to instances in which the voltage boost circuit is used constantly to
generate a large current glow, or an increase in current consumption due to the
operation of the voltage boost circuit is permissible even in the standby mode or watch
mode (see (2) above). In this case the PIOFF bit should be left at its initial value (0) and
not changed.
(4) Using Port 9 with PIOFF Set to 1
This case applies to instances in which it is necessary to change the value of the PIOFF
bit due to operating conditions or where it is desirable to keep the PIOFF bit set to 1
because no large current is required (for example, shutting down the voltage boost
circuit to reduce current consumption in the watch mode). In this case, clear port data
Rev. 8.00 Mar. 09, 2010 Page 232 of 658
REJ09B0042-0800
Section 8 I/O Ports
from 1 to 0 only when the PIOFF bit is cleared to 0. Also, if a large current flow is
required, the PIOFF bit should be set to 1 and all the port data bits set to 1. Then clear
PIOFF to 0 and, after allowing 30 clock cycles to permit stabilization of the voltage
boost circuit, clear the port data bits to 0. If time is not provided to allow the voltage
boost circuit to stabilize, it will not be possible to produce a large current flow. There are
no such restrictions when setting port data bits from 0 to 1, regardless of the size of the
current flow. To shut down the voltage boost circuit, set PIOFF to 1 after programming
the port data bits. An example of the sequence of steps is provided below.
(Example Procedure)
Shutting Down the in the Watch Mode without a Large Current
Flow to Port 9
Other operation
PIOFF = 0 (voltage boost circuit on)
PDR9 operation or other operation
PIOFF = 1 (voltage boost circuit off)
Execute SLEEP instruction
Watch mode
Cancel watch mode
Bit 2—Reserved
This bit is reserved; it can only be written with 0.
Bits 1 and 0—P9n/PWM Pin Function Switches
These pins select whether pin P9n/PWMn+1 is used as P9n or as PWMn+1.
Bit n
WKPn+1
Description
0
Functions as P9n output pin
1
Functions as PWMn+1 output pin
(initial value)
(n = 0 or 1)
Rev. 8.00 Mar. 09, 2010 Page 233 of 658
REJ09B0042-0800
Section 8 I/O Ports
8.9.3
Pin Functions
Table 8.24 shows the port 9 pin functions.
Table 8.24 Port 9 Pin Functions
Pin
Pin Functions and Selection Method
P93/Vref*
P91/PWMn+1 to
P90/PWMn+1
VREFSEL
0
1
Pin function
P93 output pin
Vref input pin
PMR9n
0
1
Pin function
P9n output pin
PWMn+1 output pin
(n = 1 or 0)
Note: * The Vref pin is the input pin for the LVD’s external reference voltage. It is implemented on
the H8/38124 Group only.
8.9.4
Pin States
Table 8.25 shows the port 9 pin states in each operating mode.
Table 8.25 Port 9 Pin States
Pins
Reset
Sleep
Subsleep Standby
P95 to P92
P9n/PWMn+1 to
P9n/PWMn+1
HighRetains Retains
impedance previous previous
state
state
Highimpedance
Watch
Subactive Active
Retains Functional Functional
previous
state
(n = 1 or 0)
Rev. 8.00 Mar. 09, 2010 Page 234 of 658
REJ09B0042-0800
Section 8 I/O Ports
8.10
Port A
8.10.1
Overview
Port A is a 4-bit I/O port, configured as shown in figure 8.9.
PA3/COM4
PA2/COM3
Port A
PA1/COM2
PA0/COM1
Figure 8.9 Port A Pin Configuration
8.10.2
Register Configuration and Description
Table 8.26 shows the port A register configuration.
Table 8.26 Port A Registers
Name
Abbr.
R/W
Initial Value
Address
Port data register A
PDRA
R/W
H'F0
H'FFDD
Port control register A
PCRA
W
H'F0
H'FFED
Port Data Register A (PDRA)
Bit
7
6
5
4
⎯
⎯
⎯
⎯
3
PA 3
2
1
PA 2
PA 1
0
PA 0
Initial value
1
1
1
1
0
0
0
0
Read/Write
⎯
⎯
⎯
⎯
R/W
R/W
R/W
R/W
PDRA is an 8-bit register that stores data for port A pins PA3 to PA0. If port A is read while
PCRA bits are set to 1, the values stored in PDRA are read, regardless of the actual pin states. If
port A is read while PCRA bits are cleared to 0, the pin states are read.
Upon reset, PDRA is initialized to H'F0.
Rev. 8.00 Mar. 09, 2010 Page 235 of 658
REJ09B0042-0800
Section 8 I/O Ports
Port Control Register A (PCRA)
Bit
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
PCRA 2
PCRA 1
Initial value
1
1
1
1
0
0
0
0
Read/Write
⎯
⎯
⎯
⎯
W
W
W
W
PCRA 3
PCRA 0
PCRA controls whether each of port A pins PA3 to PA0 functions as an input pin or output pin.
Setting a PCRA bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0
makes the pin an input pin. PCRA and PDRA settings are valid when the corresponding pins are
designated for general-purpose input/output by LPCR.
Upon reset, PCRA is initialized to H'F0.
PCRA is a write-only register, which is always read as all 1s.
Rev. 8.00 Mar. 09, 2010 Page 236 of 658
REJ09B0042-0800
Section 8 I/O Ports
8.10.3
Pin Functions
Table 8.27 shows the port A pin functions.
Table 8.27 Port A Pin Functions
Pin
Pin Functions and Selection Method
PA3/COM4
The pin function depends on bit PCRA3 in PCRA and bits SGS3 to SGS0.
PA2/COM3
PA1/COM2
PA0/COM1
SGS3 to SGS0
0000
0000
Not 0000
PCRA3
0
1
*
Pin function
PA3 input pin
PA3 output pin
COM4 output pin
The pin function depends on bit PCRA2 in PCRA and bits SGS3 to SGS0.
SGS3 to SGS0
0000
0000
Not 0000
PCRA2
0
1
*
Pin function
PA2 input pin
PA2 output pin
COM3 output pin
The pin function depends on bit PCRA1 in PCRA and bits SGS3 to SGS0.
SGS3 to SGS0
0000
0000
Not 0000
PCRA1
0
1
*
Pin function
PA1 input pin
PA1 output pin
COM2 output pin
The pin function depends on bit PCRA0 in PCRA and bits SGS3 to SGS0.
SGS3 to SGS0
0000
Not 0000
PCRA0
0
1
*
Pin function
PA0 input pin
PA0 output pin
COM1 output pin
*: Don’t care
Rev. 8.00 Mar. 09, 2010 Page 237 of 658
REJ09B0042-0800
Section 8 I/O Ports
8.10.4
Pin States
Table 8.28 shows the port A pin states in each operating mode.
Table 8.28 Port A Pin States
Pins
Reset
Sleep
Subsleep Standby
PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1
HighRetains Retains
impedance previous previous
state
state
Rev. 8.00 Mar. 09, 2010 Page 238 of 658
REJ09B0042-0800
Watch
Subactive Active
HighRetains Functional Functional
impedance previous
state
Section 8 I/O Ports
8.11
Port B
8.11.1
Overview
Port B is an 8-bit input-only port, configured as shown in figure 8.10.
PB7/AN7
PB6/AN6
PB5/AN5
PB4/AN4
Port B
PB3/AN3/IRQ1/TMIC
PB2/AN2
PB1/AN1/extU*
PB0/AN0/extD*
Note: * The extU and extD pins are implemented on the H8/38124 Group only.
Figure 8.10 Port B Pin Configuration
8.11.2
Register Configuration and Description
Table 8.29 shows the port B register configuration.
Table 8.29 Port B Register
Name
Abbr.
R/W
Initial Value
Address
Port data register B
PDRB
R
—
H'FFDE
Port mode register B
PMRB
R/W
H'F7
H'FFEE
Rev. 8.00 Mar. 09, 2010 Page 239 of 658
REJ09B0042-0800
Section 8 I/O Ports
Port Data Register B (PDRB)
Bit
Read/Write
7
6
5
4
3
2
1
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB 0
R
R
R
R
R
R
R
R
Reading PDRB always gives the pin states. However, if a port B pin is selected as an analog input
channel for the A/D converter by AMR bits CH3 to CH0, that pin reads 0 regardless of the input
voltage.
Port Mode Register B (PMRB)
Bit
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
IRQ1
⎯
⎯
⎯
Initial value
1
1
1
1
0
1
1
1
Read/Write
⎯
⎯
⎯
⎯
R/W
⎯
⎯
⎯
PMRB is an 8-bit read/write register controlling the selection of the PB3 pin function. Upon reset,
PMRB is initialized to H'F7.
Bits 7 to 4 and 2 to 0—Reserved
Bits 7 to 4 and 2 to 0 are reserved; they are always read as 1 and cannot be modified.
Bit 3—PB3/AN3/IRQ1 Pin Function Switch (IRQ1)
These bits select whether pin PB3/AN3/IRQ1 is used as PB3/AN3 or as IRQ1/TMIC.
Bit 3
IRQ1
Description
0
Functions as PB3/AN3 input pin
1
Functions as IRQ1/TMIC input pin
(initial value)
Note: Rising or falling edge sensing can be selected for the IRQ1/TMIC pin.
For TMIC pin setting information, see the Timer More Register C (TMC) description in section
9.3.2, Register Descriptions.
Rev. 8.00 Mar. 09, 2010 Page 240 of 658
REJ09B0042-0800
Section 8 I/O Ports
8.11.3
Pin Functions
Table 8.30 shows the port B pin functions.
Table 8.30 Port B Pin Functions
Pin
Pin Functions and Selection Method
PB7/AN7
The pin function depends on bits CH3 to CH0 in AMR.
PB6/AN6
PB5/AN5
PB4/AN4
PB3/AN3/IRQ1/
TMIC
CH3 to CH0
Not 1011
1011
Pin function
PB7 input pin
AN7 input pin
The pin function depends on bits CH3 to CH0 in AMR.
CH3 to CH0
Not 1010
1010
Pin function
PB6 input pin
AN6 input pin
The pin function depends on bits CH3 to CH0 in AMR.
CH3 to CH0
Not 1001
1001
Pin function
PB5 input pin
AN5 input pin
The pin function depends on bits CH3 to CH0 in AMR.
CH3 to CH0
Not 1000
1000
Pin function
PB4 input pin
AN4 input pin
The pin function depends on bits CH3 to CH0 in AMR and bit IRQ1 in PMRB and
bits TMC2 to TMC0 in TMC.
IRQ1
CH3 to CH0
TMC2 to TMC0
Pin function
0
Not 0111
1
0111
*
Not 111
*
111
PB3 input pin AN3 input pin IRQ1 input pin
TMIC input
pin
Note: When this pin is used as the TMIC input pin, clear IEN1 to 0 in IENR1 to
disable the IRQ1 interrupt.
PB2/AN2
The pin function depends on bits CH3 to CH0 in AMR.
CH3 to CH0
Not 0110
0110
Pin function
PB2 input pin
AN2 input pin
Rev. 8.00 Mar. 09, 2010 Page 241 of 658
REJ09B0042-0800
Section 8 I/O Ports
Pin
Pin Functions and Selection Method
PB1/AN1/extU
Switching is accomplished by combining CH3 to CH0 in AMR and VINTUSEL in
LVDCR as shown below. Note that VINTUSEL is implemented on the H8/38124
Group only.
VINTUSEL
0
1
CH3 to CH0
Not B'0101
B'0101
*
Pin function
PB1 input pin
AN1 input pin
extU input pin
Note: The extU pin is implemented on the H8/38124 Group only.
PB0/AN0/extD
Switching is accomplished by combining CH3 to CH0 in AMR and VINTDSEL in
LVDCR as shown below. Note that VINTDSEL is implemented on the H8/38124
Group only.
VINTDSEL
0
1
CH3 to CH0
Not B'0100
B'0100
*
Pin function
PB0 input pin
AN0 input pin
extD input pin
Note: The extD pin is implemented on the H8/38124 Group only.
*: Don’t care
8.12
Input/Output Data Inversion Function
8.12.1
Overview
With input pin RXD32 and output pin TXD32, the data can be handled in inverted form.
SCINV2
RXD32
P41/RXD32
SCINV3
P42/TXD32
TXD32
Figure 8.11 Input/Output Data Inversion Function
Rev. 8.00 Mar. 09, 2010 Page 242 of 658
REJ09B0042-0800
Section 8 I/O Ports
8.12.2
Register Configuration and Descriptions
Table 8.31 shows the registers used by the input/output data inversion function.
Table 8.31 Register Configuration
Name
Abbr.
R/W
Address
Serial port control register
SPCR
R/W
H'FF91
Serial Port Control Register (SPCR)
Bit
7
6
5
4
3
2
1
0
⎯
⎯
SPC32
⎯
⎯
⎯
Initial value
1
1
0
⎯
0
0
⎯
⎯
Read/Write
⎯
⎯
R/W
W
R/W
R/W
W
W
SCINV3 SCINV2
SPCR is an 8-bit readable/writable register that performs RXD32 and TXD32 pin input/output data
inversion switching.
Bits 7 and 6—Reserved
Bits 7 and 6 are reserved; they are always read as 1 and cannot be modified.
Bit 5—P42/TXD32 Pin Function Switch (SPC32)
This bit selects whether pin P42/TXD32 is used as P42 or as TXD32.
Bit 5
SPC32
Description
0
Functions as P42 I/O pin
1
Functions as TXD32 output pin*
(initial value)
Note: * Set the TE bit in SCR3 after setting this bit to 1.
Bit 4—Reserved
Bit 4 is reserved; it can only be written with 0.
Rev. 8.00 Mar. 09, 2010 Page 243 of 658
REJ09B0042-0800
Section 8 I/O Ports
Bit 3—TXD32 Pin Output Data Inversion Switch
Bit 3 specifies whether or not TXD32 pin output data is to be inverted.
Bit 3
SCINV3
Description
0
TXD32 output data is not inverted
1
TXD32 output data is inverted
(initial value)
Bit 2—RXD32 Pin Input Data Inversion Switch
Bit 2 specifies whether or not RXD32 pin input data is to be inverted.
Bit 2
SCINV2
Description
0
RXD32 input data is not inverted
1
RXD32 input data is inverted
(initial value)
Bits 1 and 0—Reserved
Bits 1 and 0 are reserved; they can only be written with 0.
8.12.3
Note on Modification of Serial Port Control Register
When a serial port control register is modified, the data being input or output up to that point is
inverted immediately after the modification, and an invalid data change is input or output. When
modifying a serial port control register, do so in a state in which data changes are invalidated.
Rev. 8.00 Mar. 09, 2010 Page 244 of 658
REJ09B0042-0800
Section 8 I/O Ports
8.13
Application Note
8.13.1
The Management of the Un-Use Terminal
If an I/O pin not used by the user system is floating, pull it up or down.
• If an unused pin is an input pin, handle it in one of the following ways:
⎯ Pull it up to VCC with an on-chip pull-up MOS.
⎯ Pull it up to VCC with an external resistor of approximately 100 kΩ.
⎯ Pull it down to VSS with an external resistor of approximately 100 kΩ.
⎯ For a pin also used by the A/D converter, pull it up to AVCC.
• If an unused pin is an output pin, handle it in one of the following ways:
⎯ Set the output of the unused pin to high and pull it up to VCC with an on-chip pull-up MOS.
⎯ Set the output of the unused pin to high and pull it up to VCC with an external resistor of
approximately 100 kΩ.
⎯ Set the output of the unused pin to low and pull it down to GND with an external resistor of
approximately 100 kΩ.
Rev. 8.00 Mar. 09, 2010 Page 245 of 658
REJ09B0042-0800
Section 8 I/O Ports
Rev. 8.00 Mar. 09, 2010 Page 246 of 658
REJ09B0042-0800
Section 9 Timers
Section 9 Timers
9.1
Overview
This LSI provides six timers: timers A, C, F, G, and a watchdog timer, and an asynchronous event
counter. The functions of these timers are outlined in table 9.1.
Table 9.1
Timer Functions
Event
Input Pin
Waveform
Output Pin
—
—
φ/4 to φ/8192, φW/4
(7 choices)
TMIC
—
φ/4 to φ/32, φw/4
(4 choices)
TMIF
TMOFL
TMOFH
φ/2 to φ/64, φW/4
(4 choices)
TMIG
—
Name
Functions
Internal Clock
Timer A
•
8-bit timer
•
Interval function
φ/8 to φ/8192
(8 choices)
•
Time base
φw/128 (choice of 4
overflow periods)
•
8-bit timer
•
Interval function
•
Event counting function
•
Up-count/down-count
selectable
•
16-bit timer
•
Event counting function
•
Also usable as two
independent 8-bit timers
•
Output compare output
function
•
8-bit timer
•
Input capture function
•
Interval function
•
Reset signal generated
when 8-bit counter
overflows
Timer C
Timer F
Timer G
Watchdog
timer*
Remarks
Up-count/
down-count
controllable by
software or
hardware
Counter
clearing option
Built-in capture
input signal
noise canceler
φ/8192
φW /32
—
φ/64 to φ/8192
φW /32
On-chip oscillator
—
H8/38024,
H8/38024S,
H8/38024R
Group
H8/38124
Group
Rev. 8.00 Mar. 09, 2010 Page 247 of 658
REJ09B0042-0800
Section 9 Timers
Name
Functions
Asynchro- •
nous event •
counter
16-bit counter
Also usable as two
independent 8-bit
counters
•
Counts events
asynchronous to φ and φw
•
Can count asynchronous
events (rising/falling/both
edges) independ-ently of
the MCU's internal clock
Internal Clock
φ/2 to φ/8
(3 choices)
Event
Input Pin
Waveform
Output Pin
AEVL
AEVH
IRQAEC
—
Remarks
Note: * The watchdog timer functions differently on the H8/38024, H8/38024S, H8/38024R Group
and H8/38124 Group. See section 9.6, Watchdog Timer, for details.
9.2
Timer A
9.2.1
Overview
Timer A is an 8-bit timer with interval timing and real-time clock time-base functions. The clock
time-base function is available when a 32.768 kHz crystal resonator is connected as the subclock.
Features
Features of timer A are given below.
• Choice of eight internal clock sources (φ/8192, φ/4096, φ/2048, φ/512, φ/256, φ/128, φ/32,
φ/8).
• Choice of four overflow periods (1 s, 0.5 s, 0.25 s, 31.25 ms) when timer A is used as a clock
time base (using a 32.768 kHz crystal resonator is connected as the subclock).
• An interrupt is requested when the counter overflows.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
Rev. 8.00 Mar. 09, 2010 Page 248 of 658
REJ09B0042-0800
Section 9 Timers
Block Diagram
Figure 9.1 shows a block diagram of timer A.
φW
TMA
PSW
1/4
Internal data bus
φW /4
φW/128
φ
+256*
+128*
+64*
φ/8192, φ/4096, φ/2048,
φ/512, φ/256, φ/128,
φ/32, φ/8
+8*
TCA
PSS
IRRTA
[Legend]
TMA:
TCA:
IRRTA:
PSW:
PSS:
Timer mode register A
Timer counter A
Timer A overflow interrupt request flag
Prescaler W
Prescaler S
Note: * Can be selected only when the prescaler W output (φW /128) is used as the TCA input clock.
Figure 9.1 Block Diagram of Timer A
Rev. 8.00 Mar. 09, 2010 Page 249 of 658
REJ09B0042-0800
Section 9 Timers
Register Configuration
Table 9.2 shows the register configuration of timer A.
Table 9.2
Timer A Registers
Name
Abbr.
R/W
Initial Value
Address
Timer mode register A
TMA
R/W
—
H'FFB0
Timer counter A
TCA
R
H'00
H'FFB1
Clock stop register 1
CKSTPR1
R/W
H'FF
H'FFFA
9.2.2
Register Descriptions
Timer Mode Register A (TMA)
Bit
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
TMA3
TMA2
TMA1
TMA0
Initial value
⎯
⎯
⎯
1
0
0
0
0
Read/Write
W
W
W
⎯
R/W
R/W
R/W
R/W
TMA is an 8-bit read/write register for selecting the prescaler, and input clock.
Bits 7 to 5—Reserved
Bits 7 to 5 are reserved; only 0 can be written to these bits.
Bit 4—Reserved
Bit 4 is reserved; it is always read as 1, and cannot be modified.
Rev. 8.00 Mar. 09, 2010 Page 250 of 658
REJ09B0042-0800
Section 9 Timers
Bits 3 to 0—Internal Clock Select (TMA3 to TMA0)
Bits 3 to 0 select the clock input to TCA. The selection is made as follows.
Description
Bit 3
TMA3
Bit 2
TMA2
Bit 1
TMA1
Bit 0
TMA0
Prescaler and Divider Ratio
or Overflow Period
0
0
0
0
PSS, φ/8192
1
PSS, φ/4096
0
PSS, φ/2048
1
PSS, φ/512
0
PSS, φ/256
1
PSS, φ/128
0
PSS, φ/32
1
PSS, φ/8
0
0
PSW, 1 s
1
PSW, 0.5 s
base
1
0
PSW, 0.25 s
(when using
1
PSW, 0.03125 s
32.768 kHz)
0
PSW and TCA are reset
1
1
0
1
1
0
1
0
Function
(initial value) Interval timer
Clock time
1
1
0
1
Rev. 8.00 Mar. 09, 2010 Page 251 of 658
REJ09B0042-0800
Section 9 Timers
Timer Counter A (TCA)
Bit
7
6
5
4
3
2
1
0
TCA7
TCA6
TCA5
TCA4
TCA3
TCA2
TCA1
TCA0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock
source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A
(TMA). TCA values can be read by the CPU in active mode, but cannot be read in subactive
mode. When TCA overflows, the IRRTA bit in interrupt request register 1 (IRR1) is set to 1.
TCA is cleared by setting bits TMA3 and TMA2 of TMA to 11.
Upon reset, TCA is initialized to H'00.
Clock Stop Register 1 (CKSTPR1)
7
6
⎯
⎯
Initial value:
1
1
1
1
1
1
1
1
Read/Write:
⎯
⎯
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
5
4
3
2
1
0
S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer A is described here. For details of the other bits, see the
sections on the relevant modules.
Bit 0—Timer A Module Standby Mode Control (TACKSTP)
Bit 0 controls setting and clearing of module standby mode for timer A.
TACKSTP
Description
0
Timer A is set to module standby mode
1
Timer A module standby mode is cleared
Rev. 8.00 Mar. 09, 2010 Page 252 of 658
REJ09B0042-0800
(initial value)
Section 9 Timers
9.2.3
Timer Operation
Interval Timer Operation
When bit TMA3 in timer mode register A (TMA) is cleared to 0, timer A functions as an 8-bit
interval timer.
Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting and interval
timing resume immediately. The clock input to timer A is selected by bits TMA2 to TMA0 in
TMA; any of eight internal clock signals output by prescaler S can be selected.
After the count value in TCA reaches H'FF, the next clock signal input causes timer A to
overflow, setting bit IRRTA to 1 in interrupt request register 1 (IRR1). If IENTA = 1 in interrupt
enable register 1 (IENR1), a CPU interrupt is requested.*
At overflow, TCA returns to H'00 and starts counting up again. In this mode timer A functions as
an interval timer that generates an overflow output at intervals of 256 input clock pulses.
Note: * For details on interrupts, see section 3.3, Interrupts.
Real-Time Clock Time Base Operation
When bit TMA3 in TMA is set to 1, timer A functions as a real-time clock time base by counting
clock signals output by prescaler W. The overflow period of timer A is set by bits TMA1 and
TMA0 in TMA. A choice of four periods is available. In time base operation (TMA3 = 1), setting
bit TMA2 to 1 clears both TCA and prescaler W to their initial values of H'00.
Rev. 8.00 Mar. 09, 2010 Page 253 of 658
REJ09B0042-0800
Section 9 Timers
9.2.4
Timer A Operation States
Table 9.3 summarizes the timer A operation states.
Table 9.3
Timer A Operation States
Watch
Subactive
Subsleep
Standby
Functions Functions Halted
Halted
Halted
Operation Mode
Reset Active
TCA Interval
Reset
Clock time base Reset
TMA
Reset
Sleep
Module
Standby
Halted
Halted
Functions Functions Functions Functions Functions Halted
Halted
Functions Retained
Retained
Retained
Functions Retained
Retained
Note: When the real-time clock time base function is selected as the internal clock of TCA in
active mode or sleep mode, the internal clock is not synchronous with the system clock, so
it is synchronized by a synchronizing circuit. This may result in a maximum error of 1/φ (s) in
the count cycle.
9.2.5
Application Note
When bit 0 (TACKSTP) of the clock stop register 1 (CKSTPR1) is cleared to 0, bit 3 (TMA3) of
the timer mode register A (TMA) cannot be rewritten.
Set bit 0 (TACKSTP) of the clock stop register 1 (CKSTPR1) to 1 before rewriting bit 3 (TMA3)
of the timer mode register A (TMA).
Rev. 8.00 Mar. 09, 2010 Page 254 of 658
REJ09B0042-0800
Section 9 Timers
9.3
Timer C
9.3.1
Overview
Timer C is an 8-bit timer that increments or decrements each time a clock pulse is input. This
timer has two operation modes, interval and auto reload.
Features
Features of timer C are given below.
• Choice of seven internal clock sources (φ/8192, φ/2048, φ/512, φ/64, φ/16, φ/4, φW/4) or an
external clock (can be used to count external events).
• An interrupt is requested when the counter overflows.
• Up/down-counter switching is possible by hardware or software.
• Subactive mode or subsleep mode operation is possible when φW/4 is selected as the internal
clock, or when an external clock is selected.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
Rev. 8.00 Mar. 09, 2010 Page 255 of 658
REJ09B0042-0800
Section 9 Timers
Block Diagram
Figure 9.2 shows a block diagram of timer C.
Internal data bus
TMC
UD
TCC
φ
PSS
TMIC
TLC
φW /4
IRRTC
[Legend]
TMC: Timer mode register C
TCC: Timer counter C
Timer load register C
TLC:
IRRTC: Timer C overflow interrupt request flag
PSS: Prescaler S
Figure 9.2 Block Diagram of Timer C
Pin Configuration
Table 9.4 shows the timer C pin configuration.
Table 9.4
Pin Configuration
Name
Abbr.
I/O
Function
Timer C event input
TMIC
Input
Input pin for event input to TCC
Timer C up/down select
UD
Input
Timer C up/down-count selection
Rev. 8.00 Mar. 09, 2010 Page 256 of 658
REJ09B0042-0800
Section 9 Timers
Register Configuration
Table 9.5 shows the register configuration of timer C.
Table 9.5
Timer C Registers
Name
Abbr.
R/W
Initial Value
Address
Timer mode register C
TMC
R/W
H'18
H'FFB4
Timer counter C
TCC
R
H'00
H'FFB5
Timer load register C
TLC
W
H'00
H'FFB5
Clock stop register 1
CKSTPR1
R/W
H'FF
H'FFFA
9.3.2
Register Descriptions
Timer Mode Register C (TMC)
Bit
7
6
5
4
3
2
1
0
TMC7
TMC6
TMC5
⎯
⎯
TMC2
TMC1
TMC0
Initial value
0
0
0
1
1
0
0
0
Read/Write
R/W
R/W
R/W
⎯
⎯
R/W
R/W
R/W
TMC is an 8-bit read/write register for selecting the auto-reload function and input clock, and
performing up/down-counter control.
Upon reset, TMC is initialized to H'18.
Bit 7—Auto-Reload Function Select (TMC7)
Bit 7 selects whether timer C is used as an interval timer or auto-reload timer.
Bit 7
TMC7
Description
0
Interval timer function selected
1
Auto-reload function selected
(initial value)
Rev. 8.00 Mar. 09, 2010 Page 257 of 658
REJ09B0042-0800
Section 9 Timers
Bits 6 and 5—Counter Up/Down Control (TMC6, TMC5)
Selects whether TCC up/down control is performed by hardware using UD pin input, or whether
TCC functions as an up-counter or a down-counter.
Bit 6
TMC6
Bit 5
TMC5
Description
0
0
TCC is an up-counter
0
1
TCC is a down-counter
1
*
Hardware control by UD pin input
UD pin input high: Down-counter
UD pin input low: Up-counter
(initial value)
*: Don't care
Bits 4 and 3—Reserved
Bits 4 and 3 are reserved; they are always read as 1 and cannot be modified.
Bits 2 to 0—Clock Select (TMC2 to TMC0)
Bits 2 to 0 select the clock input to TCC. For external event counting, either the rising or falling
edge can be selected.
Bit 2
TMC2
Bit 1
TMC1
Bit 0
TMC0
Description
0
0
0
Internal clock: φ/8192
0
0
1
Internal clock: φ/2048
0
1
0
Internal clock: φ/512
0
1
1
Internal clock: φ/64
1
0
0
Internal clock: φ/16
1
0
1
Internal clock: φ/4
1
1
0
Internal clock: φW /4
1
1
1
External event (TMIC): rising or falling edge*
(initial value)
Note: * The edge of the external event signal is selected by bit IEG1 in the IRQ edge select
register (IEGR). See IRQ Edge Select Register (IEGR) in section 3.3.2, Interrupt Control
Registers, for details. IRQ1 in port mode register B (PMRB) must be set to 1 before
setting 111 in bits TMC2 to TMC0.
Rev. 8.00 Mar. 09, 2010 Page 258 of 658
REJ09B0042-0800
Section 9 Timers
Timer Counter C (TCC)
Bit
7
6
5
4
3
2
1
0
TCC7
TCC6
TCC5
TCC4
TCC3
TCC2
TCC1
TCC0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
TCC is an 8-bit read-only up/down-counter, which is incremented or decremented by internal
clock or external event input. The clock source for input to this counter is selected by bits TMC2
to TMC0 in timer mode register C (TMC). TCC values can be read by the CPU at any time.
When TCC overflows from H'FF to H'00 or to the value set in TLC, or underflows from H'00 to
H'FF or to the value set in TLC, the IRRTC bit in IRR2 is set to 1.
TCC is allocated to the same address as TLC.
Upon reset, TCC is initialized to H'00.
Timer Load Register C (TLC)
Bit
7
6
5
4
3
2
1
0
TLC7
TLC6
TLC5
TLC4
TLC3
TLC2
TLC1
TLC0
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
TLC is an 8-bit write-only register for setting the reload value of timer counter C (TCC).
When a reload value is set in TLC, the same value is loaded into timer counter C as well, and TCC
starts counting up/down from that value. When TCC overflows or underflows during operation in
auto-reload mode, the TLC value is loaded into TCC. Accordingly, overflow/underflow period
can be set within the range of 1 to 256 input clocks.
The same address is allocated to TLC as to TCC.
Upon reset, TLC is initialized to H'00.
Rev. 8.00 Mar. 09, 2010 Page 259 of 658
REJ09B0042-0800
Section 9 Timers
Clock Stop Register 1 (CKSTPR1)
Bit:
7
6
⎯
⎯
5
4
3
2
1
0
S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
Initial value:
1
1
1
1
1
1
1
1
Read/Write:
⎯
⎯
R/W
R/W
R/W
R/W
R/W
R/W
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer C is described here. For details of the other bits, see the
sections on the relevant modules.
Bit 1—Timer C Module Standby Mode Control (TCCKSTP)
Bit 1 controls setting and clearing of module standby mode for timer C.
TCCKSTP
Description
0
Timer C is set to module standby mode
1
Timer C module standby mode is cleared
9.3.3
(initial value)
Timer Operation
Interval Timer Operation
When bit TMC7 in timer mode register C (TMC) is cleared to 0, timer C functions as an 8-bit
interval timer.
Upon reset, TCC is initialized to H'00 and TMC to H'18, so TCC continues up-counting as an
interval up-counter without halting immediately after a reset. The timer C operating clock is
selected from seven internal clock signals output by prescalers S and W, or an external clock input
at pin TMIC. The selection is made by bits TMC2 to TMC0 in TMC.
TCC up/down-count control can be performed either by software or hardware. The selection is
made by bits TMC6 and TMC5 in TMC.
After the count value in TCC reaches H'FF (H'00), the next clock input causes timer C to overflow
(underflow), setting bit IRRTC in IRR2 to 1. If IENTC = 1 in interrupt enable register 2 (IENR2),
a CPU interrupt is requested.
At overflow (underflow), TCC returns to H'00 (H'FF) and starts counting up (down) again.
Rev. 8.00 Mar. 09, 2010 Page 260 of 658
REJ09B0042-0800
Section 9 Timers
During interval timer operation (TMC7 = 0), when a value is set in timer load register C (TLC),
the same value is set in TCC.
Note: For details on interrupts, see section 3.3, Interrupts.
Auto-Reload Timer Operation
Setting bit TMC7 in TMC to 1 causes timer C to function as an 8-bit auto-reload timer. When a
reload value is set in TLC, the same value is loaded into TCC, becoming the value from which
TCC starts its count.
After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C to
overflow/underflow. The TLC value is then loaded into TCC, and the count continues from that
value. The overflow/underflow period can be set within a range from 1 to 256 input clocks,
depending on the TLC value.
The clock sources, up/down control, and interrupts in auto-reload mode are the same as in interval
mode.
In auto-reload mode (TMC7 = 1), when a new value is set in TLC, the TLC value is also set in
TCC.
Event Counter Operation
Timer C can operate as an event counter, counting rising or falling edges of an external event
signal input at pin TMIC. External event counting is selected by setting bits TMC2 to TMC0 in
timer mode register C (TMC) to all 1s (111). TCC counts up/down at the rising/falling edge of an
external event signal input at pin TMIC.
When timer C is used to count external event input, bit IRQ1 in PMRB should be set to 1 and bit
IEN1 in IENR1 cleared to 0 to disable interrupt IRQ1 requests.
TCC Up/Down Control by Hardware
With timer C, TCC up/down control can be performed by UD pin input. When bit TMC6 in TMC
is set to 1, TCC functions as an up-counter when UD pin input is low, and as a down-counter
when high.
When using UD pin input, set bit UD in PMR3 to 1.
Rev. 8.00 Mar. 09, 2010 Page 261 of 658
REJ09B0042-0800
Section 9 Timers
9.3.4
Timer C Operation States
Table 9.6 summarizes the timer C operation states.
Table 9.6
Timer C Operation States
Watch
Subsleep
Active
TCC
Interval
Reset
Functions Functions Halted
Functions/ Functions/ Halted
Halted*
Halted*
Halted
Auto reload
Reset
Functions Functions Halted
Functions/ Functions/ Halted
Halted*
Halted*
Halted
Reset
Functions Retained
Functions Retained
Retained
Retained
Standby
Module
Standby
Reset
TMC
Sleep
Subactive
Operation Mode
Retained
Note: * When φw/4 is selected as the TCC internal clock in active mode or sleep mode, since the
system clock and internal clock are mutually asynchronous, synchronization is maintained
by a synchronization circuit. This results in a maximum count cycle error of 1/φ (s). When
the counter is operated in subactive mode or subsleep mode, either select φw/4 as the
internal clock or select an external clock. The counter will not operate on any other
internal clock. If φw/4 is selected as the internal clock for the counter when φw/8 has been
selected as subclock φSUB, the lower 2 bits of the counter operate on the same cycle, and
the operation of the least significant bit is unrelated to the operation of the counter.
Rev. 8.00 Mar. 09, 2010 Page 262 of 658
REJ09B0042-0800
Section 9 Timers
9.4
Timer F
9.4.1
Overview
Timer F is a 16-bit timer with a built-in output compare function. As well as counting external
events, timer F also provides for counter resetting, interrupt request generation, toggle output, etc.,
using compare match signals. Timer F can also be used as two independent 8-bit timers (timer FH
and timer FL).
Features
Features of timer F are given below.
• Choice of four internal clock sources (φ/32, φ/16, φ/4, φw/4) or an external clock (can be used
as an external event counter)
• TMOFH/TMOFL pin toggle output provided using a single compare match signal (toggle
output initial value can be set)
• Counter resetting by a compare match signal
• Two interrupt sources: one compare match, one overflow
• Can operate as two independent 8-bit timers (timer FH and timer FL) (in 8-bit mode).
Timer FL
8-Bit Timer/Event Counter
Timer FH 8-Bit Timer*
Internal clock
Choice of 4 (φ/32, φ/16, φ/4, φw/4)
Event input
—
TMIF pin
Toggle output
One compare match signal, output to
TMOFH pin(initial value settable)
One compare match signal, output to
TMOFL pin (initial value settable)
Counter reset
Counter can be reset by compare match signal
Interrupt sources
One compare match
One overflow
Note: * When timer F operates as a 16-bit timer, it operates on the timer FL overflow signal.
• Operation in watch mode, subactive mode, and subsleep mode
When φw/4 is selected as the internal clock, timer F can operate in watch mode, subactive
mode, and subsleep mode.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
Rev. 8.00 Mar. 09, 2010 Page 263 of 658
REJ09B0042-0800
Section 9 Timers
Block Diagram
Figure 9.3 shows a block diagram of timer F.
φ
PSS
IRRTFL
TCRF
φW/4
TMIF
TCFL
Toggle
circuit
Comparator
Internal data bus
TMOFL
OCRFL
TCFH
TMOFH
Toggle
circuit
Comparator
Match
OCRFH
TCSRF
IRRTFH
[Legend]
TCRF:
Timer control register F
TCSRF: Timer control/status register F
TCFH:
8-bit timer counter FH
TCFL:
8-bit timer counter FL
OCRFH: Output compare register FH
OCRFL: Output compare register FL
IRRTFH: Timer FH interrupt request flag
IRRTFL: Timer FL interrupt request flag
PSS:
Prescaler S
Figure 9.3 Block Diagram of Timer F
Rev. 8.00 Mar. 09, 2010 Page 264 of 658
REJ09B0042-0800
Section 9 Timers
Pin Configuration
Table 9.7 shows the timer F pin configuration.
Table 9.7
Pin Configuration
Name
Abbr.
I/O
Function
Timer F event input
TMIF
Input
Event input pin for input to TCFL
Timer FH output
TMOFH
Output
Timer FH toggle output pin
Timer FL output
TMOFL
Output
Timer FL toggle output pin
Register Configuration
Table 9.8 shows the register configuration of timer F.
Table 9.8
Timer F Registers
Name
Abbr.
R/W
Initial Value
Address
Timer control register F
TCRF
W
H'00
H'FFB6
Timer control/status register F
TCSRF
R/W
H'00
H'FFB7
8-bit timer counter FH
TCFH
R/W
H'00
H'FFB8
8-bit timer counter FL
TCFL
R/W
H'00
H'FFB9
Output compare register FH
OCRFH
R/W
H'FF
H'FFBA
Output compare register FL
OCRFL
R/W
H'FF
H'FFBB
Clock stop register 1
CKSTPR1
R/W
H'FF
H'FFFA
Rev. 8.00 Mar. 09, 2010 Page 265 of 658
REJ09B0042-0800
Section 9 Timers
9.4.2
Register Descriptions
16-bit Timer Counter (TCF)
8-bit Timer Counter (TCFH)
8-bit Timer Counter (TCFL)
TCF
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write:
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCFH
TCFL
TCF is a 16-bit read/write up-counter configured by cascaded connection of 8-bit timer counters
TCFH and TCFL. In addition to the use of TCF as a 16-bit counter with TCFH as the upper 8 bits
and TCFL as the lower 8 bits, TCFH and TCFL can also be used as independent 8-bit counters.
TCFH and TCFL can be read and written by the CPU, but when they are used in 16-bit mode, data
transfer to and from the CPU is performed via a temporary register (TEMP). For details of TEMP,
see section 9.4.3, CPU Interface.
TCFH and TCFL are each initialized to H'00 upon reset.
a. 16-bit mode (TCF)
When CKSH2 is cleared to 0 in TCRF, TCF operates as a 16-bit counter. The TCF input clock
is selected by bits CKSL2 to CKSL0 in TCRF.
TCF can be cleared in the event of a compare match by means of CCLRH in TCSRF.
When TCF overflows from H'FFFF to H'0000, OVFH is set to 1 in TCSRF. If OVIEH in
TCSRF is 1 at this time, IRRTFH is set to 1 in IRR2, and if IENTFH in IENR2 is 1, an
interrupt request is sent to the CPU.
b. 8-bit mode (TCFL/TCFH)
When CKSH2 is set to 1 in TCRF, TCFH, and TCFL operate as two independent 8-bit
counters. The TCFH (TCFL) input clock is selected by bits CKSH2 to CKSH0 (CKSL2 to
CKSL0) in TCRF.
TCFH (TCFL) can be cleared in the event of a compare match by means of CCLRH (CCLRL)
in TCSRF.
When TCFH (TCFL) overflows from H'FF to H'00, OVFH (OVFL) is set to 1 in TCSRF. If
OVIEH (OVIEL) in TCSRF is 1 at this time, IRRTFH (IRRTFL) is set to 1 in IRR2, and if
IENTFH (IENTFL) in IENR2 is 1, an interrupt request is sent to the CPU.
Rev. 8.00 Mar. 09, 2010 Page 266 of 658
REJ09B0042-0800
Section 9 Timers
16-bit Output Compare Register (OCRF)
8-bit Output Compare Register (OCRFH)
8-bit Output Compare Register (OCRFL)
OCRF
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write:
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
OCRFH
OCRFL
OCRF is a 16-bit read/write register composed of the two registers OCRFH and OCRFL. In
addition to the use of OCRF as a 16-bit register with OCRFH as the upper 8 bits and OCRFL as
the lower 8 bits, OCRFH and OCRFL can also be used as independent 8-bit registers.
OCRFH and OCRFL can be read and written by the CPU, but when they are used in 16-bit mode,
data transfer to and from the CPU is performed via a temporary register (TEMP). For details of
TEMP, see section 9.4.3, CPU Interface.
OCRFH and OCRFL are each initialized to H'FF upon reset.
a. 16-bit mode (OCRF)
When CKSH2 is cleared to 0 in TCRF, OCRF operates as a 16-bit register. OCRF contents
are constantly compared with TCF, and when both values match, CMFH is set to 1 in TCSRF.
At the same time, IRRTFH is set to 1 in IRR2. If IENTFH in IENR2 is 1 at this time, an
interrupt request is sent to the CPU.
Toggle output can be provided from the TMOFH pin by means of compare matches, and the
output level can be set (high or low) by means of TOLH in TCRF.
b. 8-bit mode (OCRFH/OCRFL)
When CKSH2 is set to 1 in TCRF, OCRFH, and OCRFL operate as two independent 8-bit
registers. OCRFH contents are compared with TCFH, and OCRFL contents are with TCFL.
When the OCRFH (OCRFL) and TCFH (TCFL) values match, CMFH (CMFL) is set to 1 in
TCSRF. At the same time, IRRTFH (IRRTFL) is set to 1 in IRR2. If IENTFH (IENTFL) in
IENR2 is 1 at this time, an interrupt request is sent to the CPU.
Toggle output can be provided from the TMOFH pin (TMOFL pin) by means of compare
matches, and the output level can be set (high or low) by means of TOLH (TOLL) in TCRF.
Rev. 8.00 Mar. 09, 2010 Page 267 of 658
REJ09B0042-0800
Section 9 Timers
Timer Control Register F (TCRF)
Bit:
7
6
5
4
3
2
1
0
TOLH
CKSH2
CKSH1
CKSH0
TOLL
CKSL2
CKSL1
CKSL0
Initial value:
0
0
0
0
0
0
0
0
Read/Write:
W
W
W
W
W
W
W
W
TCRF is an 8-bit write-only register that switches between 16-bit mode and 8-bit mode, selects the
input clock from among four internal clock sources or external event input, and sets the output
level of the TMOFH and TMOFL pins.
TCRF is initialized to H'00 upon reset.
Bit 7—Toggle Output Level H (TOLH)
Bit 7 sets the TMOFH pin output level. The output level is effective immediately after this bit is
written.
Bit 7
TOLH
Description
0
Low level
1
High level
(initial value)
Bits 6 to 4—Clock Select H (CKSH2 to CKSH0)
Bits 6 to 4 select the clock input to TCFH from among four internal clock sources or TCFL
overflow.
Bit 6
CKSH2
Bit 5
CKSH1
Bit 4
CKSH0
Description
16-bit mode, counting on TCFL overflow signal
0
0
0
0
0
1
0
1
0
0
1
1
Use prohibited
1
0
0
Internal clock: counting on φ/32
1
0
1
Internal clock: counting on φ/16
1
1
0
Internal clock: counting on φ/4
1
1
1
Internal clock: counting on φw/4
Rev. 8.00 Mar. 09, 2010 Page 268 of 658
REJ09B0042-0800
(initial value)
Section 9 Timers
Bit 3—Toggle Output Level L (TOLL)
Bit 3 sets the TMOFL pin output level. The output level is effective immediately after this bit is
written.
Bit 3
TOLL
Description
0
Low level
1
High level
(initial value)
Bits 2 to 0—Clock Select L (CKSL2 to CKSL0)
Bits 2 to 0 select the clock input to TCFL from among four internal clock sources or external
event input.
Bit 2
CKSL2
Bit 1
CKSL1
Bit 0
CKSL0
0
0
0
0
0
1
0
1
0
0
1
1
Use prohibited
1
0
0
Internal clock: counting on φ/32
1
0
1
Internal clock: counting on φ/16
1
1
0
Internal clock: counting on φ/4
1
1
1
Internal clock: counting on φw/4
Description
Counting on external event (TMIF) rising/falling edge*
(initial value)
Note: * External event edge selection is set by IEG3 in the IRQ edge select register (IEGR). For
details, see IRQ Edge Select Register (IEGR) in section 3.3.2, Interrupt Control Registers.
Note that the timer F counter may increment if the setting of IRQ3 in port mode register 1
(PMR1) is changed from 0 to 1 or from 1 to 0 while the TMIF pin is low in order to change
the TMIF pin function.
Rev. 8.00 Mar. 09, 2010 Page 269 of 658
REJ09B0042-0800
Section 9 Timers
Timer Control/Status Register F (TCSRF)
Bit:
7
6
5
4
3
2
1
0
OVFH
CMFH
OVIEH
CCLRH
OVFL
CMFL
OVIEL
CCLRL
Initial value:
0
0
0
0
0
0
0
0
Read/Write:
R/(W)*
R/(W)*
R/W
R/W
R/(W)*
R/(W)*
R/W
R/W
Note: * Bits 7, 6, 3, and 2 can only be written with 0, for flag clearing.
TCSRF is an 8-bit read/write register that performs counter clear selection, overflow flag setting,
and compare match flag setting, and controls enabling of overflow interrupt requests.
TCSRF is initialized to H'00 upon reset.
Bit 7—Timer Overflow Flag H (OVFH)
Bit 7 is a status flag indicating that TCFH has overflowed from H'FF to H'00. This flag is set by
hardware and cleared by software. It cannot be set by software.
Bit 7
OVFH
Description
0
Clearing condition:
After reading OVFH = 1, cleared by writing 0 to OVFH
1
Setting condition:
Set when TCFH overflows from H’FF to H’00
(initial value)
Bit 6—Compare Match Flag H (CMFH)
Bit 6 is a status flag indicating that TCFH has matched OCRFH. This flag is set by hardware and
cleared by software. It cannot be set by software.
Bit 6
CMFH
Description
0
Clearing condition:
After reading CMFH = 1, cleared by writing 0 to CMFH
1
Setting condition:
Set when the TCFH value matches the OCRFH value
Rev. 8.00 Mar. 09, 2010 Page 270 of 658
REJ09B0042-0800
(initial value)
Section 9 Timers
Bit 5—Timer Overflow Interrupt Enable H (OVIEH)
Bit 5 selects enabling or disabling of interrupt generation when TCFH overflows.
Bit 5
OVIEH
Description
0
TCFH overflow interrupt request is disabled
1
TCFH overflow interrupt request is enabled
(initial value)
Bit 4—Counter Clear H (CCLRH)
In 16-bit mode, bit 4 selects whether TCF is cleared when TCF and OCRF match.
In 8-bit mode, bit 4 selects whether TCFH is cleared when TCFH and OCRFH match.
Bit 4
CCLRH
Description
0
16-bit mode: TCF clearing by compare match is disabled
8-bit mode: TCFH clearing by compare match is disabled
1
16-bit mode: TCF clearing by compare match is enabled
8-bit mode: TCFH clearing by compare match is enabled
(initial value)
Bit 3—Timer Overflow Flag L (OVFL)
Bit 3 is a status flag indicating that TCFL has overflowed from H'FF to H'00. This flag is set by
hardware and cleared by software. It cannot be set by software.
Bit 3
OVFL
Description
0
Clearing condition:
After reading OVFL = 1, cleared by writing 0 to OVFL
1
Setting condition:
Set when TCFL overflows from H’FF to H’00
(initial value)
Rev. 8.00 Mar. 09, 2010 Page 271 of 658
REJ09B0042-0800
Section 9 Timers
Bit 2—Compare Match Flag L (CMFL)
Bit 2 is a status flag indicating that TCFL has matched OCRFL. This flag is set by hardware and
cleared by software. It cannot be set by software.
Bit 2
CMFL
Description
0
Clearing condition:
After reading CMFL = 1, cleared by writing 0 to CMFL
1
Setting condition:
Set when the TCFL value matches the OCRFL value
(initial value)
Bit 1—Timer Overflow Interrupt Enable L (OVIEL)
Bit 1 selects enabling or disabling of interrupt generation when TCFL overflows.
Bit 1
OVIEL
Description
0
TCFL overflow interrupt request is disabled
1
TCFL overflow interrupt request is enabled
(initial value)
Bit 0—Counter Clear L (CCLRL)
Bit 0 selects whether TCFL is cleared when TCFL and OCRFL match.
Bit 0
CCLRL
Description
0
TCFL clearing by compare match is disabled
1
TCFL clearing by compare match is enabled
Rev. 8.00 Mar. 09, 2010 Page 272 of 658
REJ09B0042-0800
(initial value)
Section 9 Timers
Clock Stop Register 1 (CKSTPR1)
7
6
⎯
⎯
Initial value:
1
1
1
1
1
1
1
1
Read/Write:
⎯
⎯
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
5
4
3
2
1
0
S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer F is described here. For details of the other bits, see the
sections on the relevant modules.
Bit 2—Timer F Module Standby Mode Control (TFCKSTP)
Bit 2 controls setting and clearing of module standby mode for timer F.
TFCKSTP
Description
0
Timer F is set to module standby mode
1
Timer F module standby mode is cleared
9.4.3
(initial value)
CPU Interface
TCF and OCRF are 16-bit read/write registers, but the CPU is connected to the on-chip peripheral
modules by an 8-bit data bus. When the CPU accesses these registers, it therefore uses an 8-bit
temporary register (TEMP).
When performing TCF read/write access or OCRF write access in 16-bit mode, data will not be
transferred correctly if only the upper byte or only the lower byte is accessed. Access must be
performed for all 16 bits (using two consecutive byte-size MOV instructions), and the upper byte
must be accessed before the lower byte.
In 8-bit mode, there are no restrictions on the order of access.
Write Access
Write access to the upper byte results in transfer of the upper-byte write data to TEMP. Next,
write access to the lower byte results in transfer of the data in TEMP to the upper register byte,
and direct transfer of the lower-byte write data to the lower register byte.
Rev. 8.00 Mar. 09, 2010 Page 273 of 658
REJ09B0042-0800
Section 9 Timers
Figure 9.4 shows an example in which H'AA55 is written to TCF.
Write to upper byte
CPU
(H'AA)
Module data bus
Bus
interface
TEMP
(H'AA)
TCFH
(
)
TCFL
(
)
Write to lower byte
CPU
(H'55)
Module data bus
Bus
interface
TEMP
(H'AA)
TCFH
(H'AA)
TCFL
(H'55)
Figure 9.4 Write Access to TCF (CPU → TCF)
Rev. 8.00 Mar. 09, 2010 Page 274 of 658
REJ09B0042-0800
Section 9 Timers
Read Access
In access to TCF, when the upper byte is read the upper-byte data is transferred directly to the
CPU and the lower-byte data is transferred to TEMP. Next, when the lower byte is read, the
lower-byte data in TEMP is transferred to the CPU.
In access to OCRF, when the upper byte is read the upper-byte data is transferred directly to the
CPU. When the lower byte is read, the lower-byte data is transferred directly to the CPU.
Figure 9.5 shows an example in which TCF is read when it contains H'AAFF.
Read upper byte
CPU
(H'AA)
Module data bus
Bus
interface
TEMP
(H'FF)
TCFH
(H'AA)
TCFL
(H'FF)
Read lower byte
CPU
(H'FF)
Module data bus
Bus
interface
TEMP
(H'FF)
TCFH
(AB)*
TCFL
(00)*
Note: * H'AB00 if counter has been updated once.
Figure 9.5 Read Access to TCF (TCF → CPU)
Rev. 8.00 Mar. 09, 2010 Page 275 of 658
REJ09B0042-0800
Section 9 Timers
9.4.4
Operation
Timer F is a 16-bit counter that increments on each input clock pulse. The timer F value is
constantly compared with the value set in output compare register F, and the counter can be
cleared, an interrupt requested, or port output toggled, when the two values match. Timer F can
also function as two independent 8-bit timers.
Timer F Operation
Timer F has two operating modes, 16-bit timer mode and 8-bit timer mode. The operation in each
of these modes is described below.
a. Operation in 16-bit timer mode
When CKSH2 is cleared to 0 in timer control register F (TCRF), timer F operates as a 16-bit
timer.
Following a reset, timer counter F (TCF) is initialized to H'0000, output compare register F
(OCRF) to H'FFFF, and timer control register F (TCRF) and timer control/status register F
(TCSRF) to H'00. The counter starts incrementing on external event (TMIF) input. The
external event edge selection is set by IEG3 in the IRQ edge select register (IEGR).
The timer F operating clock can be selected from three internal clocks output by prescaler S or
an external clock by means of bits CKSL2 to CKSL0 in TCRF.
OCRF contents are constantly compared with TCF, and when both values match, CMFH is set
to 1 in TCSRF. If IENTFH in IENR2 is 1 at this time, an interrupt request is sent to the CPU,
and at the same time, TMOFH pin output is toggled. If CCLRH in TCSRF is 1, TCF is
cleared. TMOFH pin output can also be set by TOLH in TCRF.
When TCF overflows from H'FFFF to H'0000, OVFH is set to 1 in TCSRF. If OVIEH in
TCSRF and IENTFH in IENR2 are both 1, an interrupt request is sent to the CPU.
b. Operation in 8-bit timer mode
When CKSH2 is set to 1 in TCRF, TCF operates as two independent 8-bit timers, TCFH and
TCFL. The TCFH/TCFL input clock is selected by CKSH2 to CKSH0/CKSL2 to CKSL0 in
TCRF.
When the OCRFH/OCRFL and TCFH/TCFL values match, CMFH/CMFL is set to 1 in
TCSRF. If IENTFH/IENTFL in IENR2 is 1, an interrupt request is sent to the CPU, and at the
same time, TMOFH pin/TMOFL pin output is toggled. If CCLRH/CCLRL in TCSRF is 1,
TCFH/TCFL is cleared. TMOFH pin/TMOFL pin output can also be set by TOLH/TOLL in
TCRF.
When TCFH/TCFL overflows from H'FF to H'00, OVFH/OVFL is set to 1 in TCSRF. If
OVIEH/OVIEL in TCSRF and IENTFH/IENTFL in IENR2 are both 1, an interrupt request is
sent to the CPU.
Rev. 8.00 Mar. 09, 2010 Page 276 of 658
REJ09B0042-0800
Section 9 Timers
TCF Increment Timing
TCF is incremented by clock input (internal clock or external event input).
a. Internal clock operation
Bits CKSH2 to CKSH0 or CKSL2 to CKSL0 in TCRF select one of four internal clock
sources (φ/32, φ/16, φ/4, or φw/4) created by dividing the system clock (φ or φw).
b. External event operation
External event input is selected by clearing CKSL2 to 0 in TCRF. TCF can increment on
either the rising or falling edge of external event input. External event edge selection is set by
IEG3 in the interrupt controller’s IEGR register. An external event pulse width of at least 2
system clocks (φ) is necessary. Shorter pulses will not be counted correctly.
TMOFH/TMOFL Output Timing
In TMOFH/TMOFL output, the value set in TOLH/TOLL in TCRF is output. The output is
toggled by the occurrence of a compare match. Figure 9.6 shows the output timing.
φ
TMIF
(when IEG3 = 1)
Count input
clock
TCF
OCRF
N
N+1
N
N
N+1
N
Compare match
signal
TMOFH TMOFL
Figure 9.6 TMOFH/TMOFL Output Timing
Rev. 8.00 Mar. 09, 2010 Page 277 of 658
REJ09B0042-0800
Section 9 Timers
TCF Clear Timing
TCF can be cleared by a compare match with OCRF.
Timer Overflow Flag (OVF) Set Timing
OVF is set to 1 when TCF overflows from H'FFFF to H'0000.
Compare Match Flag Set Timing
The compare match flag (CMFH or CMFL) is set to 1 when the TCF and OCRF values match.
The compare match signal is generated in the last state during which the values match (when TCF
is updated from the matching value to a new value). When TCF matches OCRF, the compare
match signal is not generated until the next counter clock.
Timer F Operation Modes
Timer F operation modes are shown in table 9.9.
Table 9.9
Timer F Operation Modes
Sleep
Watch
Subactive
Subsleep
Standby
Module
Standby
Operation Mode
Reset
Active
TCF
Reset
Functions Functions Functions/ Functions/ Functions/ Halted
Halted*
Halted*
Halted*
Halted
OCRF
Reset
Functions Held
Held
Functions
Held
Held
Held
TCRF
Reset
Functions Held
Held
Functions
Held
Held
Held
TCSRF
Reset
Functions Held
Held
Functions
Held
Held
Held
Note: * When φw/4 is selected as the TCF internal clock in active mode or sleep mode, since the
system clock and internal clock are mutually asynchronous, synchronization is maintained
by a synchronization circuit. This results in a maximum count cycle error of 1/φ (s). When
the counter is operated in subactive mode, watch mode, or subsleep mode, φw/4 must be
selected as the internal clock. The counter will not operate if any other internal clock is
selected.
Rev. 8.00 Mar. 09, 2010 Page 278 of 658
REJ09B0042-0800
Section 9 Timers
9.4.5
Application Notes
The following types of contention and operation can occur when timer F is used.
16-bit Timer Mode
In toggle output, TMOFH pin output is toggled when all 16 bits match and a compare match
signal is generated. If a TCRF write by a MOV instruction and generation of the compare match
signal occur simultaneously, TOLH data is output to the TMOFH pin as a result of the TCRF
write. TMOFL pin output is unstable in 16-bit mode, and should not be used; the TMOFL pin
should be used as a port pin.
If an OCRFL write and compare match signal generation occur simultaneously, the compare
match signal is invalid. However, if the written data and the counter value match, a compare
match signal will be generated at that point. As the compare match signal is output in
synchronization with the TCFL clock, a compare match will not result in compare match signal
generation if the clock is stopped.
Compare match flag CMFH is set when all 16 bits match and a compare match signal is generated.
Compare match flag CMFL is set if the setting conditions for the lower 8 bits are satisfied.
When TCF overflows, OVFH is set. OVFL is set if the setting conditions are satisfied when the
lower 8 bits overflow. If a TCFL write and overflow signal output occur simultaneously, the
overflow signal is not output.
8-bit Timer Mode
a. TCFH, OCRFH
In toggle output, TMOFH pin output is toggled when a compare match occurs. If a TCRF
write by a MOV instruction and generation of the compare match signal occur simultaneously,
TOLH data is output to the TMOFH pin as a result of the TCRF write.
If an OCRFH write and compare match signal generation occur simultaneously, the compare
match signal is invalid. However, if the written data and the counter value match, a compare
match signal will be generated at that point. The compare match signal is output in
synchronization with the TCFH clock.
If a TCFH write and overflow signal output occur simultaneously, the overflow signal is not
output.
Rev. 8.00 Mar. 09, 2010 Page 279 of 658
REJ09B0042-0800
Section 9 Timers
b. TCFL, OCRFL
In toggle output, TMOFL pin output is toggled when a compare match occurs. If a TCRF
write by a MOV instruction and generation of the compare match signal occur simultaneously,
TOLL data is output to the TMOFL pin as a result of the TCRF write.
If an OCRFL write and compare match signal generation occur simultaneously, the compare
match signal is invalid. However, if the written data and the counter value match, a compare
match signal will be generated at that point. As the compare match signal is output in
synchronization with the TCFL clock, a compare match will not result in compare match
signal generation if the clock is stopped.
If a TCFL write and overflow signal output occur simultaneously, the overflow signal is not
output.
Clear Timer FH, Timer FL Interrupt Request Flags (IRRTFH, IRRTFL), Timer Overflow
Flags H, L (OVFH, OVFL) and Compare Match Flags H, L (CMFH, CMFL)
When φw/4 is selected as the internal clock, “Interrupt factor generation signal” will be operated
with φw and the signal will be outputted with φw width. And, “Overflow signal” and “Compare
match signal” are controlled with 2 cycles of φw signals. Those signals are outputted with 2 cycles
width of φw (figure 9.7)
In active (high-speed, medium-speed) mode, even if you cleared interrupt request flag during the
term of validity of “Interrupt factor generation signal”, same interrupt request flag is set. (figure
9.7 (1)) And, you cannot be cleared timer overflow flag and compare match flag during the term
of validity of “Overflow signal” and “Compare match signal”.
For interrupt request flag is set right after interrupt request is cleared, interrupt process to one time
timer FH, timer FL interrupt might be repeated. (figure 9.7 (2)) Therefore, to definitely clear
interrupt request flag in active (high-speed, medium-speed) mode, clear should be processed after
the time that calculated with below (1) formula. And, to definitely clear timer overflow flag and
compare match flag, clear should be processed after read timer control status register F (TCSRF)
after the time that calculated with below (1) formula. For ST of (1) formula, please substitute the
longest number of execution states in used instruction. (10 states of RTE instruction when
MULXU, DIVXU instruction is not used, 14 states when MULXU, DIVXU instruction is used) In
subactive mode, there are not limitation for interrupt request flag, timer overflow flag, and
compare match flag clear.
Rev. 8.00 Mar. 09, 2010 Page 280 of 658
REJ09B0042-0800
Section 9 Timers
The term of validity of “Interrupt factor generation signal”
= 1 cycle of φw + waiting time for completion of executing instruction
+ interrupt time synchronized with φ = 1/φw + ST × (1/φ) + (2/φ) (second).....(1)
ST: Executing number of execution states
Method 1 is recommended to operate for time efficiency.
Method 1
1. Prohibit interrupt in interrupt handling routine (set IENFH, IENFL to 0).
2. After program process returned normal handling, clear interrupt request flags (IRRTFH,
IRRTFL) after more than that calculated with (1) formula.
3. After read timer control status register F (TCSRF), clear timer overflow flags (OVFH,
OVFL) and compare match flags (CMFH, CMFL).
4. Operate interrupt permission (set IENFH, IENFL to 1).
Method 2
1. Set interrupt handling routine time to more than time that calculated with (1) formula.
2. Clear interrupt request flags (IRRTFH, IRRTFL) at the end of interrupt handling routine.
3. After read timer control status register F (TCSRF), clear timer overflow flags (OVFH,
OVFL) and compare match flags (CMFH, CMFL).
All above attentions are also applied in 16-bit mode and 8-bit mode.
Rev. 8.00 Mar. 09, 2010 Page 281 of 658
REJ09B0042-0800
Section 9 Timers
Interrupt request
flag clear
Interrupt request
flag clear
(2)
Program process
Interrupt
Interrupt
Normal
φW
Interrupt factor
generation signal
(Internal signal,
nega-active)
Overflow signal,
Compare match signal
(Internal signal,
nega-active)
Interrupt request flag
(IRRTFH, IRRTFL)
(1)
Figure 9.7 Clear Interrupt Request Flag when Interrupt Factor Generation Signal is Valid
Timer Counter (TCF) Read/Write
When φw/4 is selected as the internal clock in active (high-speed, medium-speed) mode, write on
TCF is impossible. And, when read TCF, as the system clock and internal clock are mutually
asynchronous, TCF synchronizes with synchronization circuit. This results in a maximum TCF
read value error of ±1.
When read/write TCF in active (high-speed, medium-speed) mode is needed, please select internal
clock except for φw/4 before read/write.
In subactive mode, even φw/4 is selected as the internal clock, normal read/write TCF is possible.
Rev. 8.00 Mar. 09, 2010 Page 282 of 658
REJ09B0042-0800
Section 9 Timers
9.5
Timer G
9.5.1
Overview
Timer G is an 8-bit timer with dedicated input capture functions for the rising/falling edges of
pulses input from the input capture input pin (input capture input signal). High-frequency
component noise in the input capture input signal can be eliminated by a noise canceler, enabling
accurate measurement of the input capture input signal duty cycle. If input capture input is not set,
timer G functions as an 8-bit interval timer.
Features
Features of timer G are given below.
• Choice of four internal clock sources (φ/64, φ/32, φ/2, φw/4)
• Dedicated input capture functions for rising and falling edges
• Level detection at counter overflow
It is possible to detect whether overflow occurred when the input capture input signal was high
or when it was low.
• Selection of whether or not the counter value is to be cleared at the input capture input signal
rising edge, falling edge, or both edges
• Two interrupt sources: one input capture, one overflow. The input capture input signal rising
or falling edge can be selected as the interrupt source.
• A built-in noise canceler eliminates high-frequency component noise in the input capture input
signal.
• Watch mode, subactive mode, or subsleep mode operation is possible when φw/4 is selected as
the internal clock.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
Rev. 8.00 Mar. 09, 2010 Page 283 of 658
REJ09B0042-0800
Section 9 Timers
Block Diagram
Figure 9.8 shows a block diagram of timer G.
φ
PSS
Level
detector
φW/4
ICRGF
TMIG
Noise
canceler
Edge
detector
NCS
Internal data bus
TMG
TCG
ICRGR
IRRTG
[Legend]
TMG:
TCG:
ICRGF:
ICRGR:
IRRTG:
NCS:
PSS:
Timer mode register G
Timer counter G
Input capture register GF
Input capture register GR
Timer G interrupt request flag
Noise canceler select
Prescaler S
Figure 9.8 Block Diagram of Timer G
Pin Configuration
Table 9.10 shows the timer G pin configuration.
Table 9.10 Pin Configuration
Name
Abbr.
I/O
Function
Input capture input
TMIG
Input
Input capture input pin
Rev. 8.00 Mar. 09, 2010 Page 284 of 658
REJ09B0042-0800
Section 9 Timers
Register Configuration
Table 9.11 shows the register configuration of timer G.
Table 9.11 Timer G Registers
Name
Abbr.
R/W
Initial Value
Address
Timer control register G
TMG
R/W
H'00
H'FFBC
Timer counter G
TCG
—
H'00
—
Input capture register GF
ICRGF
R
H'00
H'FFBD
Input capture register GR
ICRGR
R
H'00
H'FFBE
Clock stop register 1
CKSTPR1
R/W
H'FF
H'FFFA
9.5.2
Register Descriptions
Timer Counter G (TCG)
7
6
5
4
3
2
1
0
TCG7
TCG6
TCG5
TCG4
TCG3
TCG2
TCG1
TCG0
Initial value:
0
0
0
0
0
0
0
0
Read/Write:
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Bit:
TCG is an 8-bit up-counter which is incremented by clock input. The input clock is selected by
bits CKS1 and CKS0 in TMG.
TMIG in PMR1 is set to 1 to operate TCG as an input capture timer, or cleared to 0 to operate
TCG as an interval timer*. In input capture timer operation, the TCG value can be cleared by the
rising edge, falling edge, or both edges of the input capture input signal, according to the setting
made in TMG.
When TCG overflows from H'FF to H'00, if OVIE in TMG is 1, IRRTG in IRR2 is set to 1, and if
IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see section 3.3, Interrupts.
TCG cannot be read or written by the CPU. It is initialized to H'00 upon reset.
Note: * An input capture signal may be generated when TMIG is modified.
Rev. 8.00 Mar. 09, 2010 Page 285 of 658
REJ09B0042-0800
Section 9 Timers
Input Capture Register GF (ICRGF)
Bit:
7
6
5
4
3
2
1
0
ICRGF7
ICRGF6
ICRGF5
ICRGF4
ICRGF3
ICRGF2
ICRGF1
ICRGF0
Initial value:
0
0
0
0
0
0
0
0
Read/Write:
R
R
R
R
R
R
R
R
ICRGF is an 8-bit read-only register. When a falling edge of the input capture input signal is
detected, the current TCG value is transferred to ICRGF. If IIEGS in TMG is 1 at this time,
IRRTG in IRR2 is set to 1, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see section 3.3, Interrupts.
To ensure dependable input capture operation, the pulse width of the input capture input signal
must be at least 2φ or 2φSUB (when the noise canceler is not used).
ICRGF is initialized to H'00 upon reset.
Input Capture Register GR (ICRGR)
7
6
5
4
3
2
1
0
ICRGR7
ICRGR6
ICRGR5
ICRGR4
ICRGR3
ICRGR2
ICRGR1
ICRGR0
Initial value:
0
0
0
0
0
0
0
0
Read/Write:
R
R
R
R
R
R
R
R
Bit:
ICRGR is an 8-bit read-only register. When a rising edge of the input capture input signal is
detected, the current TCG value is transferred to ICRGR. If IIEGS in TMG is 0 at this time,
IRRTG in IRR2 is set to 1, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see section 3.3, Interrupts.
To ensure dependable input capture operation, the pulse width of the input capture input signal
must be at least 2φ or 2φSUB (when the noise canceler is not used).
ICRGR is initialized to H'00 upon reset.
Rev. 8.00 Mar. 09, 2010 Page 286 of 658
REJ09B0042-0800
Section 9 Timers
Timer Mode Register G (TMG)
Bit:
Initial value:
Read/Write:
7
6
5
4
3
2
1
0
OVFH
OVFL
OVIE
IIEGS
CCLR1
CCLR0
CKS1
CKS0
0
R/(W)*
0
R/(W)*
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Note: * Bits 7 and 6 can only be written with 0, for flag clearing.
TMG is an 8-bit read/write register that performs TCG clock selection from four internal clock
sources, counter clear selection, and edge selection for the input capture input signal interrupt
request, controls enabling of overflow interrupt requests, and also contains the overflow flags.
TMG is initialized to H'00 upon reset.
Bit 7—Timer Overflow Flag H (OVFH)
Bit 7 is a status flag indicating that TCG has overflowed from H'FF to H'00 when the input capture
input signal is high. This flag is set by hardware and cleared by software. It cannot be set by
software.
Bit 7
OVFH
0
1
Description
Clearing condition:
After reading OVFH = 1, cleared by writing 0 to OVFH
(initial value)
Setting condition:
Set when input capture input signal is high level and TCG overflows from H'FF to H'00
Bit 6—Timer Overflow Flag L (OVFL)
Bit 6 is a status flag indicating that TCG has overflowed from H'FF to H'00 when the input capture
input signal is low, or in interval operation. This flag is set by hardware and cleared by software.
It cannot be set by software.
Bit 6
OVFL
0
1
Description
Clearing condition:
After reading OVFL = 1, cleared by writing 0 to OVFL
(initial value)
Setting condition:
Set when TCG overflows from H'FF to H'00 while input capture input signal is high
level or during interval operation
Rev. 8.00 Mar. 09, 2010 Page 287 of 658
REJ09B0042-0800
Section 9 Timers
Bit 5—Timer Overflow Interrupt Enable (OVIE)
Bit 5 selects enabling or disabling of interrupt generation when TCG overflows.
Bit 5
OVIE
Description
0
TCG overflow interrupt request is disabled
1
TCG overflow interrupt request is enabled
(initial value)
Bit 4—Input Capture Interrupt Edge Select (IIEGS)
Bit 4 selects the input capture input signal edge that generates an interrupt request.
Bit 4
IIEGS
Description
0
Interrupt generated on rising edge of input capture input signal
1
Interrupt generated on falling edge of input capture input signal
(initial value)
Bits 3 and 2—Counter Clear 1 and 0 (CCLR1, CCLR0)
Bits 3 and 2 specify whether or not TCG is cleared by the rising edge, falling edge, or both edges
of the input capture input signal.
Bit 3
CCLR1
Bit 2
CCLR0
Description
0
0
TCG clearing is disabled
0
1
TCG cleared by falling edge of input capture input signal
1
0
TCG cleared by rising edge of input capture input signal
1
1
TCG cleared by both edges of input capture input signal
Rev. 8.00 Mar. 09, 2010 Page 288 of 658
REJ09B0042-0800
(initial value)
Section 9 Timers
Bits 1 and 0—Clock Select (CKS1, CKS0)
Bits 1 and 0 select the clock input to TCG from among four internal clock sources.
Bit 1
CKS1
Bit 0
CKS0
Description
0
0
Internal clock: counting on φ/64
0
1
Internal clock: counting on φ/32
1
0
Internal clock: counting on φ/2
1
1
Internal clock: counting on φw/4
(initial value)
Clock Stop Register 1 (CKSTPR1)
Bit:
7
6
⎯
⎯
5
4
3
2
1
0
S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
Initial value:
1
1
1
1
1
1
1
1
Read/Write:
⎯
⎯
R/W
R/W
R/W
R/W
R/W
R/W
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer G is described here. For details of the other bits, see the
sections on the relevant modules.
Bit 3—Timer G Module Standby Mode Control (TGCKSTP)
Bit 3 controls setting and clearing of module standby mode for timer G.
TGCKSTP
Description
0
Timer G is set to module standby mode
1
Timer G module standby mode is cleared
(initial value)
Rev. 8.00 Mar. 09, 2010 Page 289 of 658
REJ09B0042-0800
Section 9 Timers
9.5.3
Noise Canceler
The noise canceler consists of a digital low-pass filter that eliminates high-frequency component
noise from the pulses input from the input capture input pin. The noise canceler is set by NCS* in
PMR2.
Figure 9.9 shows a block diagram of the noise canceler.
Sampling
clock
C
Input capture
input signal
C
D
Q
D
Latch
Q
Latch
C
D
C
Q
Latch
D
C
Q
Latch
D
Q
Latch
Match
detector
Noise
canceler
output
Δt
Sampling clock
Δt: Set by CKS1 and CKS0
Figure 9.9 Noise Canceler Block Diagram
The noise canceler consists of five latch circuits connected in series and a match detector circuit.
When the noise cancellation function is not used (NCS = 0), the system clock is selected as the
sampling clock. When the noise cancellation function is used (NCS = 1), the sampling clock is the
internal clock selected by CKS1 and CKS0 in TMG, the input capture input is sampled on the
rising edge of this clock, and the data is judged to be correct when all the latch outputs match. If
all the outputs do not match, the previous value is retained. After a reset, the noise canceler output
is initialized when the falling edge of the input capture input signal has been sampled five times.
Therefore, after making a setting for use of the noise cancellation function, a pulse with at least
five times the width of the sampling clock is a dependable input capture signal. Even if noise
cancellation is not used, an input capture input signal pulse width of at least 2φ or 2φSUB is
necessary to ensure that input capture operations are performed properly
Note: * An input capture signal may be generated when the NCS bit is modified.
Figure 9.10 shows an example of noise canceler timing.
Rev. 8.00 Mar. 09, 2010 Page 290 of 658
REJ09B0042-0800
Section 9 Timers
In this example, high-level input of less than five times the width of the sampling clock at the
input capture input pin is eliminated as noise.
Input capture
input signal
Sampling clock
Noise canceler
output
Eliminated as noise
Figure 9.10 Noise Canceler Timing (Example)
Rev. 8.00 Mar. 09, 2010 Page 291 of 658
REJ09B0042-0800
Section 9 Timers
9.5.4
Operation
Timer G is an 8-bit timer with built-in input capture and interval functions.
Timer G Functions
Timer G is an 8-bit up-counter with two functions, an input capture timer function and an interval
timer function.
The operation of these two functions is described below.
a. Input capture timer operation
When the TMIG bit in port mode register 1 (PMR1) is set to 1, timer G functions as an input
capture timer*.
In a reset, timer mode register G (TMG), timer counter G (TCG), input capture register GF
(ICRGF), and input capture register GR (ICRGR) are all initialized to H'00.
Following a reset, TCG starts counting on the φ/64 internal clock.
The input clock can be selected from four internal clock sources by bits CKS1 and CKS0 in
TMG.
When a rising edge/falling edge is detected in the input capture signal input from the TMIG
pin, the TCG value at that time is transferred to ICRGR/ICRGF. When the edge selected by
IIEGS in TMG is input, IRRTG in IRR2 is set to 1, and if the IENTG bit in IENR2 is 1 at this
time, an interrupt request is sent to the CPU. For details of the interrupt, see section 3.3,
Interrupts.
TCG can be cleared by a rising edge, falling edge, or both edges of the input capture signal,
according to the setting of bits CCLR1 and CCLR0 in TMG. If TCG overflows when the
input capture signal is high, the OVFH bit in TMG is set; if TCG overflows when the input
capture signal is low, the OVFL bit in TMG is set. If the OVIE bit in TMG is 1 when these
bits are set, IRRTG in IRR2 is set to 1, and if the IENTG bit in IENR2 is 1, timer G sends an
interrupt request to the CPU. For details of the interrupt, see section 3.3, Interrupts.
Timer G has a built-in noise canceler that enables high-frequency component noise to be
eliminated from pulses input from the TMIG pin. For details, see section 9.5.3, Noise
Canceler.
Note: * An input capture signal may be generated when TMIG is modified.
Rev. 8.00 Mar. 09, 2010 Page 292 of 658
REJ09B0042-0800
Section 9 Timers
b. Interval timer operation
When the TMIG bit in PMR1 is cleared to 0, timer G functions as an interval timer.
Following a reset, TCG starts counting on the φ/64 internal clock. The input clock can be
selected from four internal clock sources by bits CKS1 and CKS0 in TMG. TCG increments
on the selected clock, and when it overflows from H'FF to H'00, the OVFL bit in TMG is set
to 1. If the OVIE bit in TMG is 1 at this time, IRRTG in IRR2 is set to 1, and if the IENTG bit
in IENR2 is 1, timer G sends an interrupt request to the CPU. For details of the interrupt, see
section 3.3, Interrupts.
Count Timing
TCG is incremented by internal clock input. Bits CKS1 and CKS0 in TMG select one of four
internal clock sources (φ/64, φ/32, φ/2, or φw/4) created by dividing the system clock (φ) or watch
clock (φw).
Input Capture Input Timing
a. Without noise cancellation function
For input capture input, dedicated input capture functions are provided for rising and falling
edges.
Figure 9.11 shows the timing for rising/falling edge input capture input.
Input capture
input signal
Input capture
signal F
Input capture
signal R
Figure 9.11 Input Capture Input Timing (without Noise Cancellation Function)
Rev. 8.00 Mar. 09, 2010 Page 293 of 658
REJ09B0042-0800
Section 9 Timers
b. With noise cancellation function
When noise cancellation is performed on the input capture input, the passage of the input
capture signal through the noise canceler results in a delay of five sampling clock cycles from
the input capture input signal edge.
Figure 9.12 shows the timing in this case.
Input capture
input signal
Sampling clock
Noise canceler
output
Input capture
signal R
Figure 9.12 Input Capture Input Timing (with Noise Cancellation Function)
Timing of Input Capture by Input Capture Input
Figure 9.13 shows the timing of input capture by input capture input
Input capture
signal
TCG
Input capture
register
N-1
N
H'XX
N+1
N
Figure 9.13 Timing of Input Capture by Input Capture Input
Rev. 8.00 Mar. 09, 2010 Page 294 of 658
REJ09B0042-0800
Section 9 Timers
TCG Clear Timing
TCG can be cleared by the rising edge, falling edge, or both edges of the input capture input
signal.
Figure 9.14 shows the timing for clearing by both edges.
Input capture
input signal
Input capture
signal F
Input capture
signal R
TCG
N
H'00
N
H'00
Figure 9.14 TCG Clear Timing
Rev. 8.00 Mar. 09, 2010 Page 295 of 658
REJ09B0042-0800
Section 9 Timers
Timer G Operation Modes
Timer G operation modes are shown in table 9.12.
Table 9.12 Timer G Operation Modes
Module
Subactive Subsleep Standby Standby
Operation Mode
Reset Active
TCG
Input capture
Reset Functions* Functions* Functions/ Functions/ Functions/ Halted
halted*
halted*
halted*
Halted
Interval
Reset Functions* Functions* Functions/ Functions/ Functions/ Halted
halted*
halted*
halted*
Halted
Sleep
Watch
ICRGF
Reset Functions* Functions* Functions/ Functions/ Functions/ Retained Retained
halted*
halted*
halted*
ICRGR
Reset Functions* Functions* Functions/ Functions/ Functions/ Retained Retained
halted*
halted*
halted*
TMG
Reset Functions Retained
Retained
Functions Retained
Retained Retained
Note: * When φw/4 is selected as the TCG internal clock in active mode or sleep mode, since the
system clock and internal clock are mutually asynchronous, synchronization is maintained
by a synchronization circuit. This results in a maximum count cycle error of 1/φ(s). When
φw/4 is selected as the TCG internal clock in watch mode, TCG and the noise canceler
operate on the φw/4 internal clock without regard to the φSUB subclock (φw/8, φw/4, φw/2).
Note that when another internal clock is selected, TCG and the noise canceler do not
operate, and input of the input capture input signal does not result in input capture.
To operate the timer G in subactive mode or subsleep mode, select φw/4 as the TCG
internal clock and φw/2 as the subclock φSUB. Note that when other internal clock is
selected, or when φw/8 or φw/4 is selected as the subclock φSUB, TCG and the noise
canceler do not operate.
Rev. 8.00 Mar. 09, 2010 Page 296 of 658
REJ09B0042-0800
Section 9 Timers
9.5.5
Application Notes
Internal Clock Switching and TCG Operation
Depending on the timing, TCG may be incremented by a switch between different internal clock
sources. Table 9.13 shows the relation between internal clock switchover timing (by write to bits
CKS1 and CKS0) and TCG operation.
When TCG is internally clocked, an increment pulse is generated on detection of the falling edge
of an internal clock signal, which is divided from the system clock (φ) or subclock (φw). For this
reason, in a case like No. 3 in table 9.13 where the switch is from a high clock signal to a low
clock signal, the switchover is seen as a falling edge, causing TCG to increment.
Table 9.13 Internal Clock Switching and TCG Operation
No.
Clock Levels Before and After
Modifying Bits CKS1 and CKS0
TCG Operation
1
Goes from low level to low level
Clock before
switching
Clock after
switching
Count
clock
TCG
N
N+1
Write to CKS1 and CKS0
2
Goes from low level to high level
Clock before
switching
Clock after
switching
Count
clock
TCG
N
N+1
N+2
Write to CKS1 and CKS0
Rev. 8.00 Mar. 09, 2010 Page 297 of 658
REJ09B0042-0800
Section 9 Timers
No.
Clock Levels Before and After
Modifying Bits CKS1 and CKS0
TCG Operation
3
Goes from high level to low level
Clock before
switching
Clock after
switching
*
Count
clock
TCG
N
N+1
N+2
Write to CKS1 and CKS0
4
Goes from high level to high level
Clock before
switching
Clock after
switching
Count
clock
TCG
N
N+1
N+2
Write to CKS1 and CKS0
Note: * The switchover is seen as a falling edge, and TCG is incremented.
Notes on Port Mode Register Modification
The following points should be noted when a port mode register is modified to switch the input
capture function or the input capture input noise canceler function.
• Switching input capture input pin function
Note that when the pin function is switched by modifying TMIG in port mode register 1
(PMR1), which performs input capture input pin control, an edge will be regarded as having
been input at the pin even though no valid edge has actually been input. Input capture input
signal input edges, and the conditions for their occurrence, are summarized in table 9.14.
Rev. 8.00 Mar. 09, 2010 Page 298 of 658
REJ09B0042-0800
Section 9 Timers
Table 9.14 Input Capture Input Signal Input Edges Due to Input Capture Input Pin
Switching, and Conditions for Their Occurrence
Input Capture Input
Signal Input Edge
Conditions
Generation of rising edge
When TMIG is modified from 0 to 1 while the TMIG pin is high
When NCS is modified from 0 to 1 while the TMIG pin is high, then
TMIG is modified from 0 to 1 before the signal is sampled five times by
the noise canceler
Generation of falling edge
When TMIG is modified from 1 to 0 while the TMIG pin is high
When NCS is modified from 0 to 1 while the TMIG pin is low, then
TMIG is modified from 0 to 1 before the signal is sampled five times by
the noise canceler
When NCS is modified from 0 to 1 while the TMIG pin is high, then
TMIG is modified from 1 to 0 after the signal is sampled five times by
the noise canceler
Note: When the P13 pin is not set as an input capture input pin, the timer G input capture input
signal is low.
• Switching input capture input noise canceler function
When performing noise canceler function switching by modifying NCS in port mode register 2
(PMR2), which controls the input capture input noise canceler, TMIG should first be cleared to
0. Note that if NCS is modified without first clearing TMIG, an edge will be regarded as
having been input at the pin even though no valid edge has actually been input. Input capture
input signal input edges, and the conditions for their occurrence, are summarized in table 9.15.
Table 9.15 Input Capture Input Signal Input Edges Due to Noise Canceler Function
Switching, and Conditions for Their Occurrence
Input Capture Input
Signal Input Edge
Conditions
Generation of rising edge
When the TMIG pin is modified from 0 to 1 while TMIG is 1, then NCS
is modified from 0 to 1 before the signal is sampled five times by the
noise canceler
Generation of falling edge
When the TMIG pin is modified from 1 to 0 while TMIG is 1, then NCS
is modified from 1 to 0 before the signal is sampled five times by the
noise canceler
Rev. 8.00 Mar. 09, 2010 Page 299 of 658
REJ09B0042-0800
Section 9 Timers
When the pin function is switched and an edge is generated in the input capture input signal, if this
edge matches the edge selected by the input capture interrupt select (IIEGS) bit, the interrupt
request flag will be set to 1. The interrupt request flag should therefore be cleared to 0 before use.
Figure 9.15 shows the procedure for port mode register manipulation and interrupt request flag
clearing. When switching the pin function, set the interrupt-disabled state before manipulating the
port mode register, then, after the port mode register operation has been performed, wait for the
time required to confirm the input capture input signal as an input capture signal (at least two
system clocks when the noise canceler is not used; at least five sampling clocks when the noise
canceler is used), before clearing the interrupt enable flag to 0. There are two ways of preventing
interrupt request flag setting when the pin function is switched: by controlling the pin level so that
the conditions shown in tables 9.14 and 9.15 are not satisfied, or by setting the opposite of the
generated edge in the IIEGS bit in TMG.
Set I bit in CCR to 1
Manipulate port mode register
*TMIG confirmation time
Clear interrupt request flag to 0
Clear I bit in CCR to 0
Disable interrupts. (Interrupts can also be disabled by
manipulating the interrupt enable bit in interrupt enable
register 2.)
After manipulating the port mode register, wait for the
TMIG confirmation time* (at least two system clocks when
the noise canceler is not used; at least five sampling
clocks when the noise canceler is used), then clear the
interrupt enable flag to 0.
Enable interrupts
Figure 9.15 Port Mode Register Manipulation and Interrupt Enable Flag Clearing
Procedure
Rev. 8.00 Mar. 09, 2010 Page 300 of 658
REJ09B0042-0800
Section 9 Timers
9.5.6
Timer G Application Example
Using timer G, it is possible to measure the high and low widths of the input capture input signal
as absolute values. For this purpose, CCLR1 and CCLR0 in TMG should both be set to 1.
Figure 9.16 shows an example of the operation in this case.
Input capture
input signal
H'FF
Input capture
register GF
Input capture
register GR
H'00
TCG
Counter cleared
Figure 9.16 Timer G Application Example
Rev. 8.00 Mar. 09, 2010 Page 301 of 658
REJ09B0042-0800
Section 9 Timers
9.6
Watchdog Timer
9.6.1
Overview
The watchdog timer has an 8-bit counter that is incremented by an input clock. If a system
runaway allows the counter value to overflow before being rewritten, the watchdog timer can reset
the chip internally. Note that stabilization times for the H8/38024, H8/38024S, and H8/38024R
Group and for the H8/38124 Group are different.
Features
Features of the watchdog timer are given below.
• Incremented by internal clock source (φ/8192 or φw/32) on the H8/38024, H8/38024S, and
H8/38024R Group.
• On the H8/38124 Group, 10 internal clocks (φ/64, φ/128, φ/256, φ/512, φ/1024, φ/2048,
φ/4096, φ/8192, φw/32, or watchdog on-chip oscillator) are available for selection for use by
the counter.
• A reset signal is generated when the counter overflows. The overflow period can be set from 1
to 256 times the selected clock (from approximately 4 ms to 1,000 ms when φ = 2.00 MHz).
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. See section 5.9, Module Standby Mode, for details.
Rev. 8.00 Mar. 09, 2010 Page 302 of 658
REJ09B0042-0800
Section 9 Timers
Block Diagram
Figures 9.17(1) and 9.17(2) show a block diagram of the watchdog timer.
φ
PSS
φ/8192
TCW
[Legend]
TCSRW: Timer control/status register W
Timer counter W
TCW:
Prescaler S
PSS:
Internal data bus
TCSRW
φW/32
Reset
signal
Figure 9.17(1) Block Diagram of Watchdog Timer
(H8/38024, H8/38024S, H8/38024R Group)
Rev. 8.00 Mar. 09, 2010 Page 303 of 658
REJ09B0042-0800
Section 9 Timers
Watchdog
on-chip
oscillator
φ
Internal data bus
TMW
TCSRW
PSS
TCW
φW/32
Interrupt/reset
controller
[Legend]
TCSRW:
TCW:
TMW:
PSS:
Internal reset signal or
interrupt request signal
Timer control/status register W
Timer counter W
Timer mode register W
Prescaler S
Figure 9.17(2) Block Diagram of Watchdog Timer
(H8/38124 Group)
Register Configuration
Table 9.16 shows the register configuration of the watchdog timer.
Table 9.16 Watchdog Timer Registers
Name
Abbr.
R/W
Initial Value
Address
Timer control/status register W
TCSRW
R/W
H'AA
H'FFB2
Timer counter W
TCW
R/W
H'00
H'FFB3
Timer mode register W *
TMW
R/W
H'FF
H'FFF8
Clock stop register 2
CKSTPR2
R/W
H'FF
H'FFFB
Port mode register 2
PMR2
R/W
H'D8
H'FFC9
Note: * This register is implemented on the H8/38124 Group only.
Rev. 8.00 Mar. 09, 2010 Page 304 of 658
REJ09B0042-0800
Section 9 Timers
9.6.2
Register Descriptions
Timer Control/Status Register W (TCSRW)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
B6WI
TCWE
B4WI
TCSRWE
B2WI
WDON
B0WI
WRST
1
0
1
0
1
0/1*2
1
0
R
(R/W)*1
R
(R/W)*1
R
(R/W)*1
R
(R/W)*1
Notes: 1. Write is enabled only under certain conditions, which are given in the descriptions
of the individual bits.
2. Initial value is 0 on H8/38024, H8/38024S, and H8/38024R Group; initial value
is 1 on H8/38124 Group.
TCSRW is an 8-bit read/write register that controls write access to TCW and TCSRW itself,
controls watchdog timer operations, and indicates operating status.
Bit 7—Bit 6 Write Disable (B6WI)
Bit 7 controls the writing of data to bit 6 in TCSRW.
Bit 7
B6WI
Description
0
Bit 6 is write-enabled
1
Bit 6 is write-protected
(initial value)
This bit is always read as 1. Data written to this bit is not stored.
Bit 6—Timer Counter W Write Enable (TCWE)
Bit 6 controls the writing of data to TCW.
Bit 6
TCWE
Description
0
Data cannot be written to TCW
1
Data can be written to TCW
(initial value)
Rev. 8.00 Mar. 09, 2010 Page 305 of 658
REJ09B0042-0800
Section 9 Timers
Bit 5—Bit 4 Write Disable (B4WI)
Bit 5 controls the writing of data to bit 4 in TCSRW.
Bit 5
B4WI
Description
0
Bit 4 is write-enabled
1
Bit 4 is write-protected
(initial value)
This bit is always read as 1. Data written to this bit is not stored.
Bit 4—Timer Control/Status Register W Write Enable (TCSRWE)
Bit 4 controls the writing of data to bits 2 and 0 in TCSRW.
Bit 4
TCSRWE
Description
0
Data cannot be written to bits 2 and 0
1
Data can be written to bits 2 and 0
(initial value)
Bit 3—Bit 2 Write Inhibit (B2WI)
Bit 3 controls the writing of data to bit 2 in TCSRW.
Bit 3
B2WI
Description
0
Bit 2 is write-enabled
1
Bit 2 is write-protected
This bit is always read as 1. Data written to this bit is not stored.
Bit 2—Watchdog Timer On (WDON)
Bit 2 enables watchdog timer operation.
Rev. 8.00 Mar. 09, 2010 Page 306 of 658
REJ09B0042-0800
(initial value)
Section 9 Timers
Bit 2
WDON
Description
0
Watchdog timer operation is disabled
(initial value)*
Clearing conditions:
Reset, or when TCSRWE is set to 1 and 0 is written to B2WI and WDON. Note that
a reset clears WDON to 0 on the H8/38024, H8/38024S, and H8/38024R Group, but
sets WDON to 1 on the H8/38124 Group.
Note: * Initial value is 0 on H8/38024, H8/38024S, and H8/38024R Group; initial
value is 1 on H8/38124 Group.
1
Watchdog timer operation is enabled
Setting condition:
When TCSRWE is set to 1 and 0 is written to B2WI and 1 is written to WDON
Counting starts when this bit is set to 1, and stops when this bit is cleared to 0.
Bit 1—Bit 0 Write Inhibit (B0WI)
Bit 1 controls the writing of data to bit 0 in TCSRW.
Bit 1
B0WI
Description
0
Bit 0 is write-enabled
1
Bit 0 is write-protected
(initial value)
This bit is always read as 1. Data written to this bit is not stored.
Bit 0—Watchdog Timer Reset (WRST)
Bit 0 indicates that TCW has overflowed, generating an internal reset signal. The internal reset
signal generated by the overflow resets the entire chip. WRST is cleared to 0 by a reset from the
RES pin, or when software writes 0.
Bit 0
WRST
Description
0
Clearing conditions:
Reset by RES pin
When TCSRWE = 1, and 0 is written in both BOWI and WRST
1
Setting condition:
When TCW overflows and an internal reset signal is generated
Rev. 8.00 Mar. 09, 2010 Page 307 of 658
REJ09B0042-0800
Section 9 Timers
Timer Counter W (TCW)
Bit
7
6
5
4
3
2
1
0
TCW7
TCW6
TCW5
TCW4
TCW3
TCW2
TCW1
TCW0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
For the H8/38024, H8/38024S, and H8/38024R groups, the clock source is φ/8,192 or φw/32. For
the H8/38124 group, the clock source is selected based on the timer mode register (TMW) setting
if WDCKS is 0 and is φw/32 if WDCKS is 1.
When TCW overflows from H'FF to H'00, an internal reset signal is generated and WRST is set to
1 in TCSRW. Upon reset, TCW is initialized to H'00.
Timer Mode Register (TMW)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
CKS3
CKS2
CKS1
CKS0
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
The TMW register is only implemented on the H8/38124. The input clock is selected using
combinations of CKS3 to CKS0.
Bits 7 to 4—Reserved
These bits are always read as 1.
Bits 3 to 0—Clock Select (CKS3 to CKS0)
These bits are used to select the clock input to TCW from among 10 internal options. Clock source
selection using this register is enabled when WDCKS in port mode register 2 (PMR2) is cleared to
0. If WDCKS is set to 1 the φw/32 clock source is selected, regardless of the settings of the bits in
this register.
Rev. 8.00 Mar. 09, 2010 Page 308 of 658
REJ09B0042-0800
Section 9 Timers
Bit 3
CKS3
Bit 2
CKS2
Bit 1
CKS1
Bit 0
CKS0
Description
1
0
0
0
Internal clock: φ/64 count
1
Internal clock: φ/128 count
1
0
Internal clock: φ/256 count
1
Internal clock: φ/512 count
0
Internal clock: φ/1024 count
1
Internal clock: φ/2048 count
0
Internal clock: φ/4096 count
1
Internal clock: φ/8192 count
X
Watchdog on-chip oscillator
1
0
1
0
X
X
(initial value)
Note: X: Don't care
Clock Stop Register 2 (CKSTPR2)
Bit
7
6
5
LVDCKSTD*
⎯
⎯
4
3
2
1
0
PW2CKSTP AECKSTP WDCKSTP PW1CKSTP LDCKSTP
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
⎯
⎯
R/W
R/W
R/W
R/W
R/W
Note: * Bits 6 and 5 are also reserved on products other than the H8/38124 Group.
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the watchdog timer is described here. For details of the other
bits, see the sections on the relevant modules.
Bit 2—Watchdog Timer Module Standby Mode Control (WDCKSTP)
Bit 2 controls setting and clearing of module standby mode for the watchdog timer.
WDCKSTP
Description
0
Watchdog timer is set to module standby mode
1
Watchdog timer module standby mode is cleared
(initial value)
Note: WDCKSTP is valid when the WDON bit is cleared to 0 in timer control/status register W
(TCSRW). If WDCKSTP is set to 0 while WDON is set to 1 (during watchdog timer
operation), 0 will be set in WDCKSTP but the watchdog timer will continue its watchdog
function and will not enter module standby mode. When the watchdog function ends and
WDON is cleared to 0 by software, the WDCKSTP setting will become valid and the
watchdog timer will enter module standby mode.
Rev. 8.00 Mar. 09, 2010 Page 309 of 658
REJ09B0042-0800
Section 9 Timers
Port Mode Register 2 (PMR2)
Bit
7
6
5
4
3
2
1
0
—
—
POF1
—
—
WDCKS
NCS
IRQ0
Initial value
1
1
0
1
1
0
0
0
Read/Write
—
—
R/W
—
—
R/W
R/W
R/W
PMR2 is an 8-bit read/write register, mainly controlling the selection of pin functions for port 2.
Only the bit relating to the watchdog timer is described here. For details of the other bits, see
section 8, I/O Ports.
Bit 2—Watchdog Timer Source Clock Select (WDCKS)
This bit selects the watchdog timer source clock. Note that stabilization times for the H8/38024,
H8/38024S, and H8/38024R Group and for the H8/38124 Group are different.
• H8/38024, H8/38024S, H8/38024R Group
WDCKS
Description
0
φ/8192 selected
1
φw/32 selected
(initial value)
• H8/38124 Group
WDCKS
Description
0
Selects clock based on timer mode register W (TMW) setting
1
φw/32 selected
Rev. 8.00 Mar. 09, 2010 Page 310 of 658
REJ09B0042-0800
(initial value)
Section 9 Timers
9.6.3
Timer Operation
The watchdog timer has an 8-bit counter (TCW) that is incremented by clock input. The input
clock is selected by the WDCKS in port mode register 2 (PMR2): on the H8/38024, H8/38024S,
and H8/38024R Group, φ/8192 is selected when WDCKS is cleared to 0, and φw/32 when set to 1.
On the H8/38124 Group, if WDCKS is cleared to 0 the clock selection is specified by the setting
of timer mode register W (TMW), and if WDCKS is set to 1 the φw/32 clock source is selected.
When TCSRWE = 1 in TCSRW, if 0 is written in B2WI and 1 is simultaneously written in
WDON, TCW starts counting up. (Write access to TCSRW is required twice to turn on the
watchdog timer. However, on the H8/38124 Group WDON is set to 1 after a reset is cancelled,
TCW starts to be incremented even without gaining write access to TCSRW.) When the TCW
count value reaches H'FF, the next clock input causes the watchdog timer to overflow, and an
internal reset signal is generated one base clock (φ or φSUB) cycle later. The internal reset signal is
output for 512 clock cycles of the φOSC clock. It is possible to write to TCW, causing TCW to
count up from the written value. The overflow period can be set in the range from 1 to 256 input
clocks, depending on the value written in TCW.
Figure 9.18 shows an example of watchdog timer operations.
Example: φ = 2 MHz and the desired overflow period is 30 ms.
2 • 106
• 30 • 10−3 = 7.3
8192
The value set in TCW should therefore be 256 − 8 = 248 (H'F8).
TCW overflow
H'FF
H'F8
TCW count
value
H'00
Start
H'F8 is written
in TCW
H'F8 is written in TCW
Reset
Internal reset
signal
512 φOSC clock cycles
Figure 9.18 Typical Watchdog Timer Operations (Example)
Rev. 8.00 Mar. 09, 2010 Page 311 of 658
REJ09B0042-0800
Section 9 Timers
9.6.4
Watchdog Timer Operation States
Table 9.17(1) and table 9.17(2) summarize the watchdog timer operation states for the H8/38024,
H8/38024S, and H8/38024R Group, and for the H8/38124 Group, respectively.
Table 9.17(1) Watchdog Timer Operation States
(H8/38024, H8/38024S, H8/38024R Group)
Operation
Mode
Reset
Active
TCW
Reset
Functions Functions Halted
Functions/ Halted
Halted*
Halted
Halted
TCSRW
Reset
Functions Functions Retained
Functions/ Retained
Halted*
Retained
Retained
Subactive Subsleep Standby
Module
Standby
Sleep
Watch
Subactive Subsleep Standby
Module
Standby
Note: * Functions when φw/32 is selected as the input clock.
Table 9.17(2) Watchdog Timer Operation States (H8/38124 Group)
Operation
Mode
Reset
Active
TCW
Reset
Functions Functions Functions/ Functions/ Functions/ Functions/ Halted
Halted*1
Halted*1
Halted*2
Halted*1
TCSRW
Reset
Functions Functions Functions/ Functions/ Functions/ Functions/ Retained
Retained*1 Halted*1
Retained*1 Retained*2
TMW
Reset
Functions Functions Functions/ Functions/ Functions/ Functions/ Retained
Retained*1 Halted*1
Retained*1 Retained*2
Sleep
Watch
Notes: 1. Operates when φw/32 or the on-chip oscillator is selected as the internal clock.
2. Operates only when the on-chip oscillator is selected.
Rev. 8.00 Mar. 09, 2010 Page 312 of 658
REJ09B0042-0800
Section 9 Timers
9.7
Asynchronous Event Counter (AEC)
9.7.1
Overview
The asynchronous event counter is incremented by external event clock or internal clock input.
Features
Features of the asynchronous event counter are given below.
• Can count asynchronous events
Can count external events input asynchronously without regard to the operation of base clocks
φ and φSUB.
The counter has a 16-bit configuration, enabling it to count up to 65536 (216) events.
• Can also be used as two independent 8-bit event counter channels.
• Can be used as single-channel independent 16-bit event counter.
• Event/clock input is enabled only when IRQAEC is high or event counter PWM output
(IECPWM) is high.
• Both edge sensing can be used for IRQAEC or event counter PWM output (IECPWM)
interrupts. When the asynchronous counter is not used, independent interrupt function use is
possible.
• When an event counter PWM is used, event clock input enabling/disabling can be performed
automatically in a fixed cycle.
• External event input or a prescaler output clock can be selected by software for the ECH and
ECL clock sources. φ/2, φ/4, or φ/8 can be selected as the prescaler output clock.
• Both edge counting is possible for AEVL and AEVH.
• Counter resetting and halting of the count-up function controllable by software
• Automatic interrupt generation on detection of event counter overflow
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
Rev. 8.00 Mar. 09, 2010 Page 313 of 658
REJ09B0042-0800
Section 9 Timers
Block Diagram
Figure 9.19 shows a block diagram of the asynchronous event counter.
IRREC
φ
ECCR
PSS
ECCSR
φ/2
φ/4, φ/8
OVH
OVL
AEVL
CK
ECL
(8 bits)
CK
Edge sensing
circuit
Edge sensing
circuit
Edge sensing
circuit
IECPWM
IRQAEC
To CPU interrupt
(IRREC2)
ECPWCRL
ECPWCRH
PWM waveform generator
φ/2, φ/4,
φ/8, φ/16,
φ/32, φ/64
ECPWDRL
ECPWDRH
AEGSR
[Legend]
ECPWCRH:
ECPWDRH:
AEGSR:
ECCSR:
ECH:
ECL:
Event counter PWM compare register H
Event counter PWM data register H
Input pin edge select register
Event counter control/status register
Event counter H
Event counter L
ECPWCRL:
ECPWDRL:
ECCR:
Event counter PWM compare register L
Event counter PWM data register L
Event counter control register
Figure 9.19 Block Diagram of Asynchronous Event Counter
Rev. 8.00 Mar. 09, 2010 Page 314 of 658
REJ09B0042-0800
Internal data bus
AEVH
ECH
(8 bits)
Section 9 Timers
Pin Configuration
Table 9.18 shows the asynchronous event counter pin configuration.
Table 9.18 Pin Configuration
Name
Abbr.
I/O
Function
Asynchronous event input H
AEVH
Input
Event input pin for input to event counter H
Asynchronous event input L
AEVL
Input
Event input pin for input to event counter L
Event input enable interrupt input
IRQAEC
Input
Input pin for interrupt enabling event input
Register Configuration
Table 9.19 shows the register configuration of the asynchronous event counter.
Table 9.19 Asynchronous Event Counter Registers
Name
Abbr.
R/W
Initial Value
Address
Event counter PWM compare register H ECPWCRH
R/W
H'FF
H'FF8C
Event counter PWM compare register L ECPWCRL
R/W
H'FF
H'FF8D
Event counter PWM data register H
ECPWDRH
W
H'00
H'FF8E
Event counter PWM data register L
ECPWDRL
W
H'00
H'FF8F
Input pin edge select register
AEGSR
R/W
H'00
H'FF92
Event counter control register
ECCR
R/W
H'00
H'FF94
Event counter control/status register
ECCSR
R/W
H'00
H'FF95
Event counter H
ECH
R
H'00
H'FF96
Event counter L
ECL
R
H'00
H'FF97
Clock stop register 2
CKSTPR2
R/W
H'FF
H'FFFB
Rev. 8.00 Mar. 09, 2010 Page 315 of 658
REJ09B0042-0800
Section 9 Timers
9.7.2
Register Configurations
Event Counter PWM Compare Register H (ECPWCRH)
Bit
7
6
5
4
3
2
1
0
ECPWCRH7 ECPWCRH6 ECPWCRH5 ECPWCRH4 ECPWCRH3 ECPWCRH2 ECPWCRH1 ECPWCRH0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWCRH
should not be modified.
When changing the conversion period, event counter PWM must be halted by clearing
ECPWME to 0 in AEGSR before modifying ECPWCRH.
ECPWCRH is an 8-bit read/write register that sets the event counter PWM waveform conversion
period.
Event Counter PWM Compare Register L (ECPWCRL)
Bit
7
6
5
4
3
2
1
0
ECPWCRL7 ECPWCRL6 ECPWCRL5 ECPWCRL4 ECPWCRL3 ECPWCRL2 ECPWCRL1 ECPWCRL0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWCRL
should not be modified.
When changing the conversion period, event counter PWM must be halted by clearing
ECPWME to 0 in AEGSR before modifying ECPWCRL.
ECPWCRL is an 8-bit read/write register that sets the event counter PWM waveform conversion
period.
Rev. 8.00 Mar. 09, 2010 Page 316 of 658
REJ09B0042-0800
Section 9 Timers
Event Counter PWM Data Register H (ECPWDRH)
Bit
7
6
5
4
3
2
1
0
ECPWDRH7 ECPWDRH6 ECPWDRH5 ECPWDRH4 ECPWDRH3 ECPWDRH2 ECPWDRH1 ECPWDRH0
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Note: When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWDRH
should not be modified.
When changing the data, event counter PWM must be halted by clearing ECPWME to 0 in
AEGSR before modifying ECPWDRH.
ECPWDRH is an 8-bit write-only register that controls event counter PWM waveform generator
data.
Event Counter PWM Data Register L (ECPWDRL)
Bit
7
6
5
4
3
2
1
0
ECPWDRL7 ECPWDRL6 ECPWDRL5 ECPWDRL4 ECPWDRL3 ECPWDRL2 ECPWDRL1 ECPWDRL0
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Note: When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWDRL
should not be modified.
When changing the data, event counter PWM must be halted by clearing ECPWME to 0 in
AEGSR before modifying ECPWDRL.
ECPWDRL is an 8-bit write-only register that controls event counter PWM waveform generator
data.
Input Pin Edge Selection Register (AEGSR)
Bit
7
6
5
4
3
2
1
AHEGS1 AHEGS0 ALEGS1 ALEGS0 AIEGS1 AIEGS0 ECPWME
0
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
AEGSR is an 8-bit read/write register that selects rising, falling, or both edge sensing for the
AEVH, AEVL, and IRQAEC pins.
Rev. 8.00 Mar. 09, 2010 Page 317 of 658
REJ09B0042-0800
Section 9 Timers
Bits 7 and 6—AEC Edge Select H
Bits 7 and 6 select rising, falling, or both edge sensing for the AEVH pin.
Bit 7
AHEGS1
Bit 6
AHEGS0
Description
0
0
Falling edge on AEVH pin is sensed
1
Rising edge on AEVH pin is sensed
0
Both edges on AEVH pin are sensed
1
Use prohibited
1
(initial value)
Bits 5 and 4—AEC Edge Select L
Bits 5 and 4 select rising, falling, or both edge sensing for the AEVL pin.
Bit 5
ALEGS1
Bit 4
ALEGS0
Description
0
0
Falling edge on AEVL pin is sensed
1
Rising edge on AEVL pin is sensed
1
0
Both edges on AEVL pin are sensed
1
Use prohibited
(initial value)
Bits 3 and 2—IRQAEC Edge Select
Bits 3 and 2 select rising, falling, or both edge sensing for the IRQAEC pin.
Bit 3
AIEGS1
Bit 2
AIEGS0
Description
0
0
Falling edge on IRQAEC pin is sensed
1
Rising edge on IRQAEC pin is sensed
0
Both edges on IRQAEC pin are sensed
1
Use prohibited
1
Rev. 8.00 Mar. 09, 2010 Page 318 of 658
REJ09B0042-0800
(initial value)
Section 9 Timers
Bit 1—Event Counter PWM Enable
Bit 1 controls enabling/disabling of event counter PWM and selection/deselection of IRQAEC.
Bit 1
ECPWME
Description
0
AEC PWM halted, IRQAEC selected
1
AEC PWM operation enabled, IRQAEC deselected
(initial value)
Bit 0—Reserved
Bit 0 is a readable/writable reserved bit. It is initialized to 0 by a reset.
Note: Do not set this bit to 1.
Event Counter Control Register (ECCR)
Bit
7
6
5
4
3
2
1
0
ACKH1
ACKH0
ACKL1
ACKL0
PWCK0
⎯
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PWCK2 PWCK1
ECCR performs counter input clock and IRQAEC/IECPWM control.
Bits 7 and 6—AEC Clock Select H (ACKH1, ACKH0)
Bits 7 and 6 select the clock used by ECH.
Bit 7
ACKH1
Bit 6
ACKH0
Description
0
0
AEVH pin input
1
φ/2
0
φ/4
1
φ/8
1
(initial value)
Rev. 8.00 Mar. 09, 2010 Page 319 of 658
REJ09B0042-0800
Section 9 Timers
Bits 5 and 4—AEC Clock Select L (ACKL1, ACKL0)
Bits 5 and 4 select the clock used by ECL.
Bit 5
ACKL1
Bit 4
ACKL0
Description
0
0
AEVL pin input
1
φ/2
0
φ/4
1
φ/8
1
(initial value)
Bits 3 to 1—Event Counter PWM Clock Select (PWCK2, PWCK1, PWCK0)
Bits 3 to 1 select the event counter PWM clock.
Bit 3
PWCK2
Bit 2
PWCK1
Bit 1
PWCK0
Description
0
0
0
φ/2
1
φ/4
1
0
φ/8
1
φ/16
0
φ/32
1
φ/64
1
*
(initial value)
*: Don’t care
Bit 0—Reserved
Bit 0 is a readable/writable reserved bit. It is initialized to 0 by a reset.
Note: Do not set this bit to 1.
Rev. 8.00 Mar. 09, 2010 Page 320 of 658
REJ09B0042-0800
Section 9 Timers
Event Counter Control/Status Register (ECCSR)
Bit
7
6
5
4
3
2
1
0
OVH
OVL
⎯
CH2
CUEH
CUEL
CRCH
CRCL
Initial Value
0
0
0
0
0
0
0
0
Read/Write
R/W*
R/W*
R/W
R/W
R/W
R/W
R/W
R/W
Note: * Bits 7 and 6 can only be written with 0, for flag clearing.
ECCSR is an 8-bit read/write register that controls counter overflow detection, counter resetting,
and halting of the count-up function.
ECCSR is initialized to H'00 upon reset.
Bit 7—Counter Overflow H (OVH)
Bit 7 is a status flag indicating that ECH has overflowed from H'FF to H'00. This flag is set when
ECH overflows. It is cleared by software but cannot be set by software. OVH is cleared by
reading it when set to 1, then writing 0.
When ECH and ECL are used as a 16-bit event counter with CH2 cleared to 0, OVH functions as a
status flag indicating that the 16-bit event counter has overflowed from H'FFFF to H'0000.
Bit 7
OVH
Description
0
ECH has not overflowed
Clearing condition:
After reading OVH = 1, cleared by writing 0 to OVH
1
ECH has overflowed
Setting condition:
Set when ECH overflows from H’FF to H’00
(initial value)
Bit 6—Counter Overflow L (OVL)
Bit 6 is a status flag indicating that ECL has overflowed from H'FF to H'00. This flag is set when
ECL overflows. It is cleared by software but cannot be set by software. OVL is cleared by
reading it when set to 1, then writing 0.
Rev. 8.00 Mar. 09, 2010 Page 321 of 658
REJ09B0042-0800
Section 9 Timers
Bit 6
OVL
Description
0
ECL has not overflowed
Clearing condition:
After reading OVL = 1, cleared by writing 0 to OVL
1
ECL has overflowed
Setting condition:
Set when ECL overflows from H'FF to H'00
(initial value)
Bit 5—Reserved
Bit 5 is a readable/writable reserved bit. It is initialized to 0 by a reset.
Bit 4—Channel Select (CH2)
Bit 4 selects whether ECH and ECL are used as a single-channel 16-bit event counter or as two
independent 8-bit event counter channels. When CH2 is cleared to 0, ECH and ECL function as a
16-bit event counter which is incremented each time an event clock is input to the AEVL pin. In
this case, the overflow signal from ECL is selected as the ECH input clock. When CH2 is set to 1,
ECH and ECL function as independent 8-bit event counters which are incremented each time an
event clock is input to the AEVH or AEVL pin, respectively.
Bit 4
CH2
Description
0
ECH and ECL are used together as a single-channel 16-bit event counter
(initial value)
1
ECH and ECL are used as two independent 8-bit event counter channels
Bit 3—Count-up Enable H (CUEH)
Bit 3 enables event clock input to ECH. When 1 is written to this bit, event clock input is enabled
and increments the counter. When 0 is written to this bit, event clock input is disabled and the
ECH value is held. The AEVH pin or the ECL overflow signal can be selected as the event clock
source by bit CH2.
Bit 3
CUEH
Description
0
ECH event clock input is disabled
ECH value is held
1
ECH event clock input is enabled
Rev. 8.00 Mar. 09, 2010 Page 322 of 658
REJ09B0042-0800
(initial value)
Section 9 Timers
Bit 2—Count-up Enable L (CUEL)
Bit 2 enables event clock input to ECL. When 1 is written to this bit, event clock input is enabled
and increments the counter. When 0 is written to this bit, event clock input is disabled and the
ECL value is held.
Bit 2
CUEL
Description
0
ECL event clock input is disabled
ECL value is held
1
ECL event clock input is enabled
(initial value)
Bit 1—Counter Reset Control H (CRCH)
Bit 1 controls resetting of ECH. When this bit is cleared to 0, ECH is reset. When 1 is written to
this bit, the counter reset is cleared and the ECH count-up function is enabled.
Bit 1
CRCH
Description
0
ECH is reset
1
ECH reset is cleared and count-up function is enabled
(initial value)
Bit 0—Counter Reset Control L (CRCL)
Bit 0 controls resetting of ECL. When this bit is cleared to 0, ECL is reset. When 1 is written to
this bit, the counter reset is cleared and the ECL count-up function is enabled.
Bit 0
CRCL
Description
0
ECL is reset
1
ECL reset is cleared and count-up function is enabled
(initial value)
Event Counter H (ECH)
Bit
7
6
5
4
3
2
1
0
ECH7
ECH6
ECH5
ECH4
ECH3
ECH2
ECH1
ECH0
Initial Value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Rev. 8.00 Mar. 09, 2010 Page 323 of 658
REJ09B0042-0800
Section 9 Timers
ECH is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or
as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ECL. The
external asynchronous event AEVH pin, φ/2, φ/4, φ/8, or the overflow signal from lower 8-bit
counter ECL can be selected as the input clock source. ECH can be cleared to H'00 by software,
and is also initialized to H'00 upon reset.
Event Counter L (ECL)
Bit
7
6
5
4
3
2
1
0
ECL7
ECL6
ECL5
ECL4
ECL3
ECL2
ECL1
ECL0
Initial Value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
ECL is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or
as the lower 8-bit up-counter of a 16-bit event counter configured in combination with ECH. The
event clock from the external asynchronous event AEVL pin, φ/2, φ/4, or φ/8 is used as the input
clock source. ECL can be cleared to H'00 by software, and is also initialized to H'00 upon reset.
Clock Stop Register 2 (CKSTPR2)
Bit
7
6
5
LVDCKSTP*
⎯
⎯
4
3
2
1
0
PW2CKSTP AECKSTP WDCKSTP PW1CKSTP LDCKSTP
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
⎯
⎯
R/W
R/W
R/W
R/W
R/W
Note: * Bits 6 and 5 are also reserved on products other than the H8/38124 Group.
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the asynchronous event counter is described here. For details of
the other bits, see the sections on the relevant modules.
Bit 3—Asynchronous Event Counter Module Standby Mode Control (AECKSTP)
Bit 3 controls setting and clearing of module standby mode for the asynchronous event counter.
AECKSTP
Description
0
Asynchronous event counter is set to module standby mode
1
Asynchronous event counter module standby mode is cleared
Rev. 8.00 Mar. 09, 2010 Page 324 of 658
REJ09B0042-0800
(initial value)
Section 9 Timers
9.7.3
Operation
16-bit Event Counter Operation
When bit CH2 is cleared to 0 in ECCSR, ECH and ECL operate as a 16-bit event counter.
Any of four input clock sources—φ/2, φ/4, φ/8, or AEVL pin input—can be selected by means of
bits ACKL1 and ACKL0 in ECCR.
When AEVL pin input is selected, input sensing is selected with bits ALEGS1 and ALEGS0.
The input clock is enabled only when IRQAEC is high or IECPWM is high. When IRQAEC is
low or IECPWM is low, the input clock is not input to the counter, which therefore does not
operate. Figure 9.20 shows an example of the software processing when ECH and ECL are used
as a 16-bit event counter.
Start
Clear CH2 to 0
Set ACKL1, ACKL0, ALEGS1, and ALEGS0
Clear CUEH, CUEL, CRCH, and CRCL to 0
Clear OVH and OVL to 0
Set CUEH, CUEL, CRCH, and CRCL to 1
End
Figure 9.20 Example of Software Processing when Using ECH and ECL as 16-Bit Event
Counter
As CH2 is cleared to 0 by a reset, ECH and ECL operate as a 16-bit event counter after a reset,
and as ACKL1 and ACKL0 are cleared to 00, the operating clock is asynchronous event input
from the AEVL pin (using falling edge sensing). When the next clock is input after the count
value reaches H'FF in both ECH and ECL, ECH and ECL overflow from H'FFFF to H'0000, the
OVH flag is set to 1 in ECCSR, the ECH and ECL count values each return to H'00, and counting
up is restarted. When overflow occurs, the IRREC bit is set to 1 in IRR2. If the IENEC bit in
IENR2 is 1 at this time, an interrupt request is sent to the CPU.
Rev. 8.00 Mar. 09, 2010 Page 325 of 658
REJ09B0042-0800
Section 9 Timers
8-bit Event Counter Operation
When bit CH2 is set to 1 in ECCSR, ECH and ECL operate as independent 8-bit event counters.
φ/2, φ/4, φ/8, or AEVH pin input can be selected as the input clock source for ECH by means of
bits ACKH1 and ACKH0 in ECCR, and φ/2, φ/4, φ/8, or AEVL pin input can be selected as the
input clock source for ECL by means of bits ACKL1 and ACKL0 in ECCR.
Input sensing is selected with bits AHEGS1 and AHEGS0 when AEVH pin input is selected, and
with bits ALEGS1 and ALEGS0 when AEVL pin input is selected.
The input clock is enabled only when IRQAEC is high or IECPWM is high. When IRQAEC is
low or IECPWM is low, the input clock is not input to the counter, which therefore does not
operate. Figure 9.21 shows an example of the software processing when ECH and ECL are used
as 8-bit event counters.
Start
Set CH2 to 1
Set ACKH1, ACKH0, ACKL1, ACKL0, AHEGS1,
AHEGS0, ALEGS1, and ALEGS0
Clear CUEH, CUEL, CRCH, and CRCL to 0
Clear OVH to 0
Set CUEH, CUEL, CRCH, and CRCL to 1
End
Figure 9.21 Example of Software Processing when Using ECH and ECL as 8-Bit Event
Counters
ECH and ECL can be used as 8-bit event counters by carrying out the software processing shown
in the example in figure 9.21. When the next clock is input after the ECH count value reaches
H'FF, ECH overflows, the OVH flag is set to 1 in ECCSR, the ECH count value returns to H'00,
and counting up is restarted. Similarly, when the next clock is input after the ECL count value
reaches H'FF, ECL overflows, the OVL flag is set to 1 in ECCSR, the ECL count value returns to
H'00, and counting up is restarted. When overflow occurs, the IRREC bit is set to 1 in IRR2. If
the IENEC bit in IENR2 is 1 at this time, an interrupt request is sent to the CPU.
Rev. 8.00 Mar. 09, 2010 Page 326 of 658
REJ09B0042-0800
Section 9 Timers
IRQAEC Operation
When ECPWME in AEGSR is 0, the ECH and ECL input clocks are enabled only when IRQAEC
is high. When IRQAEC is low, the input clocks are not input to the counters, and so ECH and
ECL do not count. ECH and ECL count operations can therefore be controlled from outside by
controlling IRQAEC. In this case, ECH and ECL cannot be controlled individually.
IRQAEC can also operate as an interrupt source. In this case the vector number is 6 and the vector
addresses are H'000C and H'000D.
Interrupt enabling is controlled by IENEC2 in IENR1. When an IRQAEC interrupt is generated,
IRR1 interrupt request flag IRREC2 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an
interrupt request is sent to the CPU.
Rising, falling, or both edge sensing can be selected for the IRQAEC input pin, with bits AIAGS1
and AIAGS0 in AEGSR.
Note: On the H8/38124 Group, control of switching between the system clock oscillator and the
on-chip oscillator during resets should be performed by setting the IRQAEC input level.
Refer to section 4, Clock Pulse Generators, for details.
Event Counter PWM Operation
When ECPWME in AEGSR is 1, the ECH and ECL input clocks are enabled only when event
counter PWM output (IECPWM) is high. When IECPWM is low, the input clocks are not input to
the counters, and so ECH and ECL do not count. ECH and ECL count operations can therefore be
controlled cyclically from outside by controlling event counter PWM. In this case, ECH and ECL
cannot be controlled individually.
IECPWM can also operate as an interrupt source. In this case the vector number is 6 and the
vector addresses are H'000C and H'000D.
Interrupt enabling is controlled by IENEC2 in IENR1. When an IECPWM interrupt is generated,
IRR1 interrupt request flag IRREC2 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an
interrupt request is sent to the CPU.
Rising, falling, or both edge detection can be selected for IECPWM interrupt sensing with bits
AIAGS1 and AIAGS0 in AEGSR.
Rev. 8.00 Mar. 09, 2010 Page 327 of 658
REJ09B0042-0800
Section 9 Timers
Figure 9.22 and table 9.20 show examples of event counter PWM operation.
toff = T × (Ndr +1)
Ton :
Toff :
Tcm :
T:
Ndr :
Clock input enabled time
Clock input disabled time
One conversion period
ECPWM input clock cycle
Value of ECPWDRH and ECPWDRL
Fixed low when Ndr = H'FFFF
Ncm : Value of ECPWCRH and ECPWCRL
ton
tcm = T × (Ncm +1)
Figure 9.22 Event Counter Operation Waveform
Note: Ndr and Ncm above must be set so that Ndr < Ncm. If the settings do not satisfy this
condition, do not set ECPWME in AEGSR to 1.
Table 9.20 Examples of Event Counter PWM Operation
Conditions: fosc = 4 MHz, fφ = 2 MHz, high-speed active mode, ECPWCR value (Ncm) = H'7A11,
ECPWDR value (Ndr) = H'16E3
Clock Source Clock Source ECPWCR
ECPWDR
Selection
Cycle (T)*
Value (Ncm) Value (Ndr)
toff = T •
(Ndr + 1)
tcm = T •
(Ncm + 1)
ton = tcm – toff
φ/2
1 µs
5.86 ms
31.25 ms
25.39 ms
φ/4
2 µs
11.72 ms
62.5 ms
50.78 ms
φ/8
4 µs
23.44 ms
125.0 ms
101.56 ms
φ/16
8 µs
46.88 ms
250.0 ms
203.12 ms
φ/32
16 µs
93.76 ms
500.0 ms
406.24 ms
φ/64
32 µs
187.52 ms 1000.0 ms 812.48 ms
H'7A11
D'31249
Note: * toff minimum width
Rev. 8.00 Mar. 09, 2010 Page 328 of 658
REJ09B0042-0800
H'16E3
D'5859
Section 9 Timers
Clock Input Enable/Disable Function Operation
The clock input to the event counter can be controlled by the IRQAEC pin when ECPWME in
AEGSR is 0, and by event counter PWM output IECPWM when ECPWME in AEGSR is 1. As
this function forcibly terminates the clock input by each signal, a maximum error of one count will
occur depending the IRQAEC or IECPWM timing.
Figure 9.23 shows an example of the operation of this function.
Input event
IRQAEC or
IECPWM
Edge generated by clock return
Actually counted
clock source
Counter value
N
N+1
N+2
N+3
N+4
N+5
N+6
Clock stopped
Figure 9.23 Example of Clock Control Operation
Rev. 8.00 Mar. 09, 2010 Page 329 of 658
REJ09B0042-0800
Section 9 Timers
9.7.4
Asynchronous Event Counter Operation Modes
Asynchronous event counter operation modes are shown in table 9.21.
Table 9.21 Asynchronous Event Counter Operation Modes
Operation
Mode
Reset Active
AEGSR
ECCR
ECCSR
Sleep
Watch
Subactive
Subsleep
Standby
Module
Standby
Reset
Functions Functions Retained*1
Functions
Functions
Retained*1
Retained
Reset
*1
Functions
Functions
Retained*1
Retained
Functions
*1
Retained
Functions Functions Retained
*1
Reset
Functions Functions Retained
ECH
Reset
Functions Functions Functions*1*2 Functions*2 Functions*2 Functions*1*2 Halted
Functions
Retained
ECL
Reset
Functions Functions Functions*1*2 Functions*2 Functions*2 Functions*1*2 Halted
IRQAEC
Reset
Functions Functions Retained*3
Functions
Functions
Retained*3
Retained*4
Event
counter
PWM
Reset
Functions Functions Retained
Retained
Retained
Retained
Retained
Notes: 1. When an asynchronous external event is input, the counter increments but the counter
overflow H/L flags are not affected.
2. Operates when asynchronous external events are selected; halted and retained
otherwise.
3. Clock control by IRQAEC operates, but interrupts do not.
4. As the clock is stopped in module standby mode, IRQAEC has no effect.
9.7.5
Application Notes
1. When reading the values in ECH and ECL, the correct value will not be returned if the event
counter increments during the read operation. Therefore, if the counter is being used in the 8bit mode, clear bits CUEH and CUEL in ECCSR to 0 before reading ECH or ECL. If the
counter is being used in the 16-bit mode, clear CUEL only to 0 before reading ECH or ECL.
2. Use a clock with a frequency of up to 16 MHz for input to the AEVH and AEVL pins, and
ensure that the high and low widths of the clock are at least half the OSC clock cycle duration.
The duty cycle is immaterial.
Rev. 8.00 Mar. 09, 2010 Page 330 of 658
REJ09B0042-0800
Section 9 Timers
Mode
Maximum AEVH/AEVL Pin Input
Clock Frequency
Active (high-speed), sleep (high-speed)
16 MHz
Active (medium-speed), sleep (medium-speed) (φ/16)
2 • fOSC
(φ/32)
fOSC
(φ/64)
1/2 • fOSC
fOSC = 1 MHz to 4 MHz
(φ/128)
1/4 • fOSC
Watch, subactive, subsleep, standby
(φw/2)
1000 kHz
(φw/4)
500 kHz
(φw/8)
250 kHz
φw = 32.768 kHz or 38.4 kHz*
Note: * Does not apply to H8/38124 Group.
3. When using the clock in the 16-bit mode, set CUEH to 1 first, then set CRCH to 1 in ECCSR.
Or, set CUEH and CRCH simultaneously before inputting the clock. After that, do not change
the CUEH value while using in the 16-bit mode. Otherwise, an error counter increment may
occur. Also, to reset the counter, clear CRCH and CRCL to 0 simultaneously or clear CRCL
and CRCH to 0 sequentially, in that order.
4. When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWCRH,
ECPWCRL, ECPWDRH, and ECPWDRL should not be modified.
When changing the data, event counter PWM must be halted by clearing ECPWME to 0 in
AEGSR before modifying these registers.
5. The event counter PWM data register and event counter PWM compare register must be set so
that event counter PWM data register < event counter PWM compare register. If the settings
do not satisfy this condition, do not set ECPWME to 1 in AEGSR.
6. As synchronization is established internally when an IRQAEC interrupt is generated, a
maximum error of 1 tcyc will occur between clock halting and interrupt acceptance.
Rev. 8.00 Mar. 09, 2010 Page 331 of 658
REJ09B0042-0800
Section 9 Timers
Rev. 8.00 Mar. 09, 2010 Page 332 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
Section 10 Serial Communication Interface
10.1
Overview
The H8/38024 Group is provided with one serial communication interface, SCI3.
Serial communication interface 3 (SCI3) can carry out serial data communication in either
asynchronous or synchronous mode.
10.1.1
Features
Features of SCI3 are listed below.
• Choice of asynchronous or synchronous mode for serial data communication
⎯ Asynchronous mode
Serial data communication is performed asynchronously, with synchronization provided
character by character. In this mode, serial data can be exchanged with standard
asynchronous communication LSIs such as a Universal Asynchronous
Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter
(ACIA).
There is a choice of 12 data transfer formats.
Data length
7, 8, 5 bits
Stop bit length
1 or 2 bits
Parity
Even, odd, or none
Receive error detection
Parity, overrun, and framing errors
Break detection
Break detected by reading the RXD32 pin level directly when a
framing error occurs
⎯ Synchronous mode
Serial data communication is synchronized with a clock. In this mode, serial data can be
exchanged with another LSI that has a synchronous communication function.
Data length
8 bits
Receive error detection
Overrun errors
Rev. 8.00 Mar. 09, 2010 Page 333 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
• Full-duplex communication
Separate transmission and reception units are provided, enabling transmission and reception to
be carried out simultaneously. The transmission and reception units are both double-buffered,
allowing continuous transmission and reception.
• On-chip baud rate generator, allowing any desired bit rate to be selected
• Choice of an internal or external clock as the transmit/receive clock source
• Six interrupt sources: transmit end, transmit data empty, receive data full, overrun error,
framing error, and parity error
Note: On the H8/38124 Group, the system clock generator must be used when carrying out this
function.
Rev. 8.00 Mar. 09, 2010 Page 334 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
10.1.2
Block Diagram
Figure 10.1 shows a block diagram of SCI3.
SCK32
External
clock
Baud rate generator
BRC
Internal clock (φ/64, φ/16, φW/2, φ)
BRR
SMR
Transmit/receive
control circuit
SCR3
SSR
TXD32
TSR
TDR
RSR
RDR
Internal data bus
Clock
SPCR
RXD32
Interrupt request
(TEI, TXI, RXI, ERI)
[Legend]
Receive shift register
RSR:
RDR: Receive data register
Transmit shift register
TSR:
Transmit data register
TDR:
SMR: Serial mode register
SCR3: Serial control register 3
Serial status register
SSR:
Bit rate register
BRR:
Bit rate counter
BRC:
SPCR: Serial port control register
Figure 10.1 SCI3 Block Diagram
Rev. 8.00 Mar. 09, 2010 Page 335 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
10.1.3
Pin Configuration
Table 10.1 shows the SCI3 pin configuration.
Table 10.1 Pin Configuration
Name
Abbr.
I/O
Function
SCI3 clock
SCK32
I/O
SCI3 clock input/output
SCI3 receive data input
RXD32
Input
SCI3 receive data input
SCI3 transmit data output
TXD32
Output
SCI3 transmit data output
10.1.4
Register Configuration
Table 10.2 shows the SCI3 register configuration.
Table 10.2 Registers
Name
Abbr.
R/W
Initial Value
Address
Serial mode register
SMR
R/W
H'00
H'FFA8
Bit rate register
BRR
R/W
H'FF
H'FFA9
Serial control register 3
SCR3
R/W
H'00
H'FFAA
Transmit data register
TDR
R/W
H'FF
H'FFAB
Serial status register
SSR
R/W
H'84
H'FFAC
Receive data register
RDR
R
H'00
H'FFAD
Transmit shift register
TSR
Protected —
—
Receive shift register
RSR
Protected —
—
Bit rate counter
BRC
Protected —
—
Clock stop register 1
CKSTPR1
R/W
H'FF
H'FFFA
Serial port control register
SPCR
R/W
—
H'FF91
Rev. 8.00 Mar. 09, 2010 Page 336 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
10.2
Register Descriptions
10.2.1
Receive Shift Register (RSR)
Bit
7
6
5
4
3
2
1
0
Read/Write
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
RSR is a register used to receive serial data. Serial data input to RSR from the RXD32 pin is set in
the order in which it is received, starting from the LSB (bit 0), and converted to parallel data.
When one byte of data is received, it is transferred to RDR automatically.
RSR cannot be read or written directly by the CPU.
10.2.2
Receive Data Register (RDR)
Bit
7
6
5
4
3
2
1
0
RDR7
RDR6
RDR5
RDR4
RDR3
RDR2
RDR1
RDR0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
RDR is an 8-bit register that stores received serial data.
When reception of one byte of data is finished, the received data is transferred from RSR to RDR,
and the receive operation is completed. RSR is then able to receive data. RSR and RDR are
double-buffered, allowing consecutive receive operations.
RDR is a read-only register, and cannot be written by the CPU.
RDR is initialized to H'00 upon reset, and in standby, module standby or watch mode.
Rev. 8.00 Mar. 09, 2010 Page 337 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
10.2.3
Transmit Shift Register (TSR)
Bit
7
6
5
4
3
2
1
0
Read/Write
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
TSR is a register used to transmit serial data. Transmit data is first transferred from TDR to TSR,
and serial data transmission is carried out by sending the data to the TXD32 pin in order, starting
from the LSB (bit 0). When one byte of data is transmitted, the next byte of transmit data is
transferred to TDR, and transmission started, automatically. Data transfer from TDR to TSR is
not performed if no data has been written to TDR (if bit TDRE is set to 1 in the serial status
register (SSR)).
TSR cannot be read or written directly by the CPU.
10.2.4
Transmit Data Register (TDR)
Bit
7
6
5
4
3
2
1
0
TDR7
TDR6
TDR5
TDR4
TDR3
TDR2
TDR1
TDR0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TDR is an 8-bit register that stores transmit data. When TSR is found to be empty, the transmit
data written in TDR is transferred to TSR, and serial data transmission is started. Continuous
transmission is possible by writing the next transmit data to TDR during TSR serial data
transmission.
TDR can be read or written by the CPU at any time.
TDR is initialized to H'FF upon reset, and in standby, module standby, or watch mode.
Rev. 8.00 Mar. 09, 2010 Page 338 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
10.2.5
Serial Mode Register (SMR)
Bit
7
6
5
4
3
2
1
0
COM
CHR
PE
PM
STOP
MP
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SMR is an 8-bit register used to set the serial data transfer format and to select the clock source for
the baud rate generator.
SMR can be read or written by the CPU at any time.
SMR is initialized to H'00 upon reset, and in standby, module standby, or watch mode.
Bit 7—Communication Mode (COM)
Bit 7 selects whether SCI3 operates in asynchronous mode or synchronous mode.
Bit 7
COM
Description
0
Asynchronous mode
1
Synchronous mode
(initial value)
Bit 6—Character Length (CHR)
Bit 6 selects either 7 or 8 bits as the data length to be used in asynchronous mode. In synchronous
mode the data length is always 8 bits, irrespective of the bit 6 setting.
Bit 6
CHR
0
1
Description
2
8-bit data/5-bit data*
1
2
7-bit data* /5-bit data*
(initial value)
Notes: 1. When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted.
2. When 5-bit data is selected, set both PE and MP to 1. The three most significant bits
(bits 7, 6, and 5) of TDR are not transmitted.
Rev. 8.00 Mar. 09, 2010 Page 339 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
Bit 5—Parity Enable (PE)
Bit 5 selects whether a parity bit is to be added during transmission and checked during reception
in asynchronous mode. In synchronous mode parity bit addition and checking is not performed,
irrespective of the bit 5 setting.
Bit 5
PE
0
1
Description
2
Parity bit addition and checking disabled*
1/ 2
Parity bit addition and checking enabled* *
(initial value)
Notes: 1. When PE is set to 1, even or odd parity, as designated by bit PM, is added to transmit
data before it is sent, and the received parity bit is checked against the parity
designated by bit PM.
2. For the case where 5-bit data is selected, see table 10.11.
Bit 4—Parity Mode (PM)
Bit 4 selects whether even or odd parity is to be used for parity addition and checking. The PM bit
setting is only valid in asynchronous mode when bit PE is set to 1, enabling parity bit addition and
checking. The PM bit setting is invalid in synchronous mode, and in asynchronous mode if parity
bit addition and checking is disabled.
Bit 4
PM
0
1
Description
1
Even parity*
2
Odd parity*
(initial value)
Notes: 1. When even parity is selected, a parity bit is added in transmission so that the total
number of 1 bits in the transmit data plus the parity bit is an even number; in reception,
a check is carried out to confirm that the number of 1 bits in the receive data plus the
parity bit is an even number.
2. When odd parity is selected, a parity bit is added in transmission so that the total
number of 1 bits in the transmit data plus the parity bit is an odd number; in reception, a
check is carried out to confirm that the number of 1 bits in the receive data plus the
parity bit is an odd number.
Rev. 8.00 Mar. 09, 2010 Page 340 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
Bit 3—Stop Bit Length (STOP)
Bit 3 selects 1 bit or 2 bits as the stop bit length in asynchronous mode. The STOP bit setting is
only valid in asynchronous mode. When synchronous mode is selected the STOP bit setting is
invalid since stop bits are not added.
Bit 3
STOP
0
1
Description
1
1 stop bit*
2
2 stop bits*
(initial value)
Notes: 1. In transmission, a single 1 bit (stop bit) is added at the end of a transmit character.
2. In transmission, two 1 bits (stop bits) are added at the end of a transmit character.
In reception, only the first of the received stop bits is checked, irrespective of the STOP bit setting.
If the second stop bit is 1 it is treated as a stop bit, but if 0, it is treated as the start bit of the next
transmit character.
Bit 2—5 Bit Communication (MP)
When this bit is one, the format of 5 bits communication becomes possible.
In the case of writing 1 to this bit, bit 5 (PE) should be written with 1 all at once.
Bit 2
MP
Description
0
5 bit communication disabled
1
5 bit communication enabled
(initial value)
Rev. 8.00 Mar. 09, 2010 Page 341 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
Bits 1 and 0—Clock Select 1, 0 (CKS1, CKS0)
Bits 1 and 0 choose φ/64, φ/16, φw/2, or φ as the clock source for the baud rate generator.
For the relation between the clock source, bit rate register setting, and baud rate, see section
10.2.8, Bit rate register (BRR).
Bit 1
CKS1
Bit 0
CKS0
Description
0
0
φ clock
0
1
φ w/2 clock /φ w clock
1
0
φ/16 clock
1
1
φ/64 clock
(initial value)
*1
*2
Notes: 1. φ w/2 clock in active (medium-speed/high-speed) mode and sleep mode
2. φ w clock in subactive mode and subsleep mode. In subactive or subsleep mode, SCI3
can be operated when CPU clock is φw/2 only.
10.2.6
Serial Control Register 3 (SCR3)
Bit
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCR3 is an 8-bit register for selecting transmit or receive operation, the asynchronous mode clock
output, interrupt request enabling or disabling, and the transmit/receive clock source.
SCR3 can be read or written by the CPU at any time.
SCR3 is initialized to H'00 upon reset, and in standby, module standby or watch mode.
Bit 7—Transmit Interrupt Enable (TIE)
Bit 7 selects enabling or disabling of the transmit data empty interrupt request (TXI) when
transmit data is transferred from the transmit data register (TDR) to the transmit shift register
(TSR), and bit TDRE in the serial status register (SSR) is set to 1.
TXI can be released by clearing bit TDRE or bit TIE to 0.
Rev. 8.00 Mar. 09, 2010 Page 342 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
Bit 7
TIE
Description
0
Transmit data empty interrupt request (TXI) disabled
1
Transmit data empty interrupt request (TXI) enabled
(initial value)
Bit 6—Receive Interrupt Enable (RIE)
Bit 6 selects enabling or disabling of the receive data full interrupt request (RXI) and the receive
error interrupt request (ERI) when receive data is transferred from the receive shift register (RSR)
to the receive data register (RDR), and bit RDRF in the serial status register (SSR) is set to 1.
There are three kinds of receive error: overrun, framing, and parity.
RXI and ERI can be released by clearing bit RDRF or the FER, PER, or OER error flag to 0, or by
clearing bit RIE to 0.
Bit 6
RIE
Description
0
Receive data full interrupt request (RXI) and receive error interrupt
request (ERI) disabled
1
Receive data full interrupt request (RXI) and receive error interrupt
request (ERI) enabled
(initial value)
Bit 5—Transmit Enable (TE)
Bit 5 selects enabling or disabling of the start of transmit operation.
Bit 5
TE
0
1
Description
1
Transmit operation disabled* (TXD32 pin is I/O port)
2
Transmit operation enabled* (TXD32 pin is transmit data pin)
(initial value)
Notes: 1. Bit TDRE in SSR is fixed at 1.
2. When transmit data is written to TDR in this state, bit TDRE in SSR is cleared to 0 and
serial data transmission is started. Be sure to carry out serial mode register (SMR)
settings, and setting of bit SPC32 in SPCR, to decide the transmission format before
setting bit TE to 1.
Rev. 8.00 Mar. 09, 2010 Page 343 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
Bit 4—Receive Enable (RE)
Bit 4 selects enabling or disabling of the start of receive operation.
Bit 4
RE
0
1
Description
1
Receive operation disabled* (RXD32 pin is I/O port)
2
Receive operation enabled* (RXD32 pin is receive data pin)
(initial value)
Notes: 1. Note that the RDRF, FER, PER, and OER flags in SSR are not affected when bit RE is
cleared to 0, and retain their previous state.
2. In this state, serial data reception is started when a start bit is detected in asynchronous
mode or serial clock input is detected in synchronous mode. Be sure to carry out serial
mode register (SMR) settings to decide the reception format before setting bit RE to 1.
Bit 3—Reserved (MPIE)
It’s a reserved bit.
Bit 2—Transmit End Interrupt Enable (TEIE)
Bit 2 selects enabling or disabling of the transmit end interrupt request (TEI) if there is no valid
transmit data in TDR when MSB data is to be sent.
Bit 2
TEIE
0
1
Description
Transmit end interrupt request (TEI) disabled
Transmit end interrupt request (TEI) enabled*
(initial value)
Note: * TEI can be released by clearing bit TDRE to 0 and clearing bit TEND to 0 in SSR, or by
clearing bit TEIE to 0.
Rev. 8.00 Mar. 09, 2010 Page 344 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0)
Bits 1 and 0 select the clock source and enabling or disabling of clock output from the SCK32 pin.
The combination of CKE1 and CKE0 determines whether the SCK32 pin functions as an I/O port,
a clock output pin, or a clock input pin.
The CKE0 bit setting is only valid in case of internal clock operation (CKE1 = 0) in asynchronous
mode. In synchronous mode, or when external clock operation is used (CKE1 = 1), bit CKE0
should be cleared to 0.
After setting bits CKE1 and CKE0, set the operating mode in the serial mode register (SMR).
For details on clock source selection, see table 10.9.
Description
Bit 1
CKE1
Bit 0
CKE0
Communication Mode
Clock Source
SCK32 Pin Function
0
0
Asynchronous
Internal clock
I/O port*
Synchronous
Internal clock
Asynchronous
Internal clock
Serial clock output*
2
Clock output*
Synchronous
Reserved
Asynchronous
External clock
Clock input*
Synchronous
External clock
Serial clock input
0
1
1
1
0
1
Asynchronous
Reserved
Synchronous
Reserved
1
1
3
Notes: 1. Initial value
2. A clock with the same frequency as the bit rate is output.
3. Input a clock with a frequency 16 times the bit rate.
Rev. 8.00 Mar. 09, 2010 Page 345 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
10.2.7
Serial Status Register (SSR)
Bit
7
6
5
4
3
2
1
0
TDRE
RDRF
OER
FER
PER
TEND
MPBR
MPBT
Initial value
1
0
0
0
0
1
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R
R
R/W
Note: * Only a write of 0 for flag clearing is possible.
SSR is an 8-bit register containing status flags that indicate the operational status of SCI3.
SSR can be read or written to by the CPU at any time, but 1 cannot be written to bits TDRE,
RDRF, OER, PER, and FER.
Bits TEND and MPBR are read-only bits, and cannot be modified.
SSR is initialized to H'84 upon reset, and in standby, module standby, or watch mode.
Bit 7—Transmit Data Register Empty (TDRE)
Bit 7 indicates that transmit data has been transferred from TDR to TSR.
Bit 7
TDRE
Description
0
Transmit data written in TDR has not been transferred to TSR
Clearing conditions:
After reading TDRE = 1, cleared by writing 0 to TDRE
When data is written to TDR by an instruction
1
Transmit data has not been written to TDR, or transmit data written in
TDR has been transferred to TSR
Setting conditions:
When bit TE in SCR3 is cleared to 0
When data is transferred from TDR to TSR
Rev. 8.00 Mar. 09, 2010 Page 346 of 658
REJ09B0042-0800
(initial value)
Section 10 Serial Communication Interface
Bit 6—Receive Data Register Full (RDRF)
Bit 6 indicates that received data is stored in RDR.
Bit 6
RDRF
Description
0
There is no receive data in RDR
Clearing conditions:
After reading RDRF = 1, cleared by writing 0 to RDRF
When RDR data is read by an instruction
(initial value)
1
There is receive data in RDR
Setting condition:
When reception ends normally and receive data is transferred from RSR to RDR
Note: If an error is detected in the receive data, or if the RE bit in SCR3 has been cleared to 0,
RDR and bit RDRF are not affected and retain their previous state.
Note that if data reception is completed while bit RDRF is still set to 1, an overrun error
(OER) will result and the receive data will be lost.
Bit 5—Overrun Error (OER)
Bit 5 indicates that an overrun error has occurred during reception.
Bit 5
OER
0
1
Description
1
Reception in progress or completed*
Clearing condition:
After reading OER = 1, cleared by writing 0 to OER
2
An overrun error has occurred during reception*
Setting condition:
When reception is completed with RDRF set to 1
(initial value)
Notes: 1. When bit RE in SCR3 is cleared to 0, bit OER is not affected and retains its previous
state.
2. RDR retains the receive data it held before the overrun error occurred, and data
received after the error is lost. Reception cannot be continued with bit OER set to 1,
and in synchronous mode, transmission cannot be continued either.
Rev. 8.00 Mar. 09, 2010 Page 347 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
Bit 4—Framing Error (FER)
Bit 4 indicates that a framing error has occurred during reception in asynchronous mode.
Bit 4
FER
Description
1
0
Reception in progress or completed*
Clearing condition:
After reading FER = 1, cleared by writing 0 to FER
1
A framing error has occurred during reception
Setting condition:
When the stop bit at the end of the receive data is checked for a value
2
of 1 at the end of reception, and the stop bit is 0*
(initial value)
Notes: 1. When bit RE in SCR3 is cleared to 0, bit FER is not affected and retains its previous
state.
2. Note that, in 2-stop-bit mode, only the first stop bit is checked for a value of 1, and the
second stop bit is not checked. When a framing error occurs the receive data is
transferred to RDR but bit RDRF is not set. Reception cannot be continued with bit
FER set to 1. In synchronous mode, neither transmission nor reception is possible
when bit FER is set to 1.
Bit 3—Parity Error (PER)
Bit 3 indicates that a parity error has occurred during reception with parity added in asynchronous
mode.
Bit 3
PER
0
1
Description
1
Reception in progress or completed*
(initial value)
Clearing condition:
After reading PER = 1, cleared by writing 0 to PER
2
A parity error has occurred during reception*
Setting condition:
When the number of 1 bits in the receive data plus parity bit does not
match the parity designated by bit PM in the serial mode register (SMR)
Notes: 1. When bit RE in SCR3 is cleared to 0, bit PER is not affected and retains its previous
state.
2. Receive data in which a parity error has occurred is still transferred to RDR, but bit
RDRF is not set. Reception cannot be continued with bit PER set to 1. In synchronous
mode, neither transmission nor reception is possible when bit FER is set to 1.
Rev. 8.00 Mar. 09, 2010 Page 348 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
Bit 2—Transmit End (TEND)
Bit 2 indicates that bit TDRE is set to 1 when the last bit of a transmit character is sent.
Bit 2 is a read-only bit and cannot be modified.
Bit 2
TEND
Description
0
Transmission in progress
Clearing conditions:
After reading TDRE = 1, cleared by writing 0 to TDRE
When data is written to TDR by an instruction
1
Transmission ended
(initial value)
Setting conditions:
When bit TE in SCR3 is cleared to 0
When bit TDRE is set to 1 when the last bit of a transmit character is sent
Bit 1—Reserved (MPBR)
It’s a reserved read-only bit.
Bit 0—Reserved (MPBT)
The write value should always be 0.
Rev. 8.00 Mar. 09, 2010 Page 349 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
10.2.8
Bit Rate Register (BRR)
Bit
7
6
5
4
3
2
1
0
BRR7
BRR6
BRR5
BRR4
BRR3
BRR2
BRR1
BRR0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BRR is an 8-bit register that designates the transmit/receive bit rate in accordance with the baud
rate generator operating clock selected by bits CKS1 and CKS0 of the serial mode register (SMR).
BRR can be read or written by the CPU at any time.
BRR is initialized to H'FF upon reset, and in standby, module standby, or watch mode.
Table 10.3 shows examples of BRR settings in asynchronous mode. The values shown are for
active (high-speed) mode.
Table 10.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
φ
16.4 kHz
Bit Rate
(bit/s)
n
110
19.2 kHz
N
Error
(%) n
—
—
—
150
—
—
200
—
250
300
600
1 MHz
N
Error
(%) n
—
—
—
—
0
3
—
—
0
0
1
2.5
—
—
—
—
—
—
1.2288 MHz
N
Error
(%) n
2
17
0
2
2
0
2
—
—
—
0
1
0
0
0
0
1200
—
—
2400
—
—
2 MHz
N
Error
(%) n
N
Error
(%)
–1.36 2
21
–0.83 3
8
–1.36
12
0.16
3
3
0
2
25
0.16
9
–2.34 3
2
0
3
4
–2.34
3
1
–2.34 0
153 –0.26 2
15
–2.34
0
103 0.16
3
1
0
2
12
0.16
0
51
0.16
3
0
0
0
103 0.16
—
0
25
0.16
2
1
0
0
51
0.16
—
0
12
0.16
2
0
0
0
25
0.16
4800
—
—
—
—
—
—
0
7
0
0
12
0.16
9600
—
—
—
—
—
—
0
3
0
—
—
—
19200
—
—
—
—
—
—
0
1
0
—
—
—
31250
—
—
—
0
0
0
—
—
—
0
1
0
38400
—
—
—
—
—
—
0
0
0
—
—
—
Rev. 8.00 Mar. 09, 2010 Page 350 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
Table 10.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
φ
5 MHz
8 MHz
10 MHz
Bit Rate
(bit/s)
n
N
Error
(%) n
N
Error
(%) n
N
Error
(%)
110
3
21
0.88
3
35
–1.36 3
43
0.88
150
3
15
1.73
3
25
0.16
3
32
–1.36
200
3
11
1.73
3
19
–2.34 3
23
1.73
250
3
9
–2.34 3
15
–2.34 3
19
–2.34
300
3
7
1.73
3
12
0.16
3
15
1.73
600
3
3
1.73
2
25
0.16
3
7
1.73
1200
3
1
1.73
2
12
0.16
3
3
1.73
2400
3
0
1.73
0
103 0.16
3
1
1.73
4800
2
1
1.73
0
51
0.16
3
0
1.73
9600
2
0
173
0
25
0.16
2
1
1.73
19200
0
7
1.73
0
12
0.16
2
0
1.73
31250
0
4
0
0
7
0
0
9
0
38400
0
3
1.73
—
—
—
0
7
1.73
Notes: No indication: Setting not possible.
—: Setting possible, but errors may result.
1. The value set in BRR is given by the following equation:
N=
where
φ
(32 × 2
B:
N:
φ:
n:
2n
× B)
–1
Bit rate (bit/s)
Baud rate generator BRR setting (0 ≤ N ≤ 255)
System clock frequency
Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 10.4.)
2. The error in table 10.3 is the value obtained from the following equation, rounded to two
decimal places.
Error (%) =
B (rate obtained from n, N, OSC) – R(bit rate in left-hand column in table 10.3.)
R (bit rate in left-hand column in table 10.3.)
× 100
Rev. 8.00 Mar. 09, 2010 Page 351 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
Table 10.4 Relation between n and Clock
SMR Setting
n
Clock
CKS1
CKS0
0
φ
0
0
0
φw/2 /φw
0
1
2
φ/16
1
0
3
φ/64
1
1
*1
*2
Notes: 1. φ w/2 clock in active (medium-speed/high-speed) mode and sleep mode
2. φ w clock in subactive mode and subsleep mode
In subactive or subsleep mode, SCI3 can be operated when CPU clock is φw/2 only.
Table 10.5 shows the maximum bit rate for each frequency. The values shown are for active
(high-speed) mode.
Table 10.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
Setting
OSC (MHz)
φ (MHz)
Maximum Bit Rate
(bit/s)
0.0384*
0.0192
600
0
0
2
1
31250
0
0
2.4576
1.2288
38400
0
0
4
2
62500
0
0
10
5
156250
0
0
16
8
250000
0
0
20
10
312500
0
0
Note: * When SMR is set up to CKS1 = 0, CKS0 = 1.
Rev. 8.00 Mar. 09, 2010 Page 352 of 658
REJ09B0042-0800
n
N
Section 10 Serial Communication Interface
Table 10.6 shows examples of BRR settings in synchronous mode. The values shown are for
active (high-speed) mode.
Table 10.6 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (1)
φ
1 MHz
19.2 kHz
2 MHz
Bit Rate
(bit/s)
n
N
Error
n
N
Error
n
N
Error
200
0
23
0
—
—
—
—
—
—
250
—
—
—
—
—
—
2
124
0
300
2
0
0
—
—
—
—
—
—
500
—
—
—
—
—
—
1K
0
249
0
—
—
—
2.5K
0
99
0
0
199
0
5K
0
49
0
0
99
0
10K
0
24
0
0
49
0
25K
0
9
0
0
19
0
50K
0
4
0
0
9
0
100K
—
—
—
0
4
0
250K
0
0
0
0
1
0
0
0
0
500K
1M
Rev. 8.00 Mar. 09, 2010 Page 353 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
Table 10.6 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (2)
φ
8 MHz
5 MHz
10 MHz
Bit Rate
(bit/s)
n
N
Error
n
N
Error
n
N
Error
200
—
—
—
—
—
—
0
12499
0
250
—
—
—
3
124
0
2
624
0
300
—
—
—
—
—
—
0
8332
0
500
—
—
—
2
249
0
0
4999
0
1K
—
—
—
2
124
0
0
2499
0
2.5K
—
—
—
2
49
0
0
999
0
5K
0
249
0
2
24
0
0
499
0
10K
0
124
0
0
199
0
0
249
0
25K
0
49
0
0
79
0
0
99
0
50K
0
24
0
0
39
0
0
49
0
100K
—
—
—
0
19
0
0
24
0
250K
0
4
0
0
7
0
0
9
0
500K
—
—
—
0
3
0
0
4
0
1M
—
—
—
0
1
0
—
—
—
Blank: Cannot be set.
—:
A setting can be made, but an error will result.
Notes: The value set in BRR is given by the following equation:
N=
where
φ
(4 × 2
B:
N:
φ:
n:
2n
× B)
–1
Bit rate (bit/s)
Baud rate generator BRR setting (0 ≤ N ≤ 255)
System clock frequency
Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 10.7.)
Rev. 8.00 Mar. 09, 2010 Page 354 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
Table 10.7 Relation between n and Clock
SMR Setting
n
Clock
CKS1
CKS0
0
φ
0
0
0
φw/2 /φw
0
1
2
φ/16
1
0
3
φ/64
1
1
*1
*2
Notes: 1. φw/2 clock in active (medium-speed/high-speed) mode and sleep mode
2. φw clock in subactive mode and subsleep mode
In subactive or subsleep mode, SCI3 can be operated when CPU clock is φw/2 only.
Rev. 8.00 Mar. 09, 2010 Page 355 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
10.2.9
Clock stop register 1 (CKSTPR1)
Bit
7
6
5
4
3
2
1
0
⎯
⎯
Initial value
1
1
1
1
1
1
1
1
Read/Write
⎯
⎯
R/W
R/W
R/W
R/W
R/W
R/W
S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bits relating to SCI3 are described here. For details of the other bits, see the
sections on the relevant modules.
Bit 5—SCI3 Module Standby Mode Control (S32CKSTP)
Bit 5 controls setting and clearing of module standby mode for SCI3.
S32CKSTP
Description
0
SCI3 is set to module standby mode*
1
SCI3 module standby mode is cleared
(initial value)
Note: * All SCI3 register is initialized in module standby mode.
10.2.10 Serial Port Control Register (SPCR)
Bit
7
6
5
4
3
2
1
0
⎯
⎯
SPC32
⎯
⎯
⎯
Initial value
1
1
0
⎯
0
0
⎯
⎯
Read/Write
⎯
⎯
R/W
W
R/W
R/W
W
W
SCINV3 SCINV2
SPCR is an 8-bit readable/writable register that performs RXD32 and TXD32 pin input/output data
inversion switching.
Bits 7 and 6—Reserved
Bits 7 and 6 are reserved; they are always read as 1 and cannot be modified.
Rev. 8.00 Mar. 09, 2010 Page 356 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
Bit 5—P42/TXD32 Pin Function Switch (SPC32)
This bit selects whether pin P42/TXD32 is used as P42 or as TXD32.
Bit 5
SPC32
Description
0
Functions as P42 I/O pin
1
Functions as TXD32 output pin*
(initial value)
Note: * Set the TE bit in SCR3 after setting this bit to 1.
Bit 4—Reserved
Bit 4 is reserved; only 0 can be written to this bit.
Bit 3—TXD32 Pin Output Data Inversion Switch
Bit 3 specifies whether or not TXD32 pin output data is to be inverted.
Bit 3
SCINV3
Description
0
TXD32 output data is not inverted
1
TXD32 output data is inverted
(initial value)
Bit 2—RXD32 Pin Input Data Inversion Switch
Bit 2 specifies whether or not RXD32 pin input data is to be inverted.
Bit 2
SCINV2
Description
0
RXD32 input data is not inverted
1
RXD32 input data is inverted
(initial value)
Bits 1 and 0—Reserved
Bits 1 and 0 are reserved; only 0 can written to these bits.
Rev. 8.00 Mar. 09, 2010 Page 357 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
10.3
Operation
10.3.1
Overview
SCI3 can perform serial communication in two modes: asynchronous mode in which
synchronization is provided character by character, and synchronous mode in which
synchronization is provided by clock pulses. The serial mode register (SMR) is used to select
asynchronous or synchronous mode and the data transfer format, as shown in table 10.8.
The clock source for SCI3 is determined by bit COM in SMR and bits CKE1 and CKE0 in SCR3,
as shown in table 10.9.
Asynchronous Mode
• Choice of 5-, 7-, or 8-bit data length
• Choice of parity addition, and addition of 1 or 2 stop bits. (The combination of these
parameters determines the data transfer format and the character length.)
• Framing error (FER), parity error (PER), overrun error (OER), and break detection during
reception
• Choice of internal or external clock as the clock source
When internal clock is selected: SCI3 operates on the baud rate generator clock, and a clock
with the same frequency as the bit rate can be output.
When external clock is selected: A clock with a frequency 16 times the bit rate must be input.
(The on-chip baud rate generator is not used.)
Synchronous Mode
• Data transfer format: Fixed 8-bit data length
• Overrun error (OER) detection during reception
• Choice of internal or external clock as the clock source
When internal clock is selected: SCI3 operates on the baud rate generator clock, and a serial
clock is output.
When external clock is selected: The on-chip baud rate generator is not used, and SCI3
operates on the input serial clock.
Rev. 8.00 Mar. 09, 2010 Page 358 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
Table 10.8 SMR Settings and Corresponding Data Transfer Formats
SMR
Data Transfer Format
Bit 7 Bit 6
COM CHR
Bit 2
MP
Bit 5
PE
Bit 3
STOP Mode
0
0
0
0
0
1
1
Data Length
Asynchronous 8-bit data
mode
0
Parity Bit
Stop Bit
Length
No
1 bit
2 bits
Yes
1
1
0
2 bits
0
7-bit data
No
1
1
1
0
0
0
1
0
0
0
1
0
1 bit
2 bits
Yes
1
0
1 bit
1 bit
2 bits
Setting prohibited
1
1
1
Asynchronous 5-bit data
mode
No
1 bit
2 bits
Setting prohibited
1
1
1
0
*
*
*
Asynchronous 5-bit data
mode
Synchronous
mode
8-bit data
Yes
1 bit
2 bits
No
No
*: Don’t care
Table 10.9 SMR and SCR3 Settings and Clock Source Selection
SMR
SCR3
Bit 7 Bit 1
Bit 0
Transmit/Receive Clock
COM CKE1 CKE0 Mode
0
0
0
1
Clock Source SCK32 Pin Function
Asynchronous Internal
mode
I/O port (SCK32 pin not used)
Outputs clock with same frequency as bit rate
1
0
1
0
0
1
0
Synchronous
mode
External
Inputs clock with frequency 16 times bit rate
Internal
Outputs serial clock
0
1
1
Reserved (Do not specify these combinations)
External
Inputs serial clock
1
0
1
1
1
1
Rev. 8.00 Mar. 09, 2010 Page 359 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
Interrupts and Continuous Transmission/Reception
SCI3 can carry out continuous reception using RXI and continuous transmission using TXI.
These interrupts are shown in table 10.10.
Table 10.10 Transmit/Receive Interrupts
Interrupt
Flags
Interrupt Request Conditions
Notes
RXI
RDRF
RIE
When serial reception is performed
normally and receive data is transferred
from RSR to RDR, bit RDRF is set to 1,
and if bit RIE is set to 1 at this time, RXI
is enabled and an interrupt is requested.
(See figure 10.2(a).)
The RXI interrupt routine reads the
receive data transferred to RDR and
clears bit RDRF to 0. Continuous
reception can be performed by
repeating the above operations until
reception of the next RSR data is
completed.
TXI
TDRE
TIE
When TSR is found to be empty (on
completion of the previous transmission)
and the transmit data placed in TDR is
transferred to TSR, bit TDRE is set to 1.
If bit TIE is set to 1 at this time, TXI is
enabled and an interrupt is requested.
(See figure 10.2(b).)
The TXI interrupt routine writes the
next transmit data to TDR and clears
bit TDRE to 0. Continuous
transmission can be performed by
repeating the above operations until
the data transferred to TSR has
been transmitted.
TEI
TEND
TEIE
When the last bit of the character in
TSR is transmitted, if bit TDRE is set to
1, bit TEND is set to 1. If bit TEIE is set
to 1 at this time, TEI is enabled and an
interrupt is requested. (See figure
10.2(c).)
TEI indicates that the next transmit
data has not been written to TDR
when the last bit of the transmit
character in TSR is sent.
Rev. 8.00 Mar. 09, 2010 Page 360 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
RDR
RDR
RSR (reception in progress)
RXD32 pin
RSR↑ (reception completed, transfer)
RXD32 pin
RDRF ← 1
(RXI request when RIE = 1)
RDRF = 0
Figure 10.2(a) RDRF Setting and RXI Interrupt
TDR (next transmit data)
TDR
TSR (transmission in progress)
↓
TSR (transmission completed, transfer)
TXD32 pin
TXD32 pin
TDRE ← 1
(TXI request when TIE = 1)
TDRE = 0
Figure 10.2(b) TDRE Setting and TXI Interrupt
TDR
TDR
TSR (transmission in progress)
TSR (reception completed)
TXD32 pin
TXD32 pin
TEND = 0
TEND ← 1
(TEI request when TEIE = 1)
Figure 10.2(c) TEND Setting and TEI Interrupt
Rev. 8.00 Mar. 09, 2010 Page 361 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
10.3.2
Operation in Asynchronous Mode
In asynchronous mode, serial communication is performed with synchronization provided
character by character. A start bit indicating the start of communication and one or two stop bits
indicating the end of communication are added to each character before it is sent.
SCI3 has separate transmission and reception units, allowing full-duplex communication. As the
transmission and reception units are both double-buffered, data can be written during transmission
and read during reception, making possible continuous transmission and reception.
Data Transfer Format
The general data transfer format in asynchronous communication is shown in figure 10.3.
(LSB)
Serial
data
(MSB)
Start
bit
Transmit/receive data
1 bit
5, 7, or 8 bits
1
Parity
bit
1 bit
or none
Stop
bit(s)
Mark
state
1 or 2 bits
One transfer data unit (character or frame)
Figure 10.3 Data Format in Asynchronous Communication
In asynchronous communication, the communication line is normally in the mark state (high
level). SCI3 monitors the communication line and when it detects a space (low level), identifies
this as a start bit and begins serial data communication.
One transfer data character consists of a start bit (low level), followed by transmit/receive data
(LSB-first format, starting from the least significant bit), a parity bit (high or low level), and
finally one or two stop bits (high level).
In asynchronous mode, synchronization is performed by the falling edge of the start bit during
reception. The data is sampled on the 8th pulse of a clock with a frequency 16 times the bit
period, so that the transfer data is latched at the center of each bit.
Rev. 8.00 Mar. 09, 2010 Page 362 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
Table 10.11 shows the 16 data transfer formats that can be set in asynchronous mode. The format
is selected by the settings in the serial mode register (SMR).
Table 10.11 Data Transfer Formats (Asynchronous Mode)
SMR
CHR PE
Serial Data Transfer Format and Frame Length
MP
STOP
1
2
3
4
5
6
7
8
9
10 11 12
0
0
0
0
S
8-bit data
STOP
0
0
0
1
S
8-bit data
STOP STOP
0
0
1
0
0
0
1
1
0
1
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
Setting prohibited
Setting prohibited
S
8-bit data
P
STOP
S
8-bit data
P
STOP STOP
S
5-bit data
STOP
S
5-bit data
STOP STOP
S
7-bit data
STOP
S
7-bit data
STOP STOP
0
1
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
Setting prohibited
Setting prohibited
S
7-bit data
P
STOP
1
S
7-bit data
P
STOP STOP
1
0
S
5-bit data
P
STOP
1
1
S
5-bit data
P
STOP STOP
[Legend]
S:
Start bit
STOP: Stop bit
P:
Parity bit
MPB: Multiprocessor bit
Rev. 8.00 Mar. 09, 2010 Page 363 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
Clock
Either an internal clock generated by the baud rate generator or an external clock input at the
SCK32 pin can be selected as the SCI3 transmit/receive clock. The selection is made by means of
bit COM in SMR and bits SCE1 and CKE0 in SCR3. See table 10.9 for details on clock source
selection.
When an external clock is input at the SCK32 pin, the clock frequency should be 16 times the bit
rate.
When SCI3 operates on an internal clock, the clock can be output at the SCK32 pin. In this case
the frequency of the output clock is the same as the bit rate, and the phase is such that the clock
rises at the center of each bit of transmit/receive data, as shown in figure 10.4.
Clock
Serial
data
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 character (1 frame)
Figure 10.4 Phase Relationship between Output Clock and Transfer Data
(Asynchronous Mode) (8-bit data, parity, 2 stop bits)
Data Transfer Operations
• SCI3 initialization
Before data is transferred on SCI3, bits TE and RE in SCR3 must first be cleared to 0, and then
SCI3 must be initialized as follows.
Note: If the operation mode or data transfer format is changed, bits TE and RE must first be
cleared to 0.
When bit TE is cleared to 0, bit TDRE is set to 1.
Note that the RDRF, PER, FER, and OER flags and the contents of RDR are retained
when RE is cleared to 0.
When an external clock is used in asynchronous mode, the clock should not be stopped
during operation, including initialization. When an external clock is used in synchronous
mode, the clock should not be supplied during operation, including initialization.
Rev. 8.00 Mar. 09, 2010 Page 364 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
Figure 10.5 shows an example of a flowchart for initializing SCI3.
Start
Clear bits TE and
RE to 0 in SCR3
Set bits CKE1
and CKE0
[1]
Set data transfer
format in SMR
[2]
Set value in BRR
[3]
Wait
Has 1-bit period
elapsed?
No
[2] Set the data transfer format in the serial
mode register (SMR).
[3] Write the value corresponding to the
transfer rate in BRR. This operation is
not necessary when an external clock
is selected.
[4] Wait for at least one bit period, then set
bits TIE, RIE, MPIE, and TEIE in SCR3,
and set bits RE or TE to 1 in SCR3.
Setting bits TE and RE enables the TXD32
and RXD32 pins to be used. In asynchronous
mode the mark state is established when
transmitting, and the idle state waiting for
a start bit when receiving.
Yes
Set bit SPC32 to
1 in SPCR
Set bits TIE, RIE,
MPIE, and TEIE in
SCR3, and set bits
RE or TE to 1
in SCR3
[1] Set clock selection in SCR3. Be sure to
clear the other bits to 0. If clock output
is selected in asynchronous mode, the
clock is output immediately after setting
bits CKE1 and CKE0. If clock output is
selected for reception in synchronous
mode, the clock is output immediately
after bits CKE1, CKE0, and RE are
set to 1.
[4]
End
Figure 10.5 Example of SCI3 Initialization Flowchart
Rev. 8.00 Mar. 09, 2010 Page 365 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
• Transmitting
Figure 10.6 shows an example of a flowchart for data transmission. This procedure should be
followed for data transmission after initializing SCI3.
Start
Sets bit SPC32 to
1 in SPCR
Read bit TDRE
in SSR
[1]
No
TDRE = 1?
Yes
Write transmit
data to TDR
[2]
Continue data
transmission?
Yes
[1] Read the serial status register (SSR)
and check that bit TDRE is set to 1,
then write transmit data to the transmit
data register (TDR). When data is
written to TDR, bit TDRE is cleared to 0
automatically.
(After the TE bit is set to 1, one frame of
1s is output, then transmission is possible.)
[2] When continuing data transmission,
be sure to read TDRE = 1 to confirm that
a write can be performed before writing
data to TDR. When data is written to
TDR, bit TDRE is cleared to 0
automatically.
[3] If a break is to be output when data
transmission ends, set the port PCR to 1
and clear the port PDR to 0, then clear bit
TE in SCR3 to 0.
No
Read bit TEND
in SSR
No
TEND = 1?
Yes
[3]
Break output?
No
Yes
Set PDR = 0,
PCR = 1
Clear bit TE to 0
in SCR3
End
Figure 10.6 Example of Data Transmission Flowchart (Asynchronous Mode)
Rev. 8.00 Mar. 09, 2010 Page 366 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
SCI3 operates as follows when transmitting data.
SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written
to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If
bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Serial data is transmitted from the TXD32 pin using the relevant data transfer format in table 10.11.
When the stop bit is sent, SCI3 checks bit TDRE. If bit TDRE is cleared to 0, SCI3 transfers data
from TDR to TSR, and when the stop bit has been sent, starts transmission of the next frame. If
bit TDRE is set to 1, bit TEND in SSR bit is set to 1the mark state, in which 1s are transmitted, is
established after the stop bit has been sent. If bit TEIE in SCR3 is set to 1 at this time, a TEI
request is made.
Figure 10.7 shows an example of the operation when transmitting in asynchronous mode.
Start
bit
Serial
data
1
0
Transmit
data
D0
D1
D7
Parity Stop Start
bit
bit bit
0/1
1
0
1 frame
Transmit
data
D0
D1
D7
Parity Stop
bit
bit
0/1
1
Mark
state
1
1 frame
TDRE
TEND
LSI
TXI request
operation
TDRE
cleared to 0
User
processing
Data written
to TDR
TXI request
TEI request
Figure 10.7 Example of Operation when Transmitting in Asynchronous Mode
(8-bit data, parity, 1 stop bit)
Rev. 8.00 Mar. 09, 2010 Page 367 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
• Receiving
Figure 10.8 shows an example of a flowchart for data reception. This procedure should be
followed for data reception after initializing SCI3.
Start
Read bits OER,
PER, FER in SSR
[1] Read bits OER, PER, and FER in the
serial status register (SSR) to determine
if there is an error. If a receive error has
occurred, execute receive error
processing.
[1]
Yes
OER + PER
+ FER = 1?
[2] Read SSR and check that bit RDRF is
set to 1. If it is, read the receive data
in RDR. When the RDR data is read,
bit RDRF is cleared to 0 automatically.
No
Read bit RDRF
in SSR
[2]
[3] When continuing data reception, finish
reading of bit RDRF and RDR before
receiving the stop bit of the current
frame. When the data in RDR is read,
bit RDRF is cleared to 0 automatically.
No
RDRF = 1?
Yes
Read receive
data in RDR
Receive error
processing
[4]
[3]
Continue data
reception?
Yes
No
(A)
Clear bit RE to
0 in SCR3
End
Figure 10.8 Example of Data Reception Flowchart (Asynchronous Mode)
Rev. 8.00 Mar. 09, 2010 Page 368 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
Start receive
error processing
[4]
Overrun error
processing
OER = 1?
Yes
No
FER = 1?
Break?
Yes
No
No
PER = 1?
Yes
[4] If a receive error has
occurred, read bits OER,
PER, and FER in SSR to
identify the error, and after
carrying out the necessary
error processing, ensure
that bits OER, PER, and
FER are all cleared to 0.
Yes
Reception cannot be
resumed if any of these
bits is set to 1. In the case
of a framing error, a break
can be detected by reading
the value of the RXD32 pin.
Framing error
processing
No
Clear bits OER, PER,
FER to 0 in SSR
Parity error
processing
(A)
End of receive
error processing
Figure 10.8 Example of Data Reception Flowchart (Asynchronous Mode) (cont)
Rev. 8.00 Mar. 09, 2010 Page 369 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
SCI3 operates as follows when receiving data.
SCI3 monitors the communication line, and when it detects a 0 start bit, performs internal
synchronization and begins reception. Reception is carried out in accordance with the relevant
data transfer format in table 10.11. The received data is first placed in RSR in LSB-to-MSB order,
and then the parity bit and stop bit(s) are received. SCI3 then carries out the following checks.
• Parity check
SCI3 checks that the number of 1 bits in the receive data conforms to the parity (odd or even)
set in bit PM in the serial mode register (SMR).
• Stop bit check
SCI3 checks that the stop bit is 1. If two stop bits are used, only the first is checked.
• Status check
SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred from
RSR to RDR.
If no receive error is found in the above checks, bit RDRF is set to 1, and the receive data is stored
in RDR. If bit RIE is set to 1 in SCR3, an RXI interrupt is requested. If the error checks identify
a receive error, bit OER, PER, or FER is set to 1 depending on the kind of error. Bit RDRF retains
its state prior to receiving the data. If bit RIE is set to 1 in SCR3, an ERI interrupt is requested.
Table 10.12 shows the conditions for detecting a receive error, and receive data processing.
Note: No further receive operations are possible while a receive error flag is set. Bits OER,
FER, PER, and RDRF must therefore be cleared to 0 before resuming reception.
Table 10.12 Receive Error Detection Conditions and Receive Data Processing
Receive Error Abbr.
Detection Conditions
Receive Data Processing
Overrun error
OER
When the next date receive
operation is completed while bit
RDRF is still set to 1 in SSR
Receive data is not transferred
from RSR to RDR
Framing error
FER
When the stop bit is 0
Receive data is transferred
from RSR to RDR
Parity error
PER
When the parity (odd or even) set Receive data is transferred
in SMR is different from that of
from RSR to RDR
the received data
Rev. 8.00 Mar. 09, 2010 Page 370 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
Figure 10.9 shows an example of the operation when receiving in asynchronous mode.
Start
bit
Serial
data
1
0
Receive
data
D0
D1
D7
Parity Stop Start
bit
bit bit
0/1
1
0
1 frame
Receive
data
D0
D1
Parity Stop
bit
bit
D7
0/1
0
Mark state
(idle state)
1
1 frame
RDRF
FER
RXI request
LSI
operation
User
processing
RDRF
cleared to 0
RDR data read
0 start bit
detected
ERI request in
response to
framing error
Framing error
processing
Figure 10.9 Example of Operation when Receiving in Asynchronous Mode
(8-Bit Data, Parity, 1 Stop Bit)
10.3.3
Operation in Synchronous Mode
In synchronous mode, SCI3 transmits and receives data in synchronization with clock pulses.
This mode is suitable for high-speed serial communication.
SCI3 has separate transmission and reception units, allowing full-duplex communication with a
shared clock.
As the transmission and reception units are both double-buffered, data can be written during
transmission and read during reception, making possible continuous transmission and reception.
Rev. 8.00 Mar. 09, 2010 Page 371 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
Data Transfer Format
The general data transfer format in asynchronous communication is shown in figure 10.10.
*
*
Serial
clock
LSB
Serial
data
Bit 0
MSB
Bit 1
Bit 2
Don't
care
Bit 3
Bit 4
Bit 5
Bit 6
8 bits
Bit 7
Don't
care
One transfer data unit (character or frame)
Note: * High level except in continuous transmission/reception
Figure 10.10 Data Format in Synchronous Communication
In synchronous communication, data on the communication line is output from one falling edge of
the serial clock until the next falling edge. Data confirmation is guaranteed at the rising edge of
the serial clock.
One transfer data character begins with the LSB and ends with the MSB. After output of the
MSB, the communication line retains the MSB state.
When receiving in synchronous mode, SCI3 latches receive data at the rising edge of the serial
clock.
The data transfer format uses a fixed 8-bit data length.
Parity bit cannot be added.
Clock
Either an internal clock generated by the baud rate generator or an external clock input at the
SCK32 pin can be selected as the SCI3 serial clock. The selection is made by means of bit COM in
SMR and bits CKE1 and CKE0 in SCR3. See table 10.9 for details on clock source selection.
When SCI3 operates on an internal clock, the serial clock is output at the SCK32 pin. Eight pulses
of the serial clock are output in transmission or reception of one character, and when SCI3 is not
transmitting or receiving, the clock is fixed at the high level.
Rev. 8.00 Mar. 09, 2010 Page 372 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
Data Transfer Operations
• SCI3 initialization
Data transfer on SCI3 first of all requires that SCI3 be initialized as described in section 10.3.2,
SCI3 initialization, and shown in figure 10.5.
• Transmitting
Figure 10.11 shows an example of a flowchart for data transmission. This procedure should be
followed for data transmission after initializing SCI3.
Start
Sets bit SPC32 to
1 in SPCR
Read bit TDRE
in SSR
[1]
No
TDRE = 1?
Yes
[2] When continuing data transmission, be
sure to read TDRE = 1 to confirm that
a write can be performed before writing
data to TDR. When data is written to
TDR, bit TDRE is cleared to 0 automatically.
Write transmit
data to TDR
[2]
Continue data
transmission?
[1] Read the serial status register (SSR) and
check that bit TDRE is set to 1, then write
transmit data to the transmit data register
(TDR). When data is written to TDR, bit
TDRE is cleared to 0 automatically, the
clock is output, and data transmission is
started. When clock output is selected,
the clock is output and data transmission
started when data is written to TDR.
Yes
No
Read bit TEND
in SSR
TEND = 1?
No
Yes
Clear bit TE to 0
in SCR3
End
Figure 10.11 Example of Data Transmission Flowchart (Synchronous Mode)
Rev. 8.00 Mar. 09, 2010 Page 373 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
SCI3 operates as follows when transmitting data.
SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written
to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If
bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
When clock output mode is selected, SCI3 outputs 8 serial clock pulses. When an external clock
is selected, data is output in synchronization with the input clock.
Serial data is transmitted from the TXD32 pin in order from the LSB (bit 0) to the MSB (bit 7).
When the MSB (bit 7) is sent, checks bit TDRE. If bit TDRE is cleared to 0, SCI3 transfers data
from TDR to TSR, and starts transmission of the next frame. If bit TDRE is set to 1, SCI3 sets bit
TEND to 1 in SSR, and after sending the MSB (bit 7), retains the MSB state. If bit TEIE in SCR3
is set to 1 at this time, a TEI request is made.
After transmission ends, the SCK pin is fixed at the high level.
Note: Transmission is not possible if an error flag (OER, FER, or PER) that indicates the data
reception status is set to 1. Check that these error flags are all cleared to 0 before a
transmit operation.
Figure 10.12 shows an example of the operation when transmitting in synchronous mode.
Serial
clock
Serial
data
Bit 0
Bit 1
Bit 7
1 frame
Bit 0
Bit 1
Bit 6
Bit 7
1 frame
TDRE
TEND
LSI
TXI request
operation
TDRE cleared
to 0
User
processing
Data written
to TDR
TXI request
TEI request
Figure 10.12 Example of Operation when Transmitting in Synchronous Mode
Rev. 8.00 Mar. 09, 2010 Page 374 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
• Receiving
Figure 10.13 shows an example of a flowchart for data reception. This procedure should be
followed for data reception after initializing SCI3.
Start
Read bit OER
in SSR
[1]
[1] Read bit OER in the serial status register
(SSR) to determine if there is an error.
If an overrun error has occurred, execute
overrun error processing.
Yes
OER = 1?
[2] Read SSR and check that bit RDRF is
set to 1. If it is, read the receive data in
RDR. When the RDR data is read, bit
RDRF is cleared to 0 automatically.
No
Read bit RDRF
in SSR
[2]
[3] When continuing data reception, finish
reading of bit RDRF and RDR before
receiving the MSB (bit 7) of the current
frame. When the data in RDR is read,
bit RDRF is cleared to 0 automatically.
No
RDRF = 1?
Yes
Read receive
data in RDR
[4]
[4] If an overrun error has occurred, read bit
OER in SSR, and after carrying out the
necessary error processing, clear bit OER
to 0. Reception cannot be resumed if bit
OER is set to 1.
Overrun error
processing
[3]
Continue data
reception?
Yes
No
Clear bit RE to
0 in SCR3
End
4
Start overrun
error processing
Overrun error
processing
Clear bit OER to
0 in SSR
End of overrun
error processing
Figure 10.13 Example of Data Reception Flowchart (Synchronous Mode)
Rev. 8.00 Mar. 09, 2010 Page 375 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
SCI3 operates as follows when receiving data.
SCI3 performs internal synchronization and begins reception in synchronization with the serial
clock input or output.
The received data is placed in RSR in LSB-to-MSB order.
After the data has been received, SCI3 checks that bit RDRF is set to 0, indicating that the receive
data can be transferred from RSR to RDR.
If this check shows that there is no overrun error, bit RDRF is set to 1, and the receive data is
stored in RDR. If bit RIE is set to 1 in SCR3, an RXI interrupt is requested. If the check
identifies an overrun error, bit OER is set to 1.
Bit RDRF remains set to 1. If bit RIE is set to 1 in SCR3, an ERI interrupt is requested.
See table 10.12 for the conditions for detecting a receive error, and receive data processing.
Note: No further receive operations are possible while a receive error flag is set. Bits OER,
FER, PER, and RDRF must therefore be cleared to 0 before resuming reception.
Figure 10.14 shows an example of the operation when receiving in synchronous mode.
Serial
clock
Serial
data
Bit 7
Bit 0
Bit 7
Bit 0
1 frame
Bit 1
Bit 6
Bit 7
1 frame
RDRF
OER
LSI
operation
RXI request
User
processing
RDRE cleared
to 0
RDR data read
RXI request
ERI request in
response to
overrun error
RDR data has
not been read
(RDRF = 1)
Overrun error
processing
Figure 10.14 Example of Operation when Receiving in Synchronous Mode
Rev. 8.00 Mar. 09, 2010 Page 376 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
• Simultaneous transmit/receive
Figure 10.15 shows an example of a flowchart for a simultaneous transmit/receive operation. This
procedure should be followed for simultaneous transmission/reception after initializing SCI3.
Start
Sets bit SPC32 to
1 in SPCR
Read bit TDRE
in SSR
[1] Read the serial status register (SSR) and
check that bit TDRE is set to 1, then write
transmit data to the transmit data register
(TDR). When data is written to TDR, bit
TDRE is cleared to 0 automatically.
[1]
No
TDRE = 1?
[2] Read SSR and check that bit RDRF is set
to 1. If it is, read the receive data in RDR.
When the RDR data is read, bit RDRF is
cleared to 0 automatically.
Yes
Write transmit
data to TDR
[3] When continuing data transmission/reception,
finish reading of bit RDRF and RDR before
receiving the MSB (bit 7) of the current frame.
Before receiving the MSB (bit 7) of the current
frame, also read TDRE = 1 to confirm that a
write can be performed, then write data to TDR.
When data is written to TDR, bit TDRE is cleared
to 0 automatically, and when the data in RDR is
read, bit RDRF is cleared to 0 automatically.
Read bit OER
in SSR
Yes
OER = 1?
[4] If an overrun error has occurred, read bit OER
in SSR, and after carrying out the necessary
error processing, clear bit OER to 0. Transmission and reception cannot be resumed if bit
OER is set to 1.
See figure 10.13 for details on overrun error
processing.
No
Read bit RDRF
in SSR
[2]
RDRF = 1?
No
Yes
Read receive data
in RDR
[4]
Overrun error
processing
[3]
Continue data
transmission/reception?
Yes
No
Clear bits TE and
RE to 0 in SCR3
End
Figure 10.15 Example of Simultaneous Data Transmission/Reception Flowchart
(Synchronous Mode)
Rev. 8.00 Mar. 09, 2010 Page 377 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
Notes: 1. When switching from transmission to simultaneous transmission/reception, check that
SCI3 has finished transmitting and that bits TDRE and TEND are set to 1, clear bit TE
to 0, and then set bits TE and RE to 1 simultaneously.
2. When switching from reception to simultaneous transmission/reception, check that
SCI3 has finished receiving, clear bit RE to 0, then check that bit RDRF and the error
flags (OER, FER, and PER) are cleared to 0, and finally set bits TE and RE to 1
simultaneously.
Rev. 8.00 Mar. 09, 2010 Page 378 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
10.4
Interrupts
SCI3 can generate six kinds of interrupts: transmit end, transmit data empty, receive data full, and
three receive error interrupts (overrun error, framing error, and parity error). These interrupts have
the same vector address.
The various interrupt requests are shown in table 10.13.
Table 10.13 SCI3 Interrupt Requests
Interrupt Abbr. Interrupt Request
Vector
Address
RXI
Interrupt request initiated by receive data full flag (RDRF)
H'0024
TXI
Interrupt request initiated by transmit data empty flag (TDRE)
TEI
Interrupt request initiated by transmit end flag (TEND)
ERI
Interrupt request initiated by receive error flag (OER, FER, PER)
Each interrupt request can be enabled or disabled by means of bits TIE and RIE in SCR3.
When bit TDRE is set to 1 in SSR, a TXI interrupt is requested. When bit TEND is set to 1 in
SSR, a TEI interrupt is requested. These two interrupts are generated during transmission.
The initial value of bit TDRE in SSR is 1. Therefore, if the transmit data empty interrupt request
(TXI) is enabled by setting bit TIE to 1 in SCR3 before transmit data is transferred to TDR, a TXI
interrupt will be requested even if the transmit data is not ready.
Also, the initial value of bit TEND in SSR is 1. Therefore, if the transmit end interrupt request
(TEI) is enabled by setting bit TEIE to 1 in SCR3 before transmit data is transferred to TDR, a
TEI interrupt will be requested even if the transmit data has not been sent.
Effective use of these interrupt requests can be made by having processing that transfers transmit
data to TDR carried out in the interrupt service routine.
To prevent the generation of these interrupt requests (TXI and TEI), on the other hand, the enable
bits for these interrupt requests (bits TIE and TEIE) should be set to 1 after transmit data has been
transferred to TDR.
When bit RDRF is set to 1 in SSR, an RXI interrupt is requested, and if any of bits OER, PER, and
FER is set to 1, an ERI interrupt is requested. These two interrupt requests are generated during
reception.
For further details, see section 3.3, Interrupts.
Rev. 8.00 Mar. 09, 2010 Page 379 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
10.5
Application Notes
The following points should be noted when using SCI3.
1. Relation between writes to TDR and bit TDRE
Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial
transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared to
0 automatically. When SCI3 transfers data from TDR to TSR, bit TDRE is set to 1.
Data can be written to TDR irrespective of the state of bit TDRE, but if new data is written to
TDR while bit TDRE is cleared to 0, the data previously stored in TDR will be lost of it has not
yet been transferred to TSR. Accordingly, to ensure that serial transmission is performed
dependably, you should first check that bit TDRE is set to 1, then write the transmit data to TDR
once only (not two or more times).
2. Operation when a number of receive errors occur simultaneously
If a number of receive errors are detected simultaneously, the status flags in SSR will be set to the
states shown in table 10.14. If an overrun error is detected, data transfer from RSR to RDR will
not be performed, and the receive data will be lost.
Table 10.14 SSR Status Flag States and Receive Data Transfer
SSR Status Flags
RDRF* OER
FER
PER
Receive Data Transfer
RSR → RDR
Receive Error Status
1
1
0
0
X
Overrun error
0
0
1
0
O
Framing error
0
0
0
1
O
Parity error
1
1
1
0
X
Overrun error + framing error
1
1
0
1
X
Overrun error + parity error
0
0
1
1
O
Framing error + parity error
1
1
1
1
X
Overrun error + framing error + parity error
O : Receive data is transferred from RSR to RDR.
X : Receive data is not transferred from RSR to RDR.
Note: * Bit RDRF retains its state prior to data reception. However, note that if RDR is read after
an overrun error has occurred in a frame because reading of the receive data in the
previous frame was delayed, RDRF will be cleared to 0.
Rev. 8.00 Mar. 09, 2010 Page 380 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
3. Break detection and processing
When a framing error is detected, a break can be detected by reading the value of the RXD32 pin
directly. In a break, the input from the RXD32 pin becomes all 0s, with the result that bit FER is
set and bit PER may also be set.
SCI3 continues the receive operation even after receiving a break. Note, therefore, that even
though bit FER is cleared to 0 it will be set to 1 again.
4. Mark state and break detection
When bit TE is cleared to 0, the TXD32 pin functions as an I/O port whose input/output direction
and level are determined by PDR and PCR. This fact can be used to set the TXD32 pin to the mark
state, or to detect a break during transmission.
To keep the communication line in the mark state (1 state) until bit TE is set to 1, set PCR = 1 and
PDR = 1. Since bit TE is cleared to 0 at this time, the TXD32 pin functions as an I/O port and 1 is
output.
To detect a break, clear bit TE to 0 after setting PCR = 1 and PDR = 0.
When bit TE is cleared to 0, the transmission unit is initialized regardless of the current
transmission state, the TXD32 pin functions as an I/O port, and 0 is output from the TXD32 pin.
5. Receive error flags and transmit operation (synchronous mode only)
When a receive error flag (OER, PER, or FER) is set to 1, transmission cannot be started even if
bit TDRE is cleared to 0. The receive error flags must be cleared to 0 before starting transmission.
Note also that receive error flags cannot be cleared to 0 even if bit RE is cleared to 0.
6. Receive data sampling timing and receive margin in asynchronous mode
In asynchronous mode, SCI3 operates on a basic clock with a frequency 16 times the transfer rate.
When receiving, SCI3 performs internal synchronization by sampling the falling edge of the start
bit with the basic clock. Receive data is latched internally at the 8th rising edge of the basic clock.
This is illustrated in figure 10.16.
Rev. 8.00 Mar. 09, 2010 Page 381 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
16 clock pulses
8 clock pulses
0
7
15 0
7
15 0
Internal
basic clock
Receive data
(RXD32)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 10.16 Receive Data Sampling Timing in Asynchronous Mode
Consequently, the receive margin in asynchronous mode can be expressed as shown in equation
(1).
M ={(0.5 –
where
1
D – 0.5
)–
– (L – 0.5) F} × 100 [%]
2N
N
..... Equation (1)
M: Receive margin (%)
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock frequency deviation
Substituting 0 for F (absolute value of clock frequency deviation) and 0.5 for D (clock duty) in
equation (1), a receive margin of 46.875% is given by equation (2).
When D = 0.5 and F = 0,
M = {0.5 – 1/(2 × 16)} × 100 [%]
= 46.875%
.... Equation (2)
However, this is only a computed value, and a margin of 20% to 30% should be allowed when
carrying out system design.
Rev. 8.00 Mar. 09, 2010 Page 382 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
7. Relation between RDR reads and bit RDRF
In a receive operation, SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0 when
reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1, this
indicates that an overrun error has occurred.
When the contents of RDR are read, bit RDRF is cleared to 0 automatically. Therefore, if bit
RDR is read more than once, the second and subsequent read operations will be performed while
bit RDRF is cleared to 0. Note that, when an RDR read is performed while bit RDRF is cleared to
0, if the read operation coincides with completion of reception of a frame, the next frame of data
may be read. This is illustrated in figure 10.17.
Communication
line
Frame 1
Frame 2
Frame 3
Data 1
Data 2
Data 3
Data 1
Data 2
RDRF
RDR
(A)
RDR read
(B)
RDR read
Data 1 is read at point (A)
Data 2 is read at point (B)
Figure 10.17 Relation between RDR Read Timing and Data
In this case, only a single RDR read operation (not two or more) should be performed after first
checking that bit RDRF is set to 1. If two or more reads are performed, the data read the first time
should be transferred to RAM, etc., and the RAM contents used. Also, ensure that there is
sufficient margin in an RDR read operation before reception of the next frame is completed. To
be precise in terms of timing, the RDR read should be completed before bit 7 is transferred in
synchronous mode, or before the STOP bit is transferred in asynchronous mode.
Rev. 8.00 Mar. 09, 2010 Page 383 of 658
REJ09B0042-0800
Section 10 Serial Communication Interface
8. Transmit and receive operations when making a state transition
Make sure that transmit and receive operations have completely finished before carrying out state
transition processing.
9. Switching SCK32 function
If pin SCK32 is used as a clock output pin by SCI3 in synchronous mode and is then switched to a
general input/output pin (a pin with a different function), the pin outputs a low level signal for half
a system clock (φ) cycle immediately after it is switched.
This can be prevented by either of the following methods according to the situation.
a. When an SCK32 function is switched from clock output to non clock-output
When stopping data transfer, issue one instruction to clear bits TE and RE to 0 and to set bits
CKE1 and CKE0 in SCR3 to 1 and 0, respectively. In this case, bit COM in SMR should be
left 1. The above prevents SCK32 from being used as a general input/output pin. To avoid an
intermediate level of voltage from being applied to SCK32, the line connected to SCK32 should
be pulled up to the VCC level via a resistor, or supplied with output from an external device.
b. When an SCK32 function is switched from clock output to general input/output
When stopping data transfer,
(i) Issue one instruction to clear bits TE and RE to 0 and to set bits CKE1 and CKE0 in SCR3
to 1 and 0, respectively.
(ii) Clear bit COM in SMR to 0
(iii) Clear bits CKE1 and CKE0 in SCR3 to 0
Note that special care is also needed here to avoid an intermediate level of voltage from being
applied to SCK32.
10. Set up at subactive or subsleep mode
At subactive or subsleep mode, SCI3 becomes possible use only at CPU clock is φw/2.
11. Oscillator use with serial communications interface (H8/38124 Group only)
When implementing the serial communications interface on the H8/38124 Group, the system
clock oscillator must be used. The on-chip oscillator should not be used in this case. See on-chip
oscillator selection method in section 4.2, System Clock Generator, for information on switching
between the system clock oscillator and the on-chip oscillator.
Rev. 8.00 Mar. 09, 2010 Page 384 of 658
REJ09B0042-0800
Section 11 10-Bit PWM
Section 11 10-Bit PWM
11.1
Overview
The H8/38024 Group is provided with two on-chip 10-bit PWMs (pulse width modulators),
designated PWM1 and PWM2, with identical functions. The PWMs can be used as D/A
converters by connecting a low-pass filter. In this section the suffix m (m = 1 or 2) is used with
register names, etc., as in PWDRLm, which denotes the PWDRL registers for each PWM.
11.1.1
Features
Features of the 10-bit PWMs are as follows.
• Choice of four conversion periods
Any of the following conversion periods can be chosen:
4,096/φ, with a minimum modulation width of 4/φ
2,048/φ, with a minimum modulation width of 2/φ
1,024/φ, with a minimum modulation width of 1/φ
512/φ, with a minimum modulation width of 1/2 φ
• Pulse division method for less ripple
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
On the H8/38124 Group it is possible to select between two types of PWM output: pulse-division
PWM and event counter PWM (PWM incorporating AEC). (The H8/38024 Group, H8/38024FZTAT Group, and H8/38024S Group can only produce pulse-division PWM output.) Refer to
section 9.7, Asynchronous Event Counter, for information on event counter PWM.
Rev. 8.00 Mar. 09, 2010 Page 385 of 658
REJ09B0042-0800
Section 11 10-Bit PWM
11.1.2
Block Diagram
Figure 11.1(1) shows a block diagram of the 10-bit PWM of the H8/38024 Group, H8/38024FZTAT Group, and H8/38024S Group. Figure 11.1(2) shows a block diagram of the 10-bit PWM of
the H8/38124 Group.
PWDRLm
φ/2
φ/4
φ/8
φ
Internal data bus
PWDRUm
PWM
waveform
generator
PWCRm
PWMm
[Legend]
PWDRLm: PWM data register L
PWDRUm: PWM data register U
PWCRm: PWM control register
m = 1 or 2
Figure 11.1(1) Block Diagram of the 10-bit PWM
(H8/38024 Group, H8/38024F-ZTAT Group, and H8/38024S Group: 1-Channel
Configuration)
Rev. 8.00 Mar. 09, 2010 Page 386 of 658
REJ09B0042-0800
Section 11 10-Bit PWM
PWDRUm
φ/2
φ/4
φ/8
φ
PWM waveform
generator
Internal data bus
PWDRLm
PWCRm
IECPWM
PWMm
(IECPWM)
[Legend]
PWCRm:
PWDRLm:
PWDRUm:
PWMm:
IECPWM:
m = 1 or 2
PWM control register
PWM data register L
PWM data register U
PWM output pin
Event counter PWM (PWM incorporating AEC)
Figure 11.1(2) Figure 11.1(1) Block Diagram of the 10-bit PWM
(H8/38124 Group: 1-Channel Configuration)
11.1.3
Pin Configuration
Table 11.1 shows the output pin assigned to the 10-bit PWM.
Table 11.1 Pin Configuration
Name
Abbr.
I/O
Function
PWM1 output pin
PWM1
Output
Pulse-division PWM waveform output (PWM1)/
event counter PWM output (IECPWM)*
PWM2 output pin
PWM2
Output
Pulse-division PWM waveform output (PWM2)/
event counter PWM output (IECPWM)*
Note: * Implemented on H8/38124 Group only.
Rev. 8.00 Mar. 09, 2010 Page 387 of 658
REJ09B0042-0800
Section 11 10-Bit PWM
11.1.4
Register Configuration
Table 11.2 shows the register configuration of the 10-bit PWM.
Table 11.2 Register Configuration
Name
Abbr.
R/W
Initial Value
Address
W
H'FC/H'F8*
H'FFD0
PWM1 control register
PWCR1
PWM1 data register U
PWDRU1
W
H'FC
H'FFD1
PWM1 data register L
PWDRL1
W
H'00
H'FFD2
PWM2 control register
PWCR2
W
H'FC/H'F8*
H'FFCD
PWM2 data register U
PWDRU2
W
H'FC
H'FFCE
PWM2 data register L
PWDRL2
W
H'00
H'FFCF
Clock stop register 2
CKSTPR2
R/W
H'FF
H'FFFB
Note: * Implemented on H8/38124 Group only.
11.2
Register Descriptions
11.2.1
PWM Control Register (PWCRm)
Bit
7
6
5
4
3
⎯
⎯
⎯
⎯
⎯
Initial value
1
1
1
1
1
Read/Write
⎯
⎯
⎯
⎯
⎯
2
1
0
⎯/
PWCRm2* PWCRm1 PWCRm0
1/0*
0
0
⎯ /W*
W
W
Note: * Implemented on H8/38124 Group only.
On the H8/38024 Group, H8/38024F-ZTAT Group, and H8/38024S Group, PWCRm is an 8-bit
write-only register for input clock selection.
Upon reset, PWCRm is initialized to H'FC. On the H8/38124 Group, PWCRm is an 8-bit writeonly register used to select the input clock and PWM output type. At reset PWCRm is initialized
to H'F8.
Rev. 8.00 Mar. 09, 2010 Page 388 of 658
REJ09B0042-0800
Section 11 10-Bit PWM
Bits 7 to 2—Reserved/Bits 7 to 3—Reserved*
Bits 7 to 2 are reserved; they are always read as 1, and cannot be modified.
Note: * Implemented on H8/38124 Group only.
Bit 2—Output Format Select (PWCRm2)*
This bit selects the format of the output from the PWMm output pin.
This bit is write-only. Reading it always returns 1.
Bit 2
PWCRm2
Description
0
Pulse-division PWM
1
Event counter PWM
(initial value)
Note: * Implemented on H8/38124 Group only.
Bits 1 and 0—Clock Select 1 and 0 (PWCRm1, PWCRm0)
Bits 1 and 0 select the clock supplied to the 10-bit PWM. These bits are write-only bits; they are
always read as 1.
Bit 1
Bit 0
PWCRm1 PWCRm0 Description
0
0
0
1
1
0
1
1
The input clock is φ (tφ* = 1/φ)
The conversion period is 512/φ, with a minimum modulation
width of 1/2φ
The input clock is φ/2 (tφ* = 2/φ)
The conversion period is 1,024/φ, with a minimum
modulation width of 1/φ
The input clock is φ/4 (tφ* = 4/φ)
The conversion period is 2,048/φ, with a minimum
modulation width of 2/φ
The input clock is φ/8 (tφ* = 8/φ)
The conversion period is 4,096/φ, with a minimum
modulation width of 4/φ
(initial value)
Note: * Period of PWM input clock.
Rev. 8.00 Mar. 09, 2010 Page 389 of 658
REJ09B0042-0800
Section 11 10-Bit PWM
11.2.2
PWM Data Registers U and L (PWDRUm, PWDRLm)
PWDRUm
Bit
7
6
5
4
3
2
⎯
⎯
⎯
⎯
⎯
⎯
Initial value
1
1
1
1
1
1
0
0
Read/Write
⎯
⎯
⎯
⎯
⎯
⎯
W
W
7
6
5
4
3
2
1
0
1
0
PWDRUm1 PWDRUm0
PWDRLm
Bit
PWDRLm7 PWDRLm6 PWDRLm5 PWDRLm4 PWDRLm3 PWDRLm2 PWDRLm1 PWDRLm0
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PWDRUm and PWDRLm form a 10-bit write-only register, with the upper 2 bits assigned to
PWDRUm and the lower 8 bits to PWDRLm. The value written to PWDRUm and PWDRLm
gives the total high-level width of one PWM waveform cycle.
When 10-bit data is written to PWDRUm and PWDRLm, the register contents are latched in the
PWM waveform generator, updating the PWM waveform generation data. The 10-bit data should
always be written in the following sequence:
1. Write the lower 8 bits to PWDRLm.
2. Write the upper 2 bits to PWDRUm for the same channel.
PWDRUm and PWDRLm are write-only registers. If they are read, all bits are read as 1.
Upon reset, PWDRUm is initialized to H'FC, and PWDRLm to H'00.
Rev. 8.00 Mar. 09, 2010 Page 390 of 658
REJ09B0042-0800
Section 11 10-Bit PWM
11.2.3
Clock Stop Register 2 (CKSTPR2)
7
6
5
LVDCKSTP*
—
—
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
—
—
R/W
R/W
R/W
R/W
R/W
Bit
4
3
2
1
0
PW2CKSTP AECKSTP WDCKSTP PW1CKSTP LDCKSTP
Note: * Bits 6 and 5 are also reserved on products other than the H8/38124 Group.
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the PWM is described here. For details of the other bits, see the
sections on the relevant modules.
Bits 4 and 1—PWM Module Standby Mode Control (PWmCKSTP)
Bits 4 and 1 control setting and clearing of module standby mode for the PWMm.
PWmCKSTP
Description
0
PWMm is set to module standby mode
1
PWMm module standby mode is cleared
(initial value)
Rev. 8.00 Mar. 09, 2010 Page 391 of 658
REJ09B0042-0800
Section 11 10-Bit PWM
11.3
Operation
11.3.1
Operation
When using the 10-bit PWM, set the registers in the following sequence.
1. Set PWM1 or PWM2 in PMR9 to 1 for the PWM channel to be used, so that pin P90/PWM1 or
P91/PWM2 is designated as the PWM output pin, or both are designated as PWM output pins.
2. Set bits PWCRm1 and PWCRm0 in the PWM control register (PWCRm) to select a
conversion period of 4,096/φ (PWCRm1 = 1, PWCRm0 = 1), 2,048/φ (PWCRm1 = 1,
PWCRm0 = 0), 1,024/φ (PWCRm1 = 0, PWCRm0 = 1), or 512/φ (PWCRm1 = 0, PWCRm0 =
0). In the case of the H8/38124 Group, select between pulse-division PWM (PWCRm2 = 0)
and event counter PWM (PWCRm2 = 1) output. Refer to section 9.7, Asynchronous Event
Counter (AEC), for information on the event counter PWM (PWM incorporating AEC) output
format.
3. Set the output waveform data in PWDRUm and PWDRLm. Be sure to write in the correct
sequence, first PWDRLm then PWDRUm for the same channel. When data is written to
PWDRUm, the data will be latched in the PWM waveform generator, updating the PWM
waveform generation in synchronization with internal signals.
One conversion period consists of 4 pulses, as shown in figure 11.2. The total of the high-level
pulse widths during this period (TH) corresponds to the data in PWDRUm and PWDRLm.
This relation can be represented as follows.
TH = (data value in PWDRUm and PWDRLm + 4) × tφ/2
where tφ is the PWM input clock period: 1/φ (PWCRm = H'0), 2/φ (PWCRm = H'1), 4/φ
(PWCRm = H'2), or 8/φ (PWCRm = H'3).
Example: Settings in order to obtain a conversion period of 1,024 µs:
When PWCRm1 = 0 and PWCRm0 = 0, the conversion period is 512/φ, so φ must be
0.5 MHz. In this case, tfn = 256 µs, with 1/2φ (resolution) = 1.0 µs.
When PWCRm1 = 0 and PWCRm0 = 1, the conversion period is 1,024/φ, so φ must be
1 MHz. In this case, tfn = 256 µs, with 1/φ (resolution) = 1.0 µs.
When PWCRm1 = 1 and PWCRm0 = 0, the conversion period is 2,048/φ , so φ must
be 2 MHz. In this case, tfn = 256 µs, with 2/φ (resolution) = 1.0 µs.
When PWCRm1 = 1 and PWCRm0 = 1, the conversion period is 4,096/φ, so φ must be
4 MHz. In this case, tfn = 256 µs, with 4/φ (resolution) = 1.0 µs
Accordingly, for a conversion period of 1,024 µs, the system clock frequency (φ) must
be 0.5 MHz, 1 MHz, 2 MHz, or 4 MHz.
Rev. 8.00 Mar. 09, 2010 Page 392 of 658
REJ09B0042-0800
Section 11 10-Bit PWM
1 conversion period
tf2
tf3
tf1
tH1
tH2
tH3
tf4
tH4
TH = tH1 + tH2 + tH3 + tH4
tf1 = tf2 = tf3 = tf4
Figure 11.2 PWM Output Waveform
11.3.2
PWM Operation Modes
PWM operation modes are shown in table 11.3.
Table 11.3 PWM Operation Modes
Operation
Mode
Reset
Active
PWCRm
Functions Functions Retained Retained Retained Retained Retained
Reset
Sleep
Watch
Subactive
Subsleep
Standby
Module
Standby
PWDRUm Reset
Functions Functions Retained Retained Retained Retained Retained
PWDRLm Reset
Functions Functions Retained Retained Retained Retained Retained
Rev. 8.00 Mar. 09, 2010 Page 393 of 658
REJ09B0042-0800
Section 11 10-Bit PWM
Rev. 8.00 Mar. 09, 2010 Page 394 of 658
REJ09B0042-0800
Section 12 A/D Converter
Section 12 A/D Converter
12.1
Overview
This LSI includes on-chip a resistance-ladder-based successive-approximation analog-to-digital
converter, and can convert up to 8 channels of analog input.
12.1.1
Features
The A/D converter has the following features.
• 10-bit resolution
• Eight input channels
• Conversion time: approx. 12.4 µs per channel (at 5-MHz operation)/6.2 µs (at 10-MHz
operation)*
• Built-in sample-and-hold function
• Interrupt requested on completion of A/D conversion
• A/D conversion can be started by external trigger input
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
Note: * H8/38124 group only.
Rev. 8.00 Mar. 09, 2010 Page 395 of 658
REJ09B0042-0800
Section 12 A/D Converter
12.1.2
Block Diagram
Figure 12.1 shows a block diagram of the A/D converter.
ADTRG
AMR
AN0
AN1
AN2
AN3
ADSR
Multiplexer
Internal data bus
AN4
AN5
AN6
AVCC
AN7
+
Comparator
−
AVCC
Reference
voltage
Control logic
AVSS
AVSS
ADRRH
ADRRL
[Legend]
AMR: A/D mode register
ADSR: A/D start register
ADRR: A/D result register
IRRAD: A/D conversion end interrupt request flag
Figure 12.1 Block Diagram of the A/D Converter
Rev. 8.00 Mar. 09, 2010 Page 396 of 658
REJ09B0042-0800
IRRAD
Section 12 A/D Converter
12.1.3
Pin Configuration
Table 12.1 shows the A/D converter pin configuration.
Table 12.1 Pin Configuration
Name
Abbr.
I/O
Function
Analog power supply
AVCC
Input
Power supply and reference voltage of analog part
Analog ground
AVSS
Input
Ground and reference voltage of analog part
Analog input 0
AN0
Input
Analog input channel 0
Analog input 1
AN1
Input
Analog input channel 1
Analog input 2
AN2
Input
Analog input channel 2
Analog input 3
AN3
Input
Analog input channel 3
Analog input 4
AN4
Input
Analog input channel 4
Analog input 5
AN5
Input
Analog input channel 5
Analog input 6
AN6
Input
Analog input channel 6
Analog input 7
AN7
Input
Analog input channel 7
External trigger input
ADTRG
Input
External trigger input for starting A/D conversion
12.1.4
Register Configuration
Table 12.2 shows the A/D converter register configuration.
Table 12.2 Register Configuration
Name
Abbr.
R/W
Initial Value
Address
A/D mode register
AMR
R/W
H'30
H'FFC6
A/D start register
ADSR
R/W
H'7F
H'FFC7
A/D result register H
ADRRH
R
Not fixed
H'FFC4
A/D result register L
ADRRL
R
Not fixed
H'FFC5
Clock stop register 1
CKSTPR1
R/W
H'FF
H'FFFA
Rev. 8.00 Mar. 09, 2010 Page 397 of 658
REJ09B0042-0800
Section 12 A/D Converter
12.2
Register Descriptions
12.2.1
A/D Result Registers (ADRRH, ADRRL)
Bit
7
Initial value
Read/Write
5
4
3
2
1
0
ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
6
5
4
3
2
1
0
7
6
⎯
⎯
⎯
⎯
⎯
⎯
Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined
R
R
R
R
R
R
R
R
R
R
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
ADRRH
ADRRL
ADRRH and ADRRL together comprise a 16-bit read-only register for holding the results of
analog-to-digital conversion. The upper 8 bits of the data are held in ADRRH, and the lower 2
bits in ADRRL.
ADRRH and ADRRL can be read by the CPU at any time, but the ADRRH and ADRRL values
during A/D conversion are not fixed. After A/D conversion is complete, the conversion result is
stored as 10-bit data, and this data is held until the next conversion operation starts.
ADRRH and ADRRL are not cleared on reset.
12.2.2
A/D Mode Register (AMR)
Bit
7
6
5
4
3
2
1
0
CKS
TRGE
⎯
⎯
CH3
CH2
CH1
CH0
Initial value
0
0
1
1
0
0
0
0
Read/Write
R/W
R/W
⎯
⎯
R/W
R/W
R/W
R/W
AMR is an 8-bit read/write register for specifying the A/D conversion speed, external trigger
option, and the analog input pins.
Upon reset, AMR is initialized to H'30.
Rev. 8.00 Mar. 09, 2010 Page 398 of 658
REJ09B0042-0800
Section 12 A/D Converter
Bit 7—Clock Select (CKS)
Bit 7 sets the A/D conversion speed.
Conversion Time
Bit 7
CKS
Conversion Period
φ = 1 MHz
φ = 5 MHz
φ = 10 MHz*
0
62/φ (initial value)
62 µs
1
31/φ
31 µs
12.4 µs
1
—*
6.2 µs
1
—*
2
Notes: 1. With the H8/38024, H8/38024S, and H8/38024F-ZTAT operation cannot be guaranteed
if the conversion time is less than 12.4 µs. Make sure to select a setting that gives a
conversion time of 12.4 µs or more.
With the H8/38124 Group operation cannot be guaranteed if the conversion time is less
than 6.2 μs. Make sure to select a setting that gives a conversion time of 6.2 μs or
more.
2. H8/38124 Group only.
Bit 6—External Trigger Select (TRGE)
Bit 6 enables or disables the start of A/D conversion by external trigger input.
Bit 6
TRGE
Description
0
Disables start of A/D conversion by external trigger
1
Enables start of A/D conversion by rising or falling edge of external trigger at pin
ADTRG*
(initial value)
Note: * The external trigger (ADTRG) edge is selected by bit IEG4 of IEGR. See 1. IRQ edge
select register (IEGR) in section 3.3.2, Interrupt Control Registers, for details.
Bits 5 and 4—Reserved
Bits 5 and 4 are reserved; they are always read as 1, and cannot be modified.
Rev. 8.00 Mar. 09, 2010 Page 399 of 658
REJ09B0042-0800
Section 12 A/D Converter
Bits 3 to 0—Channel Select (CH3 to CH0)
Bits 3 to 0 select the analog input channel.
The channel selection should be made while bit ADSF is cleared to 0.
Bit 3
CH3
Bit 2
CH2
Bit 1
CH1
Bit 0
CH0
Analog Input Channel
0
0
*
*
No channel selected
0
1
0
0
AN0
0
1
0
1
AN1
0
1
1
0
AN2
0
1
1
1
AN3
1
0
0
0
AN4
1
0
0
1
AN5
1
0
1
0
AN6
1
0
1
1
AN7
1
1
*
*
Setting prohibited
(initial value)
*: Don’t care
12.2.3
A/D Start Register (ADSR)
Bit
7
6
5
4
3
2
1
0
ADSF
—
—
—
—
—
—
—
Initial value
0
1
1
1
1
1
1
1
Read/Write
R/W
—
—
—
—
—
—
—
The A/D start register (ADSR) is an 8-bit read/write register for starting and stopping A/D
conversion.
A/D conversion is started by writing 1 to the A/D start flag (ADSF) or by input of the designated
edge of the external trigger signal, which also sets ADSF to 1. When conversion is complete, the
converted data is set in ADRRH and ADRRL, and at the same time ADSF is cleared to 0.
Rev. 8.00 Mar. 09, 2010 Page 400 of 658
REJ09B0042-0800
Section 12 A/D Converter
Bit 7—A/D Start Flag (ADSF)
Bit 7 controls and indicates the start and end of A/D conversion.
Bit 7
ADSF
Description
0
Read: Indicates the completion of A/D conversion
(initial value)
Write: Stops A/D conversion
1
Read: Indicates A/D conversion in progress
Write: Starts A/D conversion
Bits 6 to 0—Reserved
Bits 6 to 0 are reserved; they are always read as 1, and cannot be modified.
12.2.4
Clock Stop Register 1 (CKSTPR1)
Bit
7
6
5
4
3
2
1
0
⎯
⎯
Initial value
1
1
1
1
1
1
1
1
Read/Write
⎯
⎯
R/W
R/W
R/W
R/W
R/W
R/W
S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the A/D converter is described here. For details of the other bits,
see the sections on the relevant modules.
Bit 4—A/D Converter Module Standby Mode Control (ADCKSTP)
Bit 4 controls setting and clearing of module standby mode for the A/D converter.
ADCKSTP
Description
0
A/D converter is set to module standby mode
1
A/D converter module standby mode is cleared
(initial value)
Rev. 8.00 Mar. 09, 2010 Page 401 of 658
REJ09B0042-0800
Section 12 A/D Converter
12.3
Operation
12.3.1
A/D Conversion Operation
The A/D converter operates by successive approximations, and yields its conversion result as 10bit data.
A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a
value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete.
The completion of conversion also sets bit IRRAD in interrupt request register 2 (IRR2) to 1. An
A/D conversion end interrupt is requested if bit IENAD in interrupt enable register 2 (IENR2) is
set to 1.
If the conversion time or input channel needs to be changed in the A/D mode register (AMR)
during A/D conversion, bit ADSF should first be cleared to 0, stopping the conversion operation,
in order to avoid malfunction.
12.3.2
Start of A/D Conversion by External Trigger Input
The A/D converter can be made to start A/D conversion by input of an external trigger signal.
External trigger input is enabled at pin ADTRG when bit IRQ4 in PMR1 is set to 1 and bit TRGE
in AMR is set to 1. Then when the input signal edge designated in bit IEG4 of interrupt edge
select register (IEGR) is detected at pin ADTRG, bit ADSF in ADSR will be set to 1, starting A/D
conversion.
Figure 12.2 shows the timing.
φ
Pin ADTRG
(when bit
IEG4 = 0)
ADSF
A/D conversion
Figure 12.2 External Trigger Input Timing
Rev. 8.00 Mar. 09, 2010 Page 402 of 658
REJ09B0042-0800
Section 12 A/D Converter
12.3.3
A/D Converter Operation Modes
A/D converter operation modes are shown in table 12.3.
Table 12.3 A/D Converter Operation Modes
Operation
Mode
Reset
Active
AMR
Reset
Functions Functions Retained Retained Retained Retained Retained
ADSR
Reset
ADRRH
ADRRL
Sleep
Watch
Subactive
Subsleep
Standby
Module
Standby
Functions Functions Retained Retained Retained Retained Retained
*
Retained Functions Functions Retained Retained Retained Retained Retained
Retained* Functions Functions Retained Retained Retained Retained Retained
Note: * Undefined in a power-on reset.
12.4
Interrupts
When A/D conversion ends (ADSF changes from 1 to 0), bit IRRAD in interrupt request register 2
(IRR2) is set to 1.
A/D conversion end interrupts can be enabled or disabled by means of bit IENAD in interrupt
enable register 2 (IENR2).
For further details see section 3.3, Interrupts.
12.5
Typical Use
An example of how the A/D converter can be used is given below, using channel 1 (pin AN1) as
the analog input channel. Figure 12.3 shows the operation timing.
1. Bits CH3 to CH0 of the A/D mode register (AMR) are set to 0101, making pin AN1 the analog
input channel. A/D interrupts are enabled by setting bit IENAD to 1, and A/D conversion is
started by setting bit ADSF to 1.
2. When A/D conversion is complete, bit IRRAD is set to 1, and the A/D conversion result is
stored in ADRRH and ADRRL. At the same time ADSF is cleared to 0, and the A/D converter
goes to the idle state.
3. Bit IENAD = 1, so an A/D conversion end interrupt is requested.
4. The A/D interrupt handling routine starts.
5. The A/D conversion result is read and processed.
6. The A/D interrupt handling routine ends.
Rev. 8.00 Mar. 09, 2010 Page 403 of 658
REJ09B0042-0800
Section 12 A/D Converter
If ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place.
A/D conversion result (2)
Note: * ( ) indicates instruction execution by software.
Read conversion result
Read conversion result
A/D conversion result (1)
ADRRH
ADRRL
Idle
Channel 1 (AN1)
operation state
ADSF
IENAD
Interrupt
(IRRAD)
A/D conversion starts
Set*
Set*
A/D conversion (1)
Idle
Set*
A/D conversion (2)
Idle
Figures 12.4 and 12.5 show flow charts of procedures for using the A/D converter.
Figure 12.3 Typical A/D Converter Operation Timing
Rev. 8.00 Mar. 09, 2010 Page 404 of 658
REJ09B0042-0800
Section 12 A/D Converter
Start
Set A/D conversion speed
and input channel
Disable A/D conversion
end interrupt
Start A/D conversion
Read ADSR
No
ADSF = 0?
Yes
Read ADRRH/ADRRL data
Yes
Perform A/D
conversion?
No
End
Figure 12.4 Flow Chart of Procedure for Using A/D Converter (Polling by Software)
Rev. 8.00 Mar. 09, 2010 Page 405 of 658
REJ09B0042-0800
Section 12 A/D Converter
Start
Set A/D conversion speed
and input channel
Enable A/D conversion
end interrupt
Start A/D conversion
A/D conversion
end interrupt?
No
Yes
Clear bit IRRAD to
0 in IRR2
Read ADRRH/ADRRL data
Yes
Perform A/D
conversion?
No
End
Figure 12.5 Flow Chart of Procedure for Using A/D Converter (Interrupts Used)
Rev. 8.00 Mar. 09, 2010 Page 406 of 658
REJ09B0042-0800
Section 12 A/D Converter
12.6
A/D Conversion Accuracy Definitions
This LSI's A/D conversion accuracy definitions are given below.
• Resolution
The number of A/D converter digital output codes
• Quantization error
The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 12.6).
• Offset error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from the minimum voltage value 0000000000 to 0000000001
(see figure 12.7).
• Full-scale error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from 1111111110 to 1111111111 (see figure 12.7).
• Nonlinearity error
The error with respect to the ideal A/D conversion characteristics between zero voltage and
full-scale voltage. Does not include offset error, full-scale error, or quantization error.
• Absolute accuracy
The deviation between the digital value and the analog input value. Includes offset error, fullscale error, quantization error, and nonlinearity error.
Rev. 8.00 Mar. 09, 2010 Page 407 of 658
REJ09B0042-0800
Section 12 A/D Converter
Digital output
Ideal A/D conversion
characteristic
111
110
101
100
011
010
Quantization error
001
000
1
8
2
8
3
8
4
8
5
8
7 FS
8
Analog
input voltage
6
8
Figure 12.6 A/D Conversion Accuracy Definitions (1)
Full-scale error
Digital output
Ideal A/D conversion
characteristic
Nonlinearity
error
Actual A/D conversion
characteristic
Offset error
FS
Analog
input voltage
Figure 12.7 A/D Conversion Accuracy Definitions (2)
Rev. 8.00 Mar. 09, 2010 Page 408 of 658
REJ09B0042-0800
Section 12 A/D Converter
12.7
Application Notes
12.7.1
Permissible Signal Source Impedance
This LSI’s analog input is designed such that conversion precision is guaranteed for an input
signal for which the signal source impedance is 10 kΩ or less. This specification is provided to
enable the A/D converter’s sample-and-hold circuit input capacitance to be charged within the
sampling time; if the sensor output impedance exceeds 10 kΩ, charging may be insufficient and it
may not be possible to guarantee A/D conversion precision. However, a large capacitance
provided externally, the input load will essentially comprise only the internal input resistance of
10 kΩ, and the signal source impedance is ignored. However, as a low-pass filter effect is obtained
in this case, it may not be possible to follow an analog signal with a large differential coefficient
(e.g., 5 mV/μs or greater) (see figure 12.8). When converting a high-speed analog signal, a lowimpedance buffer should be inserted.
12.7.2
Influences on Absolute Precision
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely
affect absolute precision. Be sure to make the connection to an electrically stable GND.
Care is also required to ensure that filter circuits do not interfere with digital signals or act as
antennas on the mounting board.
This LSI
Sensor output
impedance
A/D converter
equivalent circuit
10 kΩ
Up to 10 kΩ
Sensor input
Low-pass
filter
C to 0.1 μF
Cin =
15 pF
20 pF
Figure 12.8 Analog Input Circuit Example
Rev. 8.00 Mar. 09, 2010 Page 409 of 658
REJ09B0042-0800
Section 12 A/D Converter
12.7.3
Additional Usage Notes
• Data in ADRRH and ADRRL should be read only when the A/D start flag (ADSF) in the A/D
start register (ADSR) is cleared to 0.
• Changing the digital input signal at an adjacent pin during A/D conversion may adversely
affect conversion accuracy.
• When A/D conversion is started after clearing module standby mode, wait for 10 φ clock
cycles before starting.
• In active mode or sleep mode, analog power supply current (AISTOP1) flows into the ladder
resistance even when the A/D converter is not operating. Therefore, if the A/D converter is not
used, it is recommended that AVCC be connected to the system power supply and the
ADCKSTP (A/D converter module standby mode control) bit be cleared to 0 in clock stop
register 1 (CKSTPR1).
Rev. 8.00 Mar. 09, 2010 Page 410 of 658
REJ09B0042-0800
Section 13 LCD Controller/Driver
Section 13 LCD Controller/Driver
13.1
Overview
This LSI has an on-chip segment type LCD control circuit, LCD driver, and power supply circuit,
enabling it to directly drive an LCD panel.
13.1.1
Features
Features of the LCD controller/driver are given below.
• Display capacity
Duty Cycle
Internal Driver
Static
32 seg
1/2
32 seg
1/3
32 seg
1/4
32 seg
• LCD RAM capacity
8 bits × 16 bytes (128 bits)
• Word access to LCD RAM
• All four segment output pins can be used individually as port pins.
• Common output pins not used because of the duty cycle can be used for common doublebuffering (parallel connection).
• Display possible in operating modes other than standby mode
• Choice of 11 frame frequencies
• Built-in power supply split-resistance, supplying LCD drive power
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
• A or B waveform selectable by software
• Removal of split-resistance can be controlled in software. Note that this capability is
implemented in the H8/38124 Group only.
Rev. 8.00 Mar. 09, 2010 Page 411 of 658
REJ09B0042-0800
Section 13 LCD Controller/Driver
13.1.2
Block Diagram
Figures 13.1(1) and 13.1(2) show a block diagram of the LCD controller/driver.
LCD drive power supply
VCC
V1
V2
V3
VSS
φ/256 to φ/2
Common
data latch
φW
Common
driver
COM1
COM4
Internal data bus
SEG32
LPCR
LCR
LCR2
32-bit shift
register
Display timing generator
Segment
driver
LCD RAM
(16 bytes)
SEG1
SEGn
[Legend]
LPCR: LCD port control register
LCR: LCD control register
LCR2: LCD control register 2
Figure 13.1(1) Block Diagram of H8/38024, H8/38024S, and H8/38024F-ZTAT Group
LCD Controller/Driver
Rev. 8.00 Mar. 09, 2010 Page 412 of 658
REJ09B0042-0800
Section 13 LCD Controller/Driver
VCC
V1
LCD drive
power supply
V2
V3
VSS
φ/256 to φ/2
Common
data latch
Internal data bus
φw
Common
driver
COM1
COM4
SEG32
LPCR
LCR
LCR2
32-bit
shift
register
Display timing generator
Segment
driver
LCD RAM
(16 bytes)
SEG1
SEGn
[Legend]
LPCR: LCD port control register
LCR:
LCD control register
LCR2: LCD control register 2
Figure 13.1(2) Block Diagram of H8/38124 Group LCD Controller/Driver
Rev. 8.00 Mar. 09, 2010 Page 413 of 658
REJ09B0042-0800
Section 13 LCD Controller/Driver
13.1.3
Pin Configuration
Table 13.1 shows the LCD controller/driver pin configuration.
Table 13.1 Pin Configuration
Name
Abbr.
I/O
Function
Segment output pins
SEG32 to SEG1
Output
LCD segment drive pins
All pins are multiplexed as port pins
(setting programmable)
Common output pins
COM4 to COM1
Output
LCD common drive pins
Pins can be used in parallel with static or
1/2 duty
LCD power supply pins
V1, V2, V3
—
Used when a bypass capacitor is
connected externally, and when an
external power supply circuit is used
13.1.4
Register Configuration
Table 13.2 shows the register configuration of the LCD controller/driver.
Table 13.2 LCD Controller/Driver Registers
Name
Abbr.
R/W
Initial Value
Address
LCD port control register
LPCR
R/W
—
H'FFC0
LCD control register
LCR
R/W
H'80
H'FFC1
LCD control register 2
LCR2
R/W
—
H'FFC2
LCD RAM
—
R/W
Undefined
H'F740 to H'F74F
Clock stop register 2
CKSTPR2
R/W
H'FF
H'FFFB
Rev. 8.00 Mar. 09, 2010 Page 414 of 658
REJ09B0042-0800
Section 13 LCD Controller/Driver
13.2
Register Descriptions
13.2.1
LCD Port Control Register (LPCR)
Bit
7
6
5
4
3
2
1
0
DTS1
DTS0
CMX
⎯
SGS3
SGS2
SGS1
SGS0
Initial value
0
0
0
⎯
0
0
0
0
Read/Write
R/W
R/W
R/W
W
R/W
R/W
R/W
R/W
LPCR is an 8-bit read/write register which selects the duty cycle and LCD driver pin functions.
Bits 7 to 5—Duty Cycle Select 1 and 0 (DTS1, DTS0), Common Function Select (CMX)
The combination of DTS1 and DTS0 selects static, 1/2, 1/3, or 1/4 duty. CMX specifies whether
or not the same waveform is to be output from multiple pins to increase the common drive power
when not all common pins are used because of the duty setting.
Bit 7
DTS1
Bit 6
DTS0
Bit 5
CMX
Duty Cycle
Common Drivers
0
0
0
Static
COM1 (initial value) Do not use COM4, COM3, and
COM2.
1
0
1
0
1/2 duty
1
1
0
0
1/3 duty
1
1
1
0
1/4 duty
Notes
COM4 to COM1
COM4, COM3, and COM2 output
the same waveform as COM1.
COM2 and COM1
Do not use COM4 and COM3.
COM4 to COM1
COM4 outputs the same waveform
as COM3, and COM2 outputs the
same waveform as COM1.
COM3 to COM1
Do not use COM4.
COM4 to COM1
Do not use COM4.
COM4 to COM1
—
1
Bit 4—Reserved
Bit 4 is reserved. It can only be written with 0.
Rev. 8.00 Mar. 09, 2010 Page 415 of 658
REJ09B0042-0800
Section 13 LCD Controller/Driver
Bits 3 to 0—Segment Driver Select 3 to 0 (SGS3 to SGS0)
Bits 3 to 0 select the segment drivers to be used.
Function of Pins SEG32 to SEG1
Bit 3
Bit 2
Bit 1
Bit 0
SEG32 to SEG28 to SEG24 to SEG20 to SEG16 to SEG12 to SEG8 to SEG4 to
SGS3 SGS2 SGS1 SGS0 SEG29
SEG25
SEG21
SEG17
SEG13
SEG9
SEG5
SEG1
Notes
0
(Initial value)
0
0
0
Port
Port
Port
Port
Port
Port
Port
Port
1
Port
Port
Port
Port
Port
Port
Port
SEG
0
Port
Port
Port
Port
Port
Port
SEG
SEG
1
Port
Port
Port
Port
Port
SEG
SEG
SEG
0
Port
Port
Port
Port
SEG
SEG
SEG
SEG
1
Port
Port
Port
SEG
SEG
SEG
SEG
SEG
0
Port
Port
SEG
SEG
SEG
SEG
SEG
SEG
1
Port
SEG
SEG
SEG
SEG
SEG
SEG
SEG
0
0
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
1
SEG
SEG
SEG
SEG
SEG
SEG
SEG
Port
1
0
SEG
SEG
SEG
SEG
SEG
SEG
Port
Port
1
SEG
SEG
SEG
SEG
SEG
Port
Port
Port
0
SEG
SEG
SEG
SEG
Port
Port
Port
Port
1
SEG
SEG
SEG
Port
Port
Port
Port
Port
0
SEG
SEG
Port
Port
Port
Port
Port
Port
1
SEG
Port
Port
Port
Port
Port
Port
Port
1
1
0
1
1
0
1
0
1
Rev. 8.00 Mar. 09, 2010 Page 416 of 658
REJ09B0042-0800
Section 13 LCD Controller/Driver
13.2.2
LCD Control Register (LCR)
Bit
7
6
5
4
3
2
1
0
⎯
PSW
ACT
DISP
CKS3
CKS2
CKS1
CKS0
Initial value
1
0
0
0
0
0
0
0
Read/Write
⎯
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LCR is an 8-bit read/write register which performs LCD drive power supply on/off control and
display data control, and selects the frame frequency.
LCR is initialized to H'80 upon reset.
Bit 7—Reserved
Bit 7 is reserved; it is always read as 1 and cannot be modified.
Bit 6—LCD Drive Power Supply On/Off Control (PSW)
Bit 6 can be used to turn the LCD drive power supply off when LCD display is not required in a
power-down mode, or when an external power supply is used. When the ACT bit is cleared to 0,
or in standby mode, the LCD drive power supply is turned off regardless of the setting of this bit.
Bit 6
PSW
Description
0
LCD drive power supply off
1
LCD drive power supply on
(initial value)
Bit 5—Display Function Activate (ACT)
Bit 5 specifies whether or not the LCD controller/driver is used. Clearing this bit to 0 halts
operation of the LCD controller/driver. The LCD drive power supply is also turned off, regardless
of the setting of the PSW bit. However, register contents are retained.
Bit 5
ACT
Description
0
LCD controller/driver operation halted
1
LCD controller/driver operates
(initial value)
Rev. 8.00 Mar. 09, 2010 Page 417 of 658
REJ09B0042-0800
Section 13 LCD Controller/Driver
Bit 4—Display Data Control (DISP)
Bit 4 specifies whether the LCD RAM contents are displayed or blank data is displayed regardless
of the LCD RAM contents.
Bit 4
DISP
Description
0
Blank data is displayed
1
LCD RAM data is display
(initial value)
Bits 3 to 0—Frame Frequency Select 3 to 0 (CKS3 to CKS0)
Bits 3 to 0 select the operating clock and the frame frequency. In subactive mode, watch mode,
and subsleep mode, the system clock (φ) is halted, and therefore display operations are not
performed if one of the clocks from φ/2 to φ/256 is selected. If LCD display is required in these
modes, φw, φw/2, or φw/4 must be selected as the operating clock.
2
Frame Frequency*
Bit 3
CKS3
Bit 2
CKS2
Bit 1
CKS1
Bit 0
CKS0
Operating Clock
φ = 2 MHz
0
*
0
0
φw
0
*
0
1
φw/2
128 Hz* (initial value)
3
64 Hz*
0
*
1
*
φw/4
32 Hz*
1
0
0
0
φ/2
—
244 Hz
1
0
0
1
φ/4
977 Hz
122 Hz
1
0
1
0
φ/8
488 Hz
61 Hz
1
0
1
1
φ/16
244 Hz
30.5 Hz
1
1
0
0
φ/32
122 Hz
—
1
1
0
1
φ/64
61 Hz
—
1
1
1
0
φ/128
30.5 Hz
—
1
1
1
1
φ/256
—
—
φ = 250 kHz*
1
3
3
*: Don’t care
Notes: 1. This is the frame frequency in active (medium-speed, φosc/16) mode when φ = 2 MHz.
2. When 1/3 duty is selected, the frame frequency is 4/3 times the value shown.
3. This is the frame frequency when φw = 32.768 kHz.
Rev. 8.00 Mar. 09, 2010 Page 418 of 658
REJ09B0042-0800
Section 13 LCD Controller/Driver
13.2.3
LCD Control Register 2 (LCR2)
Bit
7
6
5
4
3
2
1
0
LCDAB
—
—
—
CDS3*
CDS2*
CDS1*
CDS0*
Initial value
0
1
1
—
0
0
0
0
Read/Write
R/W
—
—
R/W
R/W
R/W
R/W
R/W
Note: * Applies to the H8/38124 Group only. On the H8/38024, H8/38024S, and H8/38024F-ZTAT
Group, these bits are reserved like bit 4.
LCR2 is an 8-bit read/write register which controls switching between the A waveform and B
waveform and removal of split-resistance. Note that removal of split-resistance control is only
implemented on the H8/38124 Group.
Bit 7—A Waveform/B Waveform Switching Control (LCDAB)
Bit 7 specifies whether the A waveform or B waveform is used as the LCD drive waveform.
Bit 7
LCDAB
Description
0
Drive using A waveform
1
Drive using B waveform
(initial value)
Bits 6 and 5—Reserved
Bits 6 and 5 are reserved; they are always read as 1 and cannot be modified.
Bit 4—Reserved
Bit 4 is reserved; this can only be written with 0.
Rev. 8.00 Mar. 09, 2010 Page 419 of 658
REJ09B0042-0800
Section 13 LCD Controller/Driver
Bits 3 to 0—Removal of Split-Resistance Control
These bits control whether the split-resistance is removed or connected. Note that on products
other than the H8/38124 Group, these bits are reserved like bit 4.
Bit 3
CDS3
Bit 2
CDS2
Bit 1
CDS1
Bit 0
CDS0
0
0
0
0
1
1
Description
(initial value)
Split-resistance connected
0
1
1
0
0
1
0
1
1
0
0
1
Split-resistance removed
0
Split-resistance connected
1
1
0
0
0
1
1
1
1
0
1
Rev. 8.00 Mar. 09, 2010 Page 420 of 658
REJ09B0042-0800
Section 13 LCD Controller/Driver
13.2.4
Clock Stop Register 2 (CKSTPR2)
Bit
7
6
5
LVDCKSTP*
⎯
⎯
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
⎯
⎯
R/W
R/W
R/W
R/W
R/W
4
3
2
1
0
PW2CKSTP AECKSTP WDCKSTP PW1CKSTP LDCKSTP
Note: * Bits 6 and 5 are also reserved on products other than the H8/38124 Group.
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the LCD controller/driver is described here. For details of the
other bits, see the sections on the relevant modules.
Bit 0—LCD Controller/Driver Module Standby Mode Control (LDCKSTP)
Bit 0 controls setting and clearing of module standby mode for the LCD controller/driver.
Bit 0
LDCKSTP
Description
0
LCD controller/driver is set to module standby mode
1
LCD controller/driver module standby mode is cleared
(initial value)
Rev. 8.00 Mar. 09, 2010 Page 421 of 658
REJ09B0042-0800
Section 13 LCD Controller/Driver
13.3
Operation
13.3.1
Settings up to LCD Display
To perform LCD display, the hardware and software related items described below must first be
determined.
Hardware Settings
a. Using 1/2 duty
When 1/2 duty is used, interconnect pins V2 and V3 as shown in figure 13.2.
VCC
V1
V2
V3
VSS
Figure 13.2 Handling of LCD Drive Power Supply when Using 1/2 Duty
b. Large-panel display
As the impedance of the built-in power supply split-resistance is large, it may not be suitable
for driving a large panel. If the display lacks sharpness when using a large panel, refer to
section 13.3.4, Boosting the LCD Drive Power Supply. When static or 1/2 duty is selected, the
common output drive capability can be increased. Set CMX to 1 when selecting the duty
cycle. In this mode, with a static duty cycle pins COM4 to COM1 output the same waveform,
and with 1/2 duty the COM1 waveform is output from pins COM2 and COM1, and the COM2
waveform is output from pins COM4 and COM3.
Rev. 8.00 Mar. 09, 2010 Page 422 of 658
REJ09B0042-0800
Section 13 LCD Controller/Driver
Software Settings
a. Duty selection
Any of four duty cycles—static, 1/2 duty, 1/3 duty, or 1/4 duty—can be selected with bits
DTS1 and DTS0.
b. Segment selection
The segment drivers to be used can be selected with bits SGS3 to SGS0.
c. Frame frequency selection
The frame frequency can be selected by setting bits CKS3 to CKS0. The frame frequency
should be selected in accordance with the LCD panel specification. For the clock selection
method in watch mode, subactive mode, and subsleep mode, see section 13.3.3, Operation in
Power-Down Modes.
d. A or B waveform selection
Either the A or B waveform can be selected as the LCD waveform to be used by means of
LCDAB.
Rev. 8.00 Mar. 09, 2010 Page 423 of 658
REJ09B0042-0800
Section 13 LCD Controller/Driver
13.3.2
Relationship between LCD RAM and Display
The relationship between the LCD RAM and the display segments differs according to the duty
cycle. LCD RAM maps for the different duty cycles are shown in figures 13.3 to 13.6.
After setting the registers required for display, data is written to the part corresponding to the duty
using the same kind of instruction as for ordinary RAM, and display is started automatically when
turned on. Word- or byte-access instructions can be used for RAM setting.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
H'F740
SEG2
SEG2
SEG2
SEG2
SEG1
SEG1
SEG1
SEG1
H'F74F
SEG32
SEG32
SEG32
SEG32
SEG31
SEG31
SEG31
SEG31
COM4
COM3
COM2
COM1
COM4
COM3
COM2
COM1
Figure 13.3 LCD RAM Map (1/4 Duty)
Rev. 8.00 Mar. 09, 2010 Page 424 of 658
REJ09B0042-0800
Section 13 LCD Controller/Driver
Bit 7
Bit 6
Bit 5
Bit 4
H'F740
SEG2
SEG2
H'F74F
SEG32
COM3
Bit 3
Bit 2
Bit 1
Bit 0
SEG2
SEG1
SEG1
SEG1
SEG32
SEG32
SEG31
SEG31
SEG31
COM2
COM1
COM3
COM2
COM1
Space not used for display
Figure 13.4 LCD RAM Map (1/3 Duty)
Rev. 8.00 Mar. 09, 2010 Page 425 of 658
REJ09B0042-0800
Section 13 LCD Controller/Driver
H'F740
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SEG4
SEG4
SEG3
SEG3
SEG2
SEG2
SEG1
SEG1
Display space
SEG32
SEG32
SEG31
SEG31
SEG30
SEG30
SEG29
SEG29
H'F747
Space not used for display
H'F74F
COM2
COM1
COM2
COM1
COM2
COM1
COM2
COM1
Figure 13.5 LCD RAM Map (1/2 Duty)
H'F740
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
Display
space
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
H'F743
Space not
used for
display
H'F74F
COM1
COM1
COM1
COM1
COM1
COM1
COM1
Figure 13.6 LCD RAM Map (Static Mode)
Rev. 8.00 Mar. 09, 2010 Page 426 of 658
REJ09B0042-0800
COM1
Section 13 LCD Controller/Driver
1 frame
1 frame
M
M
Data
Data
V1
V2
V3
VSS
COM1
V1
V2
V3
VSS
V1
V2
V3
VSS
COM2
COM3
V1
V2
V3
VSS
V1
V2
V3
VSS
COM4
SEGn
V1
V2
V3
VSS
COM1
V1
V2
V3
VSS
V1
V2
V3
VSS
COM2
COM3
V1
V2
V3
VSS
SEGn
(a) Waveform with 1/4 duty
(b) Waveform with 1/3 duty
1 frame
1 frame
M
M
Data
Data
V1
COM1
V1
V2, V3
VSS
COM1
COM2
V1
V2, V3
VSS
SEGn
SEGn
V1
V2, V3
VSS
(c) Waveform with 1/2 duty
VSS
V1
VSS
(d) Waveform with static output
M: LCD alternation signal
Figure 13.7 Output Waveforms for Each Duty Cycle (A Waveform)
Rev. 8.00 Mar. 09, 2010 Page 427 of 658
REJ09B0042-0800
Section 13 LCD Controller/Driver
1 frame
1 frame
1 frame
1 frame
1 frame
M
M
Data
Data
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
COM1
COM2
COM3
COM4
V1
V2
V3
VSS
SEGn
1 frame
1 frame
1 frame
1 frame
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
COM1
COM2
COM3
V1
V2
V3
VSS
SEGn
(a) Waveform with 1/4 duty
1 frame
1 frame
(b) Waveform with 1/3 duty
1 frame
1 frame
1 frame
1 frame
1 frame
M
M
Data
Data
V1
COM1
V1
V2, V3
VSS
COM1
COM2
V1
V2, V3
VSS
SEGn
SEGn
V1
V2, V3
VSS
(c) Waveform with 1/2 duty
VSS
V1
VSS
(d) Waveform with static output
M: LCD alternation signal
Figure 13.8 Output Waveforms for Each Duty Cycle (B Waveform)
Rev. 8.00 Mar. 09, 2010 Page 428 of 658
REJ09B0042-0800
Section 13 LCD Controller/Driver
Table 13.3 Output Levels
Data
0
0
1
1
M
0
1
0
1
Common output
V1
VSS
V1
VSS
Segment output
V1
VSS
VSS
V1
Common output
V2, V3
V2, V3
V1
VSS
Segment output
V1
VSS
VSS
V1
Static
1/2 duty
1/3 duty
1/4 duty
Common output
V3
V2
V1
VSS
Segment output
V2
V3
VSS
V1
Common output
V3
V2
V1
VSS
Segment output
V2
V3
VSS
V1
M: LCD alternation signal
13.3.3
Operation in Power-Down Modes
This LSI the LCD controller/driver can be operated even in the power-down modes. The
operating state of the LCD controller/driver in the power-down modes is summarized in table
13.4.
In subactive mode, watch mode, and subsleep mode, the system clock oscillator stops, and
therefore, unless φw, φw/2, or φw/4 has been selected by bits CKS3 to CKS0, the clock will not be
supplied and display will halt. Since there is a possibility that a direct current will be applied to
the LCD panel in this case, it is essential to ensure that φw, φw/2, or φw/4 is selected. In active
(medium-speed) mode, the system clock is switched, and therefore CKS3 to CKS0 must be
modified to ensure that the frame frequency does not change.
Rev. 8.00 Mar. 09, 2010 Page 429 of 658
REJ09B0042-0800
Section 13 LCD Controller/Driver
Table 13.4 Power-Down Modes and Display Operation
Reset Active
Sleep
Watch
Subactive
Subsleep
Module
Standby Standby
φ
Runs
Runs
Runs
Stops
Stops
Stops
Stops
Stops*4
φw
Runs
Runs
Runs
Runs
Runs
Runs
Stops*1
Stops*4
Stops
Stops
Stops
Stops
Stops*2
Stops
Stops*2
Stops
Mode
Clock
Display
ACT = 0
operation
ACT = 1
Stops
Functions Functions Functions
Stops
*3
Functions
Stops
*3
Functions
*3
Notes: 1. The subclock oscillator does not stop, but clock supply is halted.
2. The LCD drive power supply is turned off regardless of the setting of the PSW bit.
3. Display operation is performed only if φw, φw/2, or φw/4 is selected as the operating
clock.
4. The clock supplied to the LCD stops.
13.3.4
Boosting the LCD Drive Power Supply
When a large panel is driven, the on-chip power supply capacity may be insufficient. If the power
supply capacity is insufficient when VCC is used as the power supply, the power supply impedance
must be reduced. This can be done by connecting bypass capacitors of around 0.1 to 0.3 µF to
pins V1 to V3, as shown in figure 13.9, or by adding a split-resistance externally.
R
VCC
V1
R
This LSI
R = several kΩ to
several MΩ
V2
R
V3
C = 0.1 to 0.3 μF
R
VSS
Figure 13.9 Connection of External Split-Resistance
Rev. 8.00 Mar. 09, 2010 Page 430 of 658
REJ09B0042-0800
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only)
Section 14 Power-On Reset and Low-Voltage Detection
Circuits (H8/38124 Group Only)
14.1
Overview
This LSI can include a power-on reset circuit and low-voltage detection circuit.
The low-voltage detection circuit consists of two circuits: LVDI (interrupt by low voltage detect)
and LVDR (reset by low voltage detect) circuits.
This circuit is used to prevent abnormal operation (runaway execution) from occurring due to the
power supply voltage fall and to recreate the state before the power supply voltage fall when the
power supply voltage rises again.
Even if the power supply voltage falls, the unstable state when the power supply voltage falls
below the guaranteed operating voltage can be removed by entering standby mode* when
exceeding the guaranteed operating voltage and during normal operation. Thus, system stability
can be improved. If the power supply voltage falls more, the reset state is automatically entered. If
the power supply voltage rises again, the reset state is held for a specified period, then active mode
is automatically entered.
Figure 14.1 is a block diagram of the power-on reset circuit and the low-voltage detection circuit.
Note: * The voltage maintained in standby mode is the same as the RAM data retaining voltage
(VRAM). See section 16.8.2, DC Characteristics, for information on retaining voltage.
14.1.1
Features
The features of the power-on reset circuit and low-voltage detection circuit are described below.
• Power-on reset circuit
Uses an external capacitor to generate an internal reset signal when power is first supplied.
• Low-voltage detection circuit
LVDR: Monitors the power-supply voltage, and generates an internal reset signal when the
voltage falls below a specified value.
LVDI: Monitors the power-supply voltage, and generates an interrupt when the voltage falls
below or rises above respective specified values.
LVI0000A_000020030300
Rev. 8.00 Mar. 09, 2010 Page 431 of 658
REJ09B0042-0800
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only)
Two pairs of detection levels for reset generation voltage are available: when only the LVDR
circuit is used, or when the LVDI and LVDR circuits are both used. In addition, power supply
rise/drop detection voltages and a detection voltage reference voltage may be input from an
external source, allowing the detection level to be set freely by the user.
14.1.2
Block Diagram
A block diagram of the power-on reset circuit and low-voltage detection circuit are shown in
figure 14.1.
φ
CK
R
RES
OVF
PSS
R
Noise
canceler
Q
S
LVDCR
Vcc
External
power
supply
Vreset
−
Vint
LVDRES
+
−
extD
External
ladder
resistor
+
LVDINT
extU
Interrupt
control
circuit
LVDSR
Internal data bus
Power-on reset circuit
Noise
canceler
Ladder
resistor
Internal reset
signal
Vref
Interrupt
request
On-chip
reference voltage
generator
External
reference voltage
generator
Low-voltage detection circuit
[Legend]
PSS:
LVDCR:
LVDSR:
LVDRES:
LVDINT:
Vreset:
Vint:
extD:
extU:
Vref:
Prescaler S
Low-voltage-detection control register
Low-voltage-detection status register
Low-voltage-detection reset signal
Low-voltage-detection interrupt signal
Reset detection voltage
Power-supply fall/rise detection voltage
Power supply drop detection voltage input pin
Power supply rise detection voltage input pin
Reference voltage input pin
Figure 14.1 Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit
Rev. 8.00 Mar. 09, 2010 Page 432 of 658
REJ09B0042-0800
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only)
14.1.3
Pin Description
The pins of the power-on reset circuit and low-voltage detection circuit are listed in table 14.1.
Table 14.1 Pin Description
Pin
Symbol
I/O
Function
Low-voltage detection circuit
reference voltage input pin
Vref
Input
Reference voltage input for lowvoltage detection circuit
Low-voltage detection circuit power
supply drop detection voltage input
pin
extD
Input
Power supply drop detection voltage
input pin for low-voltage detection
circuit
Low-voltage detection circuit power
supply rise detection voltage input
pin
extU
Input
Power supply rise detection voltage
input pin for low-voltage detection
circuit
14.1.4
Register Descriptions
The registers of the power-on reset circuit and low-voltage detection circuit are listed in table 14.2.
Table 14.2 Register Descriptions
Name
Symbol
R/W
Initial Value
Address
Low-voltage detection control register
LVDCR
R/W
H'00
H'FF86
Low-voltage detection status register
LVDSR
R/W
H'00
H'FF87
Low-voltage detection counter
LVDCNT
R
H'00
H'FFC3
14.2
Individual Register Descriptions
14.2.1
Low-Voltage Detection Control Register (LVDCR)
Bit
7
6
5
—
Initial value
LVDE
0*
0
0
Read/Write
R/W
R/W
R/W
4
3
2
1
0
LVDUE
0
LVDRE
0*
LVDDE
0*
0
0
R/W
R/W
R/W
R/W
R/W
VINTDSEL VINTUSEL LVDSEL
Note: * These bits are not initialized by resets trigged by LVDR. They are initialized by power-on
resets and watchdog timer resets.
Rev. 8.00 Mar. 09, 2010 Page 433 of 658
REJ09B0042-0800
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only)
LVDCR is an 8-bit read/write register. It is used to control whether or not the low-voltage
detection circuit is used, settings for external input of power supply rise and drop detection
voltages, the LVDR detection level setting, enabling or disabling of resets triggered by the lowvoltage detection reset circuit (LVDR), and enabling or disabling of interrupts triggered by power
supply voltage drops or rises.
Bit 7—LVD Enable (LVDE)
This bit is used to control whether or not the low-voltage detection circuit is used.
Bit 7
LVDE
Description
0
Low-voltage detection circuit not used (standby status)
1
Low-voltage detection circuit used
(initial value)
Bit 6—Reserved
This bit is a read/write enabled reserved bit.
Bit 5—Power Supply Drop (LVDD) Detection Level External Input Select (VINTDSEL)
This bit is used to select the power supply drop detection level.
Bit 5
VINTDSEL
Description
0
LVDD detection level generated by on-chip ladder resistor
1
LVDD detection level input to extD pin
(initial value)
Bit 4—Power Supply Rise (LVDU) Detection Level External Input Select (VINTUSEL)
This bit is used to select the power supply rise detection level.
Bit 4
VINTUSEL
Description
0
LVDU detection level generated by on-chip ladder resistor
1
LVDU detection level input to extU pin
Rev. 8.00 Mar. 09, 2010 Page 434 of 658
REJ09B0042-0800
(initial value)
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only)
Bit 3—LVDR Detection Level Select (LVDSEL)
This bit is used to select the LVDR detection level. Select 2.3 V (typical) reset if voltage rise and
drop detection interrupts are to be used. For reset detection only, Select 3.3 V (typical) reset.
Bit 3
LVDSEL
Description
0
Reset detection voltage 2.3 V (typ.)
1
Reset detection voltage 3.3 V (typ.)
(initial value)
Bit 2—LVDR Enable (LVDRE)
This bit is used to control whether resets triggered by LVDR are enabled or disabled.
Bit 2
LVDRE
Description
0
LVDR resets disabled
1
LVDR resets enabled
(initial value)
Bit 1—Voltage Drop Interrupt Enable (LVDDE)
This bit is used to control whether voltage drop interrupt requests are enabled or disabled.
Bit 1
LVDDE
Description
0
Voltage drop interrupt requests disabled
1
Voltage drop interrupt requests enabled
(initial value)
Bit 0—Voltage Rise Interrupt Enable (LVDUE)
This bit is used to control whether voltage rise interrupt requests are enabled or disabled.
Bit 0
LVDUE
Description
0
Voltage rise interrupt requests disabled
1
Voltage rise interrupt requests enabled
(initial value)
Rev. 8.00 Mar. 09, 2010 Page 435 of 658
REJ09B0042-0800
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only)
Table 14.3 shows the relationship between LVDCR settings and function selections. Refer to table
14.3 when making settings to LVDCR.
Table 14.3 LVDCR Settings and Function Selections
LVDCR Setting Value
Power-on
Reset
Low-Voltage
Detection
Reset
LVDE
LVDSEL LVDRE
LVDDE LVDUE
0
*
*
*
*
1
1
1
0
0
1
0
0
1
0
—
1
0
0
1
1
—
1
0
1
1
1
—
Low-Voltage
Detection
Voltage Drop
Interrupt
Low-Voltage
Detection
Voltage Rise
Interrupt
—
—
—
—
—
Note: Setting values marked with an asterisk (*) are invalid.
14.2.2
Low-Voltage Detection Status Register (LVDSR)
Bit
7
6
5
4
3
2
1
0
OVF
—
—
—
VREFSEL
—
LVDDF
LVDUF
Initial value
0*
0
0
0
0
0
0*
0*
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: * These bits initialized by resets trigged by LVDR.
LVDSR is an 8-bit read/write register. It is used to control external input selection, indicates when
the reference voltage is stable, and indicates if the power supply voltage goes below or above a
specified range.
Bit 7—LVD Reference Voltage Stabilized Flag (OVF)
This bit indicates when the low-voltage detection counter (LVDCNT) overflows.
Bit 7
OVF
Description
0
[Clearing condition]
When 0 is written after reading 1
1
[Setting condition]
When the low-voltage detection counter (LVDCNT) overflows
Rev. 8.00 Mar. 09, 2010 Page 436 of 658
REJ09B0042-0800
(initial value)
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only)
Bits 6 to 4—Reserved
These bits are read/write enabled reserved bits.
Bit 3—Reference Voltage External Input Select (VREFSEL)
This bit is used to select the reference voltage.
Bit 3
VREFSEL
Description
0
The on-chip circuit is used to generate the reference voltage
1
The reference voltage is input to the Vref pin from an external source
(initial value)
Bit 2—Reserved
This bit is reserved. It is always read as 0 and cannot be written to.
Bit 1—LVD Power Supply Voltage Drop Flag (LVDDF)
This bit indicates when a power supply voltage drop has been detected.
Bit 1
LVDDF
Description
0
[Clearing condition]
When 0 is written after reading 1
(initial value)
1
[Setting condition]
When the power supply voltage drops below Vint(D)
Bit 0—LVD Power Supply Voltage Rise Flag (LVDUF)
This bit indicates when a power supply voltage rise has been detected.
Bit 0
LVDUF
0
1
Description
[Clearing condition]
When 0 is written after reading 1
(initial value)
[Setting condition]
When the power supply voltage drops below Vint(D) while the LVDUE bit in
LVDCR is set to 1, and it rises above Vint(U) before dropping below Vreset1
Rev. 8.00 Mar. 09, 2010 Page 437 of 658
REJ09B0042-0800
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only)
14.2.3
Low-Voltage Detection Counter (LVDCNT)
Bit
7
6
5
4
3
2
1
0
CNT7
CNT6
CNT5
CNT4
CNT3
CNT2
CNT1
CNT0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
LVDCNT is a read-only 8-bit up-counter. Counting begins when 1 is written to LVDE. The
counter increments using φ/4 as the clock source until it overflows by switching from H'FF to
H'00, at which time the OVF bit in the LVDSR register is set to 1, indicating that the on-chip
reference voltage generator has stabilized. If the LVD function is used, it is necessary to stand by
until the counter has overflowed. The initial value of LVDCNT is H'00.
14.2.4
Clock Stop Register 2 (CKSTPR2)
Bit
7
6
5
LVDCKSTP
—
—
4
3
PW2CKSTP AECKSTP
2
1
0
WDCKSTP PW1CKSTP LDCKSTP
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
—
—
R/W
R/W
R/W
R/W
R/W
CKSTPR2 is an 8-bit read/write register. It is used to control the module’s module standby mode.
Only the bits relevant to the LVD function are described in this section. Refer to the sections on
the other modules for information about the other bits.
Bit 7—LVD Module Standby Control (LVDCKSTP)
This bit is used to control setting of the LVD function to module standby status and cancellation of
that status.
Bit 7
LVDCKSTP
Description
0
Sets LVD to module standby status
1
Cancels LVD module standby status
(initial value)
Note: This bit is implemented on the H8/38124 Group only. On other products it is always read as
1 and cannot be written to.
Rev. 8.00 Mar. 09, 2010 Page 438 of 658
REJ09B0042-0800
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only)
14.3
14.3.1
Operation
Power-On Reset Circuit
Figure 14.2 shows the timing of the operation of the power-on reset circuit. As the power-supply
voltage rises, the capacitor which is externally connected to the RES pin is gradually charged via
the on-chip pull-up resistor (typ. 100 kΩ). Since the state of the RES pin is transmitted within the
chip, the prescaler S and the entire chip are in their reset states. When the level on the RES pin
reaches the specified value, the prescaler S is released from its reset state and it starts counting.
The OVF signal is generated to release the internal reset signal after the prescaler S has counted
131,072 clock (φ) cycles. The noise cancellation circuit of approximately 100 ns is incorporated to
prevent the incorrect operation of the chip by noise on the RES pin.
To achieve stable operation of this LSI, the power supply needs to rise to its full level and settles
within the specified time. The maximum time required for the power supply to rise and settle after
power has been supplied (tPWON) is determined by the oscillation frequency (fOSC) and capacitance
which is connected to RES pin (CRES). If tPWON means the time required to reach 90 % of power
supply voltage, the power supply circuit should be designed to satisfy the following formula.
tPWON (ms) ≤ 80 × CRES (μF) ± 10/fOSC (MHz)
(tPWON ≤ 3000 ms, CRES ≥ 0.22 μF, and fOSC = 10 in 2-MHz to 10-MHz operation)
Note that the power supply voltage (Vcc) must fall below Vpor = 100 mV and rise after charge on
the RES pin is removed. To remove charge on the RES pin, it is recommended that the diode
should be placed near Vcc. If the power supply voltage (Vcc) rises from the point above Vpor, a
power-on reset may not occur.
Rev. 8.00 Mar. 09, 2010 Page 439 of 658
REJ09B0042-0800
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only)
tPWON
Vcc
Vpor
Vss
RES
Vss
PSS-reset
signal
OVF
Internal reset
signal
131,072 cycles
PSS counter starts
Reset released
Figure 14.2 Operational Timing of Power-On Reset Circuit
14.3.2
Low-Voltage Detection Circuit
LVDR (Reset by Low Voltage Detect) Circuit:
Figure 14.3 shows the timing of the LVDR function. The LVDR enters the module-standby state
after a power-on reset is canceled. To operate the LVDR, set the LVDE bit in LVDCR to 1, wait
for 150 μs (tLVDON) until the reference voltage and the low-voltage-detection power supply have
stabilized, based on overflow of LVDNT, etc., then set the LVDRE bit in LVDCR to 1. After that,
the output settings of ports must be made. To cancel the low-voltage detection circuit, first the
LVDRE bit should be cleared to 0 and then the LVDE bit should be cleared to 0. The LVDE and
LVDRE bits must not be cleared to 0 simultaneously because incorrect operation may occur.
When the power-supply voltage falls below the Vreset voltage (typ. = 2.3 V or 3.3 V), the LVDR
clears the LVDRES signal to 0, and resets the prescaler S. The low-voltage detection reset state
remains in place until a power-on reset is generated. When the power-supply voltage rises above
the Vreset voltage again, the prescaler S starts counting. It counts 131,072 clock (φ) cycles, and
then releases the internal reset signal. In this case, the LVDE, LVDSEL, and LVDRE bits in
LVDCR are not initialized.
Note that if the power supply voltage (Vcc) falls below VLVDRmin = 1.0 V and then rises from that
point, the low-voltage detection reset may not occur.
If the power supply voltage (Vcc) falls below Vpor = 100 mV, a power-on reset occurs.
Rev. 8.00 Mar. 09, 2010 Page 440 of 658
REJ09B0042-0800
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only)
VCC
Vreset
VLVDRmin
VSS
LVDRES
PSS-reset
signal
OVF
Internal reset
signal
131,072 cycles
PSS counter starts
Reset released
Figure 14.3 Operational Timing of LVDR Circuit
LVDI (Interrupt by Low Voltage Detect) Circuit:
Figure 14.4 shows the timing of LVDI functions. The LVDI enters the module-standby state after
a power-on reset is canceled. To operate the LVDI, set the LVDE bit in LVDCR to 1, wait for 150
μs (tLVDON) until the reference voltage and the low-voltage-detection power supply have stabilized,
based on overflow of LVDNT, etc., then set the LVDDE and LVDUE bits in LVDCR to 1. After
that, the output settings of ports must be made. To cancel the low-voltage detection circuit, first
the LVDDE and LVDUE bits should all be cleared to 0 and then the LVDE bit should be cleared
to 0. The LVDE bit must not be cleared to 0 at the same timing as the LVDDE and LVDUE bits
because incorrect operation may occur.
When the power-supply voltage falls below Vint (D) (typ. = 3.7 V) voltage, the LVDI clears the
LVDINT signal to 0 and the LVDDF bit in LVDSR is set to 1. If the LVDDE bit is 1 at this time,
an IRQ0 interrupt request is simultaneously generated. In this case, the necessary data must be
saved in the external EEPROM, etc, and a transition must be made to standby mode or watch
mode. Until this processing is completed, the power supply voltage must be higher than the lower
limit of the guaranteed operating voltage.
Rev. 8.00 Mar. 09, 2010 Page 441 of 658
REJ09B0042-0800
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only)
When the power-supply voltage does not fall below Vreset1 (typ. = 2.3 V) voltage but rises above
Vint (U) (typ. = 4.0 V) voltage, the LVDI sets the LVDINT signal to 1. If the LVDUE bit is 1 at
this time, the LVDUF bit in LVDSR is set to 1 and an IRQ0 interrupt request is simultaneously
generated.
If the power supply voltage (Vcc) falls below Vreset1 (typ. = 2.3 V) voltage, the LVDR function
is performed.
Vint (U)
Vint (D)
Vcc
Vreset1
VSS
LVDINT
LVDDE
LVDDF
LVDUE
LVDUF
IRQ0 interrupt generated IRQ0 interrupt generated
Figure 14.4 Operational Timing of LVDI Circuit
The reference voltage, power supply voltage drop detection level, and power supply voltage rise
detection level can be input to the LSI from external sources via the Vref, extD, and extU pins.
Figure 14.5 shows the operational timing using input from the Vref, extD, and extU pins.
First, make sure that the voltages input to pins extD and extU are set to higher levels than the
interrupt detection voltage Vexd. After initial settings are made, a power supply drop interrupt is
generated if the extD input voltage drops below Vexd. After a power supply drop interrupt is
generated, if the external power supply voltage rises and the extU input voltage rises higher than
Vexd, a power supply rise interrupt is generated. As with the on-chip circuit, the above function
should be used in conjunction with LVDR (Vreset1) when the LVDI function is used.
Rev. 8.00 Mar. 09, 2010 Page 442 of 658
REJ09B0042-0800
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only)
External power
supply voltage
extD input voltage
extU input voltage (1)
(2)
Vexd
(3)
(4) Vreset1
VSS
LVDINTD
LVDDF
LVDINTU
LVDUF
IRQ0 interrupt
generated
IRQ0 interrupt
generated
Figure 14.5 Operational Timing of Low-Voltage Detection Interrupt Circuit
(Using Pins Vref, extD, and extU)
Rev. 8.00 Mar. 09, 2010 Page 443 of 658
REJ09B0042-0800
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only)
Figure 14.6 shows a usage example for the LVD function employing pins Vref, extD, and extU.
LVDCR
On-chip
ladder
resistor
R1
R2
D1
External power
supply voltage
R1 =
517 kΩ
U1
D2
U2
+
−
LVDRES
+
−
LVDINT
Interrupt
controller
extD
R2 =
33 kΩ
LVDSR
Interrupt
request
extU
R3 =
450 kΩ
Vref
External reference
voltage 1.3 V
On-chip reference
voltage generator
Setting conditions:
• Vref = 1.3 V external input (This Vref value results in a Vreset value of 2.5 V.)
• Power supply drop detection voltage input of 2.7 V from extD
• Power supply rise detection voltage input of 2.9 V from extU
• 1 MΩ variable resistor connected externally
Figure 14.6 LVD Function Usage Example Employing Pins Vref, extD, and extU
Below is an explanation of the method for calculating the external resistor values when using the
Vref, extD, and extU pins for input of reference and detection voltages from sources external to
the LSI.
Procedure:
1. First, determine the overall resistance value, R. The current consumed by the resistor is
determined by the value of R. A lower R will result in a greater current flow, and a higher R
will result in a reduced current flow. The value of R is dependent on the configuration of the
system in which the LSI is installed.
2. Determine the power supply drop detection voltage (Vint(D) and the power supply rise
detection voltage (Vint(U).
3. Using a resistance value calculation table like the one shown below, plug in values for R,
Vreset1, Vint(D), and Vint(U) to calculate the values of Vref, R1, R2, and R3.
Rev. 8.00 Mar. 09, 2010 Page 444 of 658
REJ09B0042-0800
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only)
Resistance Value Calculation Table
Ex. No
Vref (V)
R (kΩ)
Vreset1
Vint(D)
Vint(U)
R1 (kΩ)
R2 (kΩ)
R3 (kΩ)
1
1.30
1000
2.5
2.7
2.9
517
33
450
2
1.41
1000
2.7
2.9
3
514
16
470
3
1.57
1000
3
3.2
3.5
511
42
447
4
2.09
1000
4
4.5
4.7
536
20
444
4. Using an error calculation table like the one shown below, plug in values for R1, R2, R3, and
Vref to calculate the deviation of Vreset1, Vint(D), and Vint(U). Make sure to double check
the maximum and minimum values for each value.
Error Calculation Table
Vref (V)
R1
(kΩ)
R2
(kΩ)
R3
(kΩ)
1.3
517
33
450
Resistance Value
Error (%)
5
Comparator Vreset1
Error (V)
(V)
Vint(D)
(V)
Vint(U)
(V)
R1+Err, R2/R3-Err
0.1
2.59
2.94
3.15
0
2.49
2.84
3.05
-0.1
2.39
2.74
2.95
R1-Err, R2/R3+Err
R1/R2/R3 No Err
R1/R2+Err, R3-Err
R1/R2-Err, R3+Err
0.1
2.59
2.66
2.85
0
2.49
2.56
2.75
-0.1
2.39
2.46
2.65
0.1
2.59
2.79
2.99
0
2.49
2.69
2.89
-0.1
2.39
2.59
2.79
0.1
2.59
2.93
3.16
0
2.49
2.83
3.06
-0.1
2.39
2.73
2.96
0.1
2.59
2.67
2.84
0
2.49
2.57
2.74
-0.1
2.39
2.47
2.64
Rev. 8.00 Mar. 09, 2010 Page 445 of 658
REJ09B0042-0800
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only)
Operation and Cancellation Setting Procedure Using LVDR and LVDI:
Settings should be made as indicated below in order to ensure proper operation of the low voltage
detection circuit or to cancel operation. Figure 14.7 shows the setting timing for low voltage
detection circuit operation and cancellation.
1. To turn on the low voltage detection circuit, first set the LVDE bit in LVDCR to 1.
2. After waiting for LVDCNT overflow, etc., to ensure that the stabilization time (tLVDON = 150
μs) for the reference voltage and low voltage detection power supply has elapsed, clear bits
LVDDF and LVDUF in LVDSR to 0. If necessary, set the LVDRE, LVDDE, and LVDUE bits
in LVDCR to 1.
3. To cancel operation of the low voltage detection circuit, clear bits LVDRE, LVDDE, and
LVDUE to 0, then clear bit LVDE to 0. Bit LVDE should not be cleared at the same time as
bits LVDRE, LVDDE, and LVDUE to avoid malfunction.
LVDE
LVDRE
LVDDE
LVDUE
tLVDON
Figure 14.7 Low Voltage Detection Circuit Operation and Cancellation Setting Timing
Rev. 8.00 Mar. 09, 2010 Page 446 of 658
REJ09B0042-0800
Section 15 Power Supply Circuit (H8/38124 Group Only)
Section 15 Power Supply Circuit
(H8/38124 Group Only)
This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the
internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the
voltage of the power supply connected to the external VCC pin. As a result, the current consumed
when an external power supply is used at 3.0 V or above can be held down to virtually the same
low level as when used at approximately 3.0 V. If the external power supply is 3.0 V or below, the
internal voltage will be practically the same as the external voltage. It is, of course, also possible to
use the same level of external power supply voltage and internal power supply voltage without
using the internal power supply step-down circuit.
15.1
When Using Internal Power Supply Step-Down Circuit
Connect the external power supply to the VCC pin, and connect a capacitance of approximately 0.1
µF between CVCC and VSS, as shown in figure 15.1. The internal step-down circuit is made
effective simply by adding this external circuit. In the external circuit interface, the external power
supply voltage connected to VCC and the GND potential connected to VSS are the reference levels.
For example, for port input/output levels, the VCC level is the reference for the high level, and the
VSS level is that for the low level. The A/D converter analog power supply is not affected by the
internal step-down circuit.
VCC
Step-down circuit
Internal
logic
VCC = 2.7 to 5.5 V
CVCC
Stabilization
capacitance
(approx. 0.1 µF)
Internal
power
supply
VSS
Figure 15.1 Power Supply Connection when Internal Step-Down Circuit is Used
PSCKT00A_000020020200
Rev. 8.00 Mar. 09, 2010 Page 447 of 658
REJ09B0042-0800
Section 15 Power Supply Circuit (H8/38124 Group Only)
15.2
When Not Using Internal Power Supply Step-Down Circuit
When the internal power supply step-down circuit is not used, connect the external power supply
to the CVCC pin and VCC pin, as shown in figure 15.2. The external power supply is then input
directly to the internal power supply. The permissible range for the power supply voltage is 2.7 V
to 3.6 V. Operation cannot be guaranteed if a voltage outside this range (less than 3.0 V or more
than 3.6 V) is input.
VCC
Step-down circuit
Internal
logic
VCC = 2.7 to 3.6 V
CVCC
Internal
power
supply
VSS
Figure 15.2 Power Supply Connection when Internal Step-Down Circuit is Not Used
Rev. 8.00 Mar. 09, 2010 Page 448 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
Section 16 Electrical Characteristics
16.1
H8/38024 Group ZTAT Version and Mask ROM Version Absolute
Maximum Ratings
Table 16.1 lists the absolute maximum ratings.
Table 16.1 Absolute Maximum Ratings
Item
Symbol
Value
Unit
Note
Power supply voltage
VCC
–0.3 to +7.0
V
*
Analog power supply voltage
AVCC
–0.3 to +7.0
V
Programming voltage
VPP
–0.3 to +13.0
V
Input voltage
Ports other than Port B
and IRQAEC
Vin
–0.3 to VCC +0.3
V
Port B
AVin
–0.3 to AVCC +0.3
V
IRQAEC
HVin
–0.3 to +7.3
V
Port 9 pin voltage
VP9
–0.3 to +7.3
V
Operating temperature
Topr
–20 to +75
(regular
specifications)
°C
–40 to +85
(wide-range
specifications)
°C
–55 to +125
°C
Storage temperature
Tstg
Note: * Permanent damage may occur to the chip if maximum ratings are exceeded. Normal
operation should be under the conditions specified in Electrical Characteristics. Exceeding
these values can result in incorrect operation and reduced reliability.
Rev. 8.00 Mar. 09, 2010 Page 449 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
16.2
H8/38024 Group ZTAT Version and Mask ROM Version Electrical
Characteristics
16.2.1
Power Supply Voltage and Operating Range
The power supply voltage and operating range are indicated by the shaded region in the figures.
Power Supply Voltage and Oscillator Frequency Range
38.4
fW (kHz)
fosc (MHz)
16.0
10.0
32.768
4.0
2.0
1.8
2.7
4.5
5.5
VCC (V)
1.8
3.0
5.5
4.5
VCC (V)
• Active (high-speed) mode
• All operating
• Sleep (high-speed) mode
Note: 2. When an oscillator is used for the subclock,
hold VCC at 2.2 V to 5.5 V from power-on
until the oscillation settling time has elapsed.
Note: 1. The fosc values are those when an oscillator
is used; when an external clock is used the
minimum value of fosc is 1 MHz.
Rev. 8.00 Mar. 09, 2010 Page 450 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
Power Supply Voltage and Operating Frequency Range
8.0
5.0
16.384
2.0
1.0
(0.5)
9.6
1.8
2.7
4.5
5.5
VCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode (except CPU)
Note: 1. The figure in parentheses is the minimum operating
frequency when an external clock is input. When
using an oscillator, the minimum operating frequency
(φ) is 1 MHz.
φSUB (kHz)
φ (MHz)
19.2
8.192
4.8
4.096
1.8
3.6
5.5
VCC (V)
φ (kHz)
1000
• Subactive mode
• Subsleep mode (except CPU)
• Watch mode (except CPU)
625
250
15.625
(7.8125)
1.8
2.7
4.5
5.5
VCC (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode
(except A/D converter)
Note: 2. The figure in parentheses is the minimum operating
frequency when an external clock is input. When
using an oscillator, the minimum operating frequency
(φ) is 15.625 kHz.
Rev. 8.00 Mar. 09, 2010 Page 451 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
Analog Power Supply Voltage and A/D Converter Operating Range
1000
φ (kHz)
φ (MHz)
5.0
1.0
625
500
(0.5)
1.8
2.7
4.5
5.5
AVCC (V)
1.8
2.7
• Active (high-speed) mode
• Active (medium-speed) mode
• Sleep (high-speed) mode
• Sleep (medium-speed) mode
Note: 3. When AVCC = 1.8 V to 2.7 V, the operating range is limited to φ = 1.0 MHz when using an oscillator,
and is φ = 0.5 MHz to 1.0 MHz when using an external clock.
Rev. 8.00 Mar. 09, 2010 Page 452 of 658
REJ09B0042-0800
4.5
5.5
AVCC (V)
Section 16 Electrical Characteristics
16.2.2
DC Characteristics
Table 16.2 lists the DC characteristics of the H8/38024.
Table 16.2 DC Characteristics
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications), Ta = +75°C (Die) (including
subactive mode) unless otherwise indicated.
Values
Item
Symbol Applicable Pins Min
Typ
Max
Unit Test Condition
Input high
voltage
VIH
RES,
0.8 VCC
WKP0 to WKP7,
0.9 VCC
IRQ0, IRQ3, IRQ4,
AEVL, AEVH,
TMIC, TMIF,
TMIG, ADTRG,
SCK32
—
VCC + 0.3
V
—
VCC + 0.3
IRQ1
0.8 VCC
—
AVCC + 0.3
0.9 VCC
—
AVCC + 0.3
0.7 VCC
—
VCC + 0.3
0.8 VCC
—
VCC + 0.3
0.8 VCC
—
VCC + 0.3
0.9 VCC
—
VCC + 0.3
X1
0.9 VCC
—
VCC + 0.3
V
VCC = 1.8 V to 5.5 V
P13, P14,
P16, P17,
P30 to P37,
P40 to P43,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PA0 to PA3
0.7 VCC
—
VCC + 0.3
V
VCC = 4.0 V to 5.5 V
0.8 VCC
—
VCC + 0.3
PB0 to PB7
0.7 VCC
—
AVCC + 0.3
0.8 VCC
—
AVCC + 0.3
IRQAEC
0.8 VCC
—
7.3
0.9 VCC
—
7.3
RXD32, UD
OSC1
Notes
VCC = 4.0 V to 5.5 V
Except the above
V
VCC = 4.0 V to 5.5 V
Except the above
V
VCC = 4.0 V to 5.5 V
Except the above
V
VCC = 4.0 V to 5.5 V
Except the above
Except the above
V
VCC = 4.0 V to 5.5 V
Except the above
V
VCC = 4.0 V to 5.5 V
Except the above
Rev. 8.00 Mar. 09, 2010 Page 453 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
Values
Item
Symbol Applicable Pins Min
Typ
Max
Unit Test Condition
Input low
voltage
VIL
–0.3
—
0.2 VCC
V
–0.3
—
0.1 VCC
–0.3
—
0.3 VCC
–0.3
—
0.2 VCC
OSC1
–0.3
—
0.2 VCC
–0.3
—
0.1 VCC
X1
–0.3
—
0.1 VCC
V
VCC = 1.8 V to 5.5 V
P13, P14,
P16, P17,
P30 to P37,
P40 to P43,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PA0 to PA3,
PB0 to PB7
–0.3
—
0.3 VCC
V
VCC = 4.0 V to 5.5 V
–0.3
—
0.2 VCC
RES,
WKP0 to WKP7,
IRQ0, IRQ1,
IRQ3, IRQ4,
IRQAEC, AEVL,
AEVH, TMIC,
TMIF, TMIG,
ADTRG, SCK32
RXD32, UD
Output high VOH
voltage
P13, P14,
P16, P17,
P30 to P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PA0 to PA3
VCC = 4.0 V to 5.5 V
Except the above
V
VCC = 4.0 V to 5.5 V
Except the above
V
VCC = 4.0 V to 5.5 V
Except the above
Except the above
VCC – 1.0 —
—
VCC – 0.5 —
—
VCC = 4.0 V to 5.5 V
–IOH = 0.5 mA
VCC – 0.3 —
—
–IOH = 0.1 mA
Rev. 8.00 Mar. 09, 2010 Page 454 of 658
REJ09B0042-0800
V
VCC = 4.0 V to 5.5 V
–IOH = 1.0 mA
Notes
Section 16 Electrical Characteristics
Values
Item
Symbol Applicable Pins Min
Output low
voltage
VOL
P13, P14,
P16, P17,
P40 to P42
—
Typ
Max
Unit Test Condition
—
0.6
V
VCC = 4.0 V to 5.5 V
IOL = 1.6 mA
—
—
0.5
IOL = 0.4 mA
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PA0 to PA3
—
—
0.5
IOL = 0.4 mA
P30 to P37
—
—
1.5
VCC = 4.0 V to 5.5 V
IOL = 10 mA
—
—
0.6
VCC = 4.0 V to 5.5 V
IOL = 1.6 mA
—
—
0.5
IOL = 0.4 mA
—
—
0.5
VCC = 2.2 to 5.5 V
IOL = 25 mA
P90 to P92
Notes
*5
IOL = 15 mA
Input/output | IIL |
leakage
current
—
—
0.5
IOL = 10 mA
P93 to P95
—
—
0.5
IOL = 10 mA
RES, P43
—
—
20.0
—
—
1.0
OSC1, X1,
P13, P14,
P16, P17,
P30 to P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
IRQAEC,
P90 to P95,
PA0 to PA3
—
—
1.0
PB0 to PB7
—
—
1.0
µA
µA
VIN = 0.5 V to
VCC – 0.5 V
*6
*2
*1
VIN = 0.5 V to
VCC – 0.5 V
VIN = 0.5 V to
AVCC – 0.5 V
Rev. 8.00 Mar. 09, 2010 Page 455 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
Values
Item
Symbol Applicable Pins Min
Typ
Max
Unit Test Condition
Pull-up
MOS
current
–Ip
50.0
—
300.0
µA
—
35.0
—
All input pins
except power
supply, RES,
P43, PB0 to PB7
—
—
15.0
IRQAEC
—
—
30.0
RES
—
—
80.0
*2
—
—
15.0
*1
—
—
50.0
*2
—
—
15.0
*1
PB0 to PB7
—
—
15.0
IOPE1
VCC
—
7.0
10.0
mA
Active (high-speed) *3
*4
mode VCC = 5 V,
fOSC = 10 MHz
IOPE2
VCC
—
2.2
3.0
mA
Active (mediumspeed) mode
VCC = 5 V,
fOSC = 10 MHz
φosc/128
*3
*4
Sleep mode ISLEEP
current
dissipation
VCC
—
3.8
5.0
mA
VCC=5 V,
fOSC=10 MHz
*3
*4
Subactive
mode
current
dissipation
VCC
—
15.0
30.0
µA
VCC = 2.7 V,
LCD on 32 kHz
crystal oscillator
(φSUB=φw/2)
*3
*4
—
8.0
—
µA
VCC = 2.7 V,
LCD on 32 kHz
crystal oscillator
(φSUB=φw/8)
*3
*4
VCC = 2.7 V,
LCD on 32 kHz
crystal oscillator
(φSUB=φw/2)
*3
*4
Input
CIN
capacitance
P13, P14,
P16, P17,
P30 to P37,
P50 to P57,
P60 to P67
P43
Active
mode
current
dissipation
Subsleep
mode
current
dissipation
ISUB
ISUBSP
VCC
—
Rev. 8.00 Mar. 09, 2010 Page 456 of 658
REJ09B0042-0800
7.5
16.0
VCC = 5 V,
VIN = 0 V
VCC = 2.7 V,
VIN = 0 V
pF
µA
Notes
Reference
value
f = 1 MHz,
VIN =0 V,
Ta = 25°C
Reference
value
Section 16 Electrical Characteristics
Values
Item
Symbol Applicable Pins Min
Typ
Max
Unit Test Condition
Notes
Watch
mode
current
dissipation
IWATCH
3.8
6.0
µA
*2
*3
*4
2.8
6.0
VCC
—
*1
*3
*4
Standby
mode
current
dissipation
ISTBY
VCC
—
1.0
5.0
µA
RAM data
retaining
voltage
VRAM
VCC
1.5
—
—
V
Allowable
output low
current
(per pin)
IOL
Output pins
except port 3
and 9
—
—
2.0
mA
Port 3
—
—
10.0
Output pins
except port 9
—
—
0.5
P90 to P92
—
—
25.0
—
—
15.0
—
—
10.0
P93 to P95
—
—
10.0
Output pins
except ports 3
and 9
—
—
40.0
Port 3
—
—
80.0
Output pins
except port 9
—
—
20.0
Port 9
—
—
80.0
All output pins
—
—
2.0
—
—
0.2
Allowable
output low
current
(total)
∑ IOL
Allowable
–IOH
output high
current
(per pin)
VCC = 2.7 V,
32 kHz crystal
oscillator
LCD not used
32 kHz crystal
oscillator not used
*3
*4
VCC = 4.0 V to 5.5 V
VCC = 4.0 V to 5.5 V
VCC = 2.2 V to 5.5 V *5
mA
VCC = 4.0 V to 5.5 V
VCC = 4.0 V to 5.5 V
mA
VCC = 4.0 V to 5.5 V
Except the above
Rev. 8.00 Mar. 09, 2010 Page 457 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
Values
Item
Symbol Applicable Pins Min
Allowable
∑ – IOH
output high
current
(total)
All output pins
Typ
Max
Unit Test Condition
—
—
15.0
mA
—
—
10.0
Notes
VCC = 4.0 V to 5.5 V
Except the above
Notes: Connect the TEST pin to VSS.
1. Applies to the Mask ROM products.
2. Applies to the HD64738024.
3. Pin states during current measurement.
Mode
Active (high-speed)
mode (IOPE1)
RES
Pin
Internal State
Other
Pins
LCD Power
Supply
VCC
Operates
VCC
Halted
Oscillator Pins
System clock oscillator:
crystal
Subclock oscillator:
Pin X1 = GND
Active (mediumspeed) mode (IOPE2)
Sleep mode
VCC
Only timers operate
VCC
Halted
Subactive mode
VCC
Operates
VCC
Halted
Subsleep mode
VCC
Only timers operate,
CPU stops
VCC
Halted
Watch mode
VCC
Only time base
operates, CPU stops
VCC
Halted
Standby mode
VCC
CPU and timers both
stop
VCC
Halted
System clock oscillator:
crystal
Subclock oscillator:
crystal
System clock oscillator:
crystal
Subclock oscillator:
Pin X1 = GND
4. Excludes current in pull-up MOS transistors and output buffers.
5. When the PIOFF bit in the port mode register 9 is 0.
6. When the PIOFF bit in the port mode register 9 is 1.
Rev. 8.00 Mar. 09, 2010 Page 458 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
16.2.3
AC Characteristics
Table 16.3 lists the control signal timing, and tables 16.4 lists the serial interface timing of the
H8/38024.
Table 16.3 Control Signal Timing
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications), Ta = +75°C (Die) (including
subactive mode) unless otherwise indicated.
Item
System clock
oscillation
frequency
OSC clock (φOSC)
cycle time
System clock (φ)
cycle time
Values
Reference
Figure
Applicable
Symbol Pins
Min
Typ
Max
Unit
Test Condition
fOSC
2.0
—
16.0
MHz
VCC = 4.5 V to 5.5 V
2.0
—
10.0
VCC = 2.7 V to 5.5 V
2.0
—
4.0
Except the above
62.5
—
500
ns
(1000)
VCC = 4.5 V to 5.5 V Figure 16.2
*2
100
—
500
(1000)
VCC = 2.7 V to 5.5 V
250
—
500
(1000)
Except the above
2
—
128
tOSC
—
—
128
µs
tOSC
OSC1, OSC2
OSC1, OSC2
tcyc
Subclock oscillation fW
frequency
X1, X2
—
32.768 —
or 38.4
kHz
Watch clock (φW)
cycle time
tW
X1, X2
—
30.5 or —
26.0
µs
Figure 16.2
Subclock (φSUB)
cycle time
tsubcyc
2
—
8
tW
*1
2
—
—
tcyc
tsubcyc
—
20
45
µs
Figure 16.9
Figure 16.9
VCC = 2.2 V to 5.5 V
—
—
50
ms
Except the above
—
—
2.0
s
VCC = 2.7 V to 5.5 V *3
—
—
10.0
Instruction cycle
time
Oscillation
stabilization time
trc
OSC1, OSC2
X1, X2
VCC = 2.2 V to 5.5 V
Rev. 8.00 Mar. 09, 2010 Page 459 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
Item
External clock high
width
External clock low
width
External clock rise
time
External clock fall
time
Pin RES low width
Min
Typ
Max
Unit
Test Condition
tCPH
25
—
—
ns
VCC = 4.5 V to 5.5 V Figure 16.2
40
—
—
tCPL
tCPr
tCPf
tREL
Input pin high width tIH
Input pin low width
Values
Applicable
Symbol Pins
tIL
OSC1
Reference
Figure
VCC = 2.7 V to 5.5 V
100
—
—
X1
—
15.26
or
13.02
—
µs
Except the above
OSC1
25
—
—
ns
VCC = 4.5 V to 5.5 V Figure 16.2
40
—
—
VCC = 2.7 V to 5.5 V
100
—
—
Except the above
X1
—
15.26
or
13.02
—
µs
OSC1
—
—
6
ns
—
—
10
VCC = 2.7 V to 5.5 V
—
—
25
Except the above
X1
—
—
55.0
ns
OSC1
—
—
6
ns
VCC = 4.5 V to 5.5 V Figure 16.2
VCC = 4.5 V to 5.5 V Figure 16.2
—
—
10
VCC = 2.7 V to 5.5 V
—
—
25
Except the above
X1
—
—
55.0
ns
RES
10
—
—
tcyc
Figure 16.3
2
IRQ0, IRQ1,
IRQ3, IRQ4,
IRQAEC,
WKP0 to WKP7,
TMIC, TMIF,
TMIG, ADTRG
—
—
tcyc
tsubcyc
Figure 16.4
AEVL, AEVH
—
—
tosc
2
IRQ0, IRQ1,
IRQ3, IRQ4,
IRQAEC,
WKP0 to WKP7,
TMIC, TMIF,
TMIG, ADTRG
—
—
tcyc
tsubcyc
AEVL, AEVH
—
—
tosc
Rev. 8.00 Mar. 09, 2010 Page 460 of 658
REJ09B0042-0800
0.5
0.5
Figure 16.4
Section 16 Electrical Characteristics
Item
Applicable
Symbol Pins
UD pin minimum
transition width
tUDH
tUDL
UD
Values
Min
Typ
Max
Unit
4
—
—
tcyc
tsubcyc
Test Condition
Reference
Figure
Figure 16.7
Notes: 1. Selected with SA1 and SA0 of system control register 2 (SYSCR2).
2. The figure in parentheses applies when an external clock is used.
3. After powering on, hold VCC at 2.2 V to 5.5 V until the chip's oscillation settling time has
elapsed.
Table 16.4 Serial Interface (SCI3) Timing
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications), Ta = +75°C (Die) (including
subactive mode) unless otherwise indicated.
Values
Item
Input clock
cycle
Asynchronous
Symbol
Min
Typ
Max
Unit
tscyc
4
—
—
tcyc or
6
—
—
tsubcyc
Synchronous
Test Conditions
Figure 16.5
Input clock pulse width
tSCKW
0.4
—
0.6
tscyc
Transmit data delay time
(synchronous)
tTXD
—
—
1
tcyc or
VCC = 4.0 V to 5.5 V
—
—
1
tsubcyc
Except the above
Receive data setup time
(synchronous)
tRXS
ns
Receive data hold time
(synchronous)
tRXH
200.0
—
—
400.0
—
—
200.0
—
—
400.0
—
—
ns
Reference
Figure
Figure 16.5
Figure 16.6
VCC = 4.0 V to 5.5 V
Figure 16.6
Except the above
Figure 16.6
VCC = 4.0 V to 5.5 V
Figure 16.6
Except the above
Figure 16.6
Rev. 8.00 Mar. 09, 2010 Page 461 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
16.2.4
A/D Converter Characteristics
Table 16.5 shows the A/D converter characteristics of the H8/38024.
Table 16.5 A/D Converter Characteristics
VCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications), Ta = +75°C (Die) unless otherwise indicated.
Item
Applicable
Symbol Pins
Values
Min
Typ
Max
Unit
Analog power AVCC
supply voltage
AVCC
1.8
—
5.5
V
Analog input
voltage
AN0 to AN7
– 0.3
—
AVCC + 0.3
V
AVCC
—
—
1.5
mA
AVCC
—
600
—
µA
AVIN
Analog power AIOPE
supply current
AISTOP1
Test Condition
Reference
Figure
*1
AVCC = 5.0 V
*2
Reference
value
*3
AISTOP2
AVCC
—
—
5
µA
Analog input
capacitance
CAIN
AN0 to AN7
—
—
15.0
pF
Allowable
signal source
impedance
RAIN
—
—
10.0
kΩ
Resolution
(data length)
—
—
10
bit
Nonlinearity
error
—
—
±2.5
LSB
—
—
±5.5
AVCC = 2.0 V to 5.5 V
VCC = 2.0 V to 5.5 V
—
—
±7.5
Except the above
—
—
±0.5
Quantization
error
Rev. 8.00 Mar. 09, 2010 Page 462 of 658
REJ09B0042-0800
LSB
AVCC = 2.7 V to 5.5 V
VCC = 2.7 V to 5.5 V
*4
Section 16 Electrical Characteristics
Item
Absolute
accuracy
Conversion
time
Applicable
Symbol Pins
Values
Min
Typ
Max
Unit
Test Condition
—
—
±3.0
LSB
AVCC = 2.7 V to 5.5 V
VCC = 2.7 V to 5.5 V
—
—
±6.0
AVCC = 2.0 V to 5.5 V
VCC = 2.0 V to 5.5 V
—
—
±8.0
Except the above
12.4
—
124
62
—
124
µs
Reference
Figure
*4
AVCC = 2.7 V to 5.5 V
VCC = 2.7 V to 5.5 V
Except the above
Notes: 1. Set AVCC = VCC when the A/D converter is not used.
2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle.
3. AISTOP2 is the current at reset and in standby, watch, subactive, and subsleep modes
while the A/D converter is idle.
4. Conversion time 62 µs
Rev. 8.00 Mar. 09, 2010 Page 463 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
16.2.5
LCD Characteristics
Table 16.6 shows the LCD characteristics.
Table 16.6 LCD Characteristics
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications), Ta = +75°C (Die) (including
subactive mode) unless otherwise specified.
Item
Applicable
Symbol Pins
Min
Values
Test
Typ Max Unit Conditions
Reference
Figure
Segment driver
drop voltage
VDS
SEG1 to
SEG32
—
—
0.6
V
*1
ID = 2 µA
V1 = 2.7 V to 5.5 V
Common driver
drop voltage
VDC
COM1 to
COM4
—
—
0.3
V
*1
ID = 2 µA
V1 = 2.7 V to 5.5 V
0.5
3.0
9.0
MΩ
Between V1 and
VSS
2.2
—
5.5
V
LCD power supply RLCD
split-resistance
Liquid crystal
display voltage
VLCD
V1
*2
Notes: 1. The voltage drop from power supply pins V1, V2, V3, and VSS to each segment pin or
common pin.
2. When the liquid crystal display voltage is supplied from an external power source,
ensure that the following relationship is maintained: VCC ≥ V1 ≥ V2 ≥ V3 ≥ VSS.
Rev. 8.00 Mar. 09, 2010 Page 464 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
16.3
H8/38024 Group F-ZTAT Version and H8/38024R Group F-ZTAT
Version Absolute Maximum Ratings
Table 16.7 lists the absolute maximum ratings.
Table 16.7 Absolute Maximum Ratings
Item
Symbol
Value
Unit
Note
Power supply voltage
VCC
–0.3 to +4.3
V
*1
Analog power supply voltage
AVCC
–0.3 to +4.3
V
Input voltage
Ports other than Port B
and IRQAEC
Vin
–0.3 to VCC +0.3
V
Port B
AVin
–0.3 to AVCC +0.3
V
IRQAEC
HVin
–0.3 to +7.3
V
Port 9 pin voltage
VP9
V
Operating temperature
Topr
–0.3 to +7.3
2
–20 to +75*
(regular
specifications)
2
–40 to +85*
(wide-range
specifications)
°C
°C
+75 (products
3
shipped as chips)*
Storage temperature
Tstg
–55 to +125
°C
Notes: 1. Permanent damage may occur to the chip if maximum ratings are exceeded. Normal
operation should be under the conditions specified in Electrical Characteristics.
Exceeding these values can result in incorrect operation and reduced reliability.
2. The operating temperature ranges for flash memory programming/erasing are
Ta = –20°C to +75°C.
3. Power may be applied when the temperature is between –20°C and +75°C.
Rev. 8.00 Mar. 09, 2010 Page 465 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
16.4
H8/38024 Group F-ZTAT Version and H8/38024R Group F-ZTAT
Version Electrical Characteristics
16.4.1
Power Supply Voltage and Operating Range
The power supply voltage and operating range are indicated by the shaded region in the figures.
Power Supply Voltage and Oscillator Frequency Range
fW (kHz)
fosc (MHz)
38.4
10.0
32.768
2.0
2.7
3.6
VCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
Note: The fosc values are those when an oscillator
is used; when an external clock is used the
minimum value of fosc is 1 MHz.
Rev. 8.00 Mar. 09, 2010 Page 466 of 658
REJ09B0042-0800
2.7
• All operating
3.6
VCC (V)
Section 16 Electrical Characteristics
Power Supply Voltage and Operating Frequency Range
19.2
16.384
1.0
(0.5)
9.6
2.7
3.6
VCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode (except CPU)
Note: 1. The figure in parentheses is the minimum operating
frequency when an external clock is input. When
using an oscillator, the minimum operating frequency
(φ) is 1 MHz.
φSUB (kHz)
φ (MHz)
5.0
8.192
4.8
4.096
2.7
3.6
VCC (V)
• Subactive mode
φ (kHz)
• Subsleep mode (except CPU)
• Watch mode (except CPU)
625
15.625
(7.8125)
2.7
3.6
VCC (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode
(except A/D converter)
Note: 2. The figure in parentheses is the minimum operating
frequency when an external clock is input. When
using an oscillator, the minimum operating frequency
(φ) is 15.625 kHz.
Rev. 8.00 Mar. 09, 2010 Page 467 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
Analog Power Supply Voltage and A/D Converter Operating Range
φ (kHz)
φ (MHz)
5.0
1.0
625
500
(0.5)
2.7
3.6
AVCC (V)
2.7
• Active (high-speed) mode
• Active (medium-speed) mode
• Sleep (high-speed) mode
• Sleep (medium-speed) mode
Rev. 8.00 Mar. 09, 2010 Page 468 of 658
REJ09B0042-0800
3.6
AVCC (V)
Section 16 Electrical Characteristics
16.4.2
DC Characteristics
Table 16.8 lists the DC characteristics of the HD64F38024 and HD64F38024R.
Table 16.8 DC Characteristics
VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V
Values
Item
Symbol Applicable Pins Min
Typ
Max
Unit Test Condition
Input high
voltage
VIH
RES,
0.9 VCC
WKP0 to WKP7,
IRQ0, IRQ3, IRQ4,
AEVL, AEVH,
TMIC, TMIF,
TMIG, ADTRG,
SCK32
—
VCC + 0.3
V
IRQ1
0.9 VCC
—
AVCC + 0.3
V
RXD32, UD
0.8 VCC
—
VCC + 0.3
V
OSC1
0.9 VCC
—
VCC + 0.3
V
X1
0.9 VCC
—
VCC + 0.3
V
P13, P14,
P16, P17,
P30 to P37,
P40 to P43,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PA0 to PA3
0.8 VCC
—
VCC + 0.3
V
PB0 to PB7
0.8 VCC
—
AVCC + 0.3
V
IRQAEC, P95*5
0.9 VCC
—
7.3
V
Notes
Rev. 8.00 Mar. 09, 2010 Page 469 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
Values
Item
Symbol Applicable Pins Min
Input low
voltage
VIL
Output high VOH
voltage
Typ
Max
Unit Test Condition
RES,
WKP0 to WKP7,
IRQ0, IRQ1,
IRQ3, IRQ4,
IRQAEC, P95*5,
AEVL, AEVH,
TMIC, TMIF,
TMIG, ADTRG,
SCK32
–0.3
—
0.1 VCC
V
RXD32, UD
–0.3
—
0.2 VCC
V
OSC1
–0.3
—
0.1 VCC
V
X1
–0.3
—
0.1 VCC
V
P13, P14,
P16, P17,
P30 to P37,
P40 to P43,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PA0 to PA3,
PB0 to PB7
–0.3
—
0.2 VCC
V
P13, P14,
P16, P17,
P30 to P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PA0 to PA3
VCC – 1.0 —
—
V
VCC – 0.3 —
—
Rev. 8.00 Mar. 09, 2010 Page 470 of 658
REJ09B0042-0800
–IOH = 1.0 mA
–IOH = 0.1 mA
Notes
Section 16 Electrical Characteristics
Values
Item
Symbol Applicable Pins Min
Output low
voltage
VOL
Input/output | IIL |
leakage
current
Pull-up
MOS
current
–Ip
Input
CIN
capacitance
Typ
Max
Unit Test Condition
Notes
P13, P14,
P16, P17,
P30 to P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PA0 to PA3
—
—
0.5
V
IOL = 0.4 mA
P90 to P92
—
—
0.5
V
IOL = 25 mA
*1
IOL = 10 mA
*2
P93 to P95
—
—
0.5
V
IOL = 10 mA
RES, P43,
OSC1, X1,
P13, P14,
P16, P17,
P30 to P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
IRQAEC,
P90 to P95,
PA0 to PA3
—
—
1.0
µA
VIN = 0.5 V to
VCC – 0.5 V
PB0 to PB7
—
—
1.0
µA
VIN = 0.5 V to
AVCC – 0.5 V
P13, P14,
P16, P17,
P30 to P37,
P50 to P57,
P60 to P67
30
—
180
µA
VCC = 3 V,
VIN = 0 V
All input pins
except power
supply and
IRQAEC
—
—
15.0
pF
f = 1 MHz,
VIN =0 V,
Ta = 25°C
IRQAEC
—
—
30.0
pF
Rev. 8.00 Mar. 09, 2010 Page 471 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
Values
Item
Symbol Applicable Pins Min
Typ
Max
Unit Test Condition
Active
mode
current
dissipation
IOPE1
—
1.2
—
mA
Active (high-speed) *3
*4
mode
VCC = 3 V,
Max.
fOSC = 2 MHz
guideline
= 1.1 ×
typ.
—
1.8
—
mA
Active (high-speed) *3
*4
mode
VCC = 3 V,
Max.
fOSC = 4 MHz
guideline
= 1.1 ×
typ.
—
4.0
6.0
mA
Active (high-speed) *3
*4
mode
VCC = 3 V,
fOSC = 10 MHz
—
0.7
—
mA
Active (mediumspeed) mode
VCC = 3 V,
fOSC = 2 MHz
φosc/128
IOPE2
VCC
VCC
—
—
Rev. 8.00 Mar. 09, 2010 Page 472 of 658
REJ09B0042-0800
0.8
1.2
—
1.8
mA
mA
Active (mediumspeed) mode
VCC = 3 V,
fOSC = 4 MHz
φosc/128
Active (mediumspeed) mode
VCC = 3 V,
fOSC = 10 MHz
φosc/128
Notes
*3
*4
Max.
guideline
= 1.1 ×
typ.
*3
*4
Max.
guideline
= 1.1 ×
typ.
*3
*4
Section 16 Electrical Characteristics
Values
Item
Symbol Applicable Pins Min
Sleep mode ISLEEP
current
dissipation
VCC
—
Typ
Max
Unit Test Condition
Notes
1.0
—
mA
*3
*4
VCC= 3 V,
fOSC= 2 MHz
Max.
guideline
= 1.1 ×
typ.
—
1.5
—
mA
VCC= 3 V,
fOSC= 4 MHz
*3
*4
Max.
guideline
= 1.1 ×
typ.
Subactive
mode
current
dissipation
Subsleep
mode
current
dissipation
ISUB
ISUBSP
VCC
VCC
—
3.2
4.8
mA
VCC= 3 V,
fOSC= 10 MHz
*3
*4
—
10
—
µA
VCC = 2.7 V,
LCD on 32 kHz
crystal resonator
(φSUB=φw/8)
*3
*4
*3
*4
—
20
40
µA
VCC = 2.7 V,
LCD on 32 kHz
External Clock
(φSUB=φw/2)
—
17
40
µA
VCC = 2.7 V,
LCD on 32 kHz
crystal resonator
(φSUB=φw/2)
—
4.8
16.0
µA
VCC = 2.7 V,
LCD on 32 kHz
External Clock
(φSUB=φw/2)
—
5.4
16.0
µA
VCC = 2.7 V,
LCD on 32 kHz
crystal resonator
(φSUB=φw/2)
Reference
value
*3
*4
Rev. 8.00 Mar. 09, 2010 Page 473 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
Values
Item
Symbol Applicable Pins Min
Typ
Max
Unit Test Condition
Notes
Watch
mode
current
dissipation
IWATCH
2.0
—
µA
*3
*4
Standby
mode
current
dissipation
ISTBY
VCC
VCC
—
—
2.6
—
µA
VCC = 2.7 V,
Ta = 25°C
32 kHz crystal
resonator
LCD not used
—
2.0
6.0
µA
VCC = 2.7 V,
32 kHz External
Clock
LCD not used
—
2.6
6.0
µA
VCC = 2.7 V,
32 kHz crystal
resonator
LCD not used
—
0.3
—
µA
VCC = 3.0 V,
Ta = 25°C
32 kHz crystal
resonator not used
—
1.0
5.0
µA
RAM data
retaining
voltage
VRAM
VCC
2.0
—
—
V
Allowable
output low
current
(per pin)
IOL
Output pins
except port 9
—
—
0.5
mA
P90 to P92
—
—
25.0
mA
—
—
10.0
P93 to P95
—
—
10.0
mA
Output pins
except port 9
—
—
20.0
mA
Port 9
—
—
80.0
mA
Allowable
output low
current
(total)
VCC = 2.7 V,
Ta = 25°C
32 kHz External
Clock
LCD not used
∑ IOL
Rev. 8.00 Mar. 09, 2010 Page 474 of 658
REJ09B0042-0800
32 kHz crystal
resonator not used
Reference
value
*3
*4
*3
*4
Reference
value
*3
*4
*1
*2
*5
Section 16 Electrical Characteristics
Values
Item
Symbol Applicable Pins Min
Typ
Max
Unit Test Condition
Allowable
–IOH
output high
current
(per pin)
All output pins
—
—
0.2
mA
∑ – IOH
Allowable
output high
current
(total)
All output pins
—
—
10.0
mA
Notes
Notes: Connect the TEST pin to VSS.
1. Applied when the PIOFF bit in the port mode register 9 is 0.
2. Applied when the PIOFF bit in the port mode register 9 is 1.
3. Pin states during current measurement.
Mode
Active (high-speed)
mode (IOPE1)
RES
Pin
Internal State
Other
Pins
LCD Power
Supply
VCC
Operates
VCC
Halted
Oscillator Pins
System clock oscillator:
crystal
Subclock oscillator:
Pin X1 = GND
Active (mediumspeed) mode (IOPE2)
Sleep mode
VCC
Only on-chip timers VCC
operate
Halted
Subactive mode
VCC
Operates
VCC
Halted
Subsleep mode
VCC
Only on-chip timers VCC
operate, CPU stops
Halted
Watch mode
VCC
Only time base
operates, CPU stops
VCC
Halted
Standby mode
VCC
CPU and timers both
stop
VCC
Halted
System clock oscillator:
crystal
Subclock oscillator:
crystal
System clock oscillator:
crystal
Subclock oscillator:
Pin X1 = GND
4. Excludes current in pull-up MOS transistors and output buffers.
5. Used for the judgment of user mode or boot mode when the reset is released.
Rev. 8.00 Mar. 09, 2010 Page 475 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
16.4.3
AC Characteristics
Table 16.9 lists the control signal timing, and tables 16.10 lists the serial interface timing of the
H8/38024F.
Table 16.9 Control Signal Timing
VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V
Values
Applicable
Symbol Pins
Min
Typ
Max
Unit
System clock
oscillation
frequency
fOSC
OSC1, OSC2
2.0
—
10.0
MHz
OSC clock (φOSC)
cycle time
tOSC
OSC1, OSC2
100
—
500
ns
(1000)
System clock (φ)
cycle time
tcyc
2
—
128
tOSC
—
—
128
µs
Item
Test Condition
Reference
Figure
Figure 16.2
*2
Subclock oscillation fW
frequency
X1, X2
—
32.768 —
or 38.4
kHz
Watch clock (φW)
cycle time
tW
X1, X2
—
30.5 or —
26.0
µs
Figure 16.2
Subclock (φSUB)
cycle time
tsubcyc
2
—
8
tW
*1
2
—
—
tcyc
tsubcyc
—
0.8
2.0
ms
Instruction cycle
time
Oscillation
stabilization time
trc
OSC1, OSC2
—
X1, X2
2.0
6.0
ms
Figure 16.10
(crystal oscillator)
Figure 16.10
Figure 16.9
(crystal oscillator)
Figure 16.9
*3
*4
—
20
45
µs
Figure 16.10
Figure 16.10
(ceramic oscillator) *3
—
20
45
µs
Figure 16.9
Figure 16.9
(ceramic oscillator) *4
—
—
50
ms
Except the above
—
—
2.0
s
Rev. 8.00 Mar. 09, 2010 Page 476 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
Values
Applicable
Symbol Pins
Min
Typ
Max
Unit
External clock high
width
tCPH
OSC1
40
—
—
ns
X1
—
15.26
or
13.02
—
µs
External clock low
width
tCPL
OSC1
40
—
—
ns
X1
—
15.26
or
13.02
—
µs
External clock rise
time
tCPr
OSC1
—
—
10
ns
X1
—
—
55.0
ns
External clock fall
time
tCPf
OSC1
—
—
10
ns
X1
—
—
55.0
ns
Pin RES low width
tREL
RES
10
Item
Input pin high width tIH
2
IRQ0, IRQ1,
IRQ3, IRQ4,
IRQAEC,
WKP0 to
WKP7,
TMIC, TMIF,
TMIG, ADTRG
Input pin low width
2
IRQ0, IRQ1,
IRQ3, IRQ4,
IRQAEC,
WKP0 to
WKP7,
TMIC, TMIF,
TMIG, ADTRG
AEVL, AEVH
0.5
UD
4
AEVL, AEVH
UD pin minimum
transition width
Notes: 1.
2.
3.
4.
tIL
tUDH
tUDL
0.5
Test Condition
Reference
Figure
Figure 16.2
Figure 16.2
Figure 16.2
Figure 16.2
—
—
tcyc
Figure 16.3
—
—
tcyc
tsubcyc
Figure 16.4
—
—
tosc
—
—
tcyc
tsubcyc
—
—
tosc
—
—
tcyc
tsubcyc
Figure 16.4
Figure 16.7
Selected with SA1 and SA0 of system control register 2 (SYSCR2).
The figure in parentheses applies when an external clock is used.
Applies to the HD64F38024R.
Applies to the HD64F38024.
Rev. 8.00 Mar. 09, 2010 Page 477 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
Table 16.10 Serial Interface (SCI3) Timing
VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V
Values
Item
Input clock
cycle
Asynchronous
Symbol
Min
Typ
Max
Unit
tscyc
4
—
—
6
—
—
tcyc or
t
Synchronous
Test Conditions
Reference
Figure
Figure 16.5
subcyc
Input clock pulse width
tSCKW
0.4
—
0.6
tscyc
Figure 16.5
Transmit data delay time
(synchronous)
tTXD
—
—
1
tcyc or
tsubcyc
Figure 16.6
Receive data setup time
(synchronous)
tRXS
400.0
—
—
ns
Figure 16.6
Receive data hold time
(synchronous)
tRXH
400.0
—
—
ns
Figure 16.6
Rev. 8.00 Mar. 09, 2010 Page 478 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
16.4.4
A/D Converter Characteristics
Table 16.11 shows the A/D converter characteristics of the H8/38024F.
Table 16.11 A/D Converter Characteristics
VCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V
Item
Applicable
Symbol Pins
Values
Min
Typ
Max
Unit
Analog power AVCC
supply voltage
AVCC
2.7
—
3.6
V
Analog input
voltage
AN0 to AN7
– 0.3
—
AVCC + 0.3
V
AVCC
—
—
1.0
mA
AVCC
—
600
—
µA
AVIN
Analog power AIOPE
supply current
AISTOP1
Test Condition
Reference
Figure
*1
AVCC = 3.0 V
*2
Reference
value
*3
AISTOP2
AVCC
—
—
5
µA
Analog input
capacitance
CAIN
AN0 to AN7
—
—
15.0
pF
Allowable
signal source
impedance
RAIN
—
—
10.0
kΩ
Resolution
(data length)
—
—
10
bit
Nonlinearity
error
—
—
±3.5
LSB
Quantization
error
—
—
±0.5
LSB
Absolute
accuracy
—
±2.0
±4.0
LSB
AVCC = 2.7 V to 3.6 V
Conversion
time
12.4
—
124
µs
AVCC = 2.7 V to 3.6 V
AVCC = 2.7 V to 3.6 V
Notes: 1. Set AVCC = VCC when the A/D converter is not used.
2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle.
3. AISTOP2 is the current at reset and in standby, watch, subactive, and subsleep modes
while the A/D converter is idle.
Rev. 8.00 Mar. 09, 2010 Page 479 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
16.4.5
LCD Characteristics
Table 16.12 shows the LCD characteristics.
Table 16.12 LCD Characteristics
VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V
Item
Applicable
Symbol Pins
Min
Values
Test
Typ Max Unit Conditions
Segment driver
drop voltage
VDS
SEG1 to
SEG32
—
—
0.6
V
Common driver
drop voltage
VDC
COM1 to
COM4
—
—
0.3
V
0.5
3.0
9.0
MΩ
1.5
3.0
7.0
2.2
—
3.6
LCD power supply RLCD
split-resistance
Liquid crystal
display voltage
VLCD
V1
V
Reference
Figure
*1
ID = 2 µA
V1 = 2.7 V to 3.6 V
*1
ID = 2 µA
V1 = 2.7 V to 3.6 V
*3
Between V1 and
VSS
*4
*2
Notes: 1. The voltage drop from power supply pins V1, V2, V3, and VSS to each segment pin or
common pin.
2. When the liquid crystal display voltage is supplied from an external power source,
ensure that the following relationship is maintained: VCC ≥ V1 ≥ V2 ≥ V3 ≥ VSS.
3. Applies to the HD64F38024.
4. Applies to the HD64F38024R.
Rev. 8.00 Mar. 09, 2010 Page 480 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
16.4.6
Flash Memory Characteristics
Table 16.13 lists the flash memory characteristics.
Table 16.13 Flash Memory Characteristics
AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, VCC = 2.7 V to 3.6 V (operating voltage range in
reading), VCC = 3.0 V to 3.6 V (operating voltage range in programming/erasing), Ta = –20 to
+75°C (operating temperature range in programming/erasing)
Values
Item
Symbol
Min
Programming time (per 128 bytes)*1 *2 *4
Erase time (per block) *1 *3 *6
tP
tE
Maximum number of reprogrammings
NWEC
Data retention time
*1
Programming Wait time after SWE bit setting
Wait time after PSU bit setting*1
Wait time after P bit setting*1 *4
Erase
Max
Unit
—
7
200
ms
—
100
1200
1000
*8 *11
10000 —
*9
100
*8 *12
10000 —
*9
tDRP
10*10
—
—
Years
x
1
—
—
µs
y
50
—
—
µs
z1
28
30
32
µs
z2
198
200
202
µs
7 ≤ n ≤ 1000
z3
8
10
12
µs
Additionalprogramming
ms
Times
Wait time after P bit clear*1
α
5
—
—
µs
Wait time after PSU bit clear*1
Wait time after PV bit setting*1
β
5
—
—
µs
γ
4
—
—
µs
Wait time after dummy write*1
Wait time after PV bit clear*1
ε
2
—
—
µs
η
2
—
—
µs
Wait time after SWE bit clear*1
θ
Maximum programming count*1 *4 *5 N
100
—
—
µs
—
—
1000
Times
Wait time after SWE bit setting*1
Wait time after ESU bit setting*1
x
1
—
—
µs
y
100
—
—
µs
Wait time after E bit setting*1 *6
Wait time after E bit clear*1
z
10
—
100
ms
α
10
—
—
µs
Wait time after ESU bit clear*1
Wait time after EV bit setting*1
β
10
—
—
µs
γ
20
—
—
µs
Wait time after dummy write*1
Wait time after EV bit clear*1
ε
2
—
—
µs
Wait time after SWE bit clear*1
Maximum erase count*1 *6 *7
Test
Condition
Typ
η
4
—
—
µs
θ
100
—
—
µs
N
—
—
120
Times
1≤n≤6
Rev. 8.00 Mar. 09, 2010 Page 481 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
Notes: 1.
2.
Make the time settings in accordance with the program/erase algorithms.
The programming time for 128 bytes. (Indicates the total time for which the P bit in
flash memory control register 1 (FLMCR1) is set. The program-verify time is not
included.)
3. The time required to erase one block. (Indicates the time for which the E bit in flash
memory control register 1 (FLMCR1) is set. The erase-verify time is not included.)
4. Programming time maximum value (tP(MAX)) = wait time after P bit setting (z) ×
maximum number of writes (N)
5. Set the maximum number of writes (N) according to the actual set values of z1, z2,
and z3, so that it does not exceed the programming time maximum value (tP(MAX)).
The wait time after P bit setting (z1, z2) should be changed as follows according to the
value of the number of writes (n).
Number of writes (n)
1≤n≤6
z1 = 30 µs
7 ≤ n ≤ 1000 z2 = 200 µs
6. Erase time maximum value (tE(max)) = wait time after E bit setting (z) × maximum
number of erases (N)
7. Set the maximum number of erases (N) according to the actual set value of (z), so that
it does not exceed the erase time maximum value (tE(max)).
8. The minimum number of times all characteristics are guaranteed following
reprogramming. (The guarantee covers the range from 1 to the minimum value.)
9. Reference value at 25°C. (Guideline showing number of reprogrammings over which
functioning will be retained under normal circumstances.)
10. Data retention characteristics within the range indicated in the specifications, including
the minimum value for reprogrammings.
11. Applies to an operating voltage range when reading data of 3.0 to 3.6 V.
12. Applies to an operating voltage range when reading data of 2.7 to 3.6 V.
16.4.7
Power Supply Characteristics
Table 16.14 Power Supply Characteristics
Unless otherwise indicated, VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V
Values
Item
Symbol
Applicable Test
Pins
Condition
Power supply startup voltage
VCCSTART
VCC
0
—
0.1
V
Power supply startup slope
SVCC
VCC
0.05
—
—
V/ms
Min
Typ
Max
Unit
Notes
*1*2
Notes: 1. This LSI may not start normally when it starts with the condition beyond specification
shown in above (Refer to figure 16.1 for power supply voltage startup time.).
2. Applies to the F-ZTAT version.
Rev. 8.00 Mar. 09, 2010 Page 482 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
16.5
H8/38024S Group Mask ROM Version Absolute Maximum Ratings
Table 16.15 lists the absolute maximum ratings.
Table 16.15
Absolute Maximum Ratings
Item
Symbol
Value
Unit
Note
Power supply voltage
VCC
–0.3 to +4.3
V
*1
Analog power supply voltage
AVCC
–0.3 to +4.3
V
Input voltage
Ports other than Port B
Vin
–0.3 to VCC +0.3
V
Port B
AVin
–0.3 to AVCC +0.3
V
Port 9 pin voltage
VP9
–0.3 to VCC +0.3
V
Operating temperature
Topr
–20 to +75
(regular
specifications)
°C
–40 to +85
(wide-range
specifications)
°C
+75 (products
2
shipped as chips)*
Storage temperature
Tstg
–55 to +125
°C
Notes: 1. Permanent damage may occur to the chip if maximum ratings are exceeded. Normal
operation should be under the conditions specified in Electrical Characteristics.
Exceeding these values can result in incorrect operation and reduced reliability.
2. Power may be applied when the temperature is between –20 and +75°C.
Rev. 8.00 Mar. 09, 2010 Page 483 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
16.6
H8/38024S Group Mask ROM Version Electrical Characteristics
16.6.1
Power Supply Voltage and Operating Range
The power supply voltage and operating range are indicated by the shaded region in the figures.
Power Supply Voltage and Oscillator Frequency Range
fW (kHz)
fosc (MHz)
38.4
10.0
32.768
4.0
2.0
1.8
2.7
3.6
VCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
Note: The fosc values are those when an oscillator
is used; when an external clock is used the
minimum value of fosc is 1 MHz.
Rev. 8.00 Mar. 09, 2010 Page 484 of 658
REJ09B0042-0800
1.8
• All operating
2.7
3.6
VCC (V)
Section 16 Electrical Characteristics
Power Supply Voltage and Operating Frequency Range
5.0
16.384
2.0
1.0
(0.5)
9.6
1.8
2.7
3.6
VCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode (except CPU)
Note: 1. The figure in parentheses is the minimum operating
frequency when an external clock is input. When
using an oscillator, the minimum operating frequency
(φ) is 1 MHz.
φSUB (kHz)
φ (MHz)
19.2
8.192
4.8
4.096
1.8
2.7
3.6
VCC (V)
• Subactive mode
φ (kHz)
• Subsleep mode (except CPU)
• Watch mode (except CPU)
625
250
15.625
(7.8125)
1.8
2.7
3.6
VCC (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode
(except A/D converter)
Note: 2. The figure in parentheses is the minimum operating
frequency when an external clock is input. When
using an oscillator, the minimum operating frequency
(φ) is 15.625 kHz.
Rev. 8.00 Mar. 09, 2010 Page 485 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
Analog power Supply Voltage and A/D Converter Operating Range
φ (kHz)
φ (MHz)
5.0
1.0
625
500
(0.5)
1.8
2.7
3.6
AVCC (V)
1.8
2.7
• Active (high-speed) mode
• Active (medium-speed) mode
• Sleep (high-speed) mode
• Sleep (medium-speed) mode
Rev. 8.00 Mar. 09, 2010 Page 486 of 658
REJ09B0042-0800
3.6
AVCC (V)
Section 16 Electrical Characteristics
16.6.2
DC Characteristics
Table 16.16 lists the DC characteristics of the H8/38024S.
Table 16.16
DC Characteristics
VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V
Values
Item
Symbol Applicable Pins Min
Typ
Max
Unit Test Condition
Input high
voltage
VIH
RES,
0.9 VCC
WKP0 to WKP7,
IRQ0, IRQ3, IRQ4,
AEVL, AEVH,
TMIC, TMIF,
TMIG, ADTRG,
SCK32
—
VCC + 0.3
V
IRQ1
0.9 VCC
—
AVCC + 0.3
V
RXD32, UD
0.8 VCC
—
VCC + 0.3
V
OSC1
0.9 VCC
—
VCC + 0.3
V
X1
0.9 VCC
—
VCC + 0.3
V
P13, P14,
P16, P17,
P30 to P37,
P40 to P43,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PA0 to PA3
0.8 VCC
—
VCC + 0.3
V
PB0 to PB7
0.8 VCC
—
AVCC + 0.3
V
IRQAEC
0.9 VCC
—
VCC + 0.3
V
Notes
Rev. 8.00 Mar. 09, 2010 Page 487 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
Values
Item
Symbol Applicable Pins Min
Input low
voltage
VIL
Output high VOH
voltage
Typ
Max
Unit Test Condition
RES,
WKP0 to WKP7,
IRQ0, IRQ1,
IRQ3, IRQ4,
IRQAEC, AEVL,
AEVH, TMIC,
TMIF, TMIG,
ADTRG, SCK32
–0.3
—
0.1 VCC
V
RXD32, UD
–0.3
—
0.2 VCC
V
OSC1
–0.3
—
0.1 VCC
V
X1
–0.3
—
0.1 VCC
V
P13, P14,
P16, P17,
P30 to P37,
P40 to P43,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PA0 to PA3,
PB0 to PB7
–0.3
—
0.2 VCC
V
P13, P14,
P16, P17,
P30 to P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PA0 to PA3
VCC – 1.0 —
—
V
VCC – 0.3 —
—
Rev. 8.00 Mar. 09, 2010 Page 488 of 658
REJ09B0042-0800
–IOH = 1.0 mA
VCC = 2.7 V to 3.6 V
–IOH = 0.1 mA
Notes
Section 16 Electrical Characteristics
Values
Item
Symbol Applicable Pins Min
Output low
voltage
VOL
Input/output | IIL |
leakage
current
Pull-up
MOS
current
–Ip
Input
CIN
capacitance
Typ
Max
Unit Test Condition
P13, P14,
P16, P17,
P30 to P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PA0 to PA3
—
—
0.5
V
IOL = 0.4 mA
P90 to P95
—
—
0.5
V
IOL = 10 mA
VCC = 2.2 V to 3.6 V
—
—
0.5
V
IOL = 8 mA
VCC = 1.8 V to 3.6 V
RES, P43,
OSC1, X1,
P13, P14,
P16, P17,
P30 to P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
IRQAEC,
P90 to P95,
PA0 to PA3
—
—
1.0
µA
VIN = 0.5 V to
VCC – 0.5 V
PB0 to PB7
—
—
1.0
µA
VIN = 0.5 V to
AVCC – 0.5 V
P13, P14,
P16, P17,
P30 to P37,
P50 to P57,
P60 to P67
30
—
180
µA
VCC = 3 V,
VIN = 0 V
All input pins
except power
supply and
IRQAEC
—
—
15.0
pF
f = 1 MHz,
VIN =0 V,
Ta = 25°C
IRQAEC
—
—
30.0
pF
Notes
Rev. 8.00 Mar. 09, 2010 Page 489 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
Values
Item
Symbol Applicable Pins Min
Typ
Max
Unit Test Condition
Active
mode
current
dissipation
IOPE1
—
0.2
—
mA
Active (high-speed) *1
*2
mode
VCC = 1.8 V,
Max.
fOSC = 1 MHz
guideline
= 1.1 ×
typ.
—
0.6
—
mA
Active (high-speed) *1
*2
mode
VCC = 3 V,
Max.
fOSC = 2 MHz
guideline
= 1.1 ×
typ.
—
1.2
—
mA
Active (high-speed)
mode
VCC = 3 V,
fOSC = 4 MHz
IOPE2
VCC
VCC
Notes
*1
*2
Max.
guideline
= 1.1 ×
typ.
—
3.1
6.0
mA
Active (high-speed) *1
*2
mode
VCC = 3 V,
fOSC = 10 MHz
—
0.03
—
mA
Active (mediumspeed) mode
VCC = 1.8 V,
fOSC = 1 MHz
φosc/128
—
Rev. 8.00 Mar. 09, 2010 Page 490 of 658
REJ09B0042-0800
0.1
—
mA
Active (mediumspeed) mode
VCC = 3 V,
fOSC = 2 MHz
φosc/128
*1
*2
Max.
guideline
= 1.1 ×
typ.
*1
*2
Max.
guideline
= 1.1 ×
typ.
Section 16 Electrical Characteristics
Values
Item
Symbol Applicable Pins Min
Typ
Max
Unit Test Condition
Notes
Active
mode
current
dissipation
IOPE2
0.2
—
mA
*1
*2
Sleep mode ISLEEP
current
dissipation
VCC
VCC
—
Active (mediumspeed) mode
VCC = 3 V,
fOSC = 4 MHz
φosc/128
Max.
guideline
= 1.1 ×
typ.
—
0.6
1.8
mA
Active (mediumspeed) mode
VCC = 3 V,
fOSC = 10 MHz
φosc/128
*1
*2
—
0.08
—
mA
VCC= 1.8 V,
fOSC= 1 MHz
*1
*2
Max.
guideline
= 1.1 ×
typ.
—
0.3
—
mA
VCC= 3 V,
fOSC= 2 MHz
*1
*2
Max.
guideline
= 1.1 ×
typ.
—
0.5
—
mA
VCC= 3 V,
fOSC= 4 MHz
*1
*2
Max.
guideline
= 1.1 ×
typ.
—
1.3
4.8
mA
VCC= 3 V,
fOSC= 10 MHz
*1
*2
Rev. 8.00 Mar. 09, 2010 Page 491 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
Values
Item
Symbol Applicable Pins Min
Typ
Max
Unit Test Condition
Notes
Subactive
mode
current
dissipation
ISUB
6.2
—
µA
*1
*2
Subsleep
mode
current
dissipation
Watch
mode
current
dissipation
ISUBSP
IWATCH
VCC
VCC
VCC
—
VCC = 1.8 V,
LCD on 32 kHz
External Clock
(φSUB=φw/2)
—
5.7
—
µA
VCC = 1.8 V,
LCD on 32 kHz
crystal resonator
(φSUB=φw/2)
—
4.4
—
µA
VCC = 2.7 V,
LCD on 32 kHz
crystal resonator
(φSUB=φw/8)
—
10
40
µA
VCC = 2.7 V,
LCD on 32 kHz
External Clock
(φSUB=φw/2)
—
11
40
µA
VCC = 2.7 V,
LCD on 32 kHz
crystal resonator
(φSUB=φw/2)
—
4.6
16.0
µA
VCC = 2.7 V,
LCD on 32 kHz
External Clock
(φSUB=φw/2)
—
5.1
16.0
µA
VCC = 2.7 V,
LCD on 32 kHz
crystal resonator
(φSUB=φw/2)
—
1.2
—
µA
VCC = 1.8 V,
Ta = 25°C
32 kHz crystal
resonator
LCD not used
—
Rev. 8.00 Mar. 09, 2010 Page 492 of 658
REJ09B0042-0800
2.0
—
µA
VCC = 2.7 V,
Ta = 25°C
32 kHz External
Clock
LCD not used
Reference
value
*1
*2
*1
*2
*1
*2
Reference
value
Section 16 Electrical Characteristics
Values
Item
Symbol Applicable Pins Min
Typ
Max
Unit Test Condition
Notes
Watch
mode
current
dissipation
IWATCH
2.3
—
µA
VCC = 2.7 V,
Ta = 25°C
32 kHz crystal
resonator
LCD not used
*1
*2
*1
*2
Standby
mode
current
dissipation
ISTBY
VCC
VCC
—
—
2.0
6.0
µA
VCC = 2.7 V,
32 kHz External
Clock
LCD not used
—
2.3
6.0
µA
VCC = 2.7 V,
32 kHz crystal
resonator
LCD not used
—
0.1
—
µA
VCC = 1.8 V,
Ta = 25°C
*1
*2
32 kHz crystal
resonator not used
Reference
value
VCC = 3.0 V,
Ta = 25°C
*1
*2
32 kHz crystal
resonator not used
Reference
value
32 kHz crystal
resonator not used
*1
*2
—
0.3
—
µA
—
1.0
5.0
µA
RAM data
retaining
voltage
VRAM
VCC
1.5
—
—
V
Allowable
output low
current
(per pin)
IOL
Output pins
except port 9
—
—
0.5
mA
P90 to P95
—
—
10.0
mA
Allowable
output low
current
(total)
∑ IOL
Output pins
except port 9
—
—
20.0
mA
Port 9
—
—
80.0
mA
All output pins
—
—
0.2
mA
–IOH
Allowable
output high
current
(per pin)
Reference
value
Rev. 8.00 Mar. 09, 2010 Page 493 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
Values
Item
Symbol Applicable Pins Min
Allowable
∑ – IOH
output high
current
(total)
All output pins
—
Typ
Max
Unit Test Condition
—
10.0
mA
Notes
Notes: Connect the TEST pin to VSS.
1. Pin states during current measurement.
Mode
Active (high-speed)
mode (IOPE1)
RES
Pin
Internal State
Other
Pins
LCD Power
Supply
VCC
Operates
VCC
Halted
Active (mediumspeed) mode (IOPE2)
Oscillator Pins
System clock oscillator:
crystal
Subclock oscillator:
Pin X1 = GND
Sleep mode
VCC
Only on-chip timers
operate
VCC
Halted
Subactive mode
VCC
Operates
VCC
Halted
System clock oscillator:
Subsleep mode
VCC
Only on-chip timers
operate, CPU stops
VCC
Halted
crystal
Subclock oscillator:
Watch mode
VCC
Only time base
operates, CPU stops
VCC
Halted
crystal
Standby mode
VCC
CPU and timers both
stop
VCC
Halted
System clock oscillator:
crystal
Subclock oscillator:
Pin X1 = GND
2. Excludes current in pull-up MOS transistors and output buffers.
Rev. 8.00 Mar. 09, 2010 Page 494 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
16.6.3
AC Characteristics
Table 16.17 lists the control signal timing, and tables 16.10 lists the serial interface timing of the
H8/38024S.
Table 16.17 Control Signal Timing
VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V
Values
Applicable
Symbol Pins
Min
Typ
Max
Unit
Test Condition
System clock
oscillation
frequency
fOSC
OSC1, OSC2
2.0
—
10.0
MHz
VCC = 2.7 V to 3.6 V
2.0
—
4.0
MHz
OSC clock (φOSC)
cycle time
tOSC
OSC1, OSC2
100
—
500
ns
(1000)
VCC = 2.7 V to 3.6 V Figure 16.2
*2
250
—
500
ns
(1000)
VCC = 1.8 V to 3.6 V
Item
System clock (φ)
cycle time
tcyc
2
—
128
tOSC
—
—
128
µs
Reference
Figure
VCC = 1.8 V to 3.6 V
Subclock oscillation fW
frequency
X1, X2
—
32.768 —
or 38.4
kHz
Watch clock (φW)
cycle time
tW
X1, X2
—
30.5 or —
26.0
µs
Figure 16.2
Subclock (φSUB)
cycle time
tsubcyc
2
—
8
tW
*1
2
—
—
tcyc
tsubcyc
Instruction cycle
time
Rev. 8.00 Mar. 09, 2010 Page 495 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
Item
Oscillation
stabilization time
Min
Typ
Max
Unit
Test Condition
trc
—
20
45
µs
Ceramic oscillator Figure 16.10
VCC = 2.2 V to 3.6 V
—
80
—
µs
Ceramic oscillator
Except the above
—
0.8
2
ms
Crystal oscillator
VCC = 2.7 V to 3.6 V
—
1.2
3
ms
Crystal oscillator
VCC = 2.2 V to 3.6 V
—
—
50
ms
Except the above
—
—
2
s
VCC = 2.2 V to 3.6 V
—
4
—
s
Except the above
OSC1
40
—
—
ns
VCC = 2.7 V to 3.6 V Figure 16.2
100
—
—
ns
VCC = 1.8 V to 3.6 V
X1
—
15.26
or
13.02
—
µs
OSC1
40
—
—
ns
VCC = 2.7 V to 3.6 V Figure 16.2
100
—
—
ns
VCC = 1.8 V to 3.6 V
X1
—
15.26
or
13.02
—
µs
OSC1
—
—
10
ns
VCC = 2.7 V to 3.6 V Figure 16.2
—
—
25
ns
VCC = 1.8 V to 3.6 V
X1
—
—
55.0
ns
OSC1
—
—
10
ns
VCC = 2.7 V to 3.6 V Figure 16.2
—
—
25
ns
VCC = 1.8 V to 3.6 V
X1
—
—
55.0
ns
RES
10
—
—
tcyc
OSC1, OSC2
X1, X2
External clock high
width
External clock low
width
External clock rise
time
Values
Applicable
Symbol Pins
tCPH
tCPL
tCPr
External clock fall
time
tCPf
Pin RES low width
tREL
Rev. 8.00 Mar. 09, 2010 Page 496 of 658
REJ09B0042-0800
Reference
Figure
Figure 16.3
Section 16 Electrical Characteristics
Item
Applicable
Symbol Pins
Input pin high width tIH
Input pin low width
UD pin minimum
transition width
tIL
tUDH
tUDL
Values
Min
Typ
Max
Unit
2
IRQ0, IRQ1,
IRQ3, IRQ4,
IRQAEC,
WKP0 to
WKP7,
TMIC, TMIF,
TMIG, ADTRG
—
—
tcyc
tsubcyc
AEVL, AEVH
—
—
tosc
2
IRQ0, IRQ1,
IRQ3, IRQ4,
IRQAEC,
WKP0 to
WKP7,
TMIC, TMIF,
TMIG, ADTRG
—
—
tcyc
tsubcyc
AEVL, AEVH
0.5
—
—
tosc
UD
4
—
—
tcyc
tsubcyc
0.5
Test Condition
Reference
Figure
Figure 16.4
Figure 16.4
Figure 16.7
Notes: 1. Selected with SA1 and SA0 of system control register 2 (SYSCR2).
2. The figure in parentheses applies when an external clock is used.
Rev. 8.00 Mar. 09, 2010 Page 497 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
Table 16.18 Serial Interface (SCI3) Timing
VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V
Values
Item
Input clock
cycle
Asynchronous
Symbol
Min
Typ
Max
Unit
tscyc
4
—
—
6
—
—
tcyc or
t
Synchronous
Test Conditions
Reference
Figure
Figure 16.5
subcyc
Input clock pulse width
tSCKW
0.4
—
0.6
tscyc
Figure 16.5
Transmit data delay time
(synchronous)
tTXD
—
—
1
tcyc or
tsubcyc
Figure 16.6
Receive data setup time
(synchronous)
tRXS
400.0
—
—
ns
Figure 16.6
Receive data hold time
(synchronous)
tRXH
400.0
—
—
ns
Figure 16.6
Rev. 8.00 Mar. 09, 2010 Page 498 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
16.6.4
A/D Converter Characteristics
Table 16.19 shows the A/D converter characteristics of the H8/38024S.
Table 16.19 A/D Converter Characteristics
VCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V
Item
Applicable
Symbol Pins
Values
Min
Typ
Max
Unit
Analog power AVCC
supply voltage
AVCC
1.8
—
3.6
V
Analog input
voltage
AN0 to AN7
– 0.3
—
AVCC + 0.3
V
AVCC
—
—
1.0
mA
AVCC
—
600
—
µA
AVIN
Analog power AIOPE
supply current
AISTOP1
Test Condition
Reference
Figure
*1
AVCC = 3.0 V
*2
Reference
value
*3
AISTOP2
AVCC
—
—
5
µA
Analog input
capacitance
CAIN
AN0 to AN7
—
—
15.0
pF
Allowable
signal source
impedance
RAIN
—
—
10.0
kΩ
Resolution
(data length)
—
—
10
bit
Nonlinearity
error
—
—
±3.5
LSB
AVCC = 2.7 V to 3.6 V
VCC = 2.7 V to 3.6 V
—
—
±5.5
LSB
AVCC = 2.0 V to 3.6 V
VCC = 2.0 V to 3.6 V
—
—
±7.5
LSB
Other than above
Quantization
error
—
—
±0.5
LSB
Absolute
accuracy
—
—
±4.0
LSB
AVCC = 2.7 V to 3.6 V
VCC = 2.7 V to 3.6 V
—
—
±6.0
LSB
AVCC = 2.0 V to 3.6 V
VCC = 2.0 V to 3.6 V
—
—
±8.0
LSB
Other than above
12.4
—
124
µs
AVCC = 2.7 V to 3.6 V
VCC = 2.7 V to 3.6 V
62
—
124
µs
Other than above
Conversion
time
*4
*4
Notes: 1. Set AVCC = VCC when the A/D converter is not used.
2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle.
Rev. 8.00 Mar. 09, 2010 Page 499 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
3. AISTOP2 is the current at reset and in standby, watch, subactive, and subsleep modes
while the A/D converter is idle.
4. Conversion time: 62 μs.
16.6.5
LCD Characteristics
Table 16.20 shows the LCD characteristics.
Table 16.20 LCD Characteristics
VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V
Item
Applicable
Symbol Pins
Min
Values
Test
Typ Max Unit Conditions
Reference
Figure
Segment driver
drop voltage
VDS
SEG1 to
SEG32
—
—
0.6
V
*1
ID = 2 µA
V1 = 2.7 V to 3.6 V
Common driver
drop voltage
VDC
COM1 to
COM4
—
—
0.3
V
*1
ID = 2 µA
V1 = 2.7 V to 3.6 V
1.5
3.0
7.0
MΩ
Between V1 and
VSS
2.2
—
3.6
V
LCD power supply RLCD
split-resistance
Liquid crystal
display voltage
VLCD
V1
*2
Notes: 1. The voltage drop from power supply pins V1, V2, V3, and VSS to each segment pin or
common pin.
2. When the liquid crystal display voltage is supplied from an external power source,
ensure that the following relationship is maintained: VCC ≥ V1 ≥ V2 ≥ V3 ≥ VSS.
Rev. 8.00 Mar. 09, 2010 Page 500 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
16.7
Absolute Maximum Ratings of H8/38124 Group F-ZTAT Version
and Mask ROM Version
Table 16.21 lists the absolute maximum ratings.
Table 16.21 Absolute Maximum Ratings
Item
Symbol
Value
Unit
Note
Power supply voltage
VCC
–0.3 to +7.0
V
*1
CVCC
–0.3 to +4.3
V
Analog power supply voltage
AVCC
–0.3 to +7.0
V
Input voltage
Other than port B
Vin
–0.3 to VCC +0.3
V
Port B
AVin
–0.3 to AVCC +0.3
V
Port 9 pin voltage
VP9
Operating temperature
Topr
–0.3 to VCC +0.3
V
2
*
–20 to +75
°C
(regular specifications)
2
–40 to +85*
(wide-range temperature
specifications)
Storage temperature
Tstg
–55 to +125
°C
Notes: 1. Permanent damage may result if maximum ratings are exceeded. Normal operation
should be under the conditions specified in Electrical Characteristics. Exceeding these
values can result in incorrect operation and reduced reliability.
2. The operating temperature ranges from –20°C to +75°C when programming or erasing
the flash memory.
Rev. 8.00 Mar. 09, 2010 Page 501 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
16.8
Electrical Characteristics of H8/38124 Group F-ZTAT Version and
Mask ROM Version
16.8.1
Power Supply Voltage and Operating Ranges
Power Supply Voltage and Oscillation Frequency Range (System Clock Oscillator Selected)
fosc (MHz)
fW (kHz)
20.0
32.768
2.0
2.7
5.5
VCC (V)
2.7
• Active (high-speed) mode
• Sleep (high-speed) mode
5.5
VCC (V)
• All operating modes
fW (kHz)
fosc (MHz)
Power Supply Voltage and Oscillation Frequency Range (On-Chip Oscillator Selected)
32.768
2.0
0.7
2.7
5.5
VCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
Rev. 8.00 Mar. 09, 2010 Page 502 of 658
REJ09B0042-0800
2.7
• All operating modes
5.5
VCC (V)
Section 16 Electrical Characteristics
Power Supply Voltage and Operating Frequency Range (System Clock Oscillator Selected)
10.0
φ (MHz)
16.384
2.7
5.5
VCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode (except CPU)
φSUB (kHz)
1.0
8.192
4.096
2.7
5.5
VCC (V)
• Subactive mode
• Subsleep mode (except CPU)
• Watch mode (except CPU)
φ (kHz)
1250
15.625
2.7
5.5
VCC (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode (except A/D converter)
Rev. 8.00 Mar. 09, 2010 Page 503 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
Power Supply Voltage and Operating Frequency Range (On-Chip Oscillator Selected)
φSUB (kHz)
φ (MHz)
16.384
1.0
0.35
2.7
5.5
VCC (V)
φ (kHz)
• Active (high-speed) mode
• Sleep (high-speed) mode (except CPU)
125
6.25
2.7
5.5
VCC (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode (except A/D converter)
Rev. 8.00 Mar. 09, 2010 Page 504 of 658
REJ09B0042-0800
8.192
4.096
2.7
• Subactive mode
• Subsleep mode (except CPU)
• Watch mode (except CPU)
5.5
VCC (V)
Section 16 Electrical Characteristics
Analog Power Supply Voltage and A/D Converter Operating Range (System Clock
Oscillator Selected)
φ (kHz)
φ (MHz)
10.0
1000
500
1.0
2.7
2.7
5.5
AVCC (V)
5.5
AVCC (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode
• Active (high-speed) mode
• Sleep (high-speed) mode
Analog Power Supply Voltage and A/D Converter Operating Range (On-Chip Oscillator
Selected)
φ (kHz)
φ (MHz)
1.0
125
6.25
0.35
2.7
5.5
AVCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
2.7
5.5
AVCC (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode
Rev. 8.00 Mar. 09, 2010 Page 505 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
16.8.2
DC Characteristics
Table 16.22 lists the DC characteristics.
Table 16.22
DC Characteristics
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Values
Item
Symbol
Input high VIH
voltage
Applicable Pins
Max
Unit
Test Condition
RES,
VCC × 0.8 —
WKP0 to WKP7,
IRQ0, IRQ3, IRQ4,
AEVL, AEVH,
VCC × 0.9 —
TMIC, TMIF,
TMIG, ADTRG,
SCK32
VCC + 0.3
V
VCC = 4.0 V to 5.5 V
VCC + 0.3
Other than above
IRQ1
VCC × 0.8 —
AVCC + 0.3 V
VCC = 4.0 V to 5.5 V
VCC × 0.9 —
AVCC + 0.3
Other than above
VCC × 0.7 —
VCC + 0.3
VCC × 0.8 —
VCC + 0.3
VCC × 0.8 —
VCC + 0.3
VCC × 0.9 —
VCC + 0.3
RXD32, UD
OSC1
Min
Typ
V
VCC = 4.0 V to 5.5 V
Other than above
V
VCC = 4.0 V to 5.5 V
Other than above
P13, P14, P17,
P30 to P37,
P40 to P43,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PA0 to PA3
VCC × 0.7 —
VCC + 0.3
VCC × 0.8 —
VCC + 0.3
PB0 to PB7
VCC × 0.7 —
AVCC + 0.3 V
VCC = 4.0 V to 5.5 V
VCC × 0.8 —
AVCC + 0.3
Other than above
VCC × 0.8 —
VCC + 0.3
VCC × 0.9 —
VCC + 0.3
IRQAEC, P95*5
Note: Connect the TEST pin to VSS.
Rev. 8.00 Mar. 09, 2010 Page 506 of 658
REJ09B0042-0800
V
VCC = 4.0 V to 5.5 V
Other than above
V
VCC = 4.0 V to 5.5 V
Other than above
Notes
Section 16 Electrical Characteristics
Values
Item
Symbol
Applicable Pins
Min
Typ
Max
Unit
Test Condition
Input low
voltage
VIL
RES,
WKP0 to WKP7,
IRQ0, IRQ1,
IRQ3, IRQ4,
IRQAEC, P95*5,
AEVL, AEVH,
TMIC, TMIF,
TMIG, ADTRG,
SCK32
– 0.3
—
VCC × 0.2
V
VCC = 4.0 V to 5.5 V
– 0.3
—
VCC × 0.1
– 0.3
—
VCC × 0.3
– 0.3
—
VCC × 0.2
OSC1
– 0.3
—
VCC × 0.2
– 0.3
—
VCC × 0.1
P13, P14, P17,
P30 to P37,
P40 to P43,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PA0 to PA3,
PB0 to PB7
– 0.3
—
VCC × 0.3
– 0.3
—
VCC × 0.2
RXD32, UD
Output
high
voltage
VOH
P13, P14, P17,
P30 to P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PA0 to PA3
VCC – 1.0 —
—
Notes
Other than above
V
VCC = 4.0 V to 5.5 V
Other than above
V
VCC = 4.0 V to 5.5 V
Other than above
V
VCC = 4.0 V to 5.5 V
Other than above
V
VCC = 4.0 V to 5.5 V
–IOH = 1.0 mA
VCC – 0.5 —
—
VCC = 4.0 V to 5.5 V
VCC – 0.3 —
—
–IOH = 0.1 mA
–IOH = 0.5 mA
Rev. 8.00 Mar. 09, 2010 Page 507 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
Values
Item
Symbol
Output low VOL
voltage
Applicable Pins
Min
Typ
Max
Unit
Test Condition
P13, P14, P17,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PA0 to PA3
—
—
0.6
V
VCC = 4.0 V to 5.5 V
P30 to P37
Notes
IOL = 1.6 mA
—
—
0.5
—
—
1.0
IOL = 0.4 mA
VCC = 4.0 V to 5.5 V
IOL = 10 mA
—
—
0.6
VCC = 4.0 V to 5.5 V
IOL = 1.6 mA
P90 to P95
—
—
0.5
—
—
1.5
IOL = 0.4 mA
VCC = 4.0 V to 5.5 V
IOL = 15 mA
—
—
1.0
VCC = 4.0 V to 5.5 V
IOL = 10 mA
—
—
0.8
VCC = 4.0 V to 5.5 V
IOL = 8 mA
Input/
output
leakage
current
Pull-up
MOS
current
| IIL |
–Ip
—
—
1.0
IOL = 5 mA
—
—
0.6
IOL = 1.6 mA
—
—
0.5
RES, P43,
P13, P14, P17,
OSC1, X1,
P30 to P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
IRQAEC,
PA0 to PA3,
P90 to P95
—
—
1.0
PB0 to PB7
—
—
1.0
P13, P14, P17,
P30 to P37,
P50 to P57,
P60 to P67
20
—
200
—
40
—
Rev. 8.00 Mar. 09, 2010 Page 508 of 658
REJ09B0042-0800
IOL = 0.4 mA
µA
VIN = 0.5 V to VCC –
0.5 V
VIN = 0.5 V to AVCC
– 0.5 V
µA
VCC = 5.0 V,
VIN = 0.0 V
VCC = 2.7 V,
VIN = 0.0 V
Reference
value
Section 16 Electrical Characteristics
Values
Item
Symbol
Applicable Pins
Min
Typ
Max
Unit
Test Condition
Input
capacitance
Cin
All input pins
except power
supply pin
—
—
15.0
pF
f = 1 MHz,
VIN = 0.0 V,
Ta = 25°C
VCC
—
0.6
—
mA
Active (high-speed)
mode
VCC = 2.7 V,
fOSC = 2 MHz
IOPE1
Active
mode
current
consumption
—
1.0
Notes
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
*2 *3 *4
—
Approx.
max. value
= 1.1 ×
Typ.
—
0.8
—
Active (high-speed)
mode
VCC = 5 V,
fOSC = 2 MHz
—
1.5
—
—
1.6
—
—
2.0
—
—
3.3
7.0
—
4.0
7.0
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
*2 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
Active (high-speed)
mode
VCC = 5 V,
fOSC = 4 MHz
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
*2 *3 *4
Active (high-speed)
mode
VCC = 5 V,
fOSC = 10 MHz
*1 *3 *4
*2 *3 *4
Rev. 8.00 Mar. 09, 2010 Page 509 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
Values
Item
Symbol
Active
IOPE2
mode
current
consumption
Applicable Pins
Min
Typ
Max
Unit
Test Condition
Notes
VCC
—
0.2
—
mA
Active (mediumspeed) mode
VCC = 2.7 V,
fOSC = 2 MHz,
φOSC/128
*1 *3 *4
—
0.5
Approx.
max. value
= 1.1 ×
Typ.
*2 *3 *4
—
Approx.
max. value
= 1.1 ×
Typ.
—
—
0.4
0.8
—
Active (mediumspeed) mode
VCC = 5 V,
fOSC = 2 MHz,
φOSC/128
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
*2 *3 *4
—
Approx.
max. value
= 1.1 ×
Typ.
—
0.6
—
—
0.9
—
—
0.9
3.0
—
1.2
3.0
Rev. 8.00 Mar. 09, 2010 Page 510 of 658
REJ09B0042-0800
Active (mediumspeed) mode
VCC = 5 V,
fOSC = 4 MHz,
φOSC/128
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
*2 *3 *4
Active (mediumspeed) mode
VCC = 5 V,
fOSC = 10 MHz,
φOSC/128
*1 *3 *4
*2 *3 *4
Section 16 Electrical Characteristics
Values
Item
Symbol
ISLEEP
Sleep
mode
current
consumption
Applicable Pins
Min
Typ
Max
Unit
Test Condition
Notes
VCC
—
0.3
—
mA
VCC = 2.7 V,
fOSC = 2 MHz
*1 *3 *4
—
0.8
Approx.
max. value
= 1.1 ×
Typ.
*2 *3 *4
—
Approx.
max. value
= 1.1 ×
Typ.
—
—
0.5
0.9
—
VCC = 5 V,
fOSC = 2 MHz
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
*2 *3 *4
—
Approx.
max. value
= 1.1 ×
Typ.
—
Subactive ISUB
mode
current
consumption
VCC
0.9
—
VCC = 5 V,
fOSC = 4 MHz
*2 *3 *4
—
1.3
—
—
1.5
5.0
—
2.2
5.0
—
11.3
—
—
12.7
—
—
16.3
50
—
30
50
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
µA
VCC = 5 V,
fOSC = 10 MHz
*1 *3 *4
VCC = 2.7 V,
LCD on,
32-kHz crystal
resonator used
(φSUB = φW/8)
*1 *3 *4
VCC = 2.7 V,
LCD on,
32-kHz crystal
resonator used
(φSUB = φW/2)
*2 *3 *4
Reference
value
*2 *3 *4
Reference
value
*1 *3 *4
*2 *3 *4
Rev. 8.00 Mar. 09, 2010 Page 511 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
Values
Item
Applicable Pins
Min
Typ
Max
Unit
Test Condition
Notes
Subsleep ISUBSP
mode
current
consumption
Symbol
VCC
—
4.0
16
µA
VCC = 2.7 V,
LCD on,
32-kHz crystal
resonator used
(φSUB = φW/2)
*3 *4
Watch
IWATCH
mode
current
consumption
VCC
—
1.4
—
µA
VCC = 2.7 V,
Ta = 25°C,
32-kHz crystal
resonator used,
LCD not used
*1 *3 *4
VCC = 2.7 V,
32-kHz crystal
resonator used,
LCD not used
*3 *4
VCC = 2.7 V,
Ta = 25°C,
32-kHz crystal
resonator not used
*1 *3 *4
Standby
ISTBY
mode
current
consumption
—
VCC
1.8
6.0
—
0.3
—
—
—
—
VCC
—
—
—
RAM data VRAM
retaining
voltage
1.8
0.5
0.05
0.6
0.16
—
VCC = 2.7 V,
Ta = 25°C,
32-kHz crystal
resonator not used
—
VCC = 2.7 V,
Ta = 25°C,
SUBSTP (subclock
oscillator control
register) setting = 1
—
VCC = 5.0 V,
Ta = 25°C,
32-kHz crystal
resonator not used
—
—
1.0
5.0
2.0
—
—
Rev. 8.00 Mar. 09, 2010 Page 512 of 658
REJ09B0042-0800
µA
VCC = 5.0 V,
Ta = 25°C,
SUBSTP (subclock
oscillator control
register) setting = 1
32-kHz crystal
resonator not used
V
Reference
value
*2 *3 *4
Reference
value
Reference
value
*2 *3 *4
Reference
value
*2 *4
Reference
value
*2 *3 *4
Reference
value
*2 *4
Reference
value
*3 *4
*6
Section 16 Electrical Characteristics
Item
Symbol
Allowable output low
current (per pin)
IOL
Allowable output low
current (total)
∑IOL
Allowable output high –IOH
current (per pin)
Allowable output high ∑–IOH
current (total)
Applicable
Pins
Values
Min
Test
Condition
Typ
Max
Unit
Output pins
—
except ports 3
and 9
—
2.0
mA
Port 3
—
—
10.0
Output pins
except port 9
—
—
0.5
Port 9
—
—
15.0
VCC = 4.0 V to
5.5 V
—
—
5.0
Other than
above
Output pins
—
except ports 3
and 9
—
40.0
Port 3
—
—
80.0
Output pins
except port 9
—
—
20.0
Port 9
—
—
80.0
All output pins —
—
2.0
—
—
0.2
All output pins —
—
15.0
—
—
10.0
Notes
VCC = 4.0 V to
5.5 V
VCC = 4.0 V to
5.5 V
mA
VCC = 4.0 V to
5.5 V
VCC = 4.0 V to
5.5 V
mA
VCC = 4.0 V to
5.5 V
Other than
above
mA
VCC = 4.0 V to
5.5 V
Other than
above
Notes: Connect the TEST pin to VSS.
1. Applies to the mask-ROM version.
2. Applies to the F-ZTAT version.
Rev. 8.00 Mar. 09, 2010 Page 513 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
3. Pin states when current consumption is measured
Mode
RES Pin
Internal State
Other Pins
LCD Power
Supply
Active (high-speed)
mode (IOPE1)
VCC
Only CPU operates
VCC
Stops
System clock:
crystal resonator
Subclock:
Pin X1 = GND
Active (mediumspeed) mode (IOPE2)
Sleep mode
VCC
Only all on-chip timers
operate
VCC
Stops
Subactive mode
VCC
Only CPU operates
VCC
Stops
Subsleep mode
VCC
Only all on-chip timers
operate
VCC
Stops
VCC
Only clock time base
operates
System clock:
crystal resonator
Subclock:
crystal resonator
CPU stops
Watch mode
Oscillator Pins
VCC
Stops
VCC
Stops
CPU stops
Standby mode
VCC
CPU and timers
both stop
System clock:
crystal resonator
Subclock:
Pin X1 = GND
4. Except current which flows to the pull-up MOS or output buffer
5. Used when user mode or boot mode is determined after canceling a reset in the FZTAT version
6. Voltage maintained in standby mode
Rev. 8.00 Mar. 09, 2010 Page 514 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
16.8.3
AC Characteristics
Table 16.23 lists the control signal timing and table 16.24 lists the serial interface timing.
Table 16.23 Control Signal Timing
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Item
Symbol
Applicable
Pins
System clock
oscillation
frequency
fOSC
OSC clock (φOSC)
cycle time
tOSC
System clock (φ)
cycle time
Values
Typ
Max
Unit
OSC1, OSC2 2.0
—
20.0
MHz
0.7
—
2.0
OSC1, OSC2 50.0
—
500
500
—
1429
2
—
128
tcyc
Min
Test Condition
On-chip oscillator
selected
ns
Reference
Figure
*2
Figure 16.2
On-chip oscillator
selected
tOSC
—
—
182
µs
Subclock oscillation fW
frequency
X1, X2
—
32.768
—
kHz
Watch clock (φW)
cycle time
tW
X1, X2
—
30.5
—
µs
Figure 16.2
Subclock (φSUB)
cycle time
tsubcyc
2
—
8
tW
*1
2
—
—
tcyc
tsubcyc
OSC1,
OSC2
—
—
20
ms
Instruction cycle
time
Oscillation
stabilization time
trc
X1, X2
—
—
2.0
s
External clock high tCPH
width
trc
OSC1
20
—
—
ns
Figure 16.2
External clock low
width
tCPL
OSC1
20
—
—
ns
Figure 16.2
External clock rise
time
tCPr
OSC1
—
—
5
ns
Figure 16.2
External clock fall
time
tCPf
OSC1
—
—
5
ns
Figure 16.2
RES pin low
width
tREL
RES
10
—
—
tcyc
Figure 16.3
Rev. 8.00 Mar. 09, 2010 Page 515 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
Item
Symbol
Input pin high
width
tIH
Input pin low
width
tIL
UD pin minimum
transition width
tUDH
Applicable
Pins
Values
Min
Typ
Max
Unit
IRQ0, IRQ1, 2
IRQ3, IRQ4,
IRQAEC,
WKP0 to
WKP7, TMIC,
TMIF, TMIG,
ADTRG
—
—
tcyc
tsubcyc
AEVL, AEVH 0.5
—
—
tOSC
IRQ0, IRQ1, 2
IRQ3, IRQ4,
IRQAEC,
WKP0 to
WKP7, TMIC,
TMIF, TMIG,
ADTRG
—
—
tcyc
tsubcyc
AEVL, AEVH 0.5
—
—
tOSC
UD
—
—
tcyc
tsubcyc
4
tUDL
Test Condition
Reference
Figure
Figure 16.4
Figure 16.4
Figure 16.7
Notes: 1. Determined by the SA1 and SA0 bits in the system control register 2 (SYSCR2).
2. These characteristics are given as ranges between minimum and maximum values in
order to account for factors such as temperature, power supply voltage, and variation
among production lots. When designing systems, make sure to give due consideration
to the SPEC range. Please contact a Renesas sales or support representative for
actual performance data on the product.
Table 16.24
Serial Interface (SCI3) Timing
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Values
Test
Condition
Reference
Figure
Item
Symbol
Min
Typ Max Unit
Input clock Asynchronous
cycle
Clocked synchronous
tscyc
4
—
—
6
—
—
tcyc or
tsubcyc
Input clock pulse width
tSCKW
0.4
—
0.6
tscyc
Figure 16.5
Transmit data delay time
(clocked synchronous)
tTXD
—
—
1
tcyc or
tsubcyc
Figure 16.6
Receive data setup time
(clocked synchronous)
tRXS
150.0
—
—
ns
Figure 16.6
Receive data hold time
(clocked synchronous)
tRXH
150.0
—
—
ns
Figure 16.6
Rev. 8.00 Mar. 09, 2010 Page 516 of 658
REJ09B0042-0800
Figure 16.5
Section 16 Electrical Characteristics
16.8.4
A/D Converter Characteristics
Table 16.25 shows the A/D converter characteristics.
Table 16.25
A/D Converter Characteristics
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Values
Applicable
Min
Pins
Typ
Max
Unit
Analog power supply AVCC
voltage
AVCC
2.7
—
5.5
V
Analog input voltage
AN0 to
AN7
– 0.3
—
AVCC + 0.3 V
AVCC
—
—
1.5
mA
AVCC
—
600
—
µA
Item
Symbol
AVIN
Analog power supply AIOPE
current
AISTOP1
Test
Condition
Reference
Figure
*1
AVCC = 5.0 V
*2
Reference
value
AISTOP2
AVCC
—
—
5.0
µA
Analog input
capacitance
CAIN
AN0 to
AN7
—
—
15.0
pF
Allowable signal
source impedance
RAIN
—
—
10.0
kΩ
Resolution (data
length)
—
—
10
bit
Nonlinearity error
—
—
±3.5
LSB
—
—
±7.5
Quantization error
—
—
±0.5
LSB
Absolute accuracy
—
±2.0
±4.0
LSB
—
±2.0
±8.0
6.2
—
124
Conversion time
*3
AVCC = 4.0 V
to 5.5 V
AVCC = 2.7 V
to 5.5 V
AVCC = 4.0 V
to 5.5 V
AVCC = 2.7 V
to 5.5 V
µs
Notes: 1. Set AVCC = VCC when the A/D converter is not used.
2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle.
3. AISTOP2 is the current at reset and in standby, watch, subactive, and subsleep modes
while the A/D converter is idle.
Rev. 8.00 Mar. 09, 2010 Page 517 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
16.8.5
LCD Characteristics
Table 16.26 shows the LCD characteristics.
Table 16.26 LCD Characteristics
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Item
Symbol
Segment driver
step-down voltage
Common driver
step-down voltage
VDS
VDC
LCD power supply
split-resistance
RLCD
Liquid crystal
display voltage
VLCD
Applicable
Pins
Values
Reference
Figure
Min
Typ
Max
Unit
Test Condition
SEG1 to
SEG32
—
—
0.6
V
COM1 to
COM4
—
—
0.3
V
*1
ID = 2 µA
V1 = 2.7 V to 5.5 V
*1
ID = 2 µA
V1 = 2.7 V to 5.5 V
1.5
3.0
7.0
MΩ
2.7
—
5.5
V
V1
Between V1 and
VSS
*2
Notes: 1. The voltage step-down from power supply pins V1, V2, V3, and VSS to each segment
pin or common pin.
2. When the liquid crystal display voltage is supplied from an external power supply,
ensure that the following relationship is maintained: VCC ≥ V1 ≥ V2 ≥ V3 ≥ VSS.
Rev. 8.00 Mar. 09, 2010 Page 518 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
16.8.6
Flash Memory Characteristics
Table 16.27
Flash Memory Characteristics
Condition:
AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, VCC = 2.7 V to 5.5 V (range of
operating voltage when reading), VCC = 3.0 V to 5.5 V (range of operating voltage
when programming/erasing), Ta = –20°C to +75°C (range of operating temperature
when programming/erasing: product with regular specifications, product with widerange temperature specifications)
Values
Item
Symbol
Min
Typ
Max
Unit
Programming time*1*2*4
tP
—
7
200
ms/128 bytes
1200
ms/block
Test
Conditions
Erase time*1*3*5
tE
—
100
Reprogramming count
NWEC
1000*8
10000*9 —
times
Data retain period
tDRP
10*10
—
—
year
Programming
Wait time after
SWE-bit setting*1
x
1
—
—
µs
Wait time after
PSU-bit setting*1
y
50
—
—
µs
Wait time after
P-bit setting*1*4
z1
28
30
32
µs
1≤n≤6
z2
198
200
202
µs
7 ≤ n ≤ 1000
z3
8
10
12
µs
Additional
programming
Wait time after
P-bit clear*1
α
5
—
—
µs
Wait time after
PSU-bit clear*1
β
5
—
—
µs
Wait time after
PV-bit setting*1
γ
4
—
—
µs
Wait time after
dummy write*1
ε
2
—
—
µs
Wait time after
PV-bit clear*1
η
2
—
—
µs
Wait time after
SWE-bit clear*1
θ
100
—
—
µs
Maximum
programming
count*1*4*5
N
—
—
1000
times
Rev. 8.00 Mar. 09, 2010 Page 519 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
Values
Symbol
Min
Typ
Max
Unit
Wait time after
SWE-bit setting*1
x
1
—
—
µs
Wait time after
ESU-bit setting*1
y
100
—
—
µs
Wait time after
E-bit setting*1*6
z
10
—
100
ms
Wait time after
E-bit clear*1
α
10
—
—
µs
Wait time after
ESU-bit clear*1
β
10
—
—
µs
Wait time after
EV-bit setting*1
γ
20
—
—
µs
Wait time after
dummy write*1
ε
2
—
—
µs
Wait time after
EV-bit clear*1
η
4
—
—
µs
Wait time after
SWE-bit clear*1
θ
100
—
—
µs
Maximum erase
count*1*6*7
N
—
—
120
times
Item
Erase
Test
Conditions
Notes: 1. Set the times according to the program/erase algorithms.
2. Programming time per 128 bytes (Shows the total period for which the P bit in FLMCR1
is set. It does not include the programming verification time.)
3. Block erase time (Shows the total period for which the E bit in FLMCR1 is set. It does
not include the erase verification time.)
4. Maximum programming time (tP (max))
tP (max) = Wait time after P-bit setting (z) × maximum number of writes (N)
5. The maximum number of writes (N) should be set according to the actual set value of
z1, z2, and z3 to allow programming within the maximum programming time (tP (max)).
The wait time after P-bit setting (z1 and z2) should be alternated according to the
number of writes (n) as follows:
1≤n≤6
z1 = 30 µs
7 ≤ n ≤ 1000 z2 = 200 µs
6. Maximum erase time (tE (max))
tE (max) = Wait time after E-bit setting (z) × maximum erase count (N)
7. The maximum number of erases (N) should be set according to the actual set value of z
to allow erasing within the maximum erase time (tE (max)).
8. This minimum value guarantees all characteristics after reprogramming (the guaranteed
range is from 1 to the minimum value).
9. Reference value when the temperature is 25°C (normally reprogramming will be
performed by this count).
10. This is a data retain characteristic when reprogramming is performed within the
specification range including this minimum value.
Rev. 8.00 Mar. 09, 2010 Page 520 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
16.8.7
Power Supply Voltage Detection Circuit Characteristics
Table 16.28
Power Supply Voltage Detection Circuit Characteristics (1)
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Rated Values
Item
Symbol
Min
Typ
Max
Unit
LVDR operation drop
voltage*
VLVDRmin
1.0
—
—
V
LVD stabilization time
TLVDON
150
—
—
µs
Standby mode current
consumption
ISTBY
—
—
100
µA
Test Conditions
LVDE = 1
VCC = 5.0 V
32 oscillator not
used
Note: * In some cases no reset may occur if the power supply voltage, VCC, drops below
VLVDRmin = 1.0 V and then rises, so thorough evaluation is called for.
Table 16. 29 Power Supply Voltage Detection Circuit Characteristics (2)
Using on-chip reference voltage and ladder resistor (VREFSEL = VINTDSEL = VINTUSEL = 0)
Rated Values
Item
Symbol
Min
Typ
Max
Unit
Test Conditions
Power supply drop
detection voltage
3
Vint(D)*
3.3
3.7
4.2
V
LVDSEL = 0
Power supply rise
detection voltage
Vint(U)*
3
3.6
4.0
4.5
V
LVDSEL = 0
Reset detection voltage
1
1*
Vreset1*
3
2.0
2.3
2.7
V
LVDSEL = 0
Reset detection voltage
2
2*
Vreset2*
3
2.7
3.3
3.9
V
LVDSEL = 1
Notes: 1. The above function should be used in conjunction with the voltage drop/rise detection
function.
2. Low-voltage detection reset should be selected for low-voltage detection reset only.
3. The values of Vint(D), Vint(U), Vreset1, and Vreset2 change relative to each other.
Example: If Vint(D) is the minimum value, Vint(U), Vreset1, and Vreset2 are also the
minimum values.
Rev. 8.00 Mar. 09, 2010 Page 521 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
Table 16.30
Power Supply Voltage Detection Circuit Characteristics (3)
Using on-chip reference voltage and detect voltage external input (VREFSEL = 0, VINTDSEL
and VINTUSEL = 1)
Rated Values
Item
Symbol
Min
Typ
Max
Unit
extD/extU interrupt
detection level
Vexd
0.80
1.20
1.60
V
extD/extU pin input
2
voltage*
VextD*
1
VextU*
–0.3
—
VCC + 0.3 or AVCC
+ 0.3, whichever is
lower
V
VCC = 2.7 to 3.3 V
–0.3
—
3.6 or AVCC + 0.3,
whichever is lower
V
VCC = 3.3 to 5.5 V
1
Notes: 1. The VextD voltage must always be greater than the VextU voltage.
2. The maximum input voltage of the extD and extU pins is 3.6 V.
Rev. 8.00 Mar. 09, 2010 Page 522 of 658
REJ09B0042-0800
Test Condition
Section 16 Electrical Characteristics
Table 16.31
Power Supply Voltage Detection Circuit Characteristics (4)
Using external reference voltage and ladder resistor (VREFSEL = 1, VINTDSEL = VINTUSEL =
0)
Rated Values
Typ
Max
Test
Unit Condition
Vint(D)*1 3.08 * (Vref1 – 0.1)
3.08 * Vref1
3.08 * (Vref1 + 0.1)
V
LVDSEL = 0
Vref input voltage
(Vint(D))
Vref1*2
—
1.68
V
Vint(D)
Power supply rise
detection voltage
Vint(U)*1 3.33 * (Vref2 – 0.1)
3.33 * Vref2
3.33 * (Vref2 + 0.1)
V
LVDSEL = 0
Vref input voltage
(Vint(U))
Vref2*2
—
1.55
V
Vint(U)
Reset detection
voltage 1
Vreset1*1 1.91 * (Vref3 – 0.1)
1.91 * Vref3
1.91 * (Vref3 + 0.1)
V
LVDSEL = 0
Vref input voltage
(Vreset1)
Vref3*2
—
2.77
V
Vreset1
Reset detection
voltage 2
Vreset2*1 2.76 * (Vref4 – 0.1)
2.76 * Vref4
2.76 * (Vref4 + 0.1)
V
LVDSEL = 1
Vref input voltage
(Vreset2)
Vref4*2
—
1.89
V
Vreset2
Item
Symbol
Power supply drop
detection voltage
Notes:
Min
0.98
0.91
0.89
1.08
1. The values of Vint(D), Vint(U), Vreset1, and Vreset2 change relative to each other.
Example: If Vint(D) is the minimum value, Vint(U), Vreset1, and Vreset2 are also the
minimum values.
2. The Vref input voltage is calculated using the following formula.
2.7 V (= VCC min)
< Vint(D), Vint(U), Vreset2
< 5.5 V (= VCC max)
1.5 V (= RAM retention voltage)
< Vreset1
< 5.5 V (= VCC max)
Vref1: 2.7 < 3.08 * (Vref1 – 0.1), 3.08 * (Vref1 + 0.1) < 5.5 → 0.98 < Vref1 < 1.68
Vref2: 2.7 < 3.33 * (Vref2 – 0.1), 3.33 * (Vref2 + 0.1) < 5.5 → 0.91 < Vref2 < 1.55
Vref3: 1.5 < 1.91 * (Vref3 – 0.1), 1.91 * (Vref3 + 0.1) < 5.5 → 0.89 < Vref3 < 2.77
Vref4: 2.7 < 2.76 * (Vref4 – 0.1), 2.76 * (Vref4 + 0.1) < 5.5 → 1.08 < Vref4 < 1.89
Rev. 8.00 Mar. 09, 2010 Page 523 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
Table 16. 32 Power Supply Voltage Detection Circuit Characteristics (5)
Using external reference voltage and detect voltage external input (VREFSEL = VINTDSEL =
VINTUSEL = 1)
Rated Values
Item
Symbol
Min
Typ
Max
Unit
Test Condition
Comparator detection
accuracy
Vcdl
0.1
—
—
V
| VextU – Vref |
extD/extU pin input
voltage
VextD*
Vref pin input voltage
| VextD – Vref |
–0.3
—
VCC + 0.3 or
AVCC + 0.3,
whichever is
lower
V
VCC = 2.7 to 3.3 V
–0.3
—
3.6 or AVCC
+ 0.3, whichever
is lower
V
VCC = 3.3 to 5.5 V
0.8
—
2.8
V
VCC = 2.7 to 5.5 V
VextU*
Vref5
Note: * The VextD voltage must always be greater than the VextU voltage.
16.8.8
Power-On Reset Circuit Characteristics
Table 16.33
Power-On Reset Circuit Characteristics
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Rated Values
Item
Symbol Min
Typ
Max
Unit
RES pin pull-up
resistance
RRES
65
100
—
kΩ
Power-on reset start
voltage
Vpor
—
—
100
mV
Test Condition
Note: Make sure to drop the power supply voltage, VCC, to below Vpor = 100 mV and then raise it
after the RES pin load had thoroughly dissipated. To drain the load of the RES pin,
attaching a diode to the VCC side is recommended. The power-on reset function may not
work properly if the power supply voltage, VCC, is raised from a level exceeding 100 mV.
Rev. 8.00 Mar. 09, 2010 Page 524 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
16.8.9
Watchdog Timer Characteristics
Table 16.34
Watchdog Timer Characteristics
AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Item
Symbol
On-chip oscillator
overflow time
tOVF
Applicable
Pins
Rated Values
Min
Typ
Max
Unit
Note
Test
Condition
0.2
0.4
—
s
*
VCC = 5 V
Note: * When the on-chip oscillator is selected, the timer counts from 0 to 255, indicating the time
remaining until an internal reset is generated.
16.8.10 Power Supply Characteristics
Table 16.35
Power Supply Characteristics
Unless otherwise indicated, VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V
Values
Item
Symbol
Applicable Test
Pins
Condition
Power supply startup voltage
VCCSTART
VCC
0
—
0.1
V
Power supply startup slope
SVCC
VCC
0.05
—
—
V/ms
Min
Typ
Max
Unit
Notes
*1*2
Notes: 1. This LSI may not start normally when it starts with the condition beyond specification
shown in above (Refer to figure 16.1 for power supply voltage startup time.).
2. Applies to the F-ZTAT version.
Voltage (V)
VCC
VCCSTART
SVCC
Time (ms)
Figure 16.1 Power Supply Voltage Startup Timing
Rev. 8.00 Mar. 09, 2010 Page 525 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
16.9
Operation Timing
Figures 16.2 to 16.7 show timing diagrams.
t OSC , tw
VIH
OSC1
x1
VIL
t CPH
t CPL
t CPr
t CPf
Figure 16.2 Clock Input Timing
RES
VIL
tREL
Figure 16.3 RES Low Width
IRQ0, IRQ1, IRQ3, IRQ4,
TMIC, TMIF, TMIG,
ADTRG, WKP0 to WKP7,
IRQAEC, AEVL, AEVH
VIH
VIL
t IL
t IH
Figure 16.4 Input Timing
Rev. 8.00 Mar. 09, 2010 Page 526 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
t SCKW
SCK 32
t scyc
Figure 16.5 SCK3 Input Clock Timing
t scyc
VIH or VOH*
SCK 32
VIL or VOL*
t TXD
VOH*
VOL*
TXD32
(transmit data)
t RXS
t RXH
RXD32
(receive data)
Note: * Output timing reference levels
Output high
VOH = 1/2Vcc + 0.2 V
Output low
VOL = 0.8 V
Load conditions are shown in figure 16.8.
Figure 16.6 SCI3 Synchronous Mode Input/Output Timing
Rev. 8.00 Mar. 09, 2010 Page 527 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
VIH
VIL
UD
tUDL
tUDH
Figure 16.7 UD Pin Minimum Transition Width Timing
16.10
Output Load Circuit
VCC
2.4 kΩ
Output pin
30 pF
12 kΩ
Figure 16.8 Output Load Condition
Rev. 8.00 Mar. 09, 2010 Page 528 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
16.11
Resonator Equivalent Circuit
LS
RS
CS
OSC1
OSC2
CO
Ceramic Resonator Parameters
Crystal Resonator Parameters
Frequency
(MHz)
Frequency
(MHz)
4
4.193
10
RS (max)
100 Ω
100 Ω
30 Ω
RS (max)
CO (max)
16 pF
16 pF
16 pF
CO (max)
2
4
10
18.3 Ω
6.8 Ω
4.6 Ω
36.94 pF 36.72 pF 32.31 pF
Figure 16.9 Resonator Equivalent Circuit (1)
LS
CS
RS
OSC1
OSC2
CO
Crystal Resonator Parameters
(Manufacturer's Publicly Released Values)
Frequency
(MHz)
4
Manufacturer
RS (max)
100 Ω
Nihon Dempa Kogyo Co., Ltd.
CO (max)
16 pF
Ceramic Resonator Parameters (1)
(Manufacturer's Publicly Released Values)
Frequency
(MHz)
2
Manufacturer
RS (max)
18.3 Ω
Murata Manufacturing Co., Ltd.
CO (max)
36.94 pF
Ceramic Resonator Parameters (2)
(Manufacturer's Publicly Released Values)
Frequency
(MHz)
10
Manufacturer
RS (max)
4.6 Ω
Murata Manufacturing Co., Ltd.
CO (max)
32.31 pF
Figure 16.10 Resonator Equivalent Circuit (2)
Rev. 8.00 Mar. 09, 2010 Page 529 of 658
REJ09B0042-0800
Section 16 Electrical Characteristics
16.12
Usage Note
The ZTAT, F-ZTAT, and mask ROM versions satisfy the electrical characteristics shown in this
manual, but actual electrical characteristic values, operating margins, noise margins, and other
properties may vary due to differences in manufacturing process, on-chip ROM, layout patterns,
and so on.
When system evaluation testing is carried out using the ZTAT or F-ZTAT version, the same
evaluation testing should also be conducted for the mask ROM version when changing over to that
version.
Rev. 8.00 Mar. 09, 2010 Page 530 of 658
REJ09B0042-0800
Appendix A CPU Instruction Set
Appendix A CPU Instruction Set
A.1
Instructions
Operation Notation
Rd8/16
General register (destination) (8 or 16 bits)
Rs8/16
General register (source) (8 or 16 bits)
Rn8/16
General register (8 or 16 bits)
CCR
Condition code register
N
N (negative) flag in CCR
Z
Z (zero) flag in CCR
V
V (overflow) flag in CCR
C
C (carry) flag in CCR
PC
Program counter
SP
Stack pointer
#xx: 3/8/16
Immediate data (3, 8, or 16 bits)
d: 8/16
Displacement (8 or 16 bits)
@aa: 8/16
Absolute address (8 or 16 bits)
+
Addition
–
Subtraction
×
Multiplication
÷
Division
∧
Logical AND
∨
Logical OR
⊕
Exclusive logical OR
→
Move
—
Logical complement
Condition Code Notation
↔
Symbol
Modified according to the instruction result
*
Not fixed (value not guaranteed)
0
Always cleared to 0
—
Not affected by the instruction execution result
Rev. 8.00 Mar. 09, 2010 Page 531 of 658
REJ09B0042-0800
Appendix A CPU Instruction Set
Table A.1 lists the H8/300L CPU instruction set.
Table A.1
Instruction Set
⎯ ⎯
2
MOV.B @aa:8, Rd
B @aa:8 → Rd8
2
⎯ ⎯
MOV.B @aa:16, Rd
B @aa:16 → Rd8
4
⎯ ⎯
MOV.B Rs, @Rd
B Rs8 → @Rd16
MOV.B Rs, @(d:16, Rd)
B Rs8 → @(d:16, Rd16)
MOV.B Rs, @−Rd
B Rd16−1 → Rd16
Rs8 → @Rd16
⎯ ⎯
2
⎯ ⎯
4
⎯ ⎯
2
MOV.B Rs, @aa:8
B Rs8 → @aa:8
2
⎯ ⎯
MOV.B Rs, @aa:16
B Rs8 → @aa:16
4
⎯ ⎯
MOV.W #xx:16, Rd
W #xx:16 → Rd
MOV.W Rs, Rd
W Rs16 → Rd16
MOV.W @Rs, Rd
W @Rs16 → Rd16
⎯ ⎯
4
⎯ ⎯
2
MOV.W @(d:16, Rs), Rd W @(d:16, Rs16) → Rd16
MOV.W @Rs+, Rd
W @Rs16 → Rd16
Rs16+2 → Rs16
MOV.W @aa:16, Rd
W @aa:16 → Rd16
MOV.W Rs, @Rd
W Rs16 → @Rd16
MOV.W Rs, @(d:16, Rd) W Rs16 → @(d:16, Rd16)
MOV.W Rs, @−Rd
W Rd16−2 → Rd16
Rs16 → @Rd16
⎯ ⎯
2
⎯ ⎯
4
⎯ ⎯
2
4
⎯ ⎯
⎯ ⎯
2
⎯ ⎯
4
⎯ ⎯
2
MOV.W Rs, @aa:16
W Rs16 → @aa:16
POP Rd
W @SP → Rd16
SP+2 → SP
2
⎯ ⎯
PUSH Rs
W SP−2 → SP
Rs16 → @SP
2
⎯ ⎯
Rev. 8.00 Mar. 09, 2010 Page 532 of 658
REJ09B0042-0800
4
⎯ ⎯
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
No. of States
Implied
@@aa
@(d:8, PC)
⎯ ⎯
4
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
B @Rs16 → Rd8
Rs16+1 → Rs16
⎯ ⎯
2
↔ ↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔ ↔
MOV.B @Rs+, Rd
⎯ ⎯
0 ⎯ 2
0 ⎯ 2
0 ⎯ 4
0 ⎯ 6
0 ⎯ 6
0 ⎯ 4
0 ⎯ 6
0 ⎯ 4
0 ⎯ 6
0 ⎯ 6
0 ⎯ 4
0 ⎯ 6
0 ⎯ 4
0 ⎯ 2
0 ⎯ 4
0 ⎯ 6
0 ⎯ 6
0 ⎯ 6
↔ ↔ ↔ ↔
↔ ↔ ↔ ↔
B @(d:16, Rs16)→ Rd8
⎯ ⎯
2
0 ⎯ 6
↔ ↔
↔ ↔
B @Rs16 → Rd8
Condition Code
I H N Z V C
0 ⎯ 6
↔
↔
MOV.B @Rs, Rd
MOV.B @(d:16, Rs), Rd
@aa: 8/16
2
B Rs8 → Rd8
@−Rn/@Rn+
B #xx:8 → Rd8
MOV.B Rs, Rd
@(d:16, Rn)
#xx: 8/16
MOV.B #xx:8, Rd
@Rn
Operation
Rn
Mnemonic
Operand Size
Addressing Mode/
Instruction Length (bytes)
0 ⎯ 6
0 ⎯ 4
0 ⎯ 6
0 ⎯ 6
Appendix A CPU Instruction Set
2
No. of States
Implied
@@aa
@(d:8, PC)
@aa: 8/16
@−Rn/@Rn+
@(d:16, Rn)
@Rn
⎯ (1)
⎯
2
↔
↔
↔
↔
B Rd8+#xx:8 +C → Rd8
⎯
2
↔
↔
↔
↔
W Rd16+Rs16 → Rd16
ADDX.B #xx:8, Rd
2
↔ ↔
ADD.W Rs, Rd
⎯
2
2
↔ ↔ ↔
↔
↔ ↔ ↔
↔ ↔ ↔
B Rd8+#xx:8 → Rd8
B Rd8+Rs8 → Rd8
Condition Code
I H N Z V C
↔ ↔
ADD.B #xx:8, Rd
ADD.B Rs, Rd
Rn
Operation
#xx: 8/16
Mnemonic
Operand Size
Addressing Mode/
Instruction Length (bytes)
(2)
2
(2)
2
2
2
⎯
W Rd16+1 → Rd16
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2
ADDS.W #2, Rd
W Rd16+2 → Rd16
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2
INC.B Rd
B Rd8+1 → Rd8
2
⎯ ⎯
DAA.B Rd
B Rd8 decimal adjust → Rd8
2
⎯ *
2
⎯
2
⎯ (1)
SUBX.B #xx:8, Rd
B Rd8−#xx:8 −C → Rd8
SUBX.B Rs, Rd
B Rd8−Rs8 −C → Rd8
2
⎯
⎯
2
(2)
(2)
↔ ↔ ↔ ↔
B Rd8−Rs8 → Rd8
W Rd16−Rs16 → Rd16
⎯ 2
* (3) 2
↔ ↔ ↔ ↔
SUB.B Rs, Rd
SUB.W Rs, Rd
↔
B Rd8+Rs8 +C → Rd8
ADDS.W #1, Rd
↔ ↔
↔
↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔
ADDX.B Rs, Rd
2
2
2
2
W Rd16−1 → Rd16
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2
W Rd16−2 → Rd16
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2
DEC.B Rd
B Rd8−1 → Rd8
2
⎯ ⎯
DAS.B Rd
B Rd8 decimal adjust → Rd8
2
⎯ *
B 0−Rd → Rd
B Rd8−#xx:8
2
⎯
⎯
2
CMP.B Rs, Rd
B Rd8−Rs8
2
⎯
CMP.W Rs, Rd
W Rd16−Rs16
2
⎯ (1)
⎯ 2
↔ ↔ ↔ ↔ ↔ ↔
↔
↔ ↔ ↔ ↔
↔ ↔ ↔ ↔
NEG.B Rd
CMP.B #xx:8, Rd
↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔
SUBS.W #1, Rd
SUBS.W #2, Rd
* ⎯ 2
2
2
2
2
Rev. 8.00 Mar. 09, 2010 Page 533 of 658
REJ09B0042-0800
Appendix A CPU Instruction Set
0
↔
2
0
↔
2
0
↔
2
0
2
0
2
0 ⎯ 2
0 ⎯ 2
0 ⎯ 2
0 ⎯ 2
0 ⎯ 2
Implied
XOR.B Rs, Rd
B Rd8⊕Rs8 → Rd8
2
⎯ ⎯
NOT.B Rd
B Rd → Rd
2
⎯ ⎯
SHAL.B Rd
B
2
⎯ ⎯
2
⎯ ⎯
2
⎯ ⎯
2
⎯ ⎯ 0
2
⎯ ⎯
2
⎯ ⎯
C
0
b7
SHAR.B Rd
B
B
C
b0
C
0
b7
SHLR.B Rd
B
b0
0
C
b7
ROTXL.B Rd
B
b0
C
b7
ROTXR.B Rd
b0
B
b7
0 ⎯ 2
0 ⎯ 2
b0
b7
SHLL.B Rd
No. of States
↔
2
↔
⎯ ⎯
⎯ ⎯
↔
2
2
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
↔
B Rd8⊕#xx:8 → Rd8
↔
↔
B Rd8∨Rs8 → Rd8
⎯ ⎯
⎯ ⎯
↔
↔
OR.B Rs, Rd
XOR.B #xx:8, Rd
2
2
↔
B Rd8∨#xx:8 → Rd8
↔
↔
B Rd8∧Rs8 → Rd8
I H N Z V C
↔
↔
AND.B Rs, Rd
Condition Code
⎯ ⎯
2
OR.B #xx:8, Rd
@@aa
B Rd8∧#xx:8 → Rd8
@(d:8, PC)
AND.B #xx:8, Rd
@aa: 8/16
⎯ ⎯ (5) (6) ⎯ ⎯ 14
@−Rn/@Rn+
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 14
2
@(d:16, Rn)
2
B Rd16÷Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
@Rn
B Rd8 × Rs8 → Rd16
DIVXU.B Rs, Rd
Operation
Rn
MULXU.B Rs, Rd
#xx: 8/16
Mnemonic
Operand Size
Addressing Mode/
Instruction Length (bytes)
b0
Rev. 8.00 Mar. 09, 2010 Page 534 of 658
REJ09B0042-0800
C
Appendix A CPU Instruction Set
No. of States
Implied
@@aa
@(d:8, PC)
@aa: 8/16
@−Rn/@Rn+
⎯ ⎯
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2
↔
2
0
2
0
2
b0
B
C
b7
⎯ ⎯
↔
ROTR.B Rd
I H N Z V C
2
↔
↔
b7
Condition Code
↔
↔
C
@(d:16, Rn)
Operation
@Rn
B
Rn
ROTL.B Rd
#xx: 8/16
Mnemonic
Operand Size
Addressing Mode/
Instruction Length (bytes)
b0
BSET #xx:3, Rd
B (#xx:3 of Rd8) ← 1
BSET #xx:3, @Rd
B (#xx:3 of @Rd16) ← 1
BSET #xx:3, @aa:8
B (#xx:3 of @aa:8) ← 1
BSET Rn, Rd
B (Rn8 of Rd8) ← 1
BSET Rn, @Rd
B (Rn8 of @Rd16) ← 1
BSET Rn, @aa:8
B (Rn8 of @aa:8) ← 1
BCLR #xx:3, Rd
B (#xx:3 of Rd8) ← 0
BCLR #xx:3, @Rd
B (#xx:3 of @Rd16) ← 0
BCLR #xx:3, @aa:8
B (#xx:3 of @aa:8) ← 0
BCLR Rn, Rd
B (Rn8 of Rd8) ← 0
BCLR Rn, @Rd
B (Rn8 of @Rd16) ← 0
BCLR Rn, @aa:8
B (Rn8 of @aa:8) ← 0
BNOT #xx:3, Rd
B (#xx:3 of Rd8) ←
(#xx:3 of Rd8)
BNOT #xx:3, @Rd
B (#xx:3 of @Rd16) ←
(#xx:3 of @Rd16)
BNOT #xx:3, @aa:8
B (#xx:3 of @aa:8) ←
(#xx:3 of @aa:8)
BNOT Rn, Rd
B (Rn8 of Rd8) ←
(Rn8 of Rd8)
BNOT Rn, @Rd
B (Rn8 of @Rd16) ←
(Rn8 of @Rd16)
BNOT Rn, @aa:8
B (Rn8 of @aa:8) ←
(Rn8 of @aa:8)
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
4
4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
4
4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
4
4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
4
4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
4
4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
4
4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
Rev. 8.00 Mar. 09, 2010 Page 535 of 658
REJ09B0042-0800
Appendix A CPU Instruction Set
B (Rn8 of @aa:8) → Z
B (#xx:3 of Rd8) → C
BLD #xx:3, @Rd
B (#xx:3 of @Rd16) → C
BLD #xx:3, @aa:8
B (#xx:3 of @aa:8) → C
BILD #xx:3, Rd
B (#xx:3 of Rd8) → C
BILD #xx:3, @Rd
B (#xx:3 of @Rd16) → C
BILD #xx:3, @aa:8
B (#xx:3 of @aa:8) → C
BST #xx:3, Rd
B C → (#xx:3 of Rd8)
BST #xx:3, @Rd
B C → (#xx:3 of @Rd16)
BST #xx:3, @aa:8
B C → (#xx:3 of @aa:8)
BIST #xx:3, Rd
B C → (#xx:3 of Rd8)
BIST #xx:3, @Rd
B C → (#xx:3 of @Rd16)
BIST #xx:3, @aa:8
B C → (#xx:3 of @aa:8)
BAND #xx:3, Rd
B C∧(#xx:3 of Rd8) → C
BAND #xx:3, @Rd
B C∧(#xx:3 of @Rd16) → C
BAND #xx:3, @aa:8
B C∧(#xx:3 of @aa:8) → C
BIAND #xx:3, Rd
B C∧(#xx:3 of Rd8) → C
BIAND #xx:3, @Rd
B C∧(#xx:3 of @Rd16) → C
BIAND #xx:3, @aa:8
B C∧(#xx:3 of @aa:8) → C
BOR #xx:3, Rd
B C∨(#xx:3 of Rd8) → C
BOR #xx:3, @Rd
B C∨(#xx:3 of @Rd16) → C
BOR #xx:3, @aa:8
B C∨(#xx:3 of @aa:8) → C
BIOR #xx:3, Rd
B C∨(#xx:3 of Rd8) → C
BIOR #xx:3, @Rd
B C∨(#xx:3 of @Rd16) → C
Rev. 8.00 Mar. 09, 2010 Page 536 of 658
REJ09B0042-0800
4
⎯ ⎯ ⎯
⎯ ⎯ ⎯
2
⎯ ⎯ ⎯
4
4
⎯ ⎯ ⎯
⎯ ⎯ 6
⎯ ⎯ 6
⎯ ⎯ 2
⎯ ⎯ 6
⎯ ⎯ 6
⎯ ⎯ ⎯ ⎯ ⎯
2
⎯ ⎯ ⎯ ⎯ ⎯
4
4
⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯
2
⎯ ⎯ ⎯ ⎯ ⎯
4
4
No. of States
Implied
@@aa
@(d:8, PC)
⎯ ⎯ ⎯
4
⎯ ⎯ 2
⎯ ⎯ ⎯ ⎯ ⎯
↔ ↔ ↔ ↔ ↔ ↔
BTST Rn, @aa:8
BLD #xx:3, Rd
I H N Z V C
⎯ ⎯ ⎯
2
2
6
6
2
6
6
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
4
4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
4
4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
⎯ ⎯ ⎯ ⎯ ⎯
2
⎯ ⎯ ⎯ ⎯ ⎯
4
4
⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯
2
⎯ ⎯ ⎯ ⎯ ⎯
4
4
⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯
2
⎯ ⎯ ⎯ ⎯ ⎯
4
4
⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯
2
4
⎯ ⎯ ⎯ ⎯ ⎯
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
B (Rn8 of Rd8) → Z
B (Rn8 of @Rd16) → Z
Condition Code
↔ ↔ ↔ ↔ ↔ ↔
BTST Rn, Rd
BTST Rn, @Rd
@aa: 8/16
B (#xx:3 of @aa:8) → Z
@−Rn/@Rn+
B (#xx:3 of @Rd16) → Z
@(d:16, Rn)
BTST #xx:3, @Rd
BTST #xx:3, @aa:8
Operation
@Rn
B (#xx:3 of Rd8) → Z
Rn
BTST #xx:3, Rd
#xx: 8/16
Mnemonic
Operand Size
Addressing Mode/
Instruction Length (bytes)
2
6
6
2
6
6
2
6
6
2
6
Appendix A CPU Instruction Set
B C⊕(#xx:3 of Rd8) → C
B C⊕(#xx:3 of @Rd16) → C
BXOR #xx:3, @aa:8
B C⊕(#xx:3 of @aa:8) → C
BIXOR #xx:3, Rd
B C⊕(#xx:3 of Rd8) → C
BIXOR #xx:3, @Rd
B C⊕(#xx:3 of @Rd16) → C
BIXOR #xx:3, @aa:8
B C⊕(#xx:3 of @aa:8) → C
I H N Z V C
⎯ ⎯ ⎯ ⎯ ⎯
4
⎯ ⎯ ⎯ ⎯ ⎯
2
⎯ ⎯ ⎯ ⎯ ⎯
4
⎯ ⎯ ⎯ ⎯ ⎯
4
⎯ ⎯ ⎯ ⎯ ⎯
2
⎯ ⎯ ⎯ ⎯ ⎯
4
⎯ ⎯ ⎯ ⎯ ⎯
4
No. of States
Implied
@@aa
@(d:8, PC)
@aa: 8/16
@−Rn/@Rn+
Condition Code
↔ ↔ ↔ ↔ ↔ ↔ ↔
BXOR #xx:3, Rd
BXOR #xx:3, @Rd
@(d:16, Rn)
Operation
@Rn
B C∨(#xx:3 of @aa:8) → C
Rn
BIOR #xx:3, @aa:8
Branching
Condition
#xx: 8/16
Mnemonic
Operand Size
Addressing Mode/
Instruction Length (bytes)
6
2
6
6
2
6
6
BRA d:8 (BT d:8)
⎯ PC ← PC+d:8
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
BRN d:8 (BF d:8)
⎯ PC ← PC+2
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
BHI d:8
C∨Z=0
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
C∨Z=1
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
C=0
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
C=1
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
Z=0
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
BEQ d:8
⎯ If
condition
⎯
is true
⎯ then
⎯ PC ←
PC+d:8
⎯ else next;
⎯
Z=1
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
BVC d:8
⎯
V=0
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
BVS d:8
⎯
V=1
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
BPL d:8
⎯
N=0
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
BMI d:8
⎯
N=1
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
BGE d:8
⎯
N⊕V = 0
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
BLT d:8
⎯
N⊕V = 1
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
BGT d:8
⎯
Z ∨ (N⊕V) = 0
2
BLE d:8
⎯
Z ∨ (N⊕V) = 1
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
JMP @Rn
⎯ PC ← Rn16
JMP @aa:16
⎯ PC ← aa:16
JMP @@aa:8
⎯ PC ← @aa:8
BSR d:8
⎯ SP−2 → SP
PC → @SP
PC ← PC+d:8
BLS d:8
BCC d:8 (BHS d:8)
BCS d:8 (BLO d:8)
BNE d:8
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 6
2
4
2
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 6
Rev. 8.00 Mar. 09, 2010 Page 537 of 658
REJ09B0042-0800
Appendix A CPU Instruction Set
Condition Code
I H N Z V C
No. of States
Implied
@@aa
@(d:8, PC)
@aa: 8/16
@−Rn/@Rn+
@(d:16, Rn)
@Rn
Rn
Operation
#xx: 8/16
Mnemonic
Operand Size
Addressing Mode/
Instruction Length (bytes)
JSR @Rn
⎯ SP−2 → SP
PC → @SP
PC ← Rn16
JSR @aa:16
⎯ SP−2 → SP
PC → @SP
PC ← aa:16
JSR @@aa:8
⎯ SP−2 → SP
PC → @SP
PC ← @aa:8
RTS
⎯ PC ← @SP
SP+2 → SP
2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
RTE
⎯ CCR ← @SP
SP+2 → SP
PC ← @SP
SP+2 → SP
2
SLEEP
⎯ Transit to sleep mode.
2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
2
2
↔
↔
↔
↔
↔
↔
10
2
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2
2
STC CCR, Rd
B CCR → Rd8
ANDC #xx:8, CCR
B CCR∧#xx:8 → CCR
2
↔
↔
↔
↔
↔
↔
B Rs8 → CCR
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
2
2
ORC #xx:8, CCR
B CCR∨#xx:8 → CCR
2
↔
↔
↔
↔
↔
↔
B #xx:8 → CCR
LDC Rs, CCR
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
4
2
XORC #xx:8, CCR
B CCR⊕#xx:8 → CCR
2
↔
↔
↔
↔
↔
↔
LDC #xx:8, CCR
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 6
2
2
NOP
⎯ PC ← PC+2
2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2
EEPMOV
⎯ if R4L≠0
Repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4L−1 → R4L
Until R4L=0
else next;
4 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ (4)
Notes: (1)
(2)
(3)
(4)
Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0.
If the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0.
Set to 1 if decimal adjustment produces a carry; otherwise retains value prior to arithmetic operation.
The number of states required for execution is 4n + 9 (n = value of R4L). 4n + 8 for HD64F38024,
H8/38024S Group, and H8/38124 Group.
(5) Set to 1 if the divisor is negative; otherwise cleared to 0.
(6) Set to 1 if the divisor is zero; otherwise cleared to 0.
Rev. 8.00 Mar. 09, 2010 Page 538 of 658
REJ09B0042-0800
Appendix A CPU Instruction Set
A.2
Operation Code Map
Table A.2 is an operation code map. It shows the operation codes contained in the first byte of the
instruction code (bits 15 to 8 of the first instruction word).
Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0.
Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1.
Rev. 8.00 Mar. 09, 2010 Page 539 of 658
REJ09B0042-0800
Rev. 8.00 Mar. 09, 2010 Page 540 of 658
REJ09B0042-0800
OR
XOR
AND
MOV
C
D
E
F
Note: * The PUSH and POP instructions are identical in machine language to MOV instructions.
SUBX
BILD
8
BVC
B
BIAND
BAND
BIST
BLD
BST
BEQ
MOV
NEG
NOT
LDC
7
CMP
BIXOR
BXOR
RTE
BNE
AND
ANDC
6
A
BIOR
BOR
BSR
BCS
XOR
XORC
5
ADDX
BTST
RTS
BCC
OR
ORC
4
9
BCLR
BLS
ROTR
ROTXR
LDC
3
ADD
BNOT
BHI
ROTL
ROTXL
STC
2
8
7
BSET
DIVXU
MULXU
5
6
BRN
SHAR
SHLR
SLEEP
1
BRA
SHAL
SHLL
NOP
0
4
3
2
1
Low
SUB
ADD
MOV
BVS
9
JMP
BPL
DEC
INC
A
EEPMOV
MOV*
BMI
SUBS
ADDS
B
CMP
MOV
BLT
D
JSR
BGT
SUBX
ADDX
E
Bit-manipulation instructions
BGE
C
BLE
DAS
DAA
F
Table A.2
0
High
Appendix A CPU Instruction Set
Operation Code Map
Appendix A CPU Instruction Set
A.3
Number of Execution States
The tables here can be used to calculate the number of states required for instruction execution.
Table A.4 indicates the number of states required for each cycle (instruction fetch, read/write,
etc.), and table A.3 indicates the number of cycles of each type occurring in each instruction. The
total number of states required for execution of an instruction can be calculated from these two
tables as follows:
Execution states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed.
BSET #0, @FF00
From table A.4:
I = L = 2, J = K = M = N= 0
From table A.3:
SI = 2, SL = 2
Number of states required for execution = 2 × 2 + 2 × 2 = 8
When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and
on-chip RAM is used for stack area.
JSR @@ 30
From table A.4:
I = 2, J = K = 1, L = M = N = 0
From table A.3:
SI = SJ = SK = 2
Number of states required for execution = 2 × 2 + 1 × 2+ 1 × 2 = 8
Table A.3
Number of Cycles in Each Instruction
Access Location
Execution Status
(instruction cycle)
Instruction fetch
SI
Branch address read
SJ
Stack operation
SK
Byte data access
SL
Word data access
SM
Internal operation
SN
On-Chip Memory
On-Chip Peripheral Module
2
—
2 or 3*
—
1
Note: * Depends on which on-chip module is accessed. See section 2.9.1, Notes on Data Access
for details.
Rev. 8.00 Mar. 09, 2010 Page 541 of 658
REJ09B0042-0800
Appendix A CPU Instruction Set
Table A.4
Number of Cycles in Each Instruction
Instruction
Mnemonic
Instruction
Fetch
I
ADD
ADD.B #xx:8, Rd
1
ADDS
ADDX
AND
ADD.B Rs, Rd
1
ADD.W Rs, Rd
1
ADDS.W #1, Rd
1
ADDS.W #2, Rd
1
ADDX.B #xx:8, Rd
1
ADDX.B Rs, Rd
1
AND.B #xx:8, Rd
1
Stack
Branch
Addr. Read Operation
K
J
Byte Data
Access
L
AND.B Rs, Rd
1
ANDC
ANDC #xx:8, CCR
1
BAND
BAND #xx:3, Rd
1
BAND #xx:3, @Rd
2
1
BAND #xx:3, @aa:8
2
1
BRA d:8 (BT d:8)
2
BRN d:8 (BF d:8)
2
Bcc
BCLR
BIAND
BHI d:8
2
BLS d:8
2
BCC d:8 (BHS d:8)
2
BCS d:8 (BLO d:8)
2
BNE d:8
2
BEQ d:8
2
BVC d:8
2
BVS d:8
2
BPL d:8
2
BMI d:8
2
BGE d:8
2
BLT d:8
2
BGT d:8
2
BLE d:8
2
BCLR #xx:3, Rd
1
BCLR #xx:3, @Rd
2
2
BCLR #xx:3, @aa:8
2
2
BCLR Rn, Rd
1
BCLR Rn, @Rd
2
2
BCLR Rn, @aa:8
2
2
BIAND #xx:3, Rd
1
BIAND #xx:3, @Rd
2
1
BIAND #xx:3, @aa:8
2
1
Rev. 8.00 Mar. 09, 2010 Page 542 of 658
REJ09B0042-0800
Word Data
Access
M
Internal
Operation N
Appendix A CPU Instruction Set
Instruction
BILD
BIOR
BIST
BIXOR
BLD
BNOT
BOR
BSET
Mnemonic
Instruction
Fetch
I
Byte Data
Access
L
BILD #xx:3, Rd
1
BILD #xx:3, @Rd
2
1
BILD #xx:3, @aa:8
2
1
BIOR #xx:3, Rd
1
BIOR #xx:3, @Rd
2
1
BIOR #xx:3, @aa:8
2
1
BIST #xx:3, Rd
1
BIST #xx:3, @Rd
2
2
BIST #xx:3, @aa:8
2
2
BIXOR #xx:3, Rd
1
BIXOR #xx:3, @Rd
2
1
BIXOR #xx:3, @aa:8
2
1
BLD #xx:3, Rd
1
BLD #xx:3, @Rd
2
1
BLD #xx:3, @aa:8
2
1
BNOT #xx:3, Rd
1
BNOT #xx:3, @Rd
2
2
BNOT #xx:3, @aa:8
2
2
BNOT Rn, Rd
1
BNOT Rn, @Rd
2
2
BNOT Rn, @aa:8
2
2
BOR #xx:3, Rd
1
BOR #xx:3, @Rd
2
1
BOR #xx:3, @aa:8
2
1
BSET #xx:3, Rd
1
BSET #xx:3, @Rd
2
2
BSET #xx:3, @aa:8
2
2
BSET Rn, Rd
1
BSET Rn, @Rd
2
2
BSET Rn, @aa:8
2
2
BSR
BSR d:8
2
BST
BST #xx:3, Rd
1
BTST
Stack
Branch
Addr. Read Operation
K
J
Word Data
Access
M
Internal
Operation
N
1
BST #xx:3, @Rd
2
2
BST #xx:3, @aa:8
2
2
BTST #xx:3, Rd
1
BTST #xx:3, @Rd
2
1
BTST #xx:3, @aa:8
2
1
BTST Rn, Rd
1
BTST Rn, @Rd
2
1
Rev. 8.00 Mar. 09, 2010 Page 543 of 658
REJ09B0042-0800
Appendix A CPU Instruction Set
Stack
Branch
Addr. Read Operation
K
J
Byte Data
Access
L
Instruction
Mnemonic
Instruction
Fetch
I
BTST
BTST Rn, @aa:8
2
BXOR
BXOR #xx:3, Rd
1
BXOR #xx:3, @Rd
2
1
BXOR #xx:3, @aa:8
2
1
CMP. B #xx:8, Rd
1
CMP
CMP. B Rs, Rd
1
CMP.W Rs, Rd
1
DAA
DAA.B Rd
1
DAS
DAS.B Rd
1
DEC
DEC.B Rd
1
DIVXU
DIVXU.B Rs, Rd
1
EEPMOV
EEPMOV
2
INC
INC.B Rd
1
JMP
JMP @Rn
2
JMP @aa:16
2
JMP @@aa:8
2
JSR
LDC
MOV
12
2n+2*
2
2
2
1
2
1
JSR @@aa:8
2
LDC #xx:8, CCR
1
LDC Rs, CCR
1
1
1
1*
1
JSR @aa:16
MOV.B Rs, Rd
1
2
1
MOV.B @Rs, Rd
1
MOV.B @(d:16, Rs), Rd
2
1
MOV.B @Rs+, Rd
1
1
MOV.B @aa:8, Rd
1
1
MOV.B @aa:16, Rd
2
1
MOV.B Rs, @Rd
1
1
MOV.B Rs, @(d:16, Rd)
2
1
MOV.B Rs, @–Rd
1
1
MOV.B Rs, @aa:8
1
1
MOV.B Rs, @aa:16
2
1
MOV.W #xx:16, Rd
2
1
2
2
MOV.W Rs, Rd
1
MOV.W @Rs, Rd
1
MOV.W @(d:16, Rs), Rd
2
1
MOV.W @Rs+, Rd
1
1
MOV.W @aa:16, Rd
2
1
1
Note: * n: Initial value in R4L. The source and destination operands are accessed n + 1 times each.
Internal operation N is 0 for HD64F38024, HD64F38024F, H8/38024S Group and H8/38124 Group.
Rev. 8.00 Mar. 09, 2010 Page 544 of 658
REJ09B0042-0800
Internal
Operation
N
1
JSR @Rn
MOV.B #xx:8, Rd
Word Data
Access
M
2
Appendix A CPU Instruction Set
Stack
Branch
Addr. Read Operation
K
J
Byte Data
Access
L
Word Data
Access
M
Instruction
Mnemonic
Instruction
Fetch
I
MOV
MOV.W Rs, @Rd
1
MOV.W Rs, @(d:16, Rd)
2
1
MOV.W Rs, @–Rd
1
1
MOV.W Rs, @aa:16
2
1
MULXU
MULXU.B Rs, Rd
1
NEG
NEG.B Rd
1
NOP
NOP
1
NOT
NOT.B Rd
1
OR
OR.B #xx:8, Rd
1
OR.B Rs, Rd
1
Internal
Operation
N
1
2
12
ORC
ORC #xx:8, CCR
1
ROTL
ROTL.B Rd
1
ROTR
ROTR.B Rd
1
ROTXL
ROTXL.B Rd
1
ROTXR
ROTXR.B Rd
1
RTE
RTE
2
2
2
RTS
RTS
2
1
2
SHAL
SHAL.B Rd
1
SHAR
SHAR.B Rd
1
SHLL
SHLL.B Rd
1
SHLR
SHLR.B Rd
1
SLEEP
SLEEP
1
STC
STC CCR, Rd
1
SUB
SUB.B Rs, Rd
1
SUB.W Rs, Rd
1
SUBS
SUBS.W #1, Rd
1
SUBS.W #2, Rd
1
POP
POP Rd
1
1
2
PUSH
PUSH Rs
1
1
2
SUBX
SUBX.B #xx:8, Rd
1
SUBX.B Rs, Rd
1
XOR.B #xx:8, Rd
1
XOR
XORC
XOR.B Rs, Rd
1
XORC #xx:8, CCR
1
Rev. 8.00 Mar. 09, 2010 Page 545 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
Appendix B Internal I/O Registers
B.1
Addresses
Upper Address: H'F0
Bit Names
Lower
Address
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module Name
H'20
FLMCR1
—
SWE
ESU
PSU
EV
PV
E
P
ROM
H'21
FLMCR2
FLER
—
—
—
—
—
—
—
H'22
FLPWCR
PDWND
—
—
—
—
—
—
—
H'23
EBR
—
—
—
EB4
EB3
EB2
EB1
EB0
FENR
FLSHE
—
—
—
—
—
—
—
H'24
H'25
H'26
H'27
H'28
H'29
H'2A
H'2B
H'2C
H'2D
H'2E
H'2F
Rev. 8.00 Mar. 09, 2010 Page 546 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
Upper Address: H'FF
Lower
Address
Bit Names
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
H'86
LVDCR
LVDE
—
VINTDSEL
H'87
LVDSR
OVF
—
—
Bit 3
Bit 2
Bit 1
Bit 0
Module Name
VINTUSEL
LVDSL
LVDRE
LVDDE
LVDUE
—
VREFSEL
—
LVDDF
LVDUF
Low-voltage
detect circuit*
H'80
H'81
H'82
H'83
H'84
H'85
H'88
H'89
H'8A
H'8B
H'8C
ECPWCRH ECPWCRH7 ECPWCRH6 ECPWCRH5 ECPWCRH4 ECPWCRH3 ECPWCRH2 ECPWCRH1 ECPWCRH0 Asynchronous
H'8D
ECPWCRL ECPWCRL7 ECPWCRL6 ECPWCRL5 ECPWCRL4 ECPWCRL3 ECPWCRL2 ECPWCRL1 ECPWCRL0 event counter
H'8E
ECPWDRH ECPWDRH7 ECPWDRH6 ECPWDRH5 ECPWDRH4 ECPWDRH3 ECPWDRH2 ECPWDRH1 ECPWDRH0
H'8F
ECPWDRL ECPWDRL7 ECPWDRL6 ECPWDRL5 ECPWDRL4 ECPWDRL3 ECPWDRL2 ECPWDRL1 ECPWDRL0
H'90
WEGR
WKEGS7
WKEGS6
WKEGS5
WKEGS4
WKEGS3
WKEGS2
WKEGS1
WKEGS0
System control
H'91
SPCR
—
—
SPC32
—
SCINV3
SCINV2
—
—
SCI3
H'92
AEGSR
AHEGS1
AHEGS0
ALEGS1
ALEGS0
AIEGS1
AIEGS0
ECPWME
—
Asynchronous
ECCR
ACKH1
ACKH0
ACKL1
ACKL0
PWCK2
PWCK1
PWCK0
—
CRCL
H'93
H'94
event counter
H'95
ECCSR
OVH
OVL
—
CH2
CUEH
CUEL
CRCH
H'96
ECH
ECH7
ECH6
ECH5
ECH4
ECH3
ECH2
ECH1
ECH0
H'97
ECL
ECL7
ECL6
ECL5
ECL4
ECL3
ECL2
ECL1
ECL0
H'98
H'99
H'9A
H'9B
H'9C
H'9D
H'9E
H'9F
Rev. 8.00 Mar. 09, 2010 Page 547 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
Upper Address: H'FF
Lower
Address
Bit Names
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module Name
H'A8
SMR
COM
CHR
PE
PM
STOP
MP
CKS1
CKS0
SCI3
H'A9
BRR
BRR7
BRR6
BRR5
BRR4
BRR3
BRR2
BRR1
BRR0
H'AA
SCR3
TIE
RIE
TE
RE
—
TEIE
CKE1
CKE0
H'AB
TDR
TDR7
TDR6
TDR5
TDR4
TDR3
TDR2
TDR1
TDR0
H'A0
H'A1
H'A2
H'A3
H'A4
H'A5
H'A6
H'A7
H'AC
SSR
TDRE
RDRF
OER
FER
PER
TEND
—
—
H''AD
RDR
RDR7
RDR6
RDR5
RDR4
RDR3
RDR2
RDR1
RDR0
H'AE
H'AF
H'B0
TMA
—
—
—
—
TMA3
TMA2
TMA1
TMA0
H'B1
TCA
TCA7
TCA6
TCA5
TCA4
TCA3
TCA2
TCA1
TCA0
H'B2
TCSRW
B6WI
TCWE
B4WI
TCSRWE
B2WI
WDON
BOWI
WRST
Watchdog
H'B3
TCW
TCW7
TCW6
TCW5
TCW4
TCW3
TCW2
TCW1
TCW0
timer
H'B4
TMC
TMC7
TMC6
TMC5
—
—
TMC2
TMC1
TMC0
Timer C
H'B5
TCC/TLC
TCC7/TLC7 TCC6/TLC6 TCC5/TLC5 TCC4/TLC4 TCC3/TLC3 TCC2/TLC2 TCC1/TLC1 TCC0/TLC0
H'B6
TCRF
TOLH
CKSH2
CKSH1
CKSH0
TOLL
CKSL2
CKSL1
CKSL0
H'B7
TCSRF
OVFH
CMFH
OVIEH
CCLRH
OVFL
CMFL
OVIEL
CCLRL
H'B8
TCFH
TCFH7
TCFH6
TCFH5
TCFH4
TCFH3
TCFH2
TCFH1
TCFH0
H'B9
TCFL
TCFL7
TCFL6
TCFL5
TCFL4
TCFL3
TCFL2
TCFL1
TCFL0
H'BA
OCRFH
OCRFH7
OCRFH6
OCRFH5
OCRFH4
OCRFH3
OCRFH2
OCRFH1
OCRFH0
OCRFL0
H'BB
OCRFL
OCRFL7
OCRFL6
OCRFL5
OCRFL4
OCRFL3
OCRFL2
OCRFL1
H'BC
TMG
OVFH
OVFL
OVIE
IIEGS
CCLR1
CCLR0
CKS1
CKS0
H'BD
ICRGF
ICRGF7
ICRGF6
ICRGF5
ICRGF4
ICRGF3
ICRGF2
ICRGF1
ICRGF0
H'BE
ICRGR
ICRGR7
ICRGR6
ICRGR5
ICRGR4
ICRGR3
ICRGR2
ICRGR1
ICRGR0
H'BF
Rev. 8.00 Mar. 09, 2010 Page 548 of 658
REJ09B0042-0800
Timer A
Timer F
Timer G
Appendix B Internal I/O Registers
Upper Address: H'FF
Bit Names
Lower
Address
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module Name
H'C0
LPCR
DTS1
DTS0
CMX
—
SGS3
SGS2
SGS1
SGS0
H'C1
LCR
—
PSW
ACT
DISP
CKS3
CKS2
CKS1
CKS0
LCD controller/
driver
H'C2
LCR2
LCDAB
—
—
—
CDS3*
CDS2*
CDS1*
CDS0*
H'C3
LVDCNT
CNT7
CNT6
CNT5
CNT4
CNT3
CNT2
CNT1
CNT0
Low-voltage
detect circuit*
H'C4
ADRRH
ADR9
ADR8
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
A/D converter
H'C5
ADRRL
ADR1
ADR0
—
—
—
—
—
—
H'C6
AMR
CKS
TRGE
—
—
CH3
CH2
CH1
CH0
H'C7
ADSR
ADSF
—
—
—
—
—
—
—
H'C8
PMR1
IRQ3
—
—
IRQ4
TMIG
—
—
—
H'C9
PMR2
—
—
POF1
—
—
WDCKS
NCS
IRQ0
H'CA
PMR3
AEVL
AEVH
—
—
—
TMOFH
TMOFL
UD
H'CC
PMR5
WKP7
WKP6
WKP5
WKP4
WKP3
WKP2
WKP1
WKP0
H'CD
PWCR2
—
—
—
—
—
PWCR22*
PWCR21
PWCR20
I/O port
H'CB
H'CE
PWDRU2
—
—
—
—
—
—
PWDRU21
PWDRU20
H'CF
PWDRL2
PWDRL27
PWDRL26
PWDRL25
PWDRL24
PWDRL23
PWDRL22
PWDRL21
PWDRL20
H'D0
PWCR1
—
—
—
—
—
PWCR12*
PWCR11
PWCR10
H'D1
PWDRU1
—
—
—
—
—
—
PWDRU11
PWDRU10
H'D2
PWDRL1
PWDRL17
PWDRL16
PWDRL15
PWDRL14
PWDRL13
PWDRL12
PWDRL11
PWDRL10
PDR1
P17
P16
—
P14
P13
—
—
—
P30
10 bit PWM2
10 bit PWM1
H'D3
H'D4
I/O port
H'D5
H'D6
PDR3
P37
P36
P35
P34
P33
P32
P31
H'D7
PDR4
—
—
—
—
P43
P42
P41
P40
H'D8
PDR5
P57
P56
P55
P54
P53
P52
P51
P50
H'D9
PDR6
P67
P66
P65
P64
P63
P62
P61
P60
H'DA
PDR7
P77
P76
P75
P74
P73
P72
P71
P70
H'DB
PDR8
P87
P86
P85
P84
P83
P82
P81
P80
H'DC
PDR9
—
—
P95
P94
P93
P92
P91
P90
H'DD
PDRA
—
—
—
—
PA3
PA2
PA1
PA0
H'DE
PDRB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
H'DF
Rev. 8.00 Mar. 09, 2010 Page 549 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
Upper Address: H'FF
Lower
Address
Register
Name
Bit Names
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module Name
I/O port
H'E0
PUCR1
PUCR17
PUCR16
—
PUCR14
PUCR13
—
—
—
H'E1
PUCR3
PUCR37
PUCR36
PUCR35
PUCR34
PUCR33
PUCR32
PUCR31
PUCR30
H'E2
PUCR5
PUCR57
PUCR56
PUCR55
PUCR54
PUCR53
PUCR52
PUCR51
PUCR50
H'E3
PUCR6
PUCR67
PUCR66
PUCR65
PUCR64
PUCR63
PUCR62
PUCR61
PUCR60
H'E4
PCR1
PCR17
PCR16
—
PCR14
PCR13
—
—
—
H'E6
PCR3
PCR37
PCR36
PCR35
PCR34
PCR33
PCR32
PCR31
PCR30
H'E7
PCR4
—
—
—
—
—
PCR42
PCR41
PCR40
H'E8
PCR5
PCR57
PCR56
PCR55
PCR54
PCR53
PCR52
PCR51
PCR50
H'E9
PCR6
PCR67
PCR66
PCR65
PCR64
PCR63
PCR62
PCR61
PCR60
H'EA
PCR7
PCR77
PCR76
PCR75
PCR74
PCR73
PCR72
PCR71
PCR70
H'EB
PCR8
PCR87
PCR86
PCR85
PCR84
PCR83
PCR82
PCR81
PCR80
H'EC
PMR9
—
—
—
—
PIOFF
—
PWM2
PWM1
H'ED
PCRA
—
—
—
—
PCRA3
PCRA2
PCRA1
PCRA0
H'EE
PMRB
—
—
—
—
IRQ1
—
—
—
H'F0
SYSCR1
SSBY
STS2
STS1
STS0
LSON
—
MA1
MA0
H'F1
SYSCR2
—
—
—
NESEL
DTON
MSON
SA1
SA0
H'E5
H'EF
System control
H'F2
IEGR
—
—
—
IEG4
IEG3
—
IEG1
IEG0
H'F3
IENR1
IENTA
—
IENWP
IEN4
IEN3
IENEC2
IEN1
IEN0
H'F4
IENR2
IENDT
IENAD
—
IENTG
IENTFH
IENTFL
IENTC
IENEC
H'F5
OSCCR*
SUBSTP
—
—
—
—
IRQAECF
OSCF
—
H'F6
IRR1
IRRTA
—
—
IRRI4
IRRI3
IRREC2
IRRI1
IRRI0
H'F7
IRR2
IRRDT
IRRAD
—
IRRTG
IRRTFH
IRRTFL
IRRTC
IRREC
H'F8
TMW *
—
—
—
—
CKS3
CKS2
CKS1
CKS0
Watchdog
timer
H'F9
IWPR
IWPF7
IWPF6
IWPF5
IWPF4
IWPF3
IWPF2
IWPF1
IWPF0
System control
H'FA
CKSTPR1
—
—
S32CKSTP ADCKSTP
TGCKSTP
TFCKSTP
TCCKSTP
TACKSTP
H'FB
CKSTPR2
—
—
—
H'FC
H'FD
H'FE
H'FF
[Legend]
SCI: Serial Communication Interface
Note: * H8/38124 only
Rev. 8.00 Mar. 09, 2010 Page 550 of 658
REJ09B0042-0800
PW2CKSTP AECKSTP
WDCKSTP PW1CKSTP LDCKSTP
Appendix B Internal I/O Registers
B.2
Functions
Address to which the register is mapped.
When displayed with two-digit number,
this indicates the lower address,
and the upper address is HFF.
Register name
Register acronym
Timer F
H'B6
TCRF⎯Timer Control Register F
Name of on-chip
supporting module
Bit numbers
Bit
Initial bit values
Dashes (⎯) indicate
undefined bits.
7
6
TOLH
Initial value 0
R/W
W
5
4
3
CKSH2 CKSH1 CKSH0
0
W
0
W
TOLL
0
W
2
1
0
CKSL2 CKSL1 CKSL0
0
W
0
W
0
W
0
W
Names of the bits.
Dashes (⎯) indicate
reserved bits.
Possible types of access
R
Read only
W
Write only
Clock select L
R/W Read and write
⎯
See relevant register
description
0
*
*
Counts on external event (TMIF) rising/
falling edge
1
1
1
1
0
0
1
1
0
1
0
1
Internal clock: φ/32
Internal clock: φ/16
Internal clock: φ/4
Internal clock: φw/4
Toggle output level L
0
1
Clock select H
0
*
*
1
0
0
1
0
1
1
1
0
1
1
1
Full name of bit
Descriptions of bit
settings
Set to low level
Set to high level
16-bit mode, counts on TCFL overflow signal
Internal clock: φ/32
Internal clock: φ/16
Internal clock: φ/4
Internal clock: φw/4
* Don't care
Toggle output level H
0
1
Set to low level
Set to high level
Rev. 8.00 Mar. 09, 2010 Page 551 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
FLMCR1—Flash Memory Control Register 1
Bit
H'F020
Flash Memory
7
6
5
4
3
2
1
0
⎯
SWE
ESU
PSU
EV
PV
E
P
Initial value
0
0
0
0
0
0
0
0
Read/Write
⎯
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Program
0
Program mode cleared (initial value)
1
Transition to program mode
[Setting condition]
When SWE = 1 and PSU = 1
Erase
0
Erase mode cleared (initial value)
1
Transition to erase mode
[Setting condition]
When SWE = 1 and ESU = 1
Program-Verify
0
Program-verify mode cleared (initial value)
1
Transition to program-verify mode
[Setting condition]
When SWE = 1
Erase-Verify
0
Erase-verify mode cleared (initial value)
1
Transition to erase-verify mode
[Setting condition]
When SWE = 1
Program-Setup
0
Program-setup cleared (initial value)
1
Program setup
[Setting condition]
When SWE = 1
Erase-Setup
0
Erase-setup cleared (initial value)
1
Erase setup
[Setting condition]
When SWE = 1
Software write enable bit
0
Writing/erasing disabled (initial value)
1
Writing/erasing enabled
Rev. 8.00 Mar. 09, 2010 Page 552 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
FLMCR2—Flash Memory Control Register 2
Bit
H'F021
Flash Memory
7
6
5
4
3
2
1
0
FLER
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Flash memory error
Note: A write to FLMCR2 is prohibited.
FLPWCR—Flash Memory Power Control Register
Bit
H'F022
Flash Memory
7
6
5
4
3
2
1
0
PDWND
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Power-down Disable
0 When the system transits to sub-active mode,
the flash memory changes to low-power mode
1 When the system transits to sub-active mode,
the flash memory changes to normal mode
Rev. 8.00 Mar. 09, 2010 Page 553 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
EBR—Erase Block Register
Bit
H'F023
Flash Memory
7
6
5
4
3
2
1
0
⎯
⎯
⎯
EB4
EB3
EB2
EB1
EB0
Initial value
0
0
0
0
0
0
0
0
Read/Write
⎯
⎯
⎯
R/W
R/W
R/W
R/W
R/W
Blocks 4 to 0
0 When a block of EB4 to EB0 is not selected (initial value)
1 When a block of EB4 to EB0 is selected
Note: Set the bit of EBR to H'00 when erasing.
FENR—Flash Memory Enable Register
Bit
H'F02B
Flash Memory
7
6
5
4
3
2
1
0
FLSHE
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Flash Memory Control Register Enable
0 The flash memory control register cannot be accessed
1 The flash memory control register can be accessed
Rev. 8.00 Mar. 09, 2010 Page 554 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
LVDCR—Low-Voltage Detection Control Register
H'86
Note: This register is implemented on the H8/38124 Group only.
Bit
7
6
⎯
Initial value
LVDE
0*
Read/Write
R/W
R/W
5
3
4
LVDC
0
R/W
R/W
R/W
1
0
LVDDE
LVDUE
0
0
R/W
R/W
2
VINTDSEL VINTUSEL LVDSEL LVDRE
0
0
0*
0*
R/W
Voltage Rise Interrupt Enable
0 Voltage rise interrupt requests disabled (initial value)
1 Voltage rise interrupt requests enabled
Voltage Drop Interrupt Enable
0 Voltage drop interrupt requests disabled (initial value)
1 Voltage drop interrupt requests enabled
LVDR Enable
0 LVDR resets disabled
1 LVDR resets enabled
(initial value)
LVDR Detection Level Select
0 Reset detection voltage 2.3 V (typ.)
1 Reset detection voltage 3.3 V (typ.)
(initial value)
Power Supply Rise (LVDU) Detection Level External Input Select
0 LVDU detection level generated by on-chip ladder resistor (initial value)
1 LVDU detection level input to extU pin
Power Supply Drop (LVDD) Detection Level External Input Select
0 LVDD detection level generated by on-chip ladder resistor (initial value)
1 LVDD detection level input to extD pin
LVD Enable
0 Low-voltage detection circuit not used (standby status) (initial value)
1 Low-voltage detection circuit use
Note: * These bits are not initialized by resets trigged by LVDR. They are initialized by
power-on resets and watchdog timer resets.
Rev. 8.00 Mar. 09, 2010 Page 555 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
LVDSR—Low-Voltage Detection Status Register
H'87
Note: This register is implemented on the H8/38124 Group only.
Bit
LVDC
7
6
5
4
3
2
1
0
⎯
⎯
⎯
VREFSEL
⎯
Initial value
OVF
0*
0
0
0
0
0
LVDDF
0*
LVDUF
0*
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LVD Power Supply Voltage Rise Flag
0 [Clearing condition]
(initial v alue)
When 0 is written after reading 1
1 [Setting condition]
When the power supply voltage drops below
Vint(D) while the LVDUE bit in LVDCR is set
to 1, and it rises above Vint(U) before
dropping below Vreset1
LVD Power Supply Voltage Drop Flag
(initial value)
0 [Clearing condition]
When 0 is written after reading 1
1 [Setting condition]
When the power supply voltage drops below Vint(D)
Reference Voltage External Input Select
0 The on-chip circuit is used to generate the reference
voltage
(initial value)
1 The reference voltage is input to the Vref pin from
an external source
LVD Reference Voltage Stabilized Flag
(initial value)
0 [Clearing condition]
When 0 is written after reading 1
1 [Setting condition]
When the low-voltage detection counter (LVDCNT) overflows
Note: * These bits initialized by resets trigged by LVDR.
Rev. 8.00 Mar. 09, 2010 Page 556 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
ECPWCRH—Event Counter PWM Compare Register H H'8C
Bit
7
6
5
4
3
AEC
2
1
0
ECPWCRH7 ECPWCRH6 ECPWCRH5 ECPWCRH4 ECPWCRH3 ECPWCRH2 ECPWCRH1 ECPWCRH0
Initial value
R/W
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Sets event counter PWM waveform conversion period
ECPWCRL—Event Counter PWM Compare Register L
Bit
7
6
5
4
H'8D
3
AEC
2
1
0
ECPWCRL7 ECPWCRL6 ECPWCRL5 ECPWCRL4 ECPWCRL3 ECPWCRL2 ECPWCRL1 ECPWCRL0
Initial value
R/W
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Sets event counter PWM waveform conversion period
ECPWDRH—Event Counter PWM Data Register H
Bit
7
6
5
4
H'8E
3
AEC
2
1
0
ECPWDRH7 ECPWDRH6 ECPWDRH5 ECPWDRH4 ECPWDRH3 ECPWDRH2 ECPWDRH1 ECPWDRH0
Initial value
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
Controls event counter PWM waveform generator data
ECPWDRL—Event Counter PWM Data Register L
Bit
7
6
5
4
H'8F
3
AEC
2
1
0
ECPWDRL7 ECPWDRL6 ECPWDRL5 ECPWDRL4 ECPWDRL3 ECPWDRL2 ECPWDRL1 ECPWDRL0
Initial value
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
Controls event counter PWM waveform generator data
Rev. 8.00 Mar. 09, 2010 Page 557 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
WEGR—Wakeup Edge Select Register
Bit
7
6
5
H'90
4
3
System Control
2
1
0
WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WKPn Edge Selected
0
WKPn pin falling edge detected
1
WKPn pin rising edge detected
(n = 7 to 0)
Rev. 8.00 Mar. 09, 2010 Page 558 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
SPCR—Serial Port Control Register
Bit
H'91
7
6
5
4
3
SCI3
2
1
0
⎯
⎯
SPC32
⎯
⎯
⎯
Initial value
1
1
0
⎯
0
0
⎯
⎯
Read/Write
⎯
⎯
R/W
W
R/W
R/W
W
W
SCINV3 SCINV2
RXD32 Pin Input Data Inversion Switch
0
1
RXD32 input data is not inverted
RXD32 input data is inverted
TXD32 Pin Output Data Inversion Switch
0
1
TXD32 output data is not inverted
TXD32 output data is inverted
P42/TXD32 Pin Function Switch
0
1
Function as P42 I/O pin
Function as TXD32 output pin
Rev. 8.00 Mar. 09, 2010 Page 559 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
AEGSR—Input Pin Edge Select Register
5
6
7
Bit
H'92
3
4
AHEGS1 AHEGS0 ALEGS1 ALEGS0 AIEGS1
AEC
2
1
AIEGS0 ECPWME
0
⎯
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Event Counter PWM Enable/Disable,
IRQAEC Select/Deselect
0
1
AEC PWM halted, IRQAEC selected
AEC PWM operation enabled, IRQAEC deselected
IRQAEC Edge Select
Bit 3
Bit 2
Description
AIEGS1 AIEGS0
Falling edge on IRQAEC pin is sensed
0
0
Rising edge on IRQAEC pin is sensed
0
1
Both edges on IRQAEC pin are sensed
1
0
Use prohibited
1
1
AEC Edge Select L
Bit 5
Bit 4
ALEGS1 ALEGS0
0
0
0
1
1
0
1
1
Description
Falling edge on AEVL pin is sensed
Rising edge on AEVL pin is sensed
Both edges on AEVL pin are sensed
Use prohibited
AEC Edge Select H
Bit 7
Bit 6
AHEGS1 AHEGS0
0
0
0
1
1
0
1
1
Description
Falling edge on AEVH pin is sensed
Rising edge on AEVH pin is sensed
Both edges on AEVH pin are sensed
Use prohibited
Rev. 8.00 Mar. 09, 2010 Page 560 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
ECCR—Event Counter Control Register
Bit
H'94
7
6
5
4
ACKH1
ACKH0
ACKL1
ACKL0
3
AEC
1
2
PWCK2 PWCK1 PWCK0
0
⎯
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Event Counter PWM Clock Select
Bit 3
Bit 2
Bit 1
PWCK2 PWCK1 PWCK0
φ/2
0
0
0
φ/4
0
0
1
φ/8
0
1
0
φ/16
0
1
1
φ/32
1
*
0
φ/64
1
*
1
Description
*: Don't care
AEC Clock Select L
Bit 5
Bit 4
Description
ACKL1 ACKL0
AEVL pin input
0
0
φ/2
0
1
φ/4
1
0
φ/8
1
1
AEC Clock Select H
Bit 7
Bit 6
Description
ACKH1 ACKH0
AEVH pin input
0
0
φ/2
0
1
φ/4
1
0
φ/8
1
1
Rev. 8.00 Mar. 09, 2010 Page 561 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
ECCSR—Event Counter Control/Status Register
Bit
H'95
AEC
7
6
5
4
3
2
1
0
OVH
OVL
⎯
CH2
CUEH
CUEL
CRCH
CRCL
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Counter Reset Control L
0 ECL is reset
1 ECL reset is cleared
and count-up function
is enabled
Counter Reset Control H
0 ECH is reset
1 ECH reset is cleared and
count-up function is enabled
Count-up Enable L
0 ECL event clock input is disabled.
ECL value is held
1 ECL event clock input is enabled
Count-up Enable H
0 ECH event clock input is disabled.
ECH value is held
1 ECH event clock input is enabled
Channel Select
0 ECH and ECL are used together as a singlechannel 16-bit event counter
1
ECH and ECL are used as two independent
8-bit event counter channels
Counter Overflow L
0 ECL has not overflowed
1 ECL has overflowed
Counter Overflow H
0 ECH has not overflowed
1 ECH has overflowed
Rev. 8.00 Mar. 09, 2010 Page 562 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
ECH—Event Counter H
Bit
H'96
AEC
7
6
5
4
3
2
1
0
ECH7
ECH6
ECH5
ECH4
ECH3
ECH2
ECH1
ECH0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Count value
Note: ECH and ECL can also be used as the upper and lower halves, respectively, of a 16-bit
timer counter (EC).
ECL—Event Counter L
Bit
H'97
AEC
7
6
5
4
3
2
1
0
ECL7
ECL6
ECL5
ECL4
ECL3
ECL2
ECL1
ECL0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Count value
Note: ECH and ECL can also be used as the upper and lower halves, respectively, of a 16-bit
timer counter (EC).
Rev. 8.00 Mar. 09, 2010 Page 563 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
SMR—Serial Mode Register
Bit
H'A8
SCI3
7
6
5
4
3
2
1
0
COM
CHR
PE
PM
STOP
MP
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock Select
0 0 φ clock
0 1 φw/2 clock
1 0 φ/16 clock
1 1 φ/64 clock
5 Bit Communication
0 5 bits communication disabled
1 5 bits communication enabled
Stop Bit Length
0 1 stop bit
1 2 stop bits
Parity Mode
0 Even parity
1 Odd parity
Parity Enable
0 Parity bit addition and checking disabled
1 Parity bit addition and checking enabled
Character Length
0 8-bit data/5-bit data
1 7-bit data/5-bit data
Communication Mode
0 Asynchronous mode
1 Synchronous mode
Rev. 8.00 Mar. 09, 2010 Page 564 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
BRR—Bit Rate Register
Bit
H'A9
SCI3
7
6
5
4
3
2
1
0
BRR7
BRR6
BRR5
BRR4
BRR3
BRR2
BRR1
BRR0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Serial transmit/receive bit rate
Rev. 8.00 Mar. 09, 2010 Page 565 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
SCR3—Serial Control Register 3
Bit
H'AA
SCI3
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
⎯
TEIE
CKE1
CKE0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock Enable
Bit 1
CKE1
0
Bit 0
CKE0
0
0
1
1
0
1
1
Communication Mode
Asynchronous
Synchronous
Asynchronous
Synchronous
Asynchronous
Synchronous
Asynchronous
Synchronous
Description
Clock Source
SCK32 Pin Function
I/O port
Internal clock
Internal clock
Serial clock output
Internal clock
Clock output
Reserved (Do not specify this combination)
External clock
Clock input
External clock
Serial clock input
Reserved (Do not specify this combination)
Reserved (Do not specify this combination)
Transmit End Interrupt Enable
0
1
Transmit end interrupt request (TEI) disabled
Transmit end interrupt request (TEI) enabled
Receive Enable
0
Receive operation disabled (RXD32 pin is I/O port)
1
Receive operation enabled (RXD32 pin is receive data pin)
Transmit Enable
0
Transmit operation disabled (TXD32 pin is I/O port)
1
Transmit operation enabled (TXD32 pin is transmit data pin)
Receive Interrupt Enable
0
Receive data full interrupt request (RXI) and receive error interrupt request (ERI) disabled
1
Receive data full interrupt request (RXI) and receive error interrupt request (ERI) enabled
Transmit Interrupt Enable
0
Transmit data empty interrupt request (TXI) disabled
1
Transmit data empty interrupt request (TXI) enabled
Rev. 8.00 Mar. 09, 2010 Page 566 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
TDR—Transmit Data Register
Bit
H'AB
SCI3
7
6
5
4
3
2
1
0
TDR7
TDR6
TDR5
TDR4
TDR3
TDR2
TDR1
TDR0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data for transfer to TSR
Rev. 8.00 Mar. 09, 2010 Page 567 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
SSR—Serial Status Register
Bit
H'AC
SCI3
7
6
5
4
3
2
1
0
TDRE
RDRF
OER
FER
PER
TEND
⎯
⎯
Initial value
1
0
0
0
0
1
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R
R
R/W
Transmit End
0
Transmission in progress
[Clearing conditions] · After reading TDRE = 1, cleared by writing 0 to TDRE
· When data is written to TDR by an instruction
1
Transmission ended
[Setting conditions]
· When bit TE in serial control register3 (SCR3) is cleared to 0
· When bit TDRE is set to 1 when the last bit of a transmit character is sent
Parity Error
0
Reception in progress or completed normally
[Clearing condition] After reading PER = 1, cleared by writing 0 to PER
1
A parity error has occurred during reception
[Setting condition] When the number of 1 bits in the receive data plus parity bit does not match the parity
designated by the parity mode bit (PM) in the serial mode register (SMR)
Framing Error
0
Reception in progress or completed normally
[Clearing condition] After reading FER = 1, cleared by writing 0 to FER
1
A framing error has occurred during reception
[Setting condition] When the stop bit at the end of the receive data is checked for a value of 1 at completion of
reception, and the stop bit is 0
Overrun Error
0
Reception in progress or completed
[Clearing condition] After reading OER = 1, cleared by writing 0 to OER
1
An overrun error has occurred during reception
[Setting condition] When the next serial reception is completed with RDRF set to 1
Receive Data Register Full
0
There is no receive data in RDR
[Clearing conditions] · After reading RDRF = 1, cleared by writing 0 to RDRF
· When RDR data is read by an instruction
1
There is receive data in RDR
[Setting condition] When reception ends normally and receive data is transferred from RSR to RDR
Transmit Data Register Empty
0
Transmit data written in TDR has not been transferred to TSR
[Clearing conditions] · After reading TDRE = 1, cleared by writing 0 to TDRE
· When data is written to TDR by an instruction
1
Transmit data has not been written to TDR, or transmit data written in TDR has been transferred to TSR
[Setting conditions] · When bit TE in serial control register3 (SCR3) is cleared to 0
· When data is transferred from TDR to TSR
Note: * Only a write of 0 for flag clearing is possible.
Rev. 8.00 Mar. 09, 2010 Page 568 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
RDR—Receive Data Register
Bit
H'AD
SCI3
7
6
5
4
3
2
1
0
RDR7
RDR6
RDR5
RDR4
RDR3
RDR2
RDR1
RDR0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Serial receiving data are stored
TMA—Timer Mode Register A
Bit
H'B0
Timer A
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
TMA3
TMA2
TMA1
TMA0
Initial value
⎯
⎯
⎯
1
0
0
0
0
Read/Write
W
W
W
⎯
R/W
R/W
R/W
R/W
Internal Clock Select
Prescaler and Divider Ratio
TMA3 TMA2 TMA1 TMA0 or Overflow Period
0
0
0
φ/8192
0
PSS
1
φ/4096
PSS
φ/2048
PSS
1
0
φ/512
PSS
1
1
0
0
φ/256
PSS
1
φ/128
PSS
φ/32
1
0
PSS
φ/8
1
PSS
0
0
0
1s
1
PSW
1
0.5 s
PSW
0.25 s
1
0
PSW
0.03125 s
1
PSW
1
0
0
PSW and TCA are reset
1
1
0
1
Function
Interval
timer
Clock time
base
(when
using
32.768 kHz)
Rev. 8.00 Mar. 09, 2010 Page 569 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
TCA—Timer Counter A
Bit
H'B1
Timer A
7
6
5
4
3
2
1
0
TCA7
TCA6
TCA5
TCA4
TCA3
TCA2
TCA1
TCA0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Count value
Rev. 8.00 Mar. 09, 2010 Page 570 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
TCSRW—Timer Control/Status Register W
Bit
Initial value
Read/Write
7
6
B6WI
TCWE
1
0
R
R/(W)*1
H'B2
5
4
B4WI TCSRWE
1
0
R
R/(W)*1
Watchdog Timer
3
2
1
0
B2WI
BOWI
WRST
1
WDON
0 *2
1
0
R
R/(W)*1
R
R/(W)*1
Watchdog Timer Reset
0
Clearing conditions:
Reset by RES pin
When TCSRWE = 1, and 0 is written
in both B0WI and WRST
1
Setting condition:
When TCW overflows and an internal
reset signal is generated
Bit 0 Write Inhibit
0
Bit 0 is write-enabled
1
Bit 0 is write-disabled
Watchdog Timer On
0
Watchdog timer operation is disabled
Clearing conditions:
Reset*2, or 0 is written in both B2WI and WDON
while TCSRWE = 1
1
Watchdog timer operation is enabled
Setting condition:
0 is written in B2WI and 1 is written in WDON
while TCSRWE = 1
Bit 2 Write Inhibit
0
Bit 2 is write-enabled
1
Bit 2 is write-disabled
Timer Control/Status Register W Write Enable
0
Data cannot be written to bits 2 and 0
1
Data can be written to bits 2 and 0
Bit 4 Write Inhibit
0
Bit 4 is write-enabled
1
Bit 4 is write-disabled
Timer Counter W Write Enable
0
8-bit data cannot be written to TCW
1
8-bit data can be written to TCW
Bit 6 Write Inhibit
0
Bit 6 is write-enabled
1
Bit 6 is write-disabled
Notes: 1. Write is permitted only under certain conditions.
2. 1 on the H8/38124 Group.
Rev. 8.00 Mar. 09, 2010 Page 571 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
TCW—Timer Counter W
Bit
H'B3
Watchdog Timer
7
6
5
4
3
2
1
0
TCW7
TCW6
TCW5
TCW4
TCW3
TCW2
TCW1
TCW0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Count value
TMC—Timer Mode Register C
Bit
H'B4
Timer C
7
6
5
4
3
2
1
0
TMC7
TMC6
TMC5
⎯
⎯
TMC2
TMC1
TMC0
Initial value
0
0
0
1
1
0
0
0
Read/Write
R/W
R/W
R/W
⎯
⎯
R/W
R/W
R/W
Clock Select
0 0 0 Internal clock: φ/8192
1 Internal clock: φ/2048
1 0 Internal clock: φ/512
1 Internal clock: φ/64
1 0 0 Internal clock: φ/16
1 Internal clock: φ/4
1 0 Internal clock: φW/4
1 External event (TMIC):
rising or falling edge
Counter Up/Down Control
0 0 TCC is an up-counter
0 1 TCC is a down-counter
1 * Hardware control of TCC up/down operation by UD pin input
UD pin input high: Down-counter
UD pin input low: Up-counter
*: Don't care
Auto-Reload Function Select
0 Interval timer function selected
1 Auto-reload function selected
Rev. 8.00 Mar. 09, 2010 Page 572 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
TCC—Timer Counter C
Bit
H'B5
Timer C
7
6
5
4
3
2
1
0
TCC7
TCC6
TCC5
TCC4
TCC3
TCC2
TCC1
TCC0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Count value
Note: TCC is allocated to the same address as TLC. In a read, the TCC value is returned.
TLC—Timer Load Register C
Bit
H'B5
Timer C
7
6
5
4
3
2
1
0
TLC7
TLC6
TLC5
TLC4
TLC3
TLC2
TLC1
TLC0
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Reload value
Note: TLC is allocated to the same address as TCC. In a write, the value is written to TLC.
Rev. 8.00 Mar. 09, 2010 Page 573 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
TCRF—Timer Control Register F
Bit
H'B6
Timer F
7
6
5
4
3
2
1
0
TOLH
CKSH2
CKSH1
CKSH0
TOLL
CKSL2
CKSL1
CKSL0
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Clock Select L
0 Except
for 11
Counting on external event (TMIF)
rising/falling edge
0
1
1
1
1
Do not specify this combination
Internal clock φ/32
Internal clock φ/16
Internal clock φ/4
Internal clock φw/4
1
0
0
1
1
Toggle Output Level L
0
1
Low level
High level
Clock Select H
0 Except
for 11
16-bit mode, counting on TCFL
overflow signal
0
1
1
1
1
0
0
1
1
0
1
0
1
1
1
Do not specify this combination
Internal clock φ/32
Internal clock φ/16
Internal clock φ/4
Internal clock φw/4
Toggle Output Level H
0
1
Low level
High level
Rev. 8.00 Mar. 09, 2010 Page 574 of 658
REJ09B0042-0800
1
0
1
0
1
Appendix B Internal I/O Registers
TCSRF—Timer Control/Status Register F
Bit
H'B7
Timer F
7
6
5
4
3
2
1
0
OVFH
CMFH
OVIEH
CCLRH
OVFL
CMFL
OVIEL
CCLRL
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/W
R/W
R/(W)*
R/(W)*
R/W
R/W
Counter Clear L
0
TCFL clearing by compare match is disabled
1
TCFL clearing by compare match is enabled
Timer Overflow Interrupt Enable L
0
TCFL overflow interrupt request is disabled
1
TCFL overflow interrupt request is enabled
Compare Match Flag L
0
Clearing condition:
After reading CMFL = 1, cleared by writing 0 to CMFL
1
Setting condition:
Set when the TCFL value matches the OCRFL value
Timer Overflow Flag L
0
Clearing condition:
After reading OVFL = 1, cleared by writing 0 to OVFL
1
Setting condition:
Set when TCFL overflows from H'FF to H'00
Counter Clear H
0
16-bit mode: TCF clearing by compare match is disabled
8-bit mode: TCFH clearing by compare match is disabled
1
16-bit mode: TCF clearing by compare match is enabled
8-bit mode: TCFH clearing by compare match is enabled
Timer Overflow Interrupt Enable H
0
TCFH overflow interrupt request is disabled
1
TCFH overflow interrupt request is enabled
Compare Match Flag H
0
Clearing condition:
After reading CMFH = 1, cleared by writing 0 to CMFH
1
Setting condition:
Set when the TCFH value matches the OCRFH value
Timer Overflow Flag H
0
Clearing condition:
After reading OVFH = 1, cleared by writing 0 to OVFH
1
Setting condition:
Set when TCFH overflows from H'FF to H'00
Note: * Bits 7, 6, 3, and 2 can only be written with 0, for flag clearing.
Rev. 8.00 Mar. 09, 2010 Page 575 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
TCFH—8-Bit Timer Counter FH
Bit
H'B8
Timer F
7
6
5
4
3
2
1
0
TCFH7
TCFH6
TCFH5
TCFH4
TCFH3
TCFH2
TCFH1
TCFH0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Count value
Note: TCFH and TCFL can also be used as the upper and lower halves, respectively,
of a 16-bit timer counter (TCF).
TCFL—8-Bit Timer Counter FL
Bit
H'B9
Timer F
7
6
5
4
3
2
1
0
TCFL7
TCFL6
TCFL5
TCFL4
TCFL3
TCFL2
TCFL1
TCFL0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Count value
Note: TCFH and TCFL can also be used as the upper and lower halves, respectively,
of a 16-bit timer counter (TCF).
OCRFH—Output Compare Register FH
Bit
7
6
5
H'BA
4
3
2
Timer F
1
0
OCRFH7 OCRFH6 OCRFH5 OCRFH4 OCRFH3 OCRFH2 OCRFH1 OCRFH0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: OCRFH and OCRFL can also be used as the upper and lower halves, respectively,
of a 16-bit output compare register (OCRF).
Rev. 8.00 Mar. 09, 2010 Page 576 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
OCRFL—Output Compare Register FL
Bit
7
6
5
H'BB
4
3
Timer F
2
1
0
OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: OCRFH and OCRFL can also be used as the upper and lower halves, respectively,
of a 16-bit output compare register (OCRF).
Rev. 8.00 Mar. 09, 2010 Page 577 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
TMG—Timer Mode Register G
Bit
Initial value
Read/Write
H'BC
Timer G
7
6
5
4
3
2
1
0
OVFH
OVFL
OVIE
IIEGS
CCLR1
CCLR0
CKS1
CKS0
0
R/(W)*
0
R/(W)*
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Clock Select
0 0 Internal clock: counting on φ/64
1 Internal clock: counting on φ/32
1 0 Internal clock: counting on φ/2
1 Internal clock: counting on φW/4
Counter Clear
0 0 TCG clearing is disabled
1 TCG cleared by falling edge of input capture
input signal
1 0 TCG cleared by rising edge of input capture
input signal
1 TCG cleared by both edges of input capture
input signal
Input Capture Interrupt Edge Select
0 Interrupt generated on rising edge of input capture
input signal
1 Interrupt generated on falling edge of input capture
input signal
Timer Overflow Interrupt Enable
0 TCG overflow interrupt request is disabled
1 TCG overflow interrupt request is enabled
Timer Overflow Flag L
0 Clearing condition:
After reading OVFL = 1, cleared by writing 0 to OVFL
1 Setting condition:
Set when TCG overflows from H'FF to H'00
Timer Overflow Flag H
0 Clearing condition:
After reading OVFH = 1, cleared by writing 0 to OVFH
1 Setting condition:
Set when TCG overflows from H'FF to H'00
Note: * Bits 7 and 6 can only be written with 0, for flag clearing.
Rev. 8.00 Mar. 09, 2010 Page 578 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
ICRGF—Input Capture Register GF
Bit
7
6
H'BD
5
4
3
Timer G
2
1
0
ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGF0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Stores TCG value at falling edge of input capture signal
ICRGR—Input Capture Register GR
Bit
7
6
H'BE
5
4
3
Timer G
2
1
0
ICRGR7 ICRGR6 ICRGR5 ICRGR4 ICRGR3 ICRGR2 ICRGR1 ICRGR0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Stores TCG value at rising edge of input capture signal
Rev. 8.00 Mar. 09, 2010 Page 579 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
LPCR—LCD Port Control Register
Bit
H'C0
LCD Controller/Driver
7
6
5
4
3
2
1
0
DTS1
DTS0
CMX
⎯
SGS3
SGS2
SGS1
SGS0
Initial value
0
0
0
⎯
0
0
0
0
Read/Write
R/W
R/W
R/W
W
R/W
R/W
R/W
R/W
Segment Driver Select
Bit 3
Bit 2
Bit 1
Function of Pins SEG32 to SEG1
Bit 0
SEG32 to SEG28 to SEG24 to SEG20 to SEG16 to SEG12 to SEG8 to SEG4 to
SGS3 SGS2 SGS1 SGS0
SEG29
SEG25
SEG21
SEG17
SEG13
SEG9
SEG5
SEG1
0
0
0
1
1
0
1
1
0
0
1
1
0
1
0
Port
Port
Port
Port
Port
Port
Port
Port
1
Port
Port
Port
Port
Port
Port
Port
SEG
0
Port
Port
Port
Port
Port
Port
SEG
SEG
1
Port
Port
Port
Port
Port
SEG
SEG
SEG
0
Port
Port
Port
Port
SEG
SEG
SEG
SEG
1
Port
Port
Port
SEG
SEG
SEG
SEG
SEG
0
Port
Port
SEG
SEG
SEG
SEG
SEG
SEG
1
Port
SEG
SEG
SEG
SEG
SEG
SEG
SEG
0
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
1
SEG
SEG
SEG
SEG
SEG
SEG
SEG
Port
0
SEG
SEG
SEG
SEG
SEG
SEG
Port
Port
1
SEG
SEG
SEG
SEG
SEG
Port
Port
Port
0
SEG
SEG
SEG
SEG
Port
Port
Port
Port
1
SEG
SEG
SEG
Port
Port
Port
Port
Port
0
SEG
SEG
Port
Port
Port
Port
Port
Port
1
SEG
Port
Port
Port
Port
Port
Port
Port
Note
(Initial value)
Duty Select, Common Function Select
Bit 7 Bit 6 Bit 5
Duty Cycle Common Drivers
DTS1 DTS0 CMX
0
0
COM1
0
Static
1
COM4 to COM1
0
1
0
COM2 to COM1
1/2 duty
1
COM4 to COM1
0
0
1
COM3 to COM1
1/3 duty
1
COM4 to COM1
0
1
1
COM4 to COM1
1/4 duty
1
Notes
Do not use COM4 to COM2
COM4 to COM2 output the same waveform as COM1
Do not use COM4 and COM3
COM4 outputs the same waveform as COM3 and COM2 outputs the same waveform as COM1
Do not use COM4
Do not use COM4
Rev. 8.00 Mar. 09, 2010 Page 580 of 658
REJ09B0042-0800
⎯
Appendix B Internal I/O Registers
LCR—LCD Control Register
Bit
H'C1
LCD Controller/Driver
7
6
5
4
3
2
1
0
⎯
PSW
ACT
DISP
CKS3
CKS2
CKS1
CKS0
Initial value
1
0
0
0
0
0
0
0
Read/Write
⎯
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Frame Frequency Select
Bit 3 Bit 2 Bit 1 Bit 1
CKS3 CKS2 CKS1 CKS0
0
0
0
1
1
1
1
1
1
1
1
*
*
*
0
0
0
0
1
1
1
1
0
0
1
0
0
1
1
0
0
1
1
Display Data Control
0
1
*
0
1
0
1
0
1
0
1
Operating Clock
φw
φw/2
φw/4
φ/2
φ/4
φ/8
φ/16
φ/32
φ/64
φ/128
φ/256
*: Don't care
0 Blank data is displayed
1 LCD RAM data is displayed
Display Function Activate
0 LCD controller/driver operation halted
1 LCD controller/driver operates
LCD Drive Power Supply On/Off Control
0 LCD drive power supply off
1 LCD drive power supply on
Rev. 8.00 Mar. 09, 2010 Page 581 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
LCR2—LCD Control Register 2
Bit
H'C2
LCD
7
6
5
4
3
2
1
0
LCDAB
⎯
⎯
⎯
CDS3
CDS2
CDS1
CDS0
Initial value
0
1
1
⎯
0
0
0
0
Read/Write
R/W
⎯
⎯
W
R/W
R/W
R/W
R/W
A Waveform/B Waveform Switching Control
0 Drive using A waveform
1 Drive using B waveform
Removal of Split-Resistance Control
CDS3
0
CDS2 CDS1 CDS0
1
1
1
Other than the above
Split-resistance condition
Split-resistance removed
Split-resistance connected
Note: The removal of split-resistance control is only implemented on the
H8/38124 Group.
LVDCNT—Low-Voltage Detect Counter
H'C3 Low-Voltage Detect Circuit
Note: This register is implemented on the H8/38124 Group only.
Bit
7
6
5
4
3
2
1
0
CNT7
CNT6
CNT5
CNT4
CNT3
CNT2
CNT1
CNT0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Count value
Rev. 8.00 Mar. 09, 2010 Page 582 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
AMR—A/D Mode Register
Bit
H'C6
A/D Converter
7
6
5
4
3
2
1
0
CKS
TRGE
⎯
⎯
CH3
CH2
CH1
CH0
Initial value
0
0
1
1
0
0
0
0
Read/Write
R/W
R/W
⎯
⎯
R/W
R/W
R/W
R/W
Channel Select
Bit 3 Bit 2 Bit 1
CH3 CH2 CH1
0
0
*
1
0
Bit 0
CH0
1
1
0
0
1
1
1
*
*
0
1
0
1
0
1
0
1
*
Analog Input Channel
No channel selected
AN 0
AN 1
AN 2
AN 3
AN 4
AN 5
AN 6
AN 7
Do not specify this
combination
*: Don't care
External Trigger Select
0 Disables start of A/D conversion by external trigger
1 Enables start of A/D conversion by rising or falling edge
of external trigger at pin ADTRG
Clock Select
Bit 7
CKS Conversion Period
0
62/φ
1
31/φ
Conversion Time
φ = 1 MHz φ = 5 MHz φ = 10 MHz*2
62 μs
31 μs
12.4 μs
⎯*1
6.2 μs
⎯*1
Notes: 1. Except for the H8/38124 Group, operation cannot be
guaranteed if the conversion time is less than 12.4 µs.
Make sure to select a setting that gives a conversion time of
12.4 µs or more in such cases. For the H8/38124 Group select
a setting that gives a conversion time of 6.2 µs or more.
2. H8/38124 Group only.
Rev. 8.00 Mar. 09, 2010 Page 583 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
ADRRH—A/D Result Register H
ADRRL—A/D Result Register L
H'C4
H'C5
A/D Converter
ADRRH
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
ADR9
ADR8
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R
R
R
R
R
R
R
R
A/D conversion result
ADRRL
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
ADR1
ADR0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Undefined Undefined
R
R
A/D conversion result
ADSR—A/D Start Register
Bit
H'C7
A/D Converter
7
6
5
4
3
2
1
0
ADSF
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Initial value
0
1
1
1
1
1
1
1
Read/Write
R/W
⎯
⎯
⎯
⎯
⎯
⎯
⎯
A/D Start Flag
0 Read Indicates completion of A/D conversion
Write Stops A/D conversion
1 Read Indicates A/D conversion in progress
Write Starts A/D conversion
Rev. 8.00 Mar. 09, 2010 Page 584 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
PMR1—Port Mode Register 1
Bit
H'C8
I/O Port
7
6
5
4
3
2
1
0
IRQ3
⎯
⎯
IRQ4
TMIG
⎯
⎯
⎯
Initial value
0
1
⎯
0
0
⎯
1
⎯
Read/Write
R/W
⎯
W
R/W
R/W
W
⎯
W
P13/TMIG Pin Function Switch
0 Functions as P13 I/O pin
1 Functions as TMIG input pin
P14/IRQ4/ADTRG Pin Function Switch
0 Functions as P14 I/O pin
1 Functions as IRQ4/ADTRG input pin
P17/IRQ3/TMIF Pin Function Switch
0 Functions as P17 I/O pin
1 Functions as IRQ3/TMIF input pin
Rev. 8.00 Mar. 09, 2010 Page 585 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
PMR2—Port Mode Register 2
Bit
H'C9
I/O Port
7
6
5
4
3
2
1
0
⎯
⎯
POF1
⎯
⎯
WDCKS
NCS
IRQ0
Initial value
1
1
0
1
1
0
0
0
Read/Write
⎯
⎯
R/W
⎯
⎯
R/W
R/W
R/W
P43/IRQ0 Pin Function Switch
0 Functions as P43 I/O pin
1 Functions as IRQ0 input pin
TMIG Noise Canceller Select
0 Noise cancellation function not used
1 Noise cancellation function used
Watchdog Timer Switch
0 Selects φ8192*
1 Selects φW/32
P35 Pin Output Buffer PMOS On/Off Control
0 CMOS output
1 NMOS open-drain output
Note: * On the H8/38124 Group the clock source can be selected using the TMW register.
Rev. 8.00 Mar. 09, 2010 Page 586 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
PMR3—Port Mode Register 3
Bit
H'CA
I/O Port
7
6
5
4
3
2
1
0
AEVL
AEVH
⎯
⎯
⎯
TMOFH
TMOFL
UD
Initial value
0
0
⎯
⎯
⎯
0
0
0
Read/Write
R/W
R/W
W
W
W
R/W
R/W
R/W
P30/UD Pin Function Switch
0 Functions as P30 I/O pin
1 Functions as UD input pin
P31/TMOFL Pin Function Switch
0 Functions as P31 I/O pin
1 Functions as TMOFL output pin
P32/TMOFH Pin Function Switch
0 Functions as P32 I/O pin
1 Functions as TMOFH output pin
P36/AEVH Pin Function Switch
0 Functions as P36 I/O pin
1 Functions as AEVH input pin
P37/AEVL Pin Function Switch
0 Functions as P37 I/O pin
1 Functions as AEVL input pin
Rev. 8.00 Mar. 09, 2010 Page 587 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
PMR5—Port Mode Register 5
Bit
H'CC
I/O Port
7
6
5
4
3
2
1
0
WKP7
WKP6
WKP5
WKP4
WKP3
WKP2
WKP1
WKP0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P5n/WKPn/SEGn+1 Pin Function Switch
0 Functions as P5n I/O pin
1 Functions as WKPn input pin
(n = 7 to 0)
PWCR2—PWM2 Control Register
Bit
H'CD
7
6
5
4
3
⎯
⎯
⎯
⎯
⎯
Initial value
1
1
1
1
1
Read/Write
⎯
⎯
⎯
⎯
⎯
2
10-Bit PWM
1
0
PWCR22 PWCR21 PWCR20
0
0
0 *2
R/W
W
W
Clock Select
0
0
1
1
0
1
The input clock is φ (tφ*1 = 1/φ) The conversion period is 512/φ,
with a minimum modulation width of 1/2φ
The input clock is φ/2 (tφ*1 = 2/φ) The conversion period is 1,024/φ,
with a minimum modulation width of 1/φ
The input clock is φ/4 (tφ*1 = 4/φ) The conversion period is 2,048/φ,
with a minimum modulation width of 2/φ
The input clock is φ/8 (tφ*1 = 8/φ) The conversion period is 4,096/φ,
with a minimum modulation width of 4/φ
PWH Output Select (H8/38124 Group only)
0 10-bit PWM
1 Event counter PWM
Notes: 1. tφ: Period of PWM2 input clock
2. 1 on products other than the H8/38124 Group
Rev. 8.00 Mar. 09, 2010 Page 588 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
PWDRU2—PWM2 Data Register U
H'CE
10-Bit PWM
7
6
5
4
3
2
⎯
⎯
⎯
⎯
⎯
⎯
Initial value
1
1
1
1
1
1
0
0
Read/Write
⎯
⎯
⎯
⎯
⎯
⎯
W
W
Bit
0
1
PWDRU21 PWDRU20
Upper 2 bits of PWM2 waveform generation data
PWDRL2—PWM2 Data Register L
Bit
7
6
H'CF
5
4
3
10-Bit PWM
2
1
0
PWDRL27 PWDRL26 PWDRL25 PWDRL24 PWDRL23 PWDRL22 PWDRL21 PWDRL20
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Lower 8 bits of PWM2 waveform generation data
Rev. 8.00 Mar. 09, 2010 Page 589 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
PWCR1—PWM1 Control Register
Bit
H'D0
7
6
5
4
3
⎯
⎯
⎯
⎯
⎯
Initial value
1
1
1
1
1
Read/Write
⎯
⎯
⎯
⎯
⎯
10-Bit PWM
2
1
PWCR12 PWCR11 PWCR10
0
0
0* 2
R/W
W
Clock Select
0 The input clock is φ (tφ*1 = 1/φ)
The conversion period is 512/φ, with a minimum modulation width of 1/2φ
The input clock is φ/2 (tφ*1 = 2/φ)
The conversion period is 1,024/φ, with a minimum modulation width of 1/φ
1 The input clock is φ/4 (tφ*1 = 4/φ)
The conversion period is 2,048/φ, with a minimum modulation width of 2/φ
The input clock is φ/8 (tφ*1 = 8/φ)
The conversion period is 4,096/φ, with a minimum modulation width of 4/φ
PWH Output Select (H8/38124 Group only)
0 10-bit PWM
1 Event counter PWM
Notes: 1. tφ: Period of PWM1 input clock
2. 1 on products other than the H8/38124 Group
Rev. 8.00 Mar. 09, 2010 Page 590 of 658
REJ09B0042-0800
0
W
Appendix B Internal I/O Registers
PWDRU1—PWM1 Data Register U
Bit
H'D1
10-Bit PWM
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
⎯
Initial value
1
1
1
1
1
1
0
0
Read/Write
⎯
⎯
⎯
⎯
⎯
⎯
W
W
PWDRU11 PWDRU10
Upper 2 bits of data for generating PWM1 waveform
PWDRL1—PWM1 Data Register L
Bit
7
6
H'D2
5
4
3
10-Bit PWM
2
1
0
PWDRL17 PWDRL16 PWDRL15 PWDRL14 PWDRL13 PWDRL12 PWDRL11 PWDRL10
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Lower 8 bits of data for generating PWM1 waveform
PDR1—Port Data Register 1
Bit
H'D4
I/O Ports
7
6
5
4
3
2
1
0
P17
P16*
⎯
P14
P13
⎯
⎯
⎯
Initial value
0
0
⎯
0
0
⎯
⎯
⎯
Read/Write
R/W
R/W
⎯
R/W
R/W
⎯
⎯
⎯
Data for port 1 pins
Note: * P16 is not equipped with H8/38124 Group.
PDR3—Port Data Register 3
Bit
H'D6
I/O Ports
7
6
5
4
3
2
1
0
P3 7
P36
P35
P34
P33
P32
P31
P30
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data for port 3 pins
Rev. 8.00 Mar. 09, 2010 Page 591 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
PDR4—Port Data Register 4
Bit
H'D7
I/O Ports
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
P43
P42
P41
P40
Initial value
1
1
1
1
1
0
0
0
Read/Write
⎯
⎯
⎯
⎯
R
R/W
R/W
R/W
Data for port 4 pins
Reads P43 state
PDR5—Port Data Register 5
Bit
H'D8
I/O Ports
7
6
5
4
3
2
1
0
P5 7
P56
P55
P54
P53
P52
P51
P50
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data for port 5 pins
PDR6—Port Data Register 6
Bit
H'D9
I/O Ports
7
6
5
4
3
2
1
0
P6 7
P66
P65
P64
P63
P62
P61
P60
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data for port 6 pins
PDR7—Port Data Register 7
Bit
H'DA
I/O Ports
7
6
5
4
3
2
1
0
P7 7
P76
P75
P74
P73
P72
P71
P70
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data for port 7 pins
Rev. 8.00 Mar. 09, 2010 Page 592 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
PDR8—Port Data Register 8
Bit
H'DB
I/O Ports
7
6
5
4
3
2
1
0
P87
P86
P85
P84
P83
P82
P81
P80
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data for port 8 pins
PDR9—Port Data Register 9
Bit
H'DC
I/O Ports
7
6
5
4
3
2
1
0
⎯
⎯
P95
P94
P93
P92
P91
P90
Initial value
1
1
1
1
1
1
1
1
Read/Write
⎯
⎯
R/W
R/W
R/W
R/W
R/W
R/W
Data for port 9 pins
PDRA—Port Data Register A
Bit
H'DD
I/O Ports
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
PA3
PA2
PA1
PA0
Initial value
1
1
1
1
0
0
0
0
Read/Write
⎯
⎯
⎯
⎯
R/W
R/W
R/W
R/W
Data for port A pins
PDRB—Port Data Register B
Bit
Read/Write
H'DE
I/O Ports
7
6
5
4
3
2
1
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
R
R
R
R
R
R
R
R
Read port B pin states
Rev. 8.00 Mar. 09, 2010 Page 593 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
PUCR1—Port Pull-Up Control Register 1
Bit
7
6
H'E0
5
PUCR17 PUCR16*
I/O Ports
3
4
2
1
0
⎯
⎯
⎯
Initial value
0
0
⎯
0
0
⎯
⎯
⎯
Read/Write
R/W
R/W
W
R/W
R/W
W
W
W
⎯
PUCR14 PUCR13
Port 1 Input Pull-up MOS Control
0 Input pull-up MOS is off
1 Input pull-up MOS is on
Note: When the PCR1 specification is 0.
(Input port specification)
Note: * PUCR16 is not equipped with H8/38124 Group.
PUCR3—Port Pull-Up Control Register 3
Bit
7
6
5
H'E1
4
3
I/O Ports
2
0
1
PUCR3 7 PUCR36 PUCR35 PUCR34 PUCR33 PUCR32 PUCR31 PUCR3 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 3 Input Pull-up MOS Control
0 Input pull-up MOS is off
1 Input pull-up MOS is on
Note: When the PCR3 specification is 0.
(Input port specification)
Rev. 8.00 Mar. 09, 2010 Page 594 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
PUCR5—Port Pull-Up Control Register 5
Bit
7
6
5
H'E2
4
3
I/O Ports
2
0
1
PUCR5 7 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 5 Input Pull-up MOS Control
0 Input pull-up MOS is off
1 Input pull-up MOS is on
Note: When the PCR5 specification is 0.
(Input port specification)
PUCR6—Port Pull-Up Control Register 6
Bit
7
6
5
H'E3
4
3
I/O Ports
2
0
1
PUCR6 7 PUCR66 PUCR65 PUCR64 PUCR63 PUCR62 PUCR61 PUCR60
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 6 Input Pull-up MOS Control
0 Input pull-up MOS is off
1 Input pull-up MOS is on
Note: When the PCR6 specification is 0.
(Input port specification)
Rev. 8.00 Mar. 09, 2010 Page 595 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
PCR1—Port Control Register 1
Bit
H'E4
I/O Ports
7
6
5
4
3
2
1
0
PCR17
PCR16*
⎯
PCR14
PCR13
⎯
⎯
⎯
Initial value
0
0
⎯
0
0
⎯
⎯
⎯
Read/Write
W
W
W
W
W
W
W
W
Port 1 Input/Output Select
0 Input pin
1 Output pin
Note: * PCR16 is not equipped with H8/38124 Group.
PCR3—Port Control Register 3
Bit
H'E6
I/O Ports
7
6
5
4
3
2
1
0
PCR3 7
PCR3 6
PCR3 5
PCR3 4
PCR3 3
PCR32
PCR31
PCR3 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 3 Input/Output Select
0 Input pin
1 Output pin
PCR4—Port Control Register 4
Bit
H'E7
I/O Ports
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
PCR42
PCR41
PCR40
Initial value
1
1
1
1
1
0
0
0
Read/Write
⎯
⎯
⎯
⎯
⎯
W
W
W
Port 4 Input/Output Select
0 Input pin
1 Output pin
Rev. 8.00 Mar. 09, 2010 Page 596 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
PCR5—Port Control Register 5
Bit
H'E8
I/O Ports
7
6
5
4
3
2
1
0
PCR57
PCR56
PCR55
PCR54
PCR53
PCR52
PCR51
PCR50
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 5 Input/Output Select
0 Input pin
1 Output pin
PCR6—Port Control Register 6
Bit
H'E9
I/O Ports
7
6
5
4
3
2
1
0
PCR6 7
PCR6 6
PCR6 5
PCR6 4
PCR6 3
PCR6 2
PCR6 1
PCR6 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 6 Input/Output Select
0 Input pin
1 Output pin
PCR7—Port Control Register 7
Bit
H'EA
I/O Ports
7
6
5
4
3
2
1
0
PCR77
PCR76
PCR75
PCR74
PCR73
PCR72
PCR71
PCR70
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 7 Input/Output Select
0 Input pin
1 Output pin
Rev. 8.00 Mar. 09, 2010 Page 597 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
PCR8—Port Control Register 8
Bit
H'EB
I/O Ports
7
6
5
4
3
2
1
0
PCR87
PCR86
PCR85
PCR84
PCR83
PCR82
PCR81
PCR80
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 8 Input/Output Select
0 Input pin
1 Output pin
PMR9—Port Mode Register 9
Bit
7
6
H'EC
5
I/O Ports
4
3
2
1
0
⎯
⎯
⎯
⎯
PIOFF/⎯*
⎯
PWM2
PWM1
Initial value
1
1
1
1
0
⎯
0
0
Read/Write
⎯
⎯
⎯
⎯
R/W
W
R/W
R/W
P90/PWM1 Pin Function Switch
0 Functions as P90 output pin
1 Functions as PWM1 output pin
P91/PWM2 Pin Function Switch
0 Functions as P91 output pin
1 Functions as PWM2 output pin
P92 to P90 Step-up Circuit Control
0 Large-current port step-up circuit is turned on
1 Large-current port step-up circuit is turned off
Note: * Readable/writable reserved bit in the H8/38024S Group and H8/38124 Group.
Rev. 8.00 Mar. 09, 2010 Page 598 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
PCRA—Port Control Register A
Bit
H'ED
I/O Ports
7
6
5
4
3
2
0
1
⎯
⎯
⎯
⎯
PCRA 3
PCRA 2
Initial value
1
1
1
1
0
0
0
0
Read/Write
⎯
⎯
⎯
⎯
W
W
W
W
PCRA 1 PCRA 0
Port A Input/Output Select
0 Input pin
1 Output pin
PMRB—Port Mode Register B
Bit
H'EE
I/O Ports
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
IRQ1
⎯
⎯
⎯
Initial value
1
1
1
1
0
1
1
1
Read/Write
⎯
⎯
⎯
⎯
R/W
⎯
⎯
⎯
PB3/AN3/IRQ1 Pin Function Switch
0 Functions as PB3/AN3 input pin
1 Functions as IRQ1 input pin
Rev. 8.00 Mar. 09, 2010 Page 599 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
SYSCR1—System Control Register 1
Bit
H'F0
System Control
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
LSON
⎯
MA1
MA0
Initial value
0
0
0
0
0
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
⎯
R/W
R/W
Active (medium-speed)
Mode Clock Select
0 0 φosc/16
1 φosc/32
1 0 φosc/64
1 φosc/128
Low Speed on Flag
0 The CPU operates on the system clock (φ)
1 The CPU operates on the subclock (φ SUB)
Standby Timer Select 2 to 0
0 0 0 Wait time = 8,192 states*1
1 Wait time = 16,384 states*1
1 0 Wait time = 1,024 states*1
1 Wait time = 2,048 states*1
1 0 0 Wait time = 4,096 states*1
1 Wait time = 2 states*1
1 0 Wait time = 8 states*1
1 Wait time = 16 states*1
Wait time = 8,192 states*2
Wait time = 16,384 states*2
Wait time = 32,768 states*2
Wait time = 65,536 states*2
Wait time = 131,072 states*2
Wait time = 2 states*2
Wait time = 8 states*2
Wait time = 16 states*2
Software Standby
0 • When a SLEEP instruction is executed in active mode, a transition is
made to sleep mode
• When a SLEEP instruction is executed in subactive mode, a transition
is made to subsleep mode
1 • When a SLEEP instruction is executed in active mode, a transition is
made to standby mode or watch mode
• When a SLEEP instruction is executed in subactive mode, a transition
is made to watch mode
Notes: 1. Applies to products other than the H8/38124 Group.
2. Applies to the H8/38124 Group.
Rev. 8.00 Mar. 09, 2010 Page 600 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
SYSCR2—System Control Register 2
Bit
H'F1
System Control
7
6
5
4
3
2
1
0
⎯
⎯
⎯
NESEL
DTON
MSON
SA1
SA0
Initial value
1
1
1
1
0
0
0
0
Read/Write
⎯
⎯
⎯
R/W
R/W
R/W
R/W
R/W
Subactive Mode Clock Select
Medium Speed on Flag
0 0 φW/8
1 φW/4
1 * φW/2
*: Don't care
0 Operates in active (high-speed) mode
1 Operates in active (medium-speed) mode
Direct Transfer on Flag
0 • When a SLEEP instruction is executed in active mode, a transition is
made to standby mode, watch mode, or sleep mode
• When a SLEEP instruction is executed in subactive mode, a transition is
made to watch mode or subsleep mode
1 • When a SLEEP instruction is executed in active (high-speed) mode, a direct
transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1
• When a SLEEP instruction is executed in active (medium-speed) mode, a direct
transition is made to active (high-speed) mode if SSBY = 0, MSON = 0, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1
• When a SLEEP instruction is executed in subactive mode, a direct
transition is made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0,
and MSON = 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1,
LSON = 0, and MSON = 1
Noise Elimination Sampling Frequency Select
0 Sampling rate is φOSC/16
1 Sampling rate is φOSC/4
Rev. 8.00 Mar. 09, 2010 Page 601 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
IEGR—IRQ Edge Select Register
Bit
H'F2
System Control
7
6
5
4
3
2
1
0
⎯
⎯
⎯
IEG4
IEG3
⎯
IEG1
IEG0
Initial value
1
1
1
0
0
⎯
0
0
Read/Write
⎯
⎯
⎯
R/W
R/W
W
R/W
R/W
IRQ0 Edge Select
0 Falling edge of IRQ0 pin input is detected
1 Rising edge of IRQ0 pin input is detected
IRQ1 Edge Select
0 Falling edge of IRQ1, TMIC pin input is detected
1 Rising edge of IRQ1, TMIC pin input is detected
IRQ3 Edge Select
0 Falling edge of IRQ3, TMIF pin input is detected
1 Rising edge of IRQ3, TMIF pin input is detected
IRQ4 Edge Select
0 Falling edge of IRQ4, ADTRG pin input is detected
1 Rising edge of IRQ4, ADTRG pin input is detected
Rev. 8.00 Mar. 09, 2010 Page 602 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
IENR1—Interrupt Enable Register 1
Bit
H'F3
System Control
7
6
5
4
3
2
1
0
IENTA
⎯
IENWP
IEN4
IEN3
IENEC2
IEN1
IEN0
Initial value
0
⎯
0
0
0
0
0
0
Read/Write
R/W
W
R/W
R/W
R/W
R/W
R/W
R/W
IRQ1 to IRQ0 Interrupt Enable
0 Disables IRQ1 to IRQ0 interrupt, requests
1 Enables IRQ1 to IRQ0 interrupt requests
IRQAEC Interrupt Enable
0 Disables IRQAEC interrupt requests
1 Enables IRQAEC interrupt requests
IRQ4 and IRQ3 Interrupt Enable
0 Disables IRQ4 and IRQ3 interrupt requests
1 Enables IRQ4 and IRQ3 interrupt requests
Wakeup Interrupt Enable
0 Disables WKP7 to WKP0 interrupt requests
1 Enables WKP7 to WKP0 interrupt requests
Timer A Interrupt Enable
0 Disables timer A interrupt requests
1 Enables timer A interrupt requests
Rev. 8.00 Mar. 09, 2010 Page 603 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
IENR2—Interrupt Enable Register 2
Bit
H'F4
7
6
5
4
3
System Control
2
1
0
IENDT
IENAD
⎯
IENTG
IENTC
IENEC
Initial value
0
0
⎯
0
0
0
0
0
Read/Write
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
IENTFH IENTFL
Asynchronous Event Counter
Interrupt Enable
0 Disables asynchronous event
counter interrupt requests
1 Enables asynchronous event
counter interrupt requests
Timer C Interrupt Enable
0 Disables timer C interrupt requests
1 Enables timer C interrupt requests
Timer FL Interrupt Enable
0 Disables timer FL interrupt requests
1 Enables timer FL interrupt requests
Timer FH Interrupt Enable
0 Disables timer FH interrupt requests
1 Enables timer FH interrupt requests
Timer G Interrupt Enable
0 Disables timer G interrupt requests
1 Enables timer G interrupt requests
A/D Converter Interrupt Enable
0 Disables A/D converter interrupt requests
1 Enables A/D converter interrupt requests
Direct Transition Interrupt Enable
0 Disables direct transition interrupt requests
1 Enables direct transition interrupt requests
Rev. 8.00 Mar. 09, 2010 Page 604 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
OSCCR—Clock Pulse Generator Control Register
H'F5
Clock Pulse Generator
Note: This register is implemented on the H8/38124 Group only.
Bit
7
6
5
4
3
2
1
0
SUBSTP
⎯
⎯
⎯
⎯
IRQAECF
OSCF
⎯
Initial value
0
0
0
0
0
⎯
⎯
0
Read/Write
R/W
R
R/W
R/W
R/W
R
R
R/W
OSC Flag
0 Operation using system clock oscillator (on-chip oscillator stopped)
1 Operation using on-chip oscillator (system clock oscillator stopped)
IRQAEC Flag
0 IRQAEC pin set to GND during resets
1 IRQAEC pin set to VCC during resets
Subclock Oscillator Stop Control
0 Subclock oscillator operating (initial value)
1 Subclock oscillator stopped
Rev. 8.00 Mar. 09, 2010 Page 605 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
IRR1—Interrupt Request Register 1
Bit
H'F6
System Control
7
6
5
4
3
2
1
0
IRRTA
⎯
⎯
IRRI4
IRRI3
IRREC2
IRRI1
IRRI0
Initial value
0
⎯
1
0
0
0
0
0
Read/Write
R/(W)*
W
⎯
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
IRQ1 and IRQ0 Interrupt Request Flags
0 Clearing condition:
When IRRIn = 1, it is cleared by writing 0
1 Setting condition:
When pin IRQn is designated for interrupt
input and the designated signal edge is input
(n = 1 or 0)
IRQAEC Interrupt Request Flag
0 Clearing condition:
When IRREC2 = 1, it is cleared by writing 0
1 Setting condition:
When pin IRQAEC is designated for interrupt
input and the designated signal edge is input
IRQ4 and IRQ3 Interrupt Request Flags
0 Clearing condition:
When IRRIm = 1, it is cleared by writting 0
1 Setting condition:
When pin IRQm is designated for interrupt
input and the designated signal edge is input
(m = 4 or 3)
Timer A Interrupt Request Flag
0 Clearing condition:
When IRRTA = 1, it is cleared by writing 0
1 Setting condition:
When the timer A counter value overflows (from H'FF to H'00)
Note: * Bits 7 and 4 to 0 can only be written with 0, for flag clearing.
Rev. 8.00 Mar. 09, 2010 Page 606 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
IRR2—Interrupt Request Register 2
Bit
H'F7
7
6
5
4
3
2
System Control
1
0
IRRDT
IRRAD
⎯
IRRTC
IRREC
Initial value
0
0
⎯
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
W
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
IRRTG IRRTFH IRRTFL
Asynchronous Event Counter Interrupt Request Flag
0 Clearing condition:
When IRREC = 1, it is cleared by writing 0
1 Setting condition:
When the asynchronous event counter value
overflows
Timer C Interrupt Request Flag
0 Clearing condition:
When IRRTC = 1, it is cleared by writing 0
1 Setting condition:
When the timer C counter value overflows (from H'FF to
H'00) or underflows (from H'00 to H'FF)
Timer FL Interrupt Request Flag
0 Clearing condition:
When IRRTFL = 1, it is cleared by writing 0
1 Setting condition:
When counter FL and output compare register FL match in 8-bit
timer mode
Timer FH Interrupt Request Flag
0 Clearing condition:
When IRRTFH = 1, it is cleared by writing 0
1 Setting conditions:
When counter FH and output compare register FH match in 8-bit timer mode,
or when 16-bit counters FL and FH and output compare registers FL and
FH match in 16-bit timer mode
Timer G Interrupt Request Flag
0 Clearing condition:
When IRRTG = 1, it is cleared by writing 0
1 Setting conditions:
When the TMIG pin is designated for TMIG input and the designated signal edge is
input, and when TCG overflows while OVIE is set to 1 in TMG
A/D Converter Interrupt Request Flag
0 Clearing condition:
When IRRAD = 1, it is cleared by writing 0
1 Setting condition:
When the A/D converter completes conversion and ADSF is reset
Direct Transition Interrupt Request Flag
0 Clearing condition:
When IRRDT = 1, it is cleared by writing 0
1 Setting condition:
When a SLEEP instruction is executed while DTON is set to 1, and a direct transition is made
Note: * Bits 7, 6, and 4 to 0 can only be written with 0, for flag clearing.
Rev. 8.00 Mar. 09, 2010 Page 607 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
TMW—Timer Mode Register W
H'F8
Watchdog Timer
Note: This register is implemented on the H8/38124 Group only.
Bit
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
CKS3
CKS2
CKS1
CKS0
Initial value
1
1
1
1
1
1
1
1
Read/Write
⎯
⎯
⎯
⎯
R/W
R/W
R/W
R/W
Internal Clock Select
CDS3 CDS2 CDS1 CDS0
Clock source
1
0
0
0
φ/64
1
0
0
1
φ/128
1
0
1
0
φ/256
1
0
1
1
φ/512
1
1
0
0
φ/1024
1
1
0
1
φ/2048
1
1
1
0
φ/4096
1
1
1
1
φ/8192
0
*
*
*
On-chip oscillator
Note: Valid when WDCKS bit in PMR2 register is cleared to 0.
Rev. 8.00 Mar. 09, 2010 Page 608 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
IWPR—Wakeup Interrupt Request Register
Bit
H'F9
System Control
7
6
5
4
3
2
1
0
IWPF7
IWPF6
IWPF5
IWPF4
IWPF3
IWPF2
IWPF1
IWPF0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Wakeup Interrupt Request Register
0 Clearing condition:
When IWPFn = 1, it is cleared by writing 0
1 Setting condition:
When pin WKPn is designated for wakeup input and a
falling edge is input at that pin
(n = 7 to 0)
Note: * All bits can only be written with 0, for flag clearing.
Rev. 8.00 Mar. 09, 2010 Page 609 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
CKSTPR1—Clock Stop Register 1
Bit
7
6
H'FA
4
5
3
System Control
2
1
0
⎯
⎯
Initial value
1
1
1
1
1
1
1
1
Read/Write
⎯
⎯
R/W
R/W
R/W
R/W
R/W
R/W
S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
Timer A Module Standby Mode Control
0 Timer A is set to module standby mode
1 Timer A module standby mode is cleared
Timer C Module Standby Mode Control
0 Timer C is set to module standby mode
1 Timer C module standby mode is cleared
Timer F Module Standby Mode Control
0 Timer F is set to module standby mode
1 Timer F module standby mode is cleared
Timer G Module Standby Mode Control
0 Timer G is set to module standby mode
1 Timer G module standby mode is cleared
A/D Converter Module Standby Mode Control
0 A/D converter is set to module standby mode
1 A/D converter module standby mode is cleared
SCI3 Module Standby Mode Control
0 SCI3 is set to module standby mode
1 SCI3 module standby mode is cleared
Rev. 8.00 Mar. 09, 2010 Page 610 of 658
REJ09B0042-0800
Appendix B Internal I/O Registers
CKSTPR2—Clock Stop Register 2
Bit
H'FB
7
6
5
4
3
System Control
2
1
0
LVDCKSTP*
⎯
⎯
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
⎯
⎯
R/W
R/W
R/W
R/W
R/W
PW2CKSTP AECKSTP WDCKSTP PW1CKSTP LDCKSTP
LCD Module Standby Mode Control
0 LCD is set to module standby mode
1 LCD module standby mode is cleared
PWM1 Module Standby Mode Control
0 PWM1 is set to module standby mode
1 PWM1 module standby mode is cleared
WDT Module Standby Mode Control
0 WDT is set to module standby mode
1 WDT module standby mode is cleared
Asynchronous Event Counter Module Standby Mode Control
0 Asynchronous event counter is set to module standby mode
1 Asynchronous event counter module standby mode is cleared
PWM2 Module Standby Mode Control
0 PWM2 is set to module standby mode
1 PWM2 module standby mode is cleared
LVD Module Standby Mode Control
0 LVD is set to module standby mode
1 LVD module standby mode is cleared
Note: * Control using the LVDCKST bit is implemented on the H8/38124 Group only.
Rev. 8.00 Mar. 09, 2010 Page 611 of 658
REJ09B0042-0800
Appendix C I/O Port Block Diagrams
Appendix C I/O Port Block Diagrams
C.1
Block Diagrams of Port 1
SBY (low level during
reset and in standby
mode)
PUCR1n
VCC
PMR1n
P1n
PDR1n
VSS
Internal data bus
VCC
PCR1n
IRQm
PDR1:
Port data register 1
PCR1:
Port control register 1
PMR1:
Port mode register 1
PUCR1: Port pull-up control register 1
n = 7 and 4
m = 4 and 3
Figure C.1(a) Port 1 Block Diagram (Pins P17 and P14)
Rev. 8.00 Mar. 09, 2010 Page 612 of 658
REJ09B0042-0800
Appendix C I/O Port Block Diagrams
SBY (low level during
reset and in standby
mode)
PUCR16
VCC
PMR16
PDR16
P16
VSS
PDR1:
Port data register 1
PCR1:
Port control register 1
PMR1:
Port mode register 1
Internal data bus
VCC
PCR16
PUCR1: Port pull-up control register 1
Figure C.1(b) Port 1 Block Diagram (Pin P16, Products other than H8/38124 Group)
Rev. 8.00 Mar. 09, 2010 Page 613 of 658
REJ09B0042-0800
Appendix C I/O Port Block Diagrams
SBY
PUCR13
VCC
PMR13
PDR13
P13
Internal data bus
VCC
PCR13
VSS
Timer G
module
TMIG
PDR1:
Port data register 1
PCR1:
Port control register 1
PMR1:
Port mode register 1
PUCR1: Port pull-up control register 1
Figure C.1(c) Port 1 Block Diagram (Pin P13)
Rev. 8.00 Mar. 09, 2010 Page 614 of 658
REJ09B0042-0800
Appendix C I/O Port Block Diagrams
C.2
Block Diagrams of Port 3
SBY
PUCR3n
VCC
PMR3n
P3n
PDR3n
VSS
Internal data bus
VCC
PCR3n
AEC module
AEVH(P36)
AEVL(P37)
PDR3:
Port data register 3
PCR3:
Port control register 3
PMR3:
Port mode register 3
PUCR3: Port pull-up control register 3
n = 7 and 6
Figure C.2(a) Port 3 Block Diagram (Pins P37 and P36)
Rev. 8.00 Mar. 09, 2010 Page 615 of 658
REJ09B0042-0800
Appendix C I/O Port Block Diagrams
SBY
PUCR35
VCC
PMR25
P35
PDR35
VSS
PDR3:
Port data register 3
PCR3:
Port control register 3
PUCR3:
Port pull-up control register 3
PMR2
Port mode register 2
PCR35
Figure C.2(b) Port 3 Block Diagram (Pin P35)
Rev. 8.00 Mar. 09, 2010 Page 616 of 658
REJ09B0042-0800
Internal data bus
VCC
Appendix C I/O Port Block Diagrams
SBY
PUCR3n
VCC
P3n
PDR3n
Internal data bus
VCC
PCR3n
VSS
PDR3: Port data register 3
PCR3: Port control register 3
n = 4 and 3
Figure C.2(c) Port 3 Block Diagram (Pins P34 and P33)
Rev. 8.00 Mar. 09, 2010 Page 617 of 658
REJ09B0042-0800
Appendix C I/O Port Block Diagrams
SBY
TMOFH (P32)
TMOFL (P31)
PUCR3n
VCC
PMR3n
P3n
PDR3n
VSS
PCR3n
PDR3: Port data register 3
PCR3: Port control register 3
PMR3: Port mode register 3
PUCR3: Port pull-up control register 3
n = 2 and 1
Figure C.2(d) Port 3 Block Diagram (Pins P32 and P31)
Rev. 8.00 Mar. 09, 2010 Page 618 of 658
REJ09B0042-0800
Internal data bus
VCC
Appendix C I/O Port Block Diagrams
SBY
PUCR30
VCC
PMR30
PDR30
P30
Internal data bus
VCC
PCR30
VSS
Timer C
module
UD
PDR3:
Port data register 3
PCR3:
Port control register 3
PMR3:
Port mode register 3
PUCR3: Port pull-up control register 3
Figure C.2(e) Port 3 Block Diagram (Pin P30)
Rev. 8.00 Mar. 09, 2010 Page 619 of 658
REJ09B0042-0800
Appendix C I/O Port Block Diagrams
C.3
Block Diagrams of Port 4
Internal data bus
PMR20
P43
IRQ0
PMR2: Port mode register 2
Figure C.3(a) Port 4 Block Diagram (Pin P43)
Rev. 8.00 Mar. 09, 2010 Page 620 of 658
REJ09B0042-0800
Appendix C I/O Port Block Diagrams
SBY
SCINV3
VCC
SPC32
SCI3 module
TXD32
P42
PCR42
VSS
Internal data bus
PDR42
PDR4: Port data register 4
PCR4: Port control register 4
Figure C.3(b) Port 4 Block Diagram (Pin P42)
Rev. 8.00 Mar. 09, 2010 Page 621 of 658
REJ09B0042-0800
Appendix C I/O Port Block Diagrams
SBY
VCC
SCI3 module
RE32
RXD32
P41
PCR41
VSS
SCINV2
PDR4: Port data register 4
PCR4: Port control register 4
Figure C.3(c) Port 4 Block Diagram (Pin P41)
Rev. 8.00 Mar. 09, 2010 Page 622 of 658
REJ09B0042-0800
Internal data bus
PDR41
Appendix C I/O Port Block Diagrams
SBY
SCI3 module
SCKIE32
SCKOE32
VCC
SCKO32
SCKI32
P40
PCR40
VSS
Internal data bus
PDR40
PDR4: Port data register 4
PCR4: Port control register 4
Figure C.3(d) Port 4 Block Diagram (Pin P40)
Rev. 8.00 Mar. 09, 2010 Page 623 of 658
REJ09B0042-0800
Appendix C I/O Port Block Diagrams
C.4
Block Diagram of Port 5
SBY*
PUCR5n
VCC
VCC
P5n
PDR5n
VSS
PCR5n
Internal data bus
PMR5n
WKPn
PDR5: Port data register 5
PCR5: Port control register 5
PMR5: Port mode register 5
PUCR5: Port pull-up control register 5
Note: * The value of SBY is fixed at 1 in the HD64F38024.
n = 7 to 0
Figure C.4 Port 5 Block Diagram
Rev. 8.00 Mar. 09, 2010 Page 624 of 658
REJ09B0042-0800
Appendix C I/O Port Block Diagrams
C.5
Block Diagram of Port 6
SBY
VCC
PDR6n
VCC
PCR6n
P6n
Internal data bus
PUCR6n
VSS
PDR6: Port data register 6
PCR6: Port control register 6
PUCR6: Port pull-up control register 6
n = 7 to 0
Figure C.5 Port 6 Block Diagram
Rev. 8.00 Mar. 09, 2010 Page 625 of 658
REJ09B0042-0800
Appendix C I/O Port Block Diagrams
C.6
Block Diagram of Port 7
SBY
PDR7n
PCR7n
P7n
VSS
PDR7: Port data register 7
PCR7: Port control register 7
n = 7 to 0
Figure C.6 Port 7 Block Diagram
Rev. 8.00 Mar. 09, 2010 Page 626 of 658
REJ09B0042-0800
Internal data bus
VCC
Appendix C I/O Port Block Diagrams
C.7
Block Diagram of Port 8
VCC
PDR8n
PCR8n
P8n
Internal data bus
SBY
VSS
PDR8: Port data register 8
PCR8: Port control register 8
n = 7 to 0
Figure C.7 Port 8 Block Diagram
Rev. 8.00 Mar. 09, 2010 Page 627 of 658
REJ09B0042-0800
Appendix C I/O Port Block Diagrams
C.8
Block Diagrams of Port 9
PWM module
PWMn+1
Internal data bus
SBY
PMR9n
P9n
PDR9n
VSS
PDR9: Port data register 9
n = 1 and 0
Figure C.8(a) Port 9 Block Diagram (Pins P91 and P90)
P9n
PDR9n
VSS
PDR9: Port data register 9
n = 5 to 2
Figure C.8(b) Port 9 Block Diagram (Pins P95 to P92)
Rev. 8.00 Mar. 09, 2010 Page 628 of 658
REJ09B0042-0800
Internal data bus
SBY
Appendix C I/O Port Block Diagrams
Internal data bus
SBY
P93
PDR93
VSS
LVD module
VREFSEL
Vref
PDR9: Port data register 9
Figure C.8(c) Port 9 Block Diagram (Pins P93, H8/38124 Group only)
Rev. 8.00 Mar. 09, 2010 Page 629 of 658
REJ09B0042-0800
Appendix C I/O Port Block Diagrams
C.9
Block Diagram of Port A
SBY
VCC
PCRAn
PAn
VSS
PDRA: Port data register A
PCRA: Port control register A
n = 3 to 0
Figure C.9 Port A Block Diagram
Rev. 8.00 Mar. 09, 2010 Page 630 of 658
REJ09B0042-0800
Internal data bus
PDRAn
Appendix C I/O Port Block Diagrams
C.10
Block Diagrams of Port B
Internal
data bus
PBn
A/D module
DEC
AMR3 to AMR0
VIN
n = 7 to 0
Figure C.10(a) Port B Block Diagram
Rev. 8.00 Mar. 09, 2010 Page 631 of 658
REJ09B0042-0800
Appendix C I/O Port Block Diagrams
Internal
data bus
PB0
A/D module
DEC
AMR3 to AMR0
VIN
LVD module
VINTDSEL
extD
Figure C.10(b) Port B Block Diagram (Pin PB0, H8/38124 Group only)
Rev. 8.00 Mar. 09, 2010 Page 632 of 658
REJ09B0042-0800
Appendix C I/O Port Block Diagrams
Internal
data bus
PB1
A/D module
DEC
AMR3 to AMR0
VIN
LVD module
VINTUSEL
extU
Figure C.10(c) Port B Block Diagram (Pin PB1, H8/38124 Group only)
Rev. 8.00 Mar. 09, 2010 Page 633 of 658
REJ09B0042-0800
Appendix D Port States in the Different Processing States
Appendix D Port States in the Different Processing States
Table D.1
Port
Port States Overview
Reset
Sleep
Subsleep
Standby
Watch
Subactive Active
P17,
High
Retained
3
P16* , impedance
P14, P13
Retained
High
1
impedance*
Retained
Functions
Functions
P37 to
P30
High
Retained
impedance
Retained
High
1
impedance*
Retained
Functions
Functions
P43 to
P40
High
Retained
impedance
Retained
High
impedance
Retained
Functions
Functions
P57 to
P50
High
Retained
impedance
Retained
Retained
High
1 2
impedance* *
Functions
Functions
P67 to
P60
High
Retained
impedance
Retained
High
1
impedance*
Retained
Functions
Functions
P77 to
P70
High
Retained
impedance
Retained
High
impedance
Retained
Functions
Functions
P87 to
P80
High
Retained
impedance
Retained
High
impedance
Retained
Functions
Functions
P95 to
P90
High
Retained
impedance
Retained
High
1
impedance*
Retained
Functions
Functions
PA3 to High
Retained
PA0
impedance
Retained
High
impedance
Retained
Functions
Functions
PB7 to High
High
High
High
PB0
impedance impedance impedance impedance
High
High
High
impedance impedance impedance
Notes: 1. High level output when MOS pull-up is in on state.
2. In the HD64F38024 the previous pin state is retained.
3. Not implemented on H8/38124 Group.
Rev. 8.00 Mar. 09, 2010 Page 634 of 658
REJ09B0042-0800
Appendix E List of Product Codes
Appendix E List of Product Codes
Table E.1
H8/38024 Group Product Code Lineup
Product Type
H8/38024
Group
H8/38024
Mask ROM
versions
Regular
specifications
Wide-range
specifications
ZTAT
versions
Regular
specifications
Wide-range
specifications
F-ZTAT
versions
Regular
specifications
Wide-range
specifications
Part No.
Mark Code
Package
(Package Code)
HD64338024H
HD64338024(***)H
80-pin QFP (FP-80A)
HD64338024F
HD64338024(***)F
80-pin QFP (FP-80B)
HD64338024W
HD64338024(***)W
80-pin TQFP (TFP-80C)
HCD64338024
—
Die
80-pin QFP (FP-80A)
HD64338024D
HD64338024(***)H
HD64338024E
HD64338024(***)F
80-pin QFP (FP-80B)
HD64338024WI
HD64338024(***)W
80-pin TQFP (TFP-80C)
80-pin QFP (FP-80A)
HD64738024H
HD64738024H
HD64738024F
HD64738024F
80-pin QFP (FP-80B)
HD64738024W
HD64738024W
80-pin TQFP (TFP-80C)
80-pin QFP (FP-80A)
HD64738024D
HD64738024H
HD64738024E
HD64738024F
80-pin QFP (FP-80B)
HD64738024WI
HD64738024W
80-pin TQFP (TFP-80C)
HD64F38024H
HD64F38024H
80-pin QFP (FP-80A)
HD64F38024RH
HD64F38024H
HD64F38024F
HD64F38024F
HD64F38024RF
HD64F38024F
HD64F38024W
HD64F38024W
HD64F38024RW
HD64F38024W
80-pin QFP (FP-80B)
80-pin TQFP (TFP-80C)
HD64F38024RLPV F38024RLPV
85-pin TFLGA (TLP-85V)
HCD64F38024
—
Die
HCD64F38024R
—
HD64F38024D
HD64F38024H
HD64F38024RD
HD64F38024H
HD64F38024E
HD64F38024F
HD64F38024RE
HD64F38024F
HD64F38024WI
HD64F38024W
HD64F38024RWI
HD64F38024W
HD64F38024RLPIV F38024RLPIV
80-pin QFP (FP-80A)
80-pin QFP (FP-80B)
80-pin TQFP (TFP-80C)
85-pin TFLGA (TLP-85V)
Rev. 8.00 Mar. 09, 2010 Page 635 of 658
REJ09B0042-0800
Appendix E List of Product Codes
Product Type
H8/38024
Group
H8/38023
Mask ROM
versions
Regular
specifications
Wide-range
specifications
H8/38022
Mask ROM
versions
Regular
specifications
Wide-range
specifications
H8/38021
Mask ROM
versions
Regular
specifications
Wide-range
specifications
H8/38020
Mask ROM
versions
Regular
specifications
Wide-range
specifications
Rev. 8.00 Mar. 09, 2010 Page 636 of 658
REJ09B0042-0800
Part No.
Mark Code
Package
(Package Code)
HD64338023H
HD64338023(***)H
80-pin QFP (FP-80A)
HD64338023F
HD64338023(***)F
80-pin QFP (FP-80B)
HD64338023W
HD64338023(***)W
80-pin TQFP (TFP-80C)
HCD64338023
—
Die
HD64338023D
HD64338023(***)H
80-pin QFP (FP-80A)
HD64338023E
HD64338023(***)F
80-pin QFP (FP-80B)
HD64338023WI
HD64338023(***)W
80-pin TQFP (TFP-80C)
HD64338022H
HD64338022(***)H
80-pin QFP (FP-80A)
HD64338022F
HD64338022(***)F
80-pin QFP (FP-80B)
HD64338022W
HD64338022(***)W
80-pin TQFP (TFP-80C)
HCD64338022
—
Die
HD64338022D
HD64338022(***)H
80-pin QFP (FP-80A)
HD64338022E
HD64338022(***)F
80-pin QFP (FP-80B)
HD64338022WI
HD64338022(***)W
80-pin TQFP (TFP-80C)
HD64338021H
HD64338021(***)H
80-pin QFP (FP-80A)
HD64338021F
HD64338021(***)F
80-pin QFP (FP-80B)
HD64338021W
HD64338021(***)W
80-pin TQFP (TFP-80C)
HCD64338021
—
Die
HD64338021D
HD64338021(***)H
80-pin QFP (FP-80A)
HD64338021E
HD64338021(***)F
80-pin QFP (FP-80B)
HD64338021WI
HD64338021(***)W
80-pin TQFP (TFP-80C)
HD64338020H
HD64338020(***)H
80-pin QFP (FP-80A)
HD64338020F
HD64338020(***)F
80-pin QFP (FP-80B)
HD64338020W
HD64338020(***)W
80-pin TQFP (TFP-80C)
HCD64338020
—
Die
HD64338020D
HD64338020(***)H
80-pin QFP (FP-80A)
HD64338020E
HD64338020(***)F
80-pin QFP (FP-80B)
HD64338020WI
HD64338020(***)W
80-pin TQFP (TFP-80C)
Appendix E List of Product Codes
Product Type
H8/38024S
Group
H8/38024S
Mask ROM
versions
Regular
specifications
Wide-range
specifications
H8/38023S
Mask ROM
versions
Regular
specifications
Wide-range
specifications
H8/38022S
Mask ROM
versions
Regular
specifications
Wide-range
specifications
H8/38021S
Mask ROM
versions
Regular
specifications
Wide-range
specifications
H8/38020S
Mask ROM
versions
Regular
specifications
Wide-range
specifications
Part No.
Mark Code
Package
(Package Code)
HD64338024SH
HD64338024(***)H
80-pin QFP (FP-80A)
HD64338024SW
HD64338024(***)W
80-pin TQFP (TFP-80C)
HD64338024SLPV 338024S(***)LPV
85-pin TFLGA (TLP-85V)
HCD64338024S
—
Die
HD64338024SD
HD64338024(***)H
80-pin QFP (FP-80A)
HD64338024SWI
HD64338024(***)W
80-pin TQFP (TFP-80C)
HD64338024SLPIV 338024S(***)LPIV
85-pin TFLGA (TLP-85V)
HD64338023SH
HD64338023(***)H
80-pin QFP (FP-80A)
HD64338023SW
HD64338023(***)W
80-pin TQFP (TFP-80C)
HD64338023SLPV 338023S(***)LPV
85-pin TFLGA (TLP-85V)
HCD64338023S
—
Die
HD64338023SD
HD64338023(***)H
80-pin QFP (FP-80A)
HD64338023SWI
HD64338023(***)W
80-pin TQFP (TFP-80C)
HD64338023SLPIV 338023S(***)LPIV
85-pin TFLGA (TLP-85V)
HD64338022SH
HD64338022(***)H
80-pin QFP (FP-80A)
HD64338022SW
HD64338022(***)W
80-pin TQFP (TFP-80C)
HD64338022SLPV 338022S(***)LPV
85-pin TFLGA (TLP-85V)
HCD64338022S
—
Die
HD64338022SD
HD64338022(***)H
80-pin QFP (FP-80A)
HD64338022SWI
HD64338022(***)W
80-pin TQFP (TFP-80C)
HD64338022SLPIV 338022S(***)LPIV
85-pin TFLGA (TLP-85V)
HD64338021SH
HD64338021(***)H
80-pin QFP (FP-80A)
HD64338021SW
HD64338021(***)W
80-pin TQFP (TFP-80C)
HD64338021SLPV 338021S(***)LPV
85-pin TFLGA (TLP-85V)
HCD64338021S
—
Die
HD64338021SD
HD64338021(***)H
80-pin QFP (FP-80A)
HD64338021SWI
HD64338021(***)W
80-pin TQFP (TFP-80C)
HD64338021SLPIV 338021S(***)LPIV
85-pin TFLGA (TLP-85V)
HD64338020SH
HD64338020(***)H
80-pin QFP (FP-80A)
HD64338020SW
HD64338020(***)W
80-pin TQFP (TFP-80C)
HD64338020SLPV 338020S(***)LPV
85-pin TFLGA (TLP-85V)
HCD64338020S
—
Die
HD64338020SD
HD64338020(***)H
80-pin QFP (FP-80A)
HD64338020SWI
HD64338020(***)W
HD64338020SLPIV 338020S(***)LPIV
80-pin TQFP (TFP-80C)
85-pin TFLGA (TLP-85V)
Rev. 8.00 Mar. 09, 2010 Page 637 of 658
REJ09B0042-0800
Appendix E List of Product Codes
Part No.
Mark Code
Package
(Package Code)
Regular
specifications
HD64F38124H
F38124H
80-pin QFP (FP-80A)
HD64F38124W
F38124W
80-pin TQFP (TFP-80C)
Wide-range
specifications
HD64F38124HW
F38124H
80-pin QFP (FP-80A)
HD64F38124WW
F38124W
80-pin TQFP (TFP-80C)
80-pin QFP (FP-80A)
Product Type
H8/38124
Group
H8/38124
F-ZTAT
versions
Mask ROM
versions
Regular
specifications
Wide-range
specifications
H8/38123
H8/38122
Mask ROM
versions
F-ZTAT
versions
Mask ROM
versions
H8/38120
Mask ROM
versions
Mask ROM
versions
38124(***)H
38124(***)W
80-pin TQFP (TFP-80C)
HD64338124HW
38124(***)H
80-pin QFP (FP-80A)
HD64338124WW
38124(***)W
80-pin TQFP (TFP-80C)
Regular
specifications
HD64338123H
38123(***)H
80-pin QFP (FP-80A)
HD64338123W
38123(***)W
80-pin TQFP (TFP-80C)
Wide-range
specifications
HD64338123HW
38123(***)H
80-pin QFP (FP-80A)
HD64338123WW
38123(***)W
80-pin TQFP (TFP-80C)
Regular
specifications
HD64F38122H
F38122H
80-pin QFP (FP-80A)
HD64F38122W
F38122W
80-pin TQFP (TFP-80C)
Wide-range
specifications
HD64F38122HW
F38122H
80-pin QFP (FP-80A)
HD64F38122WW
F38122W
80-pin TQFP (TFP-80C)
80-pin QFP (FP-80A)
Regular
specifications
Wide-range
specifications
H8/38121
HD64338124H
HD64338124W
HD64338122H
38122(***)H
HD64338122W
38122(***)W
80-pin TQFP (TFP-80C)
HD64338122HW
38122(***)H
80-pin QFP (FP-80A)
HD64338122WW
38122(***)W
80-pin TQFP (TFP-80C)
Regular
specifications
HD64338121H
38121(***)H
80-pin QFP (FP-80A)
HD64338121W
38121(***)W
80-pin TQFP (TFP-80C)
Wide-range
specifications
HD64338121HW
38121(***)H
80-pin QFP (FP-80A)
HD64338121WW
38121(***)W
80-pin TQFP (TFP-80C)
Regular
specifications
HD64338120H
38120(***)H
80-pin QFP (FP-80A)
HD64338120W
38120(***)W
80-pin TQFP (TFP-80C)
Wide-range
specifications
HD64338120HW
38120(***)H
80-pin QFP (FP-80A)
HD64338120WW
38120(***)W
80-pin TQFP (TFP-80C)
Note: (***) is the ROM code.
Rev. 8.00 Mar. 09, 2010 Page 638 of 658
REJ09B0042-0800
Appendix F Package Dimensions
Appendix F Package Dimensions
Dimensional drawings of the H8/38024 Group, H8/38024S Group, and H8/38124 Group packages
FP-80A, FP-80B, and TFP-80C are shown in figures F.1, F.2, and F.3 below.
JEITA Package Code
P-QFP80-14x14-0.65
RENESAS Code
PRQP0080JB-A
Previous Code
FP-80A/FP-80AV
MASS[Typ.]
1.2g
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
HD
*1
D
60
41
61
40
bp
c
c1
HE
*2
E
b1
Reference
Symbol
ZE
Terminal cross section
21
80
20
c
θ
F
A
ZD
A2
1
L
A1
S
L1
Detail F
e
*3
bp
x
M
y S
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
θ
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Nom Max
14
14
2.70
16.9 17.2 17.5
16.9 17.2 17.5
3.05
0.00 0.10 0.25
0.24 0.32 0.40
0.30
0.12 0.17 0.22
0.15
8°
0°
0.65
0.12
0.10
0.83
0.83
0.5
0.8
1.1
1.6
Min
Figure F.1 FP-80A Package Dimensions
Rev. 8.00 Mar. 09, 2010 Page 639 of 658
REJ09B0042-0800
Appendix F Package Dimensions
JEITA Package Code
P-QFP80-14x20-0.80
RENESAS Code
PRQP0080GD-B
Previous Code
FP-80B/FP-80BV
MASS[Typ.]
1.7g
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
HD
*1
D
64
41
65
40
bp
c
c1
HE
*2
E
b1
ZE
Reference
Symbol
25
80
1
Terminal cross section
24
c
A2
A
ZD
θ
F
L
A1
S
L1
Detail F
e
y S
*3
bp
x
M
Figure F.2 FP-80B Package Dimensions
Rev. 8.00 Mar. 09, 2010 Page 640 of 658
REJ09B0042-0800
Dimension in Millimeters
Min Nom Max
D
20
E
14
A2
2.70
HD 24.4 24.8 25.2
HE 18.4 18.8 19.2
A
3.10
A1 0.00 0.20 0.30
bp 0.29 0.37 0.45
b1
0.35
c
0.12 0.17 0.22
c1
0.15
θ
10°
0°
e
0.8
x
0.15
y
0.15
ZD
0.8
ZE
1.0
L
1.0
1.2
1.4
L1
2.4
Appendix F Package Dimensions
JEITA Package Code
P-TQFP80-12x12-0.50
RENESAS Code
PTQP0080KC-A
Previous Code
TFP-80C/TFP-80CV
MASS[Typ.]
0.4g
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
HD
*1
D
60
41
61
40
bp
c
c1
HE
Reference
Symbol
*2
E
b1
Terminal cross section
21
ZE
80
c
θ
F
A
20
Index mark
A2
1
ZD
S
A1
L
L1
e
*3
bp
Detail F
x
M
y S
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
θ
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Nom Max
12
12
1.00
13.8 14.0 14.2
13.8 14.0 14.2
1.20
0.00 0.10 0.20
0.17 0.22 0.27
0.20
0.12 0.17 0.22
0.15
8°
0°
0.5
0.10
0.10
1.25
1.25
0.4
0.5
0.6
1.0
Min
Figure F.3 TFP-80C Package Dimensions
Rev. 8.00 Mar. 09, 2010 Page 641 of 658
REJ09B0042-0800
Appendix F Package Dimensions
JEITA Package Code
P-TFLGA85-7x7-0.65
RENESAS Code
PTLG0085JA-A
Previous Code
TLP-85V
MASS[Typ.]
0.1g
D
w S B
E
w S A
×4
v
y1 S
A
S
y
S
ZD
e
A
K
Reference
Symbol
e
J
H
G
B
F
E
Dimension in Millimeters
Min
Nom
D
7.0
E
7.0
Max
0.15
v
w
0.20
A
1.20
A1
D
e
b
ZE
C
B
A
0.65
0.30
0.35
0.08
y
0.10
y1
0.2
SD
1
2
3
4
5
6
φ b
7
φ
8
9
10
×M S A B
Figure F.4 TLP-85V Package Dimensions
Rev. 8.00 Mar. 09, 2010 Page 642 of 658
REJ09B0042-0800
0.40
x
SE
ZD
0.575
ZE
0.575
Appendix G Specifications of Chip Form
Appendix G Specifications of Chip Form
The specifications of the chip form of the HCD64338024, HCD64338023, HCD64338022,
HCD64338021, and HCD64338020 are shown in figure G.1. The specifications of the chip form
of the HCD64F38024 and HCD64F38024R are shown in figure G.2. The specifications of the chip
form of the HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and
HCD64338020S are shown in figure G.3.
Maximum plain
X-direction: 3.99 ± 0.25
Y-direction: 3.99 ± 0.25
Max 0.03
0.28 ± 0.02
X-direction: 3.99 ± 0.05
Y-direction: 3.99 ± 0.05
Unit: mm
Figure G.1 Chip Sectional Figure of the HCD64338024, HCD64338023, HCD64338022,
HCD64338021, and HCD64338020
Maximum plain
X-direction: 3.84 ± 0.25
Y-direction: 4.24 ± 0.25
Max 0.03
0.28 ± 0.02
X-direction: 3.84 ± 0.05
Y-direction: 4.24 ± 0.05
Unit: mm
Figure G.2 Chip Sectional Figure of the HCD64F38024 and HCD64F38024R
Rev. 8.00 Mar. 09, 2010 Page 643 of 658
REJ09B0042-0800
Appendix G Specifications of Chip Form
Maximum plain
X-direction: 2.91 ± 0.25
Y-direction: 2.91 ± 0.25
Max 0.03
0.28 ± 0.02
X-direction: 2.91 ± 0.05
Y-direction: 2.91 ± 0.05
Unit: mm
Figure G.3 Chip Sectional Figure of the HCD64338024S, HCD64338023S, HCD64338022S,
HCD64338021S, and HCD64338020S
Rev. 8.00 Mar. 09, 2010 Page 644 of 658
REJ09B0042-0800
Appendix H Form of Bonding Pads
Appendix H Form of Bonding Pads
The form of the bonding pads for the HCD64338024, HCD64338023, HCD64338022,
HCD64338021, HCD64338020, HCD64F38024, HCD64F38024R, HCD64338024S,
HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S is shown in figure H.1.
Bonding area
5 mm
72 mm
Metal layer
72 mm
5 mm
Figure H.1 Bonding Pad Form
Rev. 8.00 Mar. 09, 2010 Page 645 of 658
REJ09B0042-0800
Appendix I Specifications of Chip Tray
Appendix I Specifications of Chip Tray
The specifications of the chip tray for the HCD64338024, HCD64338023, HCD64338022,
HCD64338021, and HCD64338020 are shown in figure I.1. The specifications of the chip tray for
the HCD64F38024 and HCD64F38024R are shown in figure I.2. The specifications of the chip
tray for the HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and
HCD64338020S are shown in figure I.3.
51
Chip direction
Chip
3.99
Type name
51
3.99
6.2 ± 0.1
6.9 ± 0.1
1.8 ± 0.1
0.6 ± 0.1
4.5 ± 0.05
6.2 ± 0.1
6.9 ± 0.15
X'
4.0 ± 0.1
X
4.5 ± 0.05
Chip tray name
DAINIPPON-INK-&-CHEMICALS-INC.
Type: CT015
Carved code: TCT45-060P
Unit: mm
X-X' cross section
Figure I.1 Specifications of Chip Tray for the HCD64338024, HCD64338023,
HCD64338022, HCD64338021, and HCD64338020
Rev. 8.00 Mar. 09, 2010 Page 646 of 658
REJ09B0042-0800
Appendix I Specifications of Chip Tray
51
Chip
4.24
Chip direction
Type name
51
3.84
6.2 ± 0.1
6.9 ± 0.1
X-X' cross section
1.8 ± 0.1
0.6 ± 0.1
4.5 ± 0.05
6.2 ± 0.1
6.9 ± 0.1
X'
4.0 ± 0.1
X
4.5 ± 0.05
Chip tray name
DAINIPPON-INK-&-CHEMICALS-INC.
Type: CT015
Carved code: TCT45-060P
Unit: mm
Figure I.2 Specifications of Chip Tray for the HCD64F38024 and HCD64F38024R
Rev. 8.00 Mar. 09, 2010 Page 647 of 658
REJ09B0042-0800
Appendix I Specifications of Chip Tray
51
Chip direction
Chip
Y
Type name
X
51
Chip tray name
Type: CT290
Carved code:TCT036036-060T
3.6 ± 0.05
4.48 ± 0.1
X
X‘
5.34 ± 0.1
0.8 ± 0.05
Back of chip tray
3.6 ± 0.05
1.8
4.0
0.2 ± 0.1
5.34 ± 0.1
1.5
4.48 ± 0.1
X-X‘ Cross section
unit: mm
Figure I.3 Specifications of Chip Tray for the HCD64338024S, HCD64338023S,
HCD64338022S, HCD64338021S, and HCD64338020S
Rev. 8.00 Mar. 09, 2010 Page 648 of 658
REJ09B0042-0800
Main Revisions for This Edition
Item
Page
Revision (See Manual for Details)
1.1 Overview
5
Table amended
Table 1.1 Features
4.3 Subclock
Generator
111
Item
Specification
Serial
communication
interface
• SCI3: 8-bit synchronous/asynchronous serial interface
Figure amended
C1
C1 = C 2 = 15 pF (typ.)
X1
Figure 4.8 Typical
Connection to 32.768
kHz/38.4 kHz Crystal
Oscillator (Subclock)
X2
Frequency
Crystal oscillator
38.4 kHz
Seiko Instruments Inc. VTC-200
32.768 kHz Nihon Denpa Kogyo
C2
Products Name
MX73P
C1 = C 2 = 7 pF (typ.)
Frequency
Crystal oscillator
Products Name Motion Resistance
32.768 kHz* EPSON TOYOCOM. C-001R
35 kΩ max
Notes: Circuit constants should be detemined in consultation with the
resonator manufacture.
* H8/38124 Group only.
5.10 Usage Note
144
Newly added
6.10.6 Status Read
Mode
188
Figure amended
tds
Figure 6.19 Status
Read Mode Timing
Waveforms
10.1 Overview
I/O7−I/O0
333
tdh
H'71
tds
tdh
tdf
H'71
Description deleted
Serial communication interface 3 (SCI3) can carry out serial
data communication in either asynchronous or synchronous
mode.
.
10.1.1 Features
333
Description amended
•
Choice of asynchronous or synchronous mode for serial
data communication
…
In this mode, serial data can be exchanged with standard
asynchronous communication LSIs such as a Universal
Asynchronous Receiver/Transmitter (UART) or
Asynchronous Communication Interface Adapter (ACIA).
.
There is a choice of 12 data transfer formats.
Rev. 8.00 Mar. 09, 2010 Page 649 of 658
REJ09B0042-0800
Item
Page
Revision (See Manual for Details)
10.1.1 Features
333
Table amended
10.2.5 Serial Mode
Register (SMR)
341
Data length
7, 8, 5 bits
Stop bit length
1 or 2 bits
Parity
Even, odd, or none
Receive error detection
Parity, overrun, and framing errors
Break detection
Break detected by reading the RXD32 pin level directly when a
framing error occurs
Description amended
Bit 2—5 Bit Communication (MP)
When this bit is one, the format of 5 bits communication
becomes possible.
In the case of writing 1 to this bit, bit 5 (PE) should be written
with 1 all at once.
Table amended
10.2.6 Serial Control 344
Register 3 (SCR3)
Bit 2
MP
Description
0
5 bit communication disabled
1
5 bit communication enabled
(initial value)
Description amended
Bit 3—Reserved (MPIE)
It’s a reserved bit.
Table deleted
10.2.7 Serial Status
Register (SSR)
346
Description amended
SSR is an 8-bit register containing status flags that indicate the
operational status of SCI3
.
349
Description amended
Bit 1—Reserved (MPBR)
It’s a reserved read-only bit.
Table deleted
Description amended
Bit 0—Reserved (MPBT)
The write value should always be 0.
Table deleted
Rev. 8.00 Mar. 09, 2010 Page 650 of 658
REJ09B0042-0800
Item
Page
Revision (See Manual for Details)
10.3.1 Overview
358
Description amended
•
Asynchronous Mode
Table 10.8 SMR
Settings and
Corresponding Data
Transfer Formats
359
Choice of parity addition,
and addition of 1 or 2
stop bits. (The combination of these parameters determines
the data transfer format and the character length.)
Table amended
SMR
Bit 7 Bit 6
COM CHR
0
0
Data Transfer Format
Bit 2
MP
Bit 5
PE
Bit 3
STOP Mode
0
0
0
1
Data Length
Asynchronous 8-bit data
mode
Stop Bit
Length
No
1 bit
2 bits
0
1
Parity Bit
Yes
1 bit
1
2 bits
7-bit data
0
0
1
No
1 bit
1
2 bits
0
1
Yes
1 bit
1
2 bits
Setting prohibited
0
0
1
0
1
0
1
1
No
1 bit
2 bits
Setting prohibited
0
0
1
Asynchronous 5-bit data
mode
1
0
1
1
10.3.2 Operation in
Asynchronous Mode
363
CHR PE
10.3.3 Operation in
Synchronous Mode
372
10.3.4
Multiprocessor
Communication
Function
⎯
1 bit
2 bits
Table amended
SMR
Table 10.11 Data
Transfer Formats
(Asynchronous Mode)
Yes
Asynchronous 5-bit data
mode
Serial Data Transfer Format and Frame Length
MP
STOP
1
2
3
4
5
6
7
0
0
1
0
Setting prohibited
0
0
1
1
Setting prohibited
1
0
1
0
1
0
1
1
8
9
10 11 12
Setting prohibited
Setting prohibited
Description amended
Parity
bit cannot be added.
Description deleted
Rev. 8.00 Mar. 09, 2010 Page 651 of 658
REJ09B0042-0800
Item
Page
Revision (See Manual for Details)
16.2.2 DC
Characteristics
453
Table amended
Values
Table 16.2 DC
Characteristics
16.4.2 DC
Characteristics
469
Item
Symbol Applicable Pins
Input high
voltage
VIH
Min
Typ Max
RES,
0.8 VCC —
WKP0 to WKP7,
0.9 VCC —
IRQ0, IRQ3, IRQ4,
AEVL, AEVH,
TMIC, TMIF,
TMIG, ADTRG,
SCK32
VCC + 0.3
IRQ1
0.8 VCC —
AVCC + 0.3
0.9 VCC —
AVCC + 0.3
Unit Test Condition
V
VCC + 0.3
Notes
VCC = 4.0 V to 5.5 V
Except the above
V
VCC = 4.0 V to 5.5 V
Except the above
Table amended
Values
Table 16.8 DC
Characteristics
473
Item
Symbol Applicable Pins
Input high
voltage
VIH
Min
Typ Max
Unit Test Condition
RES,
0.9 VCC —
WKP0 to WKP7,
IRQ0, IRQ3, IRQ4,
AEVL, AEVH,
TMIC, TMIF,
TMIG, ADTRG,
SCK32
VCC + 0.3
V
IRQ1
AVCC + 0.3
V
0.9 VCC —
Notes
Table amended
Values
Item
Symbol Applicable Pins Min
Typ
Max
Unit Test Condition
Notes
Subactive
mode
current
dissipation
ISUB
10
—
μA
*3
*4
Subsleep
mode
current
dissipation
Rev. 8.00 Mar. 09, 2010 Page 652 of 658
REJ09B0042-0800
ISUBSP
VCC
VCC
—
VCC = 2.7 V,
LCD on 32 kHz
crystal resonator
(φSUB=φw/8)
—
20
40
μA
VCC = 2.7 V,
LCD on 32 kHz
External Clock
(φSUB=φw/2)
—
17
40
μA
VCC = 2.7 V,
LCD on 32 kHz
crystal resonator
(φSUB=φw/2)
—
4.8
16.0
μA
VCC = 2.7 V,
LCD on 32 kHz
External Clock
(φSUB=φw/2)
—
5.4
16.0
μA
VCC = 2.7 V,
LCD on 32 kHz
crystal resonator
(φSUB=φw/2)
Reference
value
*3
*4
*3
*4
Item
Page
Revision (See Manual for Details)
16.4.2 DC
Characteristics
474
Table amended
Values
Table 16.8 DC
Characteristics
16.4.7 Power Supply 482
Characteristics
16.6.2 DC
Characteristics
Table 16.16 DC
Characteristics
487
Item
Symbol Applicable Pins Min
Watch
mode
current
dissipation
IWATCH
VCC
—
Typ
Max
Unit Test Condition
Notes
2.0
—
μA
*3
*4
VCC = 2.7 V,
Ta = 25°C
32 kHz External
Clock
LCD not used
—
2.6
—
μA
VCC = 2.7 V,
Ta = 25°C
32 kHz crystal
resonator
LCD not used
—
2.0
6.0
μA
VCC = 2.7 V,
32 kHz External
Clock
LCD not used
—
2.6
6.0
μA
VCC = 2.7 V,
32 kHz crystal
resonator
LCD not used
Reference
value
*3
*4
Newly added
Table amended
Values
Item
Symbol Applicable Pins
Input high
voltage
VIH
Min
Typ Max
Unit Test Condition
RES,
0.9 VCC
WKP0 to WKP7,
IRQ0, IRQ3, IRQ4,
AEVL, AEVH,
TMIC, TMIF,
TMIG, ADTRG,
SCK32
—
VCC + 0.3
V
IRQ1
—
AVCC + 0.3
V
0.9 VCC
Notes
Rev. 8.00 Mar. 09, 2010 Page 653 of 658
REJ09B0042-0800
Item
Page
Revision (See Manual for Details)
16.6.2 DC
Characteristics
492
Table amended
Values
Table 16.16 DC
Characteristics
Item
Symbol Applicable Pins Min
Typ
Max
Unit Test Condition
Notes
Subactive
mode
current
dissipation
ISUB
—
6.2
—
μA
VCC = 1.8 V,
LCD on 32 kHz
External Clock
(φSUB=φw/2)
*1
*2
—
5.7
—
μA
VCC = 1.8 V,
LCD on 32 kHz
crystal resonator
(φSUB=φw/2)
—
4.4
—
μA
VCC = 2.7 V,
LCD on 32 kHz
crystal resonator
(φSUB=φw/8)
—
10
40
μA
VCC = 2.7 V,
LCD on 32 kHz
External Clock
(φSUB=φw/2)
—
11
40
μA
VCC = 2.7 V,
LCD on 32 kHz
crystal resonator
(φSUB=φw/2)
—
4.8
16.0
μA
VCC = 2.7 V,
LCD on 32 kHz
External Clock
(φSUB=φw/2)
—
5.1
16.0
μA
VCC = 2.7 V,
LCD on 32 kHz
crystal resonator
(φSUB=φw/2)
—
1.2
—
μA
VCC = 1.8 V,
Ta = 25°C
32 kHz crystal
oscillator
LCD not used
Subsleep
mode
current
dissipation
Watch
mode
current
dissipation
ISUBSP
IWATCH
VCC
VCC
VCC
—
493
2.0
—
μA
Reference
value
*1
*2
*1
*2
*1
*2
Reference
value
VCC = 2.7 V,
Ta = 25°C
32 kHz External
Clock
LCD not used
Table amended
Values
Item
Symbol Applicable Pins Min
Watch
mode
current
dissipation
IWATCH
Rev. 8.00 Mar. 09, 2010 Page 654 of 658
REJ09B0042-0800
VCC
—
Typ
Max
Unit Test Condition
Notes
2.3
—
μA
*1
*2
VCC = 2.7 V,
Ta = 25°C
32 kHz crystal
resonator
LCD not used
—
2.0
6.0
μA
VCC = 2.7 V,
32 kHz External
Clock
LCD not used
—
2.3
6.0
μA
VCC = 2.7 V,
32 kHz crystal
resonator
LCD not used
Reference
value
*1
*2
Item
Page
Revision (See Manual for Details)
16.8.2 DC
Characteristics
506
Table amended
Values
Table 16.22 DC
Characteristics
Item
Symbol Applicable Pins
Input high
voltage
VIH
Typ Max
Unit Test Condition
RES,
VCC × 0.8
WKP0 to WKP7,
IRQ0, IRQ3, IRQ4,
AEVL, AEVH,
VCC × 0.9
TMIC, TMIF,
TMIG, ADTRG,
SCK32
—
VCC + 0.3
V
—
VCC + 0.3
IRQ1
VCC × 0.8
—
AVCC + 0.3
VCC × 0.9
—
AVCC + 0.3
16.8.10 Power
525
Supply Characteristics
Newly added
B.1 Addresses
Table amended
B.2 Functions
548
564
Min
Notes
VCC = 4.0 V to 5.5 V
Other than above
V
VCC = 4.0 V to 5.5 V
Other than above
Bit Names
Lower
Address
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module Name
H'AA
SCR3
TIE
RIE
TE
RE
—
TEIE
CKE1
CKE0
SCI3
H'AC
SSR
TDRE
RDRF
OER
FER
PER
TEND
—
—
Figure amended
SMR—Serial Mode Register
Bit
H'A8
SCI3
7
6
5
4
3
2
1
0
COM
CHR
PE
PM
STOP
MP
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock Select
0 0 φ clock
0 1 φw/2 clock
1 0 φ/16 clock
1 1 φ/64 clock
5 Bit Communication
0 5 bits communication disabled
1 5 bits communication enabled
Rev. 8.00 Mar. 09, 2010 Page 655 of 658
REJ09B0042-0800
Item
Page
Revision (See Manual for Details)
B.2 Functions
566
Figure amended
SCR3—Serial Control Register 3
Bit
H'AA
SCI3
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
⎯
TEIE
CKE1
CKE0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock Enable
Bit 1
CKE1
0
Bit 0
CKE0
0
0
1
1
0
1
1
Description
Clock Source
SCK32 Pin Function
I/O port
Internal clock
Serial clock output
Internal clock
Clock output
Internal clock
Reserved (Do not specify this combination)
Clock input
External clock
Serial clock input
External clock
Reserved (Do not specify this combination)
Reserved (Do not specify this combination)
Communication Mode
Asynchronous
Synchronous
Asynchronous
Synchronous
Asynchronous
Synchronous
Asynchronous
Synchronous
Transmit End Interrupt Enable
0
1
568
Transmit end interrupt request (TEI) disabled
Transmit end interrupt request (TEI) enabled
Figure amended
SSR—Serial Status Register
Bit
Appendix F Package 639
Dimensions
H'AC
SCI3
7
6
5
4
3
2
1
0
TDRE
RDRF
OER
FER
PER
TEND
⎯
⎯
Initial value
1
0
0
0
0
1
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R
R
R/W
Figure replaced
Figure F.1 FP-80A
Package Dimensions
Figure F.2 FP-80B
Package Dimensions
640
Figure replaced
Figure F.3 TFP-80C
Package Dimensions
641
Figure replaced
Rev. 8.00 Mar. 09, 2010 Page 656 of 658
REJ09B0042-0800
Item
Page
Appendix F Package 642
Dimensions
Revision (See Manual for Details)
Figure replaced
Figure F.4 TLP-85V
Package Dimensions
Appendix I
648
Specifications of Chip
Tray
Figure replaced
Figure I.3
Specifications of Chip
Tray for the
HCD64338024S,
HCD64338023S,
HCD64338022S,
HCD64338021S, and
HCD64338020S
Rev. 8.00 Mar. 09, 2010 Page 657 of 658
REJ09B0042-0800
Rev. 8.00 Mar. 09, 2010 Page 658 of 658
REJ09B0042-0800
Renesas 8-Bit Single-Chip Microcomputer
Hardware Manual
H8/38024, H8/38024S, H8/38024R, H8/38124 Group
Publication Date: 1st Edition, November, 2000
Rev.8.00, March 9, 2010
Published by:
Sales Strategic Planning Div.
Renesas Technology Corp.
Edited by:
Customer Support Department
Global Strategic Communication Div.
Renesas Solutions Corp.
© 2010. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
RENESAS SALES OFFICES
http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2377-3473
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
Colophon 6.2
H8/38024, H8/38024S, H8/38024R,
H8/38124 Group
Hardware Manual
REJ09B0042-0800