Intersil HA5340883 High speed, low distortion, precision monolithic sample and hold amplifier Datasheet

HA5340/883
High Speed, Low Distortion, Precision Monolithic
Sample and Hold Amplifier
June 1994
Features
Description
• This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
The HA-5340/883 combines the advantages of two sample/hold
architectures to create a new generation of monolithic sample/
hold. High amplitude, high frequency signals can be sampled
with very low distortion being introduced. The combination of
exceptionally fast acquisition time and specified/characterized
hold mode distortion is an industry first. Additionally, the AC
performance is only minimally affected by additional hold
capacitance.
• Fast Acquisition Time (0.01%) . . . . . . . . . . . . . . . 900ns
• Fast Hold Mode Settling Time (0.01%) . . . . . . . . . 300ns
• Low Distortion (Hold Mode) . . . . . . . . . . . -72dBc (Typ)
(VIN = 200kHz, Fs = 450kHz, 5VP-P)
• Bandwidth Minimally Affected By External CH
• Fully Differential Analog Inputs
• Built-in 135pF Hold Capacitor
• Pin Compatible with HA-5320
Applications
• High Bandwidth Precision Data Acquisition Systems
• Inertial Navigation and Guidance Systems
• Ultrasonics
To achieve this level of performance, the benefits of an
integrating output stage have been combined with the
advantages of a buffered hold capacitor. To the user this
translates to a front-end stage that has high bandwidth due to
charging only a small capacitive load and an output stage with
constant pedestal error which can be nulled out using the offset
adjust pins. Since the performance penalty for additional hold
capacitance is low, the designer can further minimize pedestal
error and droop rate without sacrificing speed.
Low distortion, fast acquisition, and low droop rate are the
result, making the HA-5340/883 the obvious choice for high
speed, high accuracy sampling systems.
• SONAR
• RADAR
Pinouts
Ordering Information
HA-5340/883 (CERDIP)
TOP VIEW
TEMPERATURE
RANGE
PART NUMBER
-INPUT 1
14 S/H CONTROL
+INPUT 2
13 SUPPLY GND
OFFSET ADJ 3
12 NC
OFFSET ADJ 4
11 EXTERNAL
HOLD CAP
10 NC
V- 5
SIG GND 6
9 V+
OUTPUT 7
8 NC
HA1-5340/883
-55oC
HA4-5340/883
-55oC
to
14 Lead CerDIP
to
+125oC
20 Lead Ceramic LCC
Functional Diagram
CHOLD EXTERNAL
(OPTIONAL)
OFFSET
ADJUST
3
4
11
1 20 19
+IN
18 NC
5
17 NC
OFFSET ADJ
6
16 EXT. HOLD CAP.
NC
7
15 NC
S/H
CONTROL
14
9
14 NC
V- 8
OUT
+V
4
5
13
V+
NC
NC
9 10 11 12 13
SIG
GND
OUTPUT
7
6
SIGNAL
GND
NC
S/H
CNTL
SUPPLY
GND
2
2
-V
-IN
3
CCOMP
15pF
1
SUPPLY
GND
+IN
CHOLD
120pF
-IN
NC
7
*
HA-5340/883 (CLCC)
TOP VIEW
OFFSET ADJ
PACKAGE
+125oC
NOTE: Buffer acts as a buffer in sample mode, acts as a closed switch in hold
mode.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
7-8
Spec Number 511117-883
File Number 2452.1
Specifications HA5340/883
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . . 36V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24V
Digital Input Voltage (S/H Pin) . . . . . . . . . . . . . . . . . . . . . . .+8V, -6V
Output Current, Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±20mA
Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <2000V
Thermal Resistance
θJA
θJC
CerDIP Package . . . . . . . . . . . . . . . . . 68oC/W
17oC/W
Ceramic LCC Package . . . . . . . . . . . . 68oC/W
18oC/W
Package Power Dissipation at +75oC
CerDip Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5W
Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5W
Package Power Dissipation Derating Factor Above +75oC
CerDip Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mW/oC
Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . . 15mW/oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Temperature Range . . . . . . . . . . . . -55oC ≤ TA ≤ +125oC
Operating Supply Voltage (±VS) . . . . . . . . . . . . . . . . . . . . . . . . . . ±15V
Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10V
Logic Level Low (VIL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 0.8V
Logic Level High (VIH) . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0V to 5.0V
TABLE 1. DC ELECTICAL PERFORMANCE CHARACTERISTICS
Device Tested at: V+ = +15V; V- = -15V; VIL = 0.8V (Sample); VIH = 2.0V (Hold); CH = Internal = 135pF; Signal GND = Supply GND,
Unless Otherwise Specified.
PARAMETERS
Input Offset Voltage
SYMBOL
CONDITIONS
VIO
TEMPERATURE
MIN
MAX
UNITS
1
+25oC
-1.5
1.5
mV
-3
3
mV
-350
350
nA
-350
350
nA
-350
350
nA
-350
350
nA
-350
350
nA
-350
350
nA
110
-
dB
100
-
dB
110
-
dB
100
-
dB
72
-
dB
72
-
dB
72
-
dB
72
-
dB
10
-
mA
10
-
mA
-10
-
mA
-10
-
mA
10
-
V
10
-
V
-
-10
V
-
-10
V
2, 3
Input Bias Current
+IB
1
2, 3
-IB
1
2, 3
Input Offset Current
IIO
1
2, 3
Open Loop Voltage Gain
+AVS
-AVS
Common Mode
Rejection Ratio
+CMRR
-CMRR
Output Current
+IO
RL = 2kΩ, CL = 60pF,
VOUT = +10V
1
2, 3
RL = 2kΩ, CL = 60pF,
VOUT = -10V
1
2, 3
V+ = 5V, V- = -25V,
VOUT = -10V, VS/H = -9.2V
V+ = 25V, V- = -5V,
VOUT = +10V, VS/H = 10.8V
VOUT = +10V
1
2, 3
1
2, 3
1
2, 3
-IO
VOUT = -10V
1
2, 3
Output Voltage Swing
+VOP
RL = 2kΩ, CL = 60pF
1
2, 3
-VOP
RL = 2kΩ, CL = 60pF
LIMITS
GROUP A
SUBGROUP
1
2, 3
+125oC,
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
+25oC
+125oC,
CAUTION: These devices are sensitive to electronic discharge. Proper IC handling procedures should be followed.
7-9
-55oC
-55oC
Spec Number
511117-883
Specifications HA5340/883
TABLE 1. DC ELECTICAL PERFORMANCE CHARACTERISTICS (Continued)
Device Tested at: V+ = +15V; V- = -15V; VIL = 0.8V (Sample); VIH = 2.0V (Hold); CH = Internal = 135pF; Signal GND = Supply GND,
Unless Otherwise Specified.
PARAMETERS
Power Supply Current
SYMBOL
+ICC
-ICC
Power Supply Rejection
Ratio
+PSRR
-PSRR
Digital Input Current
IINL
IINH
Digital Input Voltage
CONDITIONS
VOUT = 0V, IOUT = 0mA
VOUT = 0V, IOUT = 0mA
V+ = 13.5V, 16.5V
V- = -15V, -15V
V+ = +15V, +15V,
V- = -13.5V, -16.5V
VIN = 0V
VIN = 5V
VIL
VIH
Output Voltage Droop
Rate
VD
VOUT = 0V
LIMITS
GROUP A
SUBGROUP
TEMPERATURE
MIN
MAX
UNITS
1
+25oC
-
25
mA
2, 3
+125oC, -55oC
-
25
mA
1
+25oC
-25
-
mA
2, 3
+125oC, -55oC
-25
-
mA
1
+25oC
75
-
dB
2, 3
+125oC, -55oC
75
-
dB
1
+25oC
75
-
dB
2, 3
+125oC, -55oC
75
-
dB
1
+25oC
-
40
µA
2, 3
+125oC, -55oC
-
40
µA
1
+25oC
-
40
µA
2, 3
+125oC, -55oC
-
40
µA
1
+25oC
-
0.8
V
2, 3
+125oC, -55oC
-
0.8
V
1
+25oC
2.0
-
V
2, 3
+125oC, -55oC
2.0
-
V
2
+125oC
-
95
µV/µs
TABLE 2. AC ELECTICAL PERFORMANCE CHARACTERISTICS
Device Tested at: V+ = +15V; V- = -15V; VIL = 0.8V (Sample); VIH = 2.0V (Hold); CH = Internal = 135pF; - Input Tied to Output, Signal
GND = Supply GND, Unless Otherwise Specified.
PARAMETERS
Hold Step Error
Rise Time & Fall Time
SYMBOL
VERROR
TR
TF
Overshoot
+OS
-OS
Slew Rate
+SR
-SR
LIMITS
GROUP A
SUBGROUP
TEMPERATURE
MIN
MAX
UNITS
VIL = 0V, VIH = 4.0V,
tRISE(VS/H) = 15ns
4
+25oC
-50
50
mV
CL=60pF, RL=2kΩ, AV = +1,
VOUT = 0V to +200mV Step
10%, 90%pts
4
+25oC
-
50
ns
-
50
ns
CONDITIONS
5, 6
+125oC,
-55oC
CL = 60pF, RL = 2kΩ,
AV = +1, VOUT = 0V to
-200mV Step 10%, 90%pts
4
+25oC
-
50
ns
CL = 60pF, RL = 2kΩ,
AV = +1, VOUT = 0V to
+200mV Step
4
+25oC
-
60
%
-
60
%
-
60
%
-
60
%
40
-
V/µs
40
-
V/µs
40
-
V/µs
40
-
V/µs
5, 6
CL = 60pF, RL = 2kΩ,
AV = +1, VOUT = 0V
to -200mV Step
4
5, 6
CL = 60pF, RL = 2kΩ,
AV = +1, VOUT = 0V to +10V
Step, 25%, 75% pts
CL = 60pF, RL = 2kΩ,
AV = +1, VOUT = 0V to -10V
Step, 25%, 75% pts
4
5, 6
4
5, 6
+125oC,
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
+25oC
+125oC,
CAUTION: These devices are sensitive to electronic discharge. Proper IC handling procedures should be followed.
7-10
-55oC
-55oC
Spec Number
511117-883
Specifications HA5340/883
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
Hold Mode Feedthrough
VHMF
NOTES
TEMPERATURE
MIN
MAX
UNITS
VIN = 20VP-P , 200kHz
1
+25oC
-
-70
dB
En(SAMPLE)
DC to 10MHz, VS/H = 0V,
RLOAD = 2K
1
+25oC
-
335
µVRMS
Hold Mode Noise
Voltage
En(HOLD)
DC to 10MHz, VS/H = 5V,
RLOAD = 2K
1
+25oC
-
100
µVRMS
Input Capacitance
CIN
VS/H = 0V
1
+25oC
-
5
pF
Input Resistance
RIN
VS/H = 0V, Delta VIN = 20V
1
+25oC
1
-
MΩ
CL = 60pF, RL = 2K, VOUT = 0V
to 10V Step
1
+25oC
-
600
ns
Sample Mode Noise
Voltage
CONDITIONS
0.1% Acquisition Time
TACQ 0.1%
Total Harmonic
Distortion Hold Mode
THD200K(HOLD)
FS = 450kHz,
VIN = 20VP-P , 200kHz
1
+25oC
-
-50
dBc
THD500K(HOLD)
FS = 450kHz,
VIN = 5VP-P , 500kHz
1
+25oC
-
-47
dBc
THD200K(SAMPLE)
VIN = 20VP-P , 200kHz
1
+25oC
-
-60
dBc
THD500K(SAMPLE)
VIN = 5VP-P , 500kHz
1
+25oC
-
-49
dBc
Total Harmonic
Distortion Sample Mode
NOTE:
1. The parameters listed in this table are controlled via design or process parameters and are not directly tested. These parameters are
characterized upon initial design release and upon design changes which would affect these characteristics.
TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS
SUBGROUPS (SEE TABLES 1 AND 2)
Interim Electrical Parameters (Pre Burn-In)
-
Final Electrical Test Parameters
1(Note 1), 2, 3, 4, 5, 6
Group A Test Requirements
1, 2, 3, 4, 5, 6
Groups C and D Endpoints
1
NOTE:
1. PDA applies to Subgroup 1 only. No other subgroups are included in PDA.
CAUTION: These devices are sensitive to electronic discharge. Proper IC handling procedures should be followed.
7-11
Spec Number
511117-883
HA-5340/883
Die Characteristics
DIE DIMENSIONS:
84 x 139 x 19mils
METALLIZATION:
Type: Al, 1% Cu
Thickness: 16kÅ ± 2kÅ
GLASSIVATION:
Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos)
Silox Thickness: 12kÅ ± 2.0kÅ
Nitride Thickness: 3.5kÅ ± 1.5kÅ
DIE ATTACH:
Material: Gold Silicon Eutectic Alloy
Temperature:Ceramic DIP - 460oC (Max)
Ceramic LCC - 420oC (Max)
WORST CASE CURRENT DENSITY:
5.33 x 104 A/cm2
Metallization Mask Layout
(11) EXTERNAL
HOLD CAP
HA-5340/883
SUPPLY (13)
GND
S/H (14)
CONTROL
(9) +VSUPPLY
-IN (1)
(7) OUTPUT
(7) OUTPUT
+IN (2)
-VSUPPLY (5)
OFFSET ADJ (4)
OFFSET ADJ (3)
(6) SIG GND
Spec Number
7-12
511117-883
HA-5340/883
Burn-In Circuits
HA-5340/883 DIP BURN-IN/LIFE TEST CIRCUIT
R1
-15V
D2
C2
1
14
2
13
3
12
4
11
5
10
6
9
7
8
+15V
D1
C1
HA-5340/883 LCC BURN-IN/LIFE TEST CIRCUIT
R1
3
2
1
20
19
4
18
5
17
6
16
7
15
14
8
-15V
D2
C2
9
10
11
12
13
+15V
C1
D1
NOTES:
1. R1 = 100kΩ, 5%, 1/4W or 1/2W (per socket).
2. C1, C2 = 0.01µF minimum per socket or 0.1µF minimum per row.
3. D1, D2 = 1N4002 or equivalent (per board).
Spec Number
7-13
511117-883
HA-5340/883
Packaging†
14 PIN CERAMIC DIP
LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic, 90% Alumina
PACKAGE SEAL:
Material: Glass Frit
Temperature: 450oC ± 10oC
Method: Furnace Seal
INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510-D-1
20 PIN CERAMIC LCC
LEAD MATERIAL: Type C
LEAD FINISH: Type A
PACKAGE MATERIAL: Multilayer Ceramic, 90% Alumina
PACKAGE SEAL:
Material: Gold/Tin (80/20)
Temperature: 320oC ± 10oC
Method: Furnace Seal
NOTE:
All Dimensions are
Min
, Dimensions are in inches.
Max
INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510-C-2
Spec Number
7-14
511117-883
HA5340
Semiconductor
DESIGN INFORMATION
High Speed, Low Distortion, Precision
Monolithic Sample and Hold Amplifier
August 1999
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Applying the HA-5340
The HA-5340 has the uncommitted differential inputs of an
op amp, allowing the Sample and Hold function to be combined with many conventional op amp circuits. See the Intersil Application Note 517 for a collection of circuit ideas.
Layout
A printed circuit board with ground plane is recommended
for best performance. Bypass capacitors (0.01 to 0.1µF,
ceramic) should be provided from each power supply terminal to the Supply Ground terminal on pin 13.
The ideal ground connections are pin 6 (SIG. Ground)
directly to the system Signal Ground, and pin 13 (Supply
Ground) directly to the system Supply Common.
Hold Capacitor
The HA-5340 includes a 135pF MOS hold capacitor, sufficient for most high speed applications (the Electrical Specifications section is based on this internal capacitor).
Additional capacitance may be added between pins 7 and
11. This external hold capacitance will reduce droop rate at
the expense of acquisition time, and provide other trade-offs
as shown in the Performance Curves.
The hold capacitor CH should have high insulation resistance and low dielectric absorption, to minimize droop
errors. Teflon, polystyrene and polypropylene dielectric
capacitor types offer good performance over the specified
operating temperature range.
The hold capacitor terminal (pin 11) remains at virtual
ground potential. Any PC connection to this terminal should
be kept short and ‘‘guarded’’ by the ground plane, since
nearby signal lines or power supply voltages will introduce
errors due to drift current.
Teflon is a registered Trademark of Dupont Corporation.
Applications
Figure 1 shows the HA-5340 connected as a unity gain noninverting amplifier – its most widely used configuration. As
an input device for a fast successive – approximation A/D
converter, it offers very high throughput rate for a monolithic
IC sample/hold amplifier. Also, the HA-5340’s hold step error
is adjustable to zero using the Offset Adjust potentiometer,
to deliver a 12-bit accurate output from the converter.
The HA-5340 output circuit does not include short circuit
protection, and consequently its output impedance remains
low at high frequencies. Thus, the step changes in load current which occur during an A/D conversion are absorbed at
the S/H output with minimum voltage error. A momentary
short circuit to ground is permissible, but the output is not
designed to tolerate a short of indefinite duration.
-15V +15V
OFFSET
ADJUST
≈ ±15mV
50KΩ
3
4
CH
5
9
HI-774
11
135pF
1
VIN
S/H CONTROL
H
S
2
7
13
INPUT
14
DIGITAL
OUTPUT
CONVERT
HA- 5340
13
6
5
9
SYSTEM
POWER
GROUND
R/C
ANALOG
COMMON
SYSTEM
SIGNAL
GROUND
FIGURE 1. TYPICAL HA-5340 CONNECTIONS; NONINVERTING UNITY GAIN MODE
NOTE: Pin Numbers Refer to DIP Package Only.
Spec Number
7-15
511117-883
HA5340
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Test Circuits
HOLD STEP ERROR AND DROOP RATE
1
7
-INPUT
2
8
+INPUT
S/H
CONTROL
INPUT
VO
OUTPUT
14
N.C.
11
S/H CONTROL
N.C.
HA-5340
(CH = 135pF = INTERNAL)
HOLD STEP ERROR
1. Observe the ‘‘hold step’’ voltage Vp:
DROOP RATE TEST
1. Observe the voltage ‘‘droop’’, ∆VO/∆T:
HOLD (4.0V)
S/H CONTROL
HOLD (4.0V)
S/H CONTROL
SAMPLE (0V)
SAMPLE (0V)
VO
∆VO
VO
Vp
∆T
2. Measure the slope of the output during hold, ∆VO /∆T.
3. Droop can be positive or negative - usually to one rail or the other
not to GND.
HOLD MODE FEED THROUGH ATTENUATION
+V
VIN
ANALOG
MUX OR
SWITCH
HA-5340
9
1
20Vp-p
200kHz
SINE WAVE
2
AIN
-V
14
5
VOUT
-IN
+IN
OUT
S/H
CONTROL
SUPPLY
GND
13
S/H CONTROL
INPUT
TO
SUPPLY
COMMON
Feedthrough in dB = 20 Log
7
CH
11
N.C.
REF
COM
6
TO
SIGNAL
GND
VOUT where:
VIN
VOUT = Voltsp-p, Hold Mode,
VIN = Voltsp-p.
Spec Number
7-16
511117-883
HA5340
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Performance Curves
VS = ±15V, TA = +25oC, Unless Otherwise Specified.
TACQ POS 0 TO +10 STEP
TACQ vs. ADDITIONAL CH
S/H
CONTROL
S/H
CONTROL
VOUT
VOUT
DROOP RATE vs. HOLD CAPACITOR SIZE
ACQUISITION TIME (0.01%) vs. HOLD CAPACITANCE
HOLD STEP ERROR vs. TRISE
CH = Internal; Temperature +25oC
HOLD STEP ERROR vs. HOLD CAPACITANCE
TRISE = 5ns; Temperature = +25oC
Spec Number
7-17
511117-883
HA5340
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Performance Curves
(Continued) VS = ±15V, TA = +25oC, Unless Otherwise Specified.
HOLD STEP ERROR vs. TEMPERATURE
VIH = 4V, CH = 470pF
HOLD STEP ERROR vs. TEMPERATURE
VIH = 4V, CH = Internal
tr = 5ns, 10ns, 20ns
CLOSED LOOP PHASE/GAIN
AV = +100, ±15V and ±12V Supplies*
CLOSED LOOP PHASE/GAIN
AV = +100
* ±15V and ±12V supplies trace the same line within the width of the
line, therefore only one line is shown.
Spec Number
7-18
511117-883
HA-5340
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Typical Performance Characteristics
PARAMETER
TEMPERATURE
TYP
UNITS
Input Voltage Range
Full
±10
V
Offset Voltage Drift
Full
30
µV/C
Av = +1, VO = 200mVpp, RL = 2K, CL = 60pF
+25oC
10
MHz
Av = +1, VO = 200mVpp, RL = 2K, CL = 60pF
+25oC
9.6
MHz
Gain Bandwidth Product (ChExt = 1000pF) Av = +1, VO = 200mVpp, RL = 2K, CL = 60pF
+25oC
6.7
MHz
Full Power Bandwidth
+25oC
900
KHz
+25oC
0.05
Ω
Gain Bandwidth Product (ChExt = 0pF)
Gain Bandwidth Product (ChExt = 100pF)
CONDITIONS
VO = 20Vpp, RL = 2K, CL = 60pF, Slew Rate
Limited
Output Resistance (Hold Mode)
0.1% Acquisition Time
VO = 10V Step, RL = 2K, CL = 60pF
+25oC
430
ns
0.01% Acquisition Time
VO = 10V Step, RL = 2K, CL = 60pF
+25oC
700
ns
Effective Aperture Delay Time
+25oC
-15
ns
Aperture Uncertainty
+25oC
0.2
ns
1mV Hold Mode Settling Time
+25oC
200
ns
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number
7-19
511117-883
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