Harris HC1-55564-2 Continuously variable slope delta-modulator (cvsd) Datasheet

[ /Title
(HC55564
)
/Subject
(Continuously
Variable
Slope
DeltaModulator
(CVS
D))
/
Autho
r ()
/Keywords
(Harris
Semiconductor
, Telecom,
SLICs
,
SLAC
s,
Telephone,
Telephony,
Low Bit Rate Voiceband Encoders/Decoder
Semiconductor
February 1999
HC-55564
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REP 00-442-7
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.com
COM pplicatio @harris
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Call or email
Continuously Variable
Slope Delta-Modulator (CVSD)
Features
Description
• All Digital
The HC-55564 is a half duplex modulator/demodulator CMOS
intergrated circuit used to convert voice signals into serial NRZ
digital data and to reconvert that data into voice. The conversion is by delta-modulation, using the Continuously Variable
Slope (CVSD) method of modulation/demodulation.
• Requires Few External Parts
• Low Power Drain: 1.5mW Typical From Single 4.5V
To 6V Supply
• Time Constants Determined by Clock Frequency;
No Calibration or Drift Problems: Automatic Offset
Adjustment
• Half Duplex Operation Under Digital Control
• Filter Reset Under Digital Control
• Automatic Overload Recovery
• Automatic “Quiet” Pattern Generation
• AGC Control Signal Available
While the signals are compatible with other CVSD circuits, the internal design is unique. The analog loop filters have been replaced by
very low power digital filters which require no external timing components. This approach allows inclusion of many desirable features
which would be difficult to implement using other approaches.
The fundamental advantages of delta-modulation, along with its
simplicity and serial data format, provide an efficient (low data
rate/low memory requirements) method for voice digitization.
The HC-55564 is usable from 9kbits/s to above 64kbps. See the
Harris Military databook for a MIL-STD-883C compliant CVSD.
Application Note 607.
Applications
• Voice Transmission Over Data Channels (Modems)
• Voice/Data Multiplexing (Pair Gain)
Ordering Information
• Voice Encryption/Scrambling
PART
NUMBER
• Voicemail
• Audio Manipulations: Delay Lines, Time Compression,
Echo Generation/Suppression, Special Effects, etc.
• Pagers/Satellites
• Data Acquisition Systems
• Voice I/O for Digital Systems and Speech Synthesis
Requiring Small Size, Low Weight, and Ease of
Reprogrammability
TEMP.
RANGE (oC)
PACKAGE
PKG. NO.
HC1-55564-2
-55 to 125
14 Ld CERDIP
F14.3
HC1-55564-5
0 to 75
14 Ld CERDIP
F14.3
HC1-55564-9
-40 to 85
14 Ld CERDIP
F14.3
HC3-55564-5
0 to 75
14 Ld PDIP
E14.3
HC9P55564-5
0 to 75
16 Ld Plastic SOIC (W) M16.3
• Related Literature
- AN607, Delta Modulation for Voice Transmission
Pinouts
HC-55564
(PDIP, CERDIP)
TOP VIEW
VDD
1
ANALOG GND 2
AOUT
3
HC-55564
(SOIC)
TOP VIEW
VDD
14 DIG OUT
1
ANALOG GND 2
13 FZ
AOUT
12 DIG IN
3
AGC 4
AGC 4
11 APT
15 FZ
14 DIG IN
13 APT
AIN 5
12 ENC/DEC
10 ENC/DEC
NC 6
11 CLOCK
NC 6
9 CLOCK
NC 7
10 DIG GND
NC 7
8 DIG GND
NC 8
AIN
5
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
16 DIG OUT
© Harris Corporation 1999
1
9 NC
File Number
2889.5
HC-55564
Absolute Maximum Ratings
Thermal Information
Voltage at Any Pin . . . . . . . . . . . . . . . . . . . .GND -0.3V to VDD 0.3V
Maximum VDD Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
98
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range
HC-55564-5, -7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 750C
HC-55564-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 850C
HC-55564-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 1250C
Operating VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 6.0V
Die Characteristics
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1897
Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 x 82
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VDD
Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BiMOSE
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
Unless Otherwise Specified, typical parameters are at 25oC, Min-Max are over operating temperature
ranges. VDD = 5.0V, Sampling Rate = 16Kbps, AG = DG = 0V, AIN = 1.2VRMS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
9
16
64
kbps
-
0.3
1.5
mA
3.5
-
-
V
Note 3
-
-
1.5
V
Note 4
4.0
-
-
V
VOL
Note 4
-
-
0.4
V
30
-
70
%
AIN
AC Coupled (Note 5)
-
0.5
1.2
VRMS
AOUT
AC Coupled (Note 6)
-
0.5
1.2
VRMS
Sampling Rate
CLK
Note 2
Supply Current
IDD
Logic ‘1’ Input
VIH
Note 3
Logic ‘0’ Input
VIL
Logic ‘1’ Output
VOH
Logic ‘0’ Output
Clock Duty Cycle
Audio Input Voltage
Audio Output Voltage
Audio Input Impedance
ZIN
Note 7
-
280
-
kΩ
Audio Output Impedance
ZOUT
Note 7
-
150
-
kΩ
Transfer Gain
AE-D
No Load, Audio In to Audio Out.
-2.0
-
+2.0
dB
Syllabic Filter Time Constant
tSF
Note 8
-
4.0
-
ms
Signal Estimate Filter Time
Constant
tSE
Note 8
1.0
-
-
ms
mVPEAK
AIN at 100Hz (Note 9), (Typ) 0.3% = 15mVRMS
-
6
-
Minimum Step Size
MSS
Note 10
-
0.1
-
%VDD
Quieting Pattern Amplitude
VQP
FZ = 0V or APT = 0V (Note 11)
-
10
-
mVP-P
AGC Threshold
VATH
Note 12
-
0.1
-
F.S.
Clamping Threshold
VCTH
Note 13
-
0.75
-
F.S.
Enc Threshold
NOTES:
2. There is one NRZ (Non-Return Zero) data bit per clock period. Data is clocked out on the negative clock edge. Data is clocked into the
CVSD on the positive going edge (see Figure 2). Clock may be run at less than 9kbps and greater than 64kbps.
3. Logic inputs are CMOS compatible at supply voltage and are diode protected. Digital data input is NRZ at clock rate.
4. Logic outputs are CMOS compatible at supply voltage and will withstand short-circuits to VDD or ground. Digital data output is NRZ and
changes with negative clock transitions. Each output will drive one LS TTL load.
5. Recommended voice input range for best voice performance. Should be externally AC coupled.
6. May be used for side-tone in encode mode. Should be externally AC coupled. Varies with audio input level by ±2dB.
7. Presents series impedance with audio signal. Zero signal reference is approximately VDD/2.
8. Note that filter time constants are inversely proportional to clock rate. Both filters approximate single pole responses.
9. The minimum audio input voltage above which encoding takes place.
10. The minimum audio output voltage change that can be produced by the internal DAC.
11. Settled value, the “quieting” pattern or idle-channel audio output steps at one-half the bit rate, changing state on negative clock transitions.
12. A logic “0” will appear at the AGC output pin when the recovered signal reaches one-half of full-scale value (positive or negative), i.e., at
VDD/2 ±25% of VDD.
13. The recovered signal will be clamped, and the computation will be inhibited, when the recovered signal reaches three-quarters of fullscale value, and will unclamp when it falls below this value (positive or negative).
2
HC-55564
Pin Descriptions
PIN NUMBER
14 LEAD DIP
SYMBOL
1
VDD
2
Analog GND
3
AOUT
Audio Out recovered from 10-bit DAC. May be used as side tone at the transmitter. Presents
approximately 150kΩ source with DC offset of VDD/2. Within ±2dB of Audio Input. Should be externally AC coupled.
4
AGC
Automatic Gain Control output. A logic low level will appear at this output when the recovered
signal excursion reaches one-half of full scale value. In each half cycle full scale is VDD /2. The
mark-space ratio is proportional to the average signal level.
5
AIN
Audio Input to comparator. Should be externally AC coupled. Presents approximately 280kΩ in
series with VDD/2.
6, 7
NC
No internal connection is made to these pins.
8
Digital GND
9
Clock
Sampling rate clock. In the decode mode, must be synchronized with the digital input data such
that the data is valid at the positive clock transition. In the encode mode, the digital data is clocked
out on the negative going clock transition. The clock rate equals the data rate.
10
Encode/
Decode
A single CVSD can provide half-duplex operation. The encode or decode function is selected by the
logic level applied to this input. A low level selects the encode mode, a high level the decode mode.
11
APT
Alternate Plain Text input. Activating this input caused a digital quieting pattern to be transmitted, however; internally the CVSD is still functional and a signal is still available at the AOUT port. Active low.
12
Digital In
13
FZ
14
Digital Out
DESCRIPTION
Positive Supply Voltage. Voltage range is 4.5V to 6.0V.
Analog Ground connection to D/A ladders and comparator.
Logic ground. 0V reference for all logic inputs and outputs.
Input for the received digital NRZ data.
Force Zero input. Activating this input resets the internal logic and forces the digital output and the
recovered audio output into the “quieting” condition. An alternating 1-0 pattern appears at the
digital output at 1/2 the clock rate. When this is decoded by a receive CVSD, a 10mVP-P inaudible
signal appears at audio output. Active low.
Output for transmitted digital NRZ data.
NOTE:
14. No active input should be left in a “floating condition.”
Functional Diagram
(DIP Pin Numbers Shown)
(1)
(12)
DIGITAL
IN
VDD
3V TO 6V
(10)
ENC/DEC
(11) (13) FORCE
APT
ZERO
VDD
2
RESET
T
(5)
(9)
(8)
CLOCK
F/F
Q
D
AIN
ZIN
(2)
ANALOG
GND
COMPARATOR
10 BIT
DAC
10
10
(3) AOUT
(SIDE TONE)
ZOUT
(14)
DIGITAL
OUT
3 BIT
SHIFT
REGISTER
STEP
SIZE
LOGIC
RESET
SIGNAL
ESTIMATE
FILTER 1msec
DIGITAL
GND
6
DIGITAL
MODULATOR
±1
SYLLABIC
FILTER
4ms
10 BIT
DAC
RESET
(4) AGC OUT
3
HC-55564
Timing Waveforms
SAMPLING CLOCK
FZ/APT
DEC/ENC
DIGITAL NRZ IN
1
0
1
tDS
0
DIGITAL NRZ OUT
0
1
1
tDS: DATA SET UP TIME 100ns TYPICAL
FIGURE 2. CVSD TIMING DIAGRAM
Interface Circuit for HC-55564 CVSD
(DIP Pin Numbers Shown)
AUDIO SOURCE
TP3040
1
RC
INPUT
LEVEL ADJUST
RA, RB, CA
OPTIONAL
2
3
CA
4
RA
RB 5
5V
-5V
9
8
VFX1+
VFX1-
VFX0
GSX
VFRI
6
5
0.1µ
10
CLK0
VBB
PDN
GNDD
14
13
EXTERNAL
CONTROL
CLK
AIN
DIN
AOUT
APT
VDD
E/D
0.1µ
8
11
AGC
DOUT
FZ
1
VCC
15
3
0.1µ
RD (NOTE)
PWRI
0.1µ
4
AUDIO OUT
16
VFR0
GNDA
0.1µ
HC-55564
PWR0+
DIGITAL ANALOG
GND
GND
CLK
12
14
12
(TO DATA I/F)
(FROM DATA I/F)
13
11
10
EXTERNAL
CONTROL
2
9
÷n
NOTE: RD = 100kΩ to 1MΩ
CLK GEN
only to Pin 2.
CVSD Hookup for Evaluation
5. Digital inputs and outputs are compatible with standard
CMOS logic using the same supply voltage. All unused
logic inputs must be tied to the appropriate logic level for
desired operation. It is recommended that unused inputs
tied high be done so through a pull-up resistor (1kΩ to
10kΩ). TTL outputs will require 1kΩ pull-up resistors. Pins
4 and 14 will each drive CMOS logic or one low power TTL
input.
The circuit in Figure 3 is sufficient to evaluate the voice quality of the CVSD, since when encoding, the feedback signal at
the audio output pin is the reconstructed audio input signal.
CVSD design considerations are as follows:
1. Care should be taken in layout to maintain isolation
between analog and digital signal paths for proper noise
consideration.
6. Since the Audio Out pins are internally DC biased to VDD/2,
AC coupling is required. In general, a value of 0.1µF is sufficient for AC coupling of the CVSD audio pins to a filter circuit.
2. Power supply decoupling is necessary as close to the
device as possible. A 0.1µF should be sufficient.
3. Ground, then power, must be present before any input signals are applied to the CVSD. Failure to observe this may
cause a latchup condition which may be destructive.
Latchup may be removed by cycling the power off/on. A
power-up reset circuit may be used that strobes Force
Zero (Pin 13) during power-up as follows:
7. The AGC output may be externally integrated to drive an
AGC pre-amp, or it could drive an LED indicator through a
buffer to indicate proper speaking volume.
VDD
R
4. Analog (signal) ground (Pin 2) should be externally tied to
Digital GND (Pin 8) and power supply ground. It is recommended that the AIN and AOUT ground returns connect
(13)
C
4
FZ
HC-55564
clock rate. The flat bandwidth at 0dB doubles for every
doubling in sampling rate. The output levels were measured in the encode mode, without filtering, from AIN to
AOUT, at VDD = 5V. 0dB = 1.2VRMS.
Figures 4, 5, and 6 illustrate the typical frequency
response of the HC-55564 for varying input levels and for
varying sampling rates. To prevent slope overload (slew
limiting), the 0dB boundary should not be exceeded. The
frequency response is directly proportional to the sampling
AOUT
0dB = INPUT SIGNAL LEVEL
AIN
-10
-6dB
-12dB
-20
dB
-18dB
-24dB
-30
-30dB
-36dB
-40
100
1000
10000
INPUT FREQUENCY AT AIN (Hz)
FIGURE 4. 16kbps
AOUT
0dB = INPUT SIGNAL LEVEL
AIN
-10
-6dB
-12dB
-20
dB
-18dB
-24dB
-30
-30dB
-40
-36dB
100
1000
INPUT FREQUENCY AT AIN (Hz)
10000
FIGURE 5. 32kbps
AOUT
0dB = INPUT SIGNAL LEVEL
-10
-6dB
-12dB
-20
-18dB
dB
AIN
-24dB
-30
-30dB
-40
-36dB
100
1000
INPUT FREQUENCY AT AIN (Hz)
FIGURE 6. 64kbps
5
10000
HC-55564
and 3rd harmonic distortion, an HP-3582A spectrum
analyzer. All measurement conditions were at VDD = 5V, and
2nd and 3rd harmonic distortion measurements were Cmessage filtered. 0dB = 1.2VRMS.
The following typical performance distortion graphs were
realized with the test configuration of Figure 7. The
measurement vehicle for Total Harmonic Distortion (THD)
was an HP-339A distortion measurement set, and for 2nd
HC-55564
0.33µF
5
FUNCT.
GEN.
1
AOUT
AIN
0.33µF
3
HP3582A
SPECTRUM
ANALYZER
OR HP339A
DISTORTION
ANALYZER
C-MESSAGE
FILTER
DEC/ 10
ENC
11
8
APT
DGND
13
2
FZ
AGND
VDD
-20
THD
(dB)
-30
-16
-8
VIN = 0.5VRMS
16kHz CLOCK
16kHz CLOCK
3RD
-20
-30
2ND
-40
-50
-24
-50
-11
-3.8
+3.0
3RD
-30
-40
-17
0
CVSD SIGNAL TO 2ND AND 3RD HARMONIC DISTORTION
C-MESSAGE WEIGHTED
dB
dB
3%
-10
INPUT
-20 FREQUENCY 1kHz
2ND
0
1000
INPUT SIGNAL LEVEL (dB)
2000
3000
INPUT FREQUENCY (Hz)
FIGURE 9A.
FIGURE 10A.
CVSD INPUT LEVEL vs 2ND AND 3RD HARMONIC DISTORTION
C-MESSAGE WEIGHTED
CVSD SIGNAL TO 2ND AND 3RD HARMONIC DISTORTION
C-MESSAGE WEIGHTED
-10
-10
INPUT
FREQUENCY 1kHz
-20
dB
-30
2ND
-40
-50
-24
VIN = 0.5VRMS
32kHz CLOCK
-20
32kHz CLOCK
3RD
dB
64KHz
FIGURE 8. CVSD SIGNAL LEVEL vs TOTAL HARMONIC
DISTORTION
-10
-30
2ND
-40
-50
3RD
-60
-17
-11
-3.8
0
+3.0
1000
INPUT SIGNAL LEVEL (dB)
2000
3000
4000
INPUT FREQUENCY (Hz)
FIGURE 9B.
FIGURE 10B.
CVSD INPUT LEVEL vs 2ND AND 3RD HARMONIC DISTORTION
C-MESSAGE WEIGHTED
CVSD SIGNAL TO 2ND AND 3RD HARMONIC DISTORTION
C-MESSAGE WEIGHTED
-10
-10
INPUT
64kHz CLOCK
VIN = 0.5VRMS
64kHz CLOCK
-20
FREQUENCY 1kHz
-30
dB
dB
10%
INPUT SIGNAL LEVEL (dB)
CVSD INPUT LEVEL vs 2ND AND 3RD HARMONIC DISTORTION
C-MESSAGE WEIGHTED
2ND
-40
-30
-40
2ND
-50
3RD
-50
-24
32KHz
1%
-40
-24
FIGURE 7. TEST AND MEASUREMENT CIRCUIT
-20
INPUT
FREQ. = 1kHz
16KHz
+1.0µF
5V
30%
-10
3RD
-60
-17
-11
-3.8
0
+3.0
INPUT SIGNAL LEVEL (dB)
1000
2000
3000
INPUT FREQUENCY (Hz)
FIGURE 9C.
FIGURE 10C.
FIGURE 9. CVSD INPUT LEVEL vs 2ND AND 3RD HARMONIC
DISTORTION
FIGURE 10. CVSD INPUT FREQUENCY vs 2ND AND 3RD
HARMONIC DISTORTION
6
4000
HC-55564
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1
F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)
LEAD FINISH
14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
-A-
BASE
METAL
INCHES
(c)
SYMBOL
E
M
-Bbbb S
C A-B S
Q
-C-
SEATING
PLANE
S1
-
0.200
-
5.08
-
0.014
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.785
-
19.94
5
E
0.220
0.310
5.59
7.87
5
eA
b2
b
ccc M
C A-B S
e
D S
eA/2
NOTES
b
α
A A
MAX
A
A
L
MIN
M
(b)
D
BASE
PLANE
MAX
b1
SECTION A-A
D S
MILLIMETERS
MIN
c
e
aaa M C A - B S D S
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
-
7
α
90o
105o
90o
105o
-
aaa
-
0.015
-
0.38
-
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
N
14
14
8
Rev. 0 4/94
7
HC-55564
Dual-In-Line Plastic Packages (PDIP)
E14.3 (JEDEC MS-001-AA ISSUE D)
N
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
-B-AE
D
BASE
PLANE
A2
-C-
SEATING
PLANE
A
L
D1
e
B1
D1
B
0.010 (0.25) M
A1
eC
C A B S
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.15
1.77
8
eA
C
0.008
0.014
D
0.735
0.775
C
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm).
8
0.204
0.355
18.66
19.68
5
D1
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
eA
0.300 BSC
eB
-
L
0.115
N
14
2.54 BSC
-
7.62 BSC
6
0.430
-
0.150
2.93
14
10.92
7
3.81
4
9
Rev. 0 12/93
HC-55564
Small Outline Plastic Packages (SOIC)
M16.3 (JEDEC MS-013-AA ISSUE C)
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
-B1
2
3
L
SEATING PLANE
-A-
A
D
hx
-C-
e
0.25(0.010) M
C
0.10(0.004)
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.3977
0.4133
10.10
10.50
3
E
0.2914
0.2992
7.40
7.60
4
e
α
A1
B
45o
B S
0.050 BSC
9
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
N
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
MILLIMETERS
α
16
0
o
16
8
o
0
o
7
8
o
Rev. 0 12/93
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