HD66730/HD66731 (Dot-Matrix Liquid Crystal Display Controller/Driver Supporting Japanese Kanji, Korean Font Display) Description The HD66730/1 is a dot-matrix liquid crystal display controller (LCD) and driver LSI that displays Japanese characters consisting of kanji, hiragana and katakana according to the Japanese Industrial Standard (JIS) Level-1 Kanji Set. The HD66730/1 incorporates the following five functions on a single chip: (i) display control function for the dot matrix LCD, (ii) a display RAM to store character codes, (iii) ROM fonts to support kanji, (iv) liquid crystal driver, and (v) a booster to drive the LCD. A two 6-character (HD66730) or four 10-character (HD66731) kanji display can easily be achieved by receiving character codes (2 bytes/character) from the MPU. The font ROM includes 2,965 kanji from the JIS Level-1 Kanji Set, 524 JIS non-kanji characters, and 128 half-size alphanumeric characters and symbols. Full-size fonts such as Japanese kanji and half-size of fonts such as alphanumeric characters can be displayed together. In addition, display control equivalent to full bit mapping can be performed through horizontal and vertical dot-by-dot smooth scroll functions for each display line. To help make systems more compact, a three-line clock synchronous serial transfer method is adopted in addition to an 8-bit bus for interfacing with a microcomputer. Features • Dot-matrix liquid crystal display controller/driver supporting the display of kanji according to JIS Level-1 Kanji Set • Large character generator ROM: 510 kbits Kanji according to JIS Level-1 Kanji Set (11 × 12 dots): 2,965-character font JIS non-kanji (11 × 12 dots): 524-character font Half-size alphanumeric characters and symbols (5 × 12 dots): 128-character font • Display of 11 × 12 dots for full-size fonts consisting of kanji and kana, 5 × 12 dots for half-size fonts of alphanumeric characters and symbols in the same display • 2-line 6-character full-size font display with a single chip (HD66730) • 4-line 10-character full-size font display with a single chip (HD66731) • Expansion driver interface: maximum 2-line 20-character (or 4-line 10-character) display (HD66730) • Dot matrix font and 71 marks and icons (96 at HD66731) 1 HD66730/HD66731 • Various display control functions: horizontal smooth scroll (in dot units), vertical smooth scroll, white black inversion/blinking/white black inversion blinking character display, cursor display, display on/off • Display data RAM: 40 × 2 bytes (stores codes to support 40 characters in a full-size font) • Character generator RAM: 8 × 26 bytes (displays 8 characters of a 12 × 13 dot user font) • 16-byte 96-segment RAM • Three-line clock synchronous serial bus, 8-bit bus interface • Built-in double/triple liquid-crystal voltage booster circuit and built-in oscillator (operating frequency can be adjusted through external resistors) • Operating power supply voltage: 2.4V to 5.5V; liquid crystal display voltage: 3.0V to 13.0V • HD66730: QFP 1420-128 (0.5 mm pitch), bare-chip • HD66731: TCP-171 (straight), TCP-206 (bent), chip with bump List 1 Programmable Duty Cycles Duty Drive Setting Number of Display Characters in Full-Size Font Number of Segments/Marks HD66730 HD66731 HD66730 HD66731 1/14 One 6-character One 10-character 71pcs 96pcs 1/27 Two 6-character Two 10-character 71pcs 96pcs 1/40 — Three 10-characters — 96pcs 1/53 — Four 10-characters — 96pcs Ordering Information Type No. Package Number of Display character CGROM HD66730A00FS FP-128 Two 6-characters JIS Level-1 Kanji (A00) HCD66730A00 Bare chip Two 6-characters HD66731A00TA0L Straight TCP Three 8-characters HD66731A00TB0L Bending TCP Four 10-characters HCD66731A00BP Au-bumped chip Four 10-characters HD66730A01FS FP-128 Two 6-characters HCD66730A01 Bare chip Two 6-characters HD66731A01TA0L Straight TCP Three 8-characters HD66731A01TB0L Bending TCP Four 10-characters HCD66731A01BP Au-bumped chip Four 10-characters 2 Korean font (A01) HD66730/HD66731 Block Diagram (HD66730) OSC1 OSC2 Oscillation circuit (CPG) CL1 CL2 M Timing generator RESET* Control register (R0 to R7) Index register (I DR) COM25/ COMD 7 8 RS/CS* E/SCLK RAM address counter (RAR: R8) COM1 to COM24 COMS SEGD DB0/SOD I/O buffer RAM data register (RDR: R9) 8 Segment RAM (SEGRAM) 16 bytes Vci Booster Character generator RAM (CGRAM) 208 bytes Character Character generator generator ROM for ROM for full-size half-size character font character font (FCGROM) (HCGROM) 506,880 bits 9,216 bits (704 b × 720 w) (768 b × 12 w) 12 12 71-bit latch circuit Segment driver Address generator 3 7 12 8 C2 V5OUT2 71-bit shift register 8 8 Busy flag (BF) SEG1 to SEG71 8 4 V5OUT3 Common driver 8 8 DB1 to DB7 25-bit shift register 7 System interface • Serial • 8 bit RW/SID C1 Display data RAM (DDRAM) 80 × 8 bits 4 IM LCD drive voltage selector 11 Display attribute control circuit 12 12 Cursol control circuit Parallel/serial converter and scroll control circuit VCC GND V1 V2 V3 V4 V5 3 HD66730/HD66731 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 Pin Arrangement (HD66730) HD66730 (Top view) 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 VCC RESET* OSC2 OSC1 CL1 CL2 SEGD M RW/SID RS/CS* E/SCLK IM DB0/SOD DB1 DB2 DB3 DB4 DB5 DB6 DB7 GND Vci C2 C1 V5OUT2 V5OUT3 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 4 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COMS COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25/COMD V1 V2 V3 V4 V5 HD66730/HD66731 TCP Dimensions (HD66731TA0: Three 8-characters) LCD Driver Output COM19 Dummy Dummy SEG1 COMS COM1 COM20 SEG96 0.24mm pitch 0.80mm pitch NC VCC OSC2 OSC1 TESED RESET* RW/SID RS/CS* E/SCLK IM DB0/SOD DB1 DB2 DB3 DB4 DB5 DB6 DB7 GND Vci C2 C1 V5OUT2 V5OUT3 V5 V4 V3 V2 V1 NC Dummy Dummy COM40 0.24p × (141–1) = 33.60mm 0.8p × (30–1) = 23.2mm I/O, Power Supply 5 NC VCC OSC2 OSC1 TESED RESET* RW/SID RS/CS* E/SCLK IM DB0/SOD DB1 DB2 DB3 DB4 DB5 DB6 DB7 GND Vci C2 C1 V5OUT2 V5OUT3 V5 V4 V3 V2 V1 NC 6 0.20mm pitch 0.80mm pitch 0.8p × (30–1) = 23.2mm I/O, Power Supply COM19 COM46 COM51 Dummy Dummy SEG1 COMS COM1 COM20 SEG119 Dummy Dummy COM53 COM45 HD66730/HD66731 TCP Dimensions (HD66731TB0: Four 10-characters) LCD Driver Output 0.20p × (176–1) = 35.0mm HD66730/HD66731 The Location of Bonding Pads (HD66730) HCD66730 1 pin 128 pin Chip size (X × Y): Coordinate: Origin: Pad size (X × Y): 99 pin 4 pin HD66730 Type code 7.48 × 6.46 mm2 Pad center Chip center 100 × 100 µm2 Y 68 pin 35 pin (unit: µm) X Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Coordinate Function SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 X –2602 –2984 –3263 –3522 –3522 –3522 –3522 –3522 –3522 –3522 –3522 –3522 –3522 –3522 –3522 –3522 –3522 –3522 –3522 –3522 –3522 –3522 –3522 –3522 –3522 –3522 –3522 –3522 –3522 –3522 Y 3012 3012 3012 3012 2782 2582 2341 2161 1981 1801 1621 1440 1260 1030 800 620 439 259 79 –101 –281 –462 –642 –822 –1002 –1182 –1363 –1543 –1723 –1939 Pin No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Coordinate Function SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 VCC RESET* OSC2 OSC1 CL1 CL2 SEGD M RW/SID RS/CS* E/SCLK IM DB0/SOD DB1 DB2 DB3 DB4 DB5 DB6 DB7 GND Vci X –3522 –3522 –3522 –3522 –3522 –3160 –2860 –2660 –2435 –2233 –2063 –1859 –1689 –1519 –1349 –1179 –975 –771 –567 –363 –146 71 287 504 721 938 1154 1371 1533 1730 Y –2183 –2364 –2544 –2774 –2984 –2984 –2984 –2984 –2984 –2984 –2984 –2984 –2984 –2984 –2984 –2984 –2984 –2984 –2984 –2984 –2984 –2984 –2984 –2984 –2984 –2984 –2984 –2984 –2984 –2959 Pin No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 Coordinate Function C2 C1 V5OUT2 V5OUT3 V5 V4 V3 V2 V1 COM25/D COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 X 1896 2057 2219 2478 2782 3016 3253 3522 3522 3522 3522 3522 3522 3522 3522 3522 3522 3522 3522 3522 3522 3522 3522 3522 3522 3522 3522 3522 3522 3522 Y –2959 –2959 –2959 –2959 –2984 –2984 –2984 –2984 –2806 –2626 –2445 –2265 –2085 –1855 –1625 –1444 –1264 –1084 –854 –624 –443 –263 –83 97 277 458 638 818 998 1178 7 HD66730/HD66731 Pin No. 91 92 93 94 95 96 97 98 99 100 101 102 103 8 Coordinate Function COM4 COM3 COM2 COM1 COMS SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 X 3522 3522 3522 3522 3522 3522 3522 3522 3522 3222 2942 2662 2332 Y 1409 1639 1819 1999 2179 2410 2590 2819 3012 3012 3012 3012 3012 Pin No. 104 105 106 107 108 109 110 111 112 113 114 115 116 Coordinate Function SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 X 2152 1972 1791 1611 1431 1251 1071 890 710 530 350 170 –11 Y 3012 3012 3012 3012 3012 3012 3012 3012 3012 3012 3012 3012 3012 Pin No. 117 118 119 120 121 122 123 124 125 126 127 128 Coordinate Function SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 X –191 –371 –551 –731 –912 –1092 –1272 –1452 –1632 –1813 –1993 –2173 Y 3012 3012 3012 3012 3012 3012 3012 3012 3012 3012 3012 3012 HD66730/HD66731 The Location of Bonding Pads (HD66731) • Chip size : 7.48 × 6.46mm2 • Coordinate : Pad center • Origin : Chip center • Au bumped distance : 80µm (Min.) : 100µm × 50µm Dummy1 Dummy18 Dummy17 Dummy16 Dummy15 Dummy14 Dummy13 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SRG32 SEG31 SEG30 SEG29 Dummy12 Dummy11 Dummy10 Dummy9 Dummy8 Dummy7 Dummy6 • Bump size 158 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 157 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 98 99 HD66731 Type Code HD66731 (Top view) COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 CON38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM53 VCC VCC VCC VCC VCC COMS COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 CON10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM46 COM47 COM48 COM49 COM50 COM51 V1 V1 V2 V2 V3 V3 Dummy5 Y X 39 V4 Dummy4 V5 V4 V5 V5 V5OUT3 V5OUT3 V5OUT2 V5OUT2 C1 V5OUT2 C1 C1 C2 C2 Vci C2 Vci Vci GND GND DB7 GND DB6 DB5 DB4 DB3 DB2 DB1 IM DB0/SOD RS/CS* E/SCLK RW/SID RESET* OSC1 TESTD OSC2 Dummy3 Dummy2 38 1 221 9 HD66730/HD66731 Pin No. — 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 — — 39 40 41 42 43 44 10 Coordinate Function Dummy3 OSC2 OSC1 TESTD RESET* RW/SID RS/CS E/SCLK IM DB0/SOD DB1 DB2 DB3 DB4 DB5 DB6 DB7 GND GND GND Vci Vci Vci C2 C2 C2 C1 C1 C1 V5OUT2 V5OUT2 V5OUT2 V5OUT3 V5OUT3 V5 V5 V5 V4 V4 dummy4 dummy5 V3 V3 V2 V2 V1 V1 X –3202 –2926 –2722 –2543 –2339 –2135 –1931 –1727 –1523 –1306 –1090 –873 –656 –439 –223 –6 211 373 509 645 781 917 1053 1189 1325 1461 1597 1733 1869 2005 2141 2277 2413 2549 2685 2821 2957 3093 3229 3474 3474 3474 3474 3474 3474 3474 3474 Y –2984 –2984 –2984 –2984 –2984 –2984 –2984 –2984 –2984 –2984 –2984 –2984 –2984 –2984 –2984 –2984 –2984 –2971 –2971 –2971 –2971 –2971 –2971 –2971 –2971 –2971 –2971 –2971 –2971 –2971 –2971 –2971 –2971 –2971 –2971 –2971 –2971 –2971 –2971 –2971 –2699 –2563 –2427 –2291 –2155 –2019 –1883 Pin No. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 Coordinate Function COM51 COM50 COM49 COM48 COM47 COM46 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COMS SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 X 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 Y –1621 –1541 –1460 –1379 –1298 –1218 –1137 –1056 –975 –895 –814 –733 –652 –572 –491 –410 –329 –249 –168 –87 –6 74 155 236 317 397 559 640 720 801 882 963 1043 1124 1205 1286 1366 1447 1528 1609 1689 1770 1851 1932 2012 2093 2174 Pin No. 92 93 94 95 96 97 98 — — — — — — — 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 Coordinate Function SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 dummy6 dummy7 dummy8 dummy9 dummy10 dummy11 dummy12 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 X 3474 3474 3474 3474 3474 3474 3474 3474 3202 3066 2930 2794 2658 2522 2343 2262 2182 2101 2020 1939 1859 1778 1697 1616 1536 1455 1374 1293 1213 1132 1051 970 890 809 728 647 567 468 405 324 244 163 82 1 –79 –160 –241 Y 2255 2335 2416 2497 2578 2658 2739 3027 3027 3027 3027 3027 3027 3027 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 HD66730/HD66731 Pin No. 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 — — — — — — — Coordinate Function SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 dummy13 dummy14 dummy15 dummy16 dummy17 dummy18 dummy1 X –322 –402 –483 –564 –645 –725 –806 –887 –968 –1048 –1129 –1210 –1291 –1371 –1452 –1533 –1614 –1694 –1775 –1856 –1937 –2017 –2098 –2179 –2260 –2340 –2522 –2658 –2794 –2930 –3066 –3202 –3474 Y 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 3027 3027 3027 3027 3027 3027 3027 Pin No. 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 Coordinate Function SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 COM20 X –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 Y 2728 2647 2567 2486 2405 2324 2244 2163 2082 2001 1921 1840 1759 1678 1598 1517 1436 1355 1275 1194 1113 1032 952 871 79 709 629 548 467 386 306 225 63 Pin No. 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 — Coordinate Function COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM53 VCC VCC VCC VCC VCC dymmy2 X –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 –3474 Y –17 –98 –179 –260 –340 –421 –502 –583 –663 –744 –825 –906 –986 –1067 –1148 –1229 –1309 –1390 –1471 –1552 –1632 –1713 –1794 –1875 –1955 –2036 –2169 –2305 –2441 –2577 –2713 –2984 11 HD66730/HD66731 Pin Function (HD66730) Table 1 Pin Functional Description Signal Number of Pins I/O Device Interfaced with RESET* 1 I — Acts as a reset input pin. The LSI is initialized during low level. Refer to Reset Function. Must be reset after power-on. IM 1 I — Selects interface mode with the MPU; Low: Serial mode High: 8-bit bus mode RS/CS* 1 I MPU Selects registers during bus mode: Low: Index register (write); Status register (read) High: Control register (write); RAM data (read/write) Acts as chip-select during serial mode: Low: Select (access enable) High: Not selected (access disable) RW/SID 1 I MPU Selects read/write during bus mode; Low: Write High: Read Inputs serial data during serial mode. E/SCLK 1 I MPU Starts data read/write during bus mode; Inputs (Receives) serial clock during serial mode. DB1 to DB7 7 I/O MPU Seven high-order bidirectional tristate data bus pins. Used for data transfer between the MPU and the HD66730. DB7 can be used as a busy flag. Open these pins during serial mode since these signals are not used. DB0/ SOD 1 I/O /O MPU The lowest bidirectional data bit (DB0) during bus mode. Outputs (transmits) serial data during serial mode. Open this pin if reading (transmission) is not performed. SEG1 to SEG71 71 O LCD Display data output signals for the segment extension driver. COMS 1 O LCD Acts as a common output signal for segment display. Used to display icon and marks beside the character display. COM1 to COM24 24 O LCD Acts as common output signals for character display. COM15 toCOM24 become non-selective waveforms when the duty ratio is 1/14. COM25/ COMD 1 O LCD/ extension driver Acts as common output sign al (COM25) for character display when EXT2 bit is 0. Acts as a common extension pulse signal (COMD) when EXT2 bit is 1. The pin is grounded after RESET input is cleared. When this signal is used as COMD, GND ≥ V5 must be maintained. 12 Function HD66730/HD66731 Table 1 Pin Functional Description (cont. HD66730) Signal Number of Pins I/O Device Interfaced with CL1 1 O Extension driver Outputs the latch pulse of segment extension driver.Cam also be used as a shift clock of common extention driver. Exters tristate when both EXT1 and EXT2 are 0. CL2 1 O Extension driver Outputs shift clock of segment extension driver. Can also be used as a common extension driver latch clock. Enters tristate when both EXT1 and EXT2 are 0. SEGD 1 O Extension driver Outputs data of extension driver. Data after the 72nd dot is output. Enters tristate when EXT1 bit is 0. M 1 O Extension driver Acts as an alternating current signal of extension driver. Enters tristate when both EXT1 and EXT2 bits are 0. V1 to V5 5 — Power supply Power supply for LCD drive VCC – V5 = 15V (max) VCC/GND 2 — Power supply VCC: +2.4V to +5.5V, GND: 0V OSC1/ OSC2 2 — Oscillation resistor/ clock When crystal oscillation is performed, an external resistor must be connected. When the pin input is an external clock, it must be input to OSC1. Vci 1 I — Inputs voltage to the booster to generate the liquid crystal display drive voltage. Vci is reference voltage and power supply for the booster. Vci: 1.0V to 5.0V ≤ VCC. V5OUT2 1 O V5 pin/ booster capacitor Voltage input to the Vci pin is boosted twice and output. When the voltage is boosted three times, a capacitor with the same capacitance as that of C1–C2 should be connected here. V5OUT3 1 O V5 pin Voltage input to the Vci pin is boosted three times and output. C1/C2 2 — Booster capacitor External capacitor should be connected here when using the booster. Function 13 HD66730/HD66731 Pin Function (HD66731) Table 2 Pin Functional Description Signal Number of Pins I/O Device Interfaced with RESET* 1 I — Acts as a reset input pin. The LSI is initialized during low level. Refer to Reset Function. Must be reset after power-on. IM 1 I — Selects interface mode with the MPU; Low: Serial mode High: 8-bit bus mode RS/CS* 1 I MPU Selects registers during bus mode: Low: Index register (write); Status register (read) High: Control register (write); RAM data (read/write) Acts as chip-select during serial mode: Low: Select (access enable) High: Not selected (access disable) RW/SID 1 I MPU Selects read/write during bus mode; Low: Write High: Read Inputs serial data during serial mode. E/SCLK 1 I MPU Starts data read/write during bus mode; Inputs (Receives) serial clock during serial mode. DB1 to DB7 7 I/O MPU Seven high-order bidirectional tristate data bus pins. Used for data transfer between the MPU and the HD66731. DB7 can be used as a busy flag. Open these pins during serial mode since these signals are not used. DB0/ SOD 1 I/O /O MPU The lowest bidirectional data bit (DB0) during bus mode. Outputs (transmits) serial data during serial mode. Open this pin if reading (transmission) is not performed. SEG1 to SEG119 119 O LCD Display data output signals for the segment extension driver. COMS 1 O LCD Acts as a common output signal for segment display. Used to display icon and marks beside the character display. COM1 to COM51 51 O LCD Acts as common output signals for character display. COM14 acts as same as COMS when 1/14 duty. COM27 acts as same as COMS when 1/27 duty. COM40 acts as same as COMS when 1/40 duty. Unused common pins output non-selective waveforms. COM53 1 O LCD Acts as common output signal for segment display when 1/53 duty. The waveform is same as coms. This COM53 outputs non-selective waveform when another duty. 14 Function HD66730/HD66731 Table 2 Pin Functional Description (cont. HD66731) Signal Number of Pins I/O Device Interfaced with V1 to V5 5 — Power supply Power supply for LCD drive VCC – V5 = 15V (max) VCC/GND 2 — Power supply VCC: +2.4V to +5.5V, GND: 0V OSC1/ OSC2 2 — Oscillation resistor/ clock When crystal oscillation is performed, an external resistor must be connected. When the pin input is an external clock, it must be input to OSC1. Vci 1 I — Inputs voltage to the booster to generate the liquid crystal display drive voltage. Vci is reference voltage and power supply for the booster. Vci: 1.0V to 5.0V ≤ VCC. V5OUT2 1 O V5 pin/ booster capacitor Voltage input to the Vci pin is boosted twice and output. When the voltage is boosted three times, a capacitor with the same capacitance as that of C1–C2 should be connected here. V5OUT3 1 O V5 pin Voltage input to the Vci pin is boosted three times and output. C1/C2 2 — Booster capacitor External capacitor should be connected here when using the booster. TESTD 1 O — Test pin. Must be left disconnected. Dummy1 to Dummy18 18 — — Dummy pads. These pads are electrically floating level. Function 15 HD66730/HD66731 Function Description System Interface The HD66730/1 has two system interfaces: a synchronized serial one and an 8-bit bus. Both are selected by the IM pin. The HD66730/1 has five types of 8-bit registers: an index register (IDR), status register (STR), various control registers, RAM address register (RAR), and RAM data register (RDR). The index register (IDR) selects control registers, the RAM address register (RAR) or the RAM data register (RDR) for performing data transfer. The status register (STR) indicates the internal state of the system. Various control registers store display control data here. The RAM address register (RAR) stores the address data of display data RAM (DDRAM), character generator RAM (CGRAM), and segment RAM (SEGRAM). The RAM data register (RDR) temporarily stores data to be written into DDRAM, CGRAM, or SEGRAM. Data written into the RDR from the MPU is automatically written into DDRAM, CGRAM, or SEGRAM by internal operations. The RDR is also used for data storage when reading data from DDRAM, CGRAM, or SEGRAM. Here, when address information is written into the RAR, data is read and then stored into the RDR from DDRAM, CGRAM, or SEGRAM by internal operations. Data transfer between the MPU is then completed when the MPU reads the RDR. After this read, data in DDRAM, CGRAM, or SEGRAM stored at the next address is sent to the RDR at the next data read from the MPU. These registers can be selected by the register select signal (RS) and the read/write signal (R/W) in the 8-bit bus interface, and by the RS bit and R/W bit of start-byte data in the synchronized serial interface. Busy Flag When the busy flag is 1, the HD66730/1 is in internal operation mode, and only the status register (STR) can be accessed. The busy flag (BF) is output from bit 7 (DB7). Access of other registers can be performed only after confirming that the busy flag is 0. RAM Address Counter (RAR) The RAM address counter (RAR) provides addresses for accessing DDRAM, CGRAM, or SEGRAM. When an initial address value is written into the RAM counter (RAR), the RAR is automatically incremented or decremented by 1. Note that a control register specifies which RAM (DDRAM, CGRAM, SEGRAM) to select. 16 HD66730/HD66731 Table 3 Register Selection RS R/W Operation 0 0 IDR write 0 1 STR read 1 0 Control register write, RAM address register (RAR) write, and RAM data register (RDR) write 1 1 RAM data register (RDR) read 17 HD66730/HD66731 Display Data RAM (DDRAM) Display data RAM (DDRAM) stores character codes and display attribute codes for displaying data. A full-size font is displayed using two bytes, and a half-size font is displayed using one byte. Since the RAM capacity is 80 bytes, 40 full-size characters or 80 half-size characters can be stored. DDRAM displays only that data stored within the range corresponding to the number of display columns. Data stored outside the range is ignored. Refer to Combined Display of Full-Size and Half-Size characters for details on character codes stored in DDRAM. The relationship between DDRAM addresses and LCD display position depends on the number of display lines (1 line/2 lines/4 lines). Execution of the display-clear instruction writes H'A0 corresponding to the half-size character for “space” throughout DDRAM. Note: The HD66730/1 performs display by reading character codes from the DDRAM according to the number of display columns set by the control register. In particular, reading from the DDRAM begins at the position corresponding to the rightmost character as set by the maximum number of display columns. This means that one byte of a two-byte full-size character code should not be set in a position exceeding the maximum number of display columns. For example, do not write a fullsize code (2 bytes) in the 12th and 13th byte when the display is set for six characters. • 1-line display (NL1/0 = 00) 80 bytes of consecutive addresses from H'00 to H'4F are allocated for DDRAM addresses. When there are fewer than 40 display characters (at full size), only the number of display characters specified by NC1/0 are displayed starting from H'00 in the DDRAM. For example, 12 bytes of addresses from H'00 to H'0B are used when a 6-character display (NC1/0 = 00) is performed using one HD66730; addresses from H'0C on are ignored. In this case, do not write a full-size code into bytes H'0B and H'0C because a half-size character may be displayed. See Figure 1 for a 1-line display. • 2-line display (NL1/0 = 01) The first line in the DDRAM address is displayed for the 40 bytes of addresses from H'00 to H'27, and the second line is displayed for the 40 bytes of addresses from H'40 to H'67. When there are fewer than 20 display characters (at full size), only the number of display characters specified by NC1/0 will be displayed starting from the leftmost address of the DDRAM. For example, 24 bytes of addresses from H'00 to H'0B and H'40 to H'4B are used when a 6-character display (NC1/0 = 00) is performed using one HD66730. Addresses from H'0C and H'4C on are ignored. See Figure 2 for a 2-line display. • 4-line display (NL1/0 = 11) The first line in the DDRAM address is displayed from H'00 to H'13, the second line from H'20 to H'33, the third line from H'40 to H'53, and the fourth line from H'60 to H'73. For a 6-character display (NC1/0 = 00) (at full-size), only 12 bytes from the leftmost address of DDRAM are displayed. See Figure 3 for a 4-line display. 18 HD66730/HD66731 1 6-character display setting (NC1/0 = 00) 2 3 4 5 6 Display position 00 01 02 03 04 05 06 07 08 09 0A 0B 1 20-character display setting (NC1/0 = 01) 2 3 4 5 DDRAM address 6 19 00 01 02 03 04 05 06 07 08 09 0A 0B 1 40-character display setting (NC1/0 = 10) 2 3 4 5 20 Display position DDRAM address 24 25 26 27 6 39 00 01 02 03 04 05 06 07 08 09 0A 0B 40 Display position DDRAM addres 4C 4D 4E 4F Figure 1 1-Line Display (NL1/0 = 00) 1 6-character display setting (NC1/0 = 00) 4 5 6 Display position 1st line DDRAM address 40 41 42 43 44 45 46 47 48 49 4A 4B 2nd line DDRAM address 2 3 4 5 6 9 10 Display position 00 01 02 03 04 05 06 07 08 09 0A 0B 10 11 12 13 1st line DDRAM address 40 41 42 43 44 45 46 47 48 49 4A 4B 50 51 52 53 2nd line DDRAM address 1 20-character display setting (NC1/0 = 10) 3 00 01 02 03 04 05 06 07 08 09 0A 0B 1 10-character display setting (NC1/0 = 01) 2 2 3 4 5 6 19 20 Display position 00 01 02 03 04 05 06 07 08 09 0A 0B 24 25 26 27 1st line DDRAM address 40 41 42 43 44 45 46 47 48 49 4A 4B 64 65 66 67 2nd line DDRAM address Figure 2 2-Line Display (NL1/0 = 01) 1 6-character display setting (NC1/0 = 00) 3 4 5 6 Display position 00 01 02 03 04 05 06 07 08 09 0A 0B 1st line DDRAM address 20 21 22 23 24 25 26 27 28 29 2A 2B 2nd line DDRAM address 40 41 42 43 44 45 46 47 48 49 4A 4B 3rd line DDRAM address 60 61 62 63 64 65 66 67 68 69 6A 6B 4th line DDRAM address 1 10-character display setting (NC1/0 = 01) 2 2 3 4 5 6 7 8 9 10 Display position 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 1st line DDRAM address 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 2nd line DDRAM address 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 3rd line DDRAM address 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 4th line DDRAM address Figure 3 4-Line Display (NL1/0 = 11) 19 HD66730/HD66731 Character Generator ROM for a Full-Size Font (FCGROM) The character generator ROM for a full-size font (FCGROM) generates 3,840 11 × 12 dot full-size character patterns from a 12-bit character code. This includes 2,965 kanji according to the JIS Level-1 Kanji Set and 524 JIS non-kanji. Table 4 shows the relationship between character codes set in DDRAM and full-size font patterns. Refer to Combined Display of Full-Size and Half-Size Characters for the relationship between JIS codes and the character codes to be set in the DDRAM. Character Generator ROM for a Half-Size Font (HCGROM) The character generator ROM for a half-size font (HCGROM) generates 128 6 × 12 dot character patterns from 7-bit character codes. A half-size font (alphanumeric characters and symbols) can be displayed together with a full-size font. Refer to Combined Display of Full-Size and Half-Size Characters for details. Character Generator RAM (CGRAM) The character generator RAM (CGRAM) allows the user to display arbitrary full-size font patterns. It can display 8 12 × 13 dot fonts. This RAM can also display double-size characters and figures by combining multiple CGRAM fonts. Specify character codes from H'000 to H'007 in a full size of character code when displaying font patterns stored in the CGRAM. Segment RAM (SEGRAM) The segment RAM (SEGRAM) is used to control icons and marks in segment units by the user program. Bits in SEGRAM corresponding to segments to be displayed are directly set by the MPU, regardless of the contents of DDRAM and CGRAM. The SEGRAM is read and displayed when the COMS output pin is selected. Up to 71 icons can be displayed using a single HD66730. Up to 96 icons can be displayed by expanding the drivers on the segment side. SEGRAM data is stored in eight bits. The lower six bits control the display of each segment, and the upper two bits control segment blinking. HD66731 can display 96 icons without the expanding driver. 20 HD66730/HD66731 Timing Generator The timing generator generates timing signals for the operation of internal circuits such as DDRAM, FCGROM, HCGROM, CGRAM, and SEGRAM. RAM read timing for display and internal operation timing for MPU access are generated separately to avoid interference. This prevents undesirable interferences, such as flickering, in areas other than the display area when writing data to DDRAM, for example. The timing generator of HD66730 generates interface control signals CL1, CL2, M, and COMD-output of extension drivers for a extension configuration. Display Attribute Controller The display attribute controller displays white/black inverse, blinking, and white/black inverse blinking for a full size font in FCGROM according to the attribute code set in the DDRAM. Refer to Display Attribute Designation for details. Fonts in CGRAM and bit patterns in SEGRAM control display attributes using the upper two bits (bits 7 and 6) in each display-pattern data. Cursor Control Circuit The cursor control circuit is used to produce a cursor on a displayed character corresponding to the DDRAM address set in the RAM address counter (RAR). Cursors can be chosen from three types: 12th raster-row cursor that is displayed only on the 12th raster-row of each font; blink cursor that periodically displays the whole font in black and white and black inverted cursor that periodically displays the font in white and black (see Figure 9). Note that when the RAM address counter (RAR) is selecting CGRAM or SEGRAM, a cursor would be generated at that address, however, it does not have any meaning. Note: One display line consists of 13 raster-rows. Smooth Scroll Control Circuit The smooth scroll control circuit is used to perform a smooth-scroll in units of dots. When the number of characters to be displayed is greater than that possible at one time in the liquid crystal module, this horizontal smooth scroll can be used to display characters in an easy-to-read manner for each line. Refer to Horizontal Smooth Scroll for details for each line. 21 HD66730/HD66731 Liquid Crystal Display Driver Circuit The liquid crystal display driver circuit of HD66730 consists of 26 common signal drivers and 71 segment signal drivers. HD66731 has 54 common signal drivers and 119 segment signal drivers. When the liquid crystal driver duty ratio is set by a program, the necessary common signal drivers output drive waveforms and the remaining common drivers output non-selected waveforms. In addition, drivers can be expanded on the common and segment sides through register settings. Display pattern data is sent serially through a shift register and latched when all needed data has arrived. The latched data then enables the LCD driver to generate drive waveform outputs. This serial data is sent from the display pattern that corresponds to the last address of the DDRAM and is latched when the character pattern of the display data corresponding to the first address enters the internal shift register. Booster The booster outputs a voltage that is two or three times higher than the reference voltage input from pin Vci. Since the LCD voltage can be generated from the LSI operation power supply, this circuit can operate with a single power supply. Refer to Power Supply for Liquid Crystal Display Drive for details. Oscillator The HD66730/1 performs R-C oscillation by adding a single external oscillation resistor. The oscillation frequency corresponding to display size and frame frequency can be adjusted by changing the oscillation resistor. Refer to Oscillator for details. 22 HD66730/HD66731 Table 4 Relationship between Full-Size Character Code and Kanji Upper / Lower 23 HD66730/HD66731 Table 4 Relationship between Full-Size Character Code and Kanji (cont) Upper / Lower 24 HD66730/HD66731 Table 4 Relationship between Full-Size Character Code and Kanji (cont) Upper / Lower 25 HD66730/HD66731 Table 4 Relationship between Full-Size Character Code and Kanji (cont) Upper / Lower 26 HD66730/HD66731 Table 5 Relationship between Full-Size Character Code and Non-Kanji Upper / Lower 27 HD66730/HD66731 Table 6 Upper (4 bits) Lower (3 bits) xxxx 000 xxxx 001 xxxx 010 xxxx 011 xxxx 100 xxxx 101 xxxx 110 xxxx 111 28 Relationship between Half-Size Character Code and Character Pattern (ROM Code: A00) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 (Space) HD66730/HD66731 Relationship between Character Codes (DDRAM), CGRAM Addresses, and Display Characters Full size character codes H'000 to H'007 can be used to access 8 character patterns in the CGRAM. Since each character pattern can be displayed up to 12 × 13 dots, CGRAM patterns can be displayed immediately next to each other (to the right, left, top, or bottom) without any character spaces between them. Table 6 shows the correspondence between CGRAM addresses and full-size character codes for access of the CGRAM by the MPU. Table 7 Relationship between Character Codes (DDRAM), CGRAM Addresses, and Display Characters Character Code CGRAM Address C11 C3 C7 C6 C5 A7 A6 A5 A4 A3 A2 A1 0 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 0 00 00 00 00 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 0 00 00 00 00 1 62 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 CGRAM Data A0 = 0 A0 = 1 D7D6 D5 D4D3 D2D1 D0 D7 D6 D5D4D3D2D1D0 A A 0 0 0 0 0 0 A A 0 0 0 0 0 0 A A 0 1 1 1 1 1 A A 1 1 1 1 0 0 A A 0 1 0 0 0 0 A A 0 0 0 1 0 0 A A 0 1 0 0 0 0 A A 0 0 0 1 0 0 A A 0 1 0 0 0 0 A A 0 0 0 1 0 0 A A 0 1 0 0 0 0 A A 0 0 0 1 0 0 A A 0 1 1 1 1 1 A A 1 1 1 1 0 0 A A 0 1 0 0 0 0 A A 0 0 0 1 0 0 A A 0 1 0 0 0 0 A A 0 0 0 1 0 0 A A 0 1 0 0 0 0 A A 0 0 0 1 0 0 A A 0 1 0 0 0 0 A A 0 0 0 1 0 0 A A 0 1 1 1 1 1 A A 1 1 1 1 0 0 A A 0 0 0 0 0 0 A A 0 0 0 0 0 0 A A 0 0 0 0 0 1 A A 0 0 0 0 0 0 A A 0 0 0 0 0 0 A A 1 0 0 0 0 0 A A 0 1 1 1 1 1 A A 1 1 1 1 0 0 A A 0 0 0 0 0 0 A A 0 0 0 0 0 0 A A 0 0 1 0 0 0 A A 0 0 1 0 0 0 A A 0 0 1 0 0 0 A A 0 0 1 0 0 0 A A 0 0 1 0 0 0 A A 0 0 1 0 0 0 A A 0 0 0 1 0 0 A A 0 1 0 0 0 0 A A 0 0 0 1 0 0 A A 0 1 0 0 0 0 A A 0 0 0 1 0 0 A A 0 1 0 0 0 0 A A 0 0 0 0 0 0 A A 0 0 0 0 0 0 A A 1 1 1 1 1 1 A A 1 1 1 1 1 0 A A 0 0 0 0 0 0 A A 0 0 0 0 0 0 A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Character pattern (1) Character pattern (2) Character pattern (8) HD66730/HD66731 Notes: 1. CGRAM is selected when the upper 9 bits (C3 to C11) of the full size character codes are 0. In this case, the lower 3 bits (C0 to C2) of the character code correspond to bits 5 to 7 (A5 to A7) (3 bits: 8 types) in the CGRAM address. 2. CGRAM address bits 1 to 4 (A1 to A4) designate the character pattern line position. The 12th line is the cursor position and its display is formed by a logical OR with the cursor. 3. CGRAM address 0 (A0) corresponds to the left-half and right-half of a full-size character pattern. 4. The character data is stored with the rightmost character element in bit 0 (LSB), as shown in the table above. Pattern produced by bits 0 to 5 is displayed and 13 raster-rows are displayed together. Thus, an arbitrary character pattern consisting of 12 × 13 dots can be displayed. 5. A set bit in the CGRAM data corresponds to display selection, and 0 to non-selection. 6. The upper two bits (AA) of CGRAM data indicate the display attribute for the lower 6-bit pattern. In this case, display attributes specified for the DDRAM during full-size character display is disabled. When these upper two bits are 00, the CGRAM pattern is simply displayed as set; when 01, the pattern reverses (black/white), when 10, the pattern blinks; and when 11, the pattern reverses and blinks. 63 HD66730/HD66731 Relationship between SEGRAM Addresses and Display Patterns SEGRAM data is displayed when the select level of the COMS pin is output. Since SEGRAM data does not depend on character code data in DDRAM, and does not undergo horizontal smooth scroll, it can be used to display icon and marks. The following shows the relationship between SEGRAM addresses and segment output pins. Table 8 Relationship between SEGRAM Addresses and Display Patterns SEGRAM Address SEGRAM Data A3 A2 A1 A0 D7 D6 D5 D4 D3 0 0 0 0 B1 B0 SEG1 SEG2 SEG3 0 0 0 1 B1 B0 SEG7 SEG8 SEG9 0 0 1 0 B1 B0 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 0 0 0 1 1 B1 B0 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 1 0 0 B1 B0 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 0 1 0 1 B1 B0 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 0 1 1 0 B1 B0 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 0 1 1 1 B1 B0 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 1 0 0 0 B1 B0 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 1 0 0 1 B1 B0 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 1 0 1 0 B1 B0 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 1 1 0 1 1 B1 B0 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 1 0 0 B1 B0 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 1 1 0 1 B1 B0 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 1 1 1 0 B1 B0 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 1 1 1 1 B1 B0 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 Blinking control D2 D1 D0 SEG4 SEG5 SEG6 SEG10 SEG11 SEG12 Pattern on/off Notes: 1. SEG1 to SEG71 are pin numbers of the segment output driver of the HD66730. Pin SEG1 is positioned on the left edge of the display. Segments from SEG72 on are displayed by extension drivers. After SEG 96, display is performed from SEG1 again. 2. The lower six bits (D0 to D5) indicate display on/off for of each segment. A bit setting of 1 selects display while 0 selects no display. 3. Pattern blinking of the lower six bits is controlled by the upper two bits (D6 and D7) of SEGRAM data. When the upper two bits (B0 and B1) are 10, segments whose corresponding bits in the lower 6 bits are set to 1 will blink on the display. When the upper two bits (B0 and B1) are 01, only the bit-5 pattern can blink. Do not attempt to set the upper two bits (B0 and B1) to 11 (setting is prohibited). 64 HD66730/HD66731 Register Functions Outline Data can be written from the MPU to the internal control registers and internal RAM of the HD66730/1 via an 8-bit bus interface or a serial interface. There are five types of internal control registers, as follows (details are described later): • • • • • Index register: Selects and designates which control register the MPU is to access Status register: Indicates the internal state Control registers: Designates display control RAM address register: Sets an address for accessing the various RAMs RAM data register: Receives and transmits data to and from the various RAMs Table 17 shows the instruction list and the number of execution cycles of each instruction after performing register setting. Instructions that perform data transfer with the RAM data register tend to be used the most. However, auto-incrementation by 1 (or auto decrementation by 1) of internal HD66730/1 RAM addresses after each data write can lighten the program load on the MPU. Note that when an instruction is being executed (internal operations are being performed), only the busy flag in the status register can be read. Since the busy flag is 1 during execution, the MPU should check this value before accessing a register. When accessing a register without checking the busy flag, an interval longer than the instruction execution time is needed before the next access. Refer to Table 17 Instruction Registers, for instruction execution times. When rewriting DDRAM, character display will momentarily breakdown if the data (character codes) that is being rewritten is also being read by the system for display. For this reason, check the display read line position (NF) and the display read raster-row position (LF) in the status register (SR), and rewrite a DDRAM line that is not being read and displayed. 65 HD66730/HD66731 Functional Description Index Register (IR) The index register (Figure 4) designates control registers (R0 to R7), RAM address register (RAR: R8), and RAM data register (RDR: R9). The register number must be set between addresses 0000 to 1001 in binary digits. Note that if address 1111 is set, the test register will be selected. Addresses 1010 to 1110 are ignored. R/W RS DB7 0 0 0 DB0 0 0 0 ID3 ID2 ID1 ID0 Figure 4 Index Register 66 HD66730/HD66731 Status Register (ST) The status register (Figure 5) includes the busy flag (BF), display line bits (NF1/0), and display raster-row bits (LF0 to LF3). If BF is 1, an instruction is being executed, and another instruction will not be accepted during this time. Any attempt to write data to a register at this time is ignored. Rasters-rows are driven one at a time according to specific timing to perform liquid crystal display. Bits NF1 and NF0 indicate display lines, and bits LF3 to LF0 indicate the raster-row in a line. If character display degenerates when rewriting DDRAM, rewrite only those display lines that are not currently being read out by the system for display. During segment display, the next state of the last raster-row in the character display is read out. Table 9 Display State According to NF1 and NF0 NF1 NF0 Display State 0 0 Displaying the first line 0 1 Displaying the second line 1 0 Displaying the third line 1 1 Displaying the fourth line Table 10 Display State According to LF3 to LF0 LF3 LF2 LF1 LF0 Display State 0 0 0 0 Displaying the first raster-row 0 0 0 1 Displaying the second raster-row 0 0 1 0 Displaying the third raster-row 0 0 1 1 Displaying the fourth raster-row • • • 1 • • • 1 0 0 Displaying the 13th raster-row R/W RS DB7 1 0 BF NF1 NF0 DB0 0 LF3 LF2 LF1 LF0 Figure 5 Status Register 67 HD66730/HD66731 Entry Mode Register (R0) The entry mode register (Figure 6) includes bits I/D, RM1, and RM0. I/D: Increments (I/D = 1) or decrements (I/D = 0) the DDRAM address by 1 when a character code is written into or read out from the DDRAM. When the DDRAM address is incremented by 1, the cursor or blinking will also shift to the right. This applies to both CGRAM and SEGRAM. RM1/0: Selects DDRAM, CGRAM, or SEGRAM for access (Table 10). Table 11 RAM Selection by RM1 and RM0 RM1 RM0 Selected RAM 0 0/1 Display data RAM (DDRAM) 1 0 Character generator RAM (CGRAM) 1 1 Segment RAM (SEGRAM) R/W RS DB7 0 1 0 DB0 0 0 0 0 I/D RM1 RM0 Figure 6 Entry Mode Register 68 HD66730/HD66731 Function Set Register (R1) The function set register (Figure 7) includes bits BST, EXT2, EXT1, DT1, DT0, and DCL. BST: When BST is 1, the booster starts to operate. When the LCD voltage is external, set BST to 0 to stop operation of the internal booster. In addition, the consumption current can be suppressed by stopping the booster when entering standby mode without display. EXT2/1: Extends the common driver and segment driver of HD66730. Set EXT2 to 1 to extend the driver to the common side if the duty ratio is 1/40 or 1/53. Extend the driver to the segment side by setting EXT1 to 1 when displaying 7 or more digits (of full size) in the horizontal direction. DDRAM capacity is 80 bytes. When the HD66731, these EXT2/1 bits must be set to 1. DT1/0: Selects the duty ratio of the LCD (Table 11). Although this bit can be set separately from the display line designation (NL1/0), the duty ratio must be selected so that it will be smaller than the number of display lines. DCL: When DCL is 1, the display is cleared by writing the code for half-size space (H'A0) into all DDRAM addresses. Then H'00 is written into the RAM address counter (RAR) and the DDRAM is selected. The character code for character code H'A0 must be a blank pattern when rewriting HCGROM used for half-size characters. Cursor Control Register (R2) The cursor control register includes bits CHM, C, CM1, and CM0. CHM: When CHM is set to 1, DDRAM is selected, the RAM address counter (RAR) is set to 0, and the cursor home instruction is executed. The contents of DDRAM do not change. The cursor or blinking moves to the left edge of the display (the left edge of the first line if two lines are displayed). C: When C = 1, cursor display is turned on. The cursor is displayed at the position corresponding to the count value of the RAM address counter (RAR). To set data in the RAR, set the index register (IDR) to 1000 to select it, and modify the data in the RAR. Note that the RAM address counter (RAR) automatically increments (decrements) when the RAM is accessed, and the cursor will move accordingly. CM1/0: Selects cursor display mode (Table 12 and Figure 9). The blinking frequency (cycle) of the blink cursor and the white/black inverted cursor has 64 frames. 69 HD66730/HD66731 Table 12 Duty Drive Ratio DT1 DT0 Duty Drive Ratio 0 0 1/14 duty drive 0 1 1/27 duty drive 1 0 1/40 duty drive 1 1 1/53 duty drive Table 13 Cursor Mode Selection CM1 CM0 Selected Cursor Mode 0 0 12th raster-row cursor 0 1 Blink cursor 1 0/1 White/black inverted cursor R/W RS DB7 DB0 1 DCL 0 0 BST EXT2 EXT1 DT1 DT0 0 Figure 7 Function Set Register R/W RS DB7 0 1 0 DB0 0 0 0 CHM C CM1 CM0 Figure 8 Cursor Control Register 70 HD66730/HD66731 Cursor Normal display example i) 12th-raster-row display example Alternating display ii) Blink display example Alternating display iii) White/black inverted display example Figure 9 Cursor Display Examples 71 HD66730/HD66731 Display Control Register 1 (R3) The display control register 1 (Figure 10) includes bits ST, DC, and DS. ST: When ST is 1, the display control register 1 enters the standby mode. The internal operation clock is divided into 32. Data cannot be displayed on the LCD panel, however, the consumption current can be suppressed during the standby mode. Note that the register setting value and the data inside the RAM are maintained. DC: When DC is 1, the character display is turned on. DS: When DS is 1, the segment display is turned on. Bit DS can selectively display marks. Display Control Register 2 (R4) NC1/0: Selects the display character in the horizontal direction. When performing a horizontal smooth scroll, set the number of display characters larger than the actual number of liquid crystal drive characters. When the frame frequency (cycle) is stable, the operation frequency is proportional to the display characters. Operation frequency must be suppressed by setting the number of display character as small as possible because the consumption current is proportional to the operation frequency. Refer to Oscillator for details. NL1/0: Sets the number of display lines. Set the number of display lines larger than the duty drive ratio (DT1/0). Do not set 10 to these bits. Table 13 indicates the settings of the display lines. Table 14 Display Control Register 2 Setting Display Characters: NC1/0 Display Lines NL1/0 00 01 10 00 1-line 6 characters 1-line 20 characters 1-line 40 characters 01 2-line 6 characters 2-line 10 characters 2-line 20 characters 10 11 Setting is inhibited. 4-line 6 characters 4-line 10 characters R/W RS DB7 0 1 0 DB0 0 0 0 0 ST DC DS Figure 10 Display Control Register 1 R/W RS DB7 0 1 0 DB0 0 0 NC1 NC0 0 NL1 NL0 Figure 11 Display Control Register 2 72 4-line 10 characters HD66730/HD66731 Scroll Control Register 1 (R5) The scroll control register 1 (Figure 12) includes bits SN1, SN0, SL3, SL2, SL1, and SL0. SN1/0: Selects the starting line to be displayed. When SN1/0 shows 00, display begins from the first line. When SN1/0 shows 01, 10, 11, display begins from the second, third, or fourth line, respectively. Use these bits within the display line setting (NL1/0). SN can be used to display a smooth scroll and DDRAM memory bank switching. SL0 to SL3: Selects the scroll starting raster-row of the line set by the start display line (SL1/0). When these bits show 0000, a display line starting from the head raster-row (first raster-row) is displayed and can be set to 1100 (13th raster-row) showing the last raster-row. A vertical smooth scroll can be performed by sequentially incrementing the first raster-row. Refer to Vertical Smooth Scroll for details. Note that bits SL0 to SL3 that are set to a value above 1100 will not operate correctly. Scroll Control Register 2 (R6) The scroll control register 2 (Figure 13) includes bits PS1, PS0, SE4, SE3, SE2, and SE1. PS1/0: Selects the partial smooth scroll mode. When PS1/0 bits are 00, all characters scroll horizontally across the display. When bits PS1/0 are 01, only the leftmost character is fixed and the remaining characters perform horizontal smooth scroll display. When bits PS1/0 are 10, the two leftmost bits, and when 11, the three leftmost characters are fixed and the remaining characters perform horizontal smooth scroll Refer to Partial Smooth Scroll for details. SE1 to SE4: These bits enable a dot scroll in display lines designated by scroll control register 3 (R7). When bit SE is 1, the first line is scrolled according to scroll control register 3 (R7). When SE2 is 1, the second line scrolls independently, when SE3 is 1, the third line scrolls independently, when SE4 is 1, the fourth line scrolls independently. Scrolling multiple lines at the same time is also possible. R/W RS DB7 0 1 DB0 0 SN1 SN0 0 SL3 SL2 SL1 SL0 Figure 12 Scroll Control Register 1 R/W RS DB7 0 1 0 DB0 0 PS1 PS0 SE4 SE3 SE2 SE1 Figure 13 Scroll Control Register 2 73 HD66730/HD66731 Scroll Control Register 3 (R7) The scroll control register 3 (Figure 14) includes bits SQ5, SQ4, SQ3, SQ2, SQ1, and SQ0. SQ0 to SQ5: These bits designate the number of dots to be horizontally scrolled to the left on the panel. Horizontal smooth scroll can be performed for any number of dots between 1 and 48 inclusive by using the non-display DDRAM area. When these bits are 000000, scrolling is not performed. When these bits are 110000, 48 dots are scrolled to the left. If these bits are set to a value above 110000, 48 dots are still scrolled. Refer to Horizontal Smooth Scroll for details. RAM Address Register (R8) The RAM address register (Figure15) initially contains the RAM address at which incrementation (decrementation) starts. RAM selection bits (RM1/0) in the entry mode register (R0) select which RAM to access (DDRAM/CGRAM/SEGRAM). When DDRAM (RM1/0 = 00) is selected, address allocation differs according to the number of display lines, but in all cases the most significant bit (RA7) is ignored. During a 1-line display (NL1/0 = 00), addresses H'00 to H'4F are allocated to that line. During a 2-line display, addresses H'00 to H'27 are allocated to the first line, and addresses H'40 to H'67 are allocated to the second line. During a 4-line display, addresses H'00 to H'13 are allocated to the first line, H'20 to H'33 to the second , H'40 to H'53 to the third, and H'60 to H'73 to the fourth. See Table 14. When CGRAM (RM1/0 = 10) is selected, addresses H'00 to H'19 are allocated to the first character and addresses H'20 to H'39 are allocated to the second character, and so on (Table 15). The setting of addresses between characters (example: H'1A to H'1F) is ignored here. When SEGRAM is selected (RM1/0 = 11), addresses H'0 to H'F are allocated to the RAM and the upper four bits (R4 to R7) are ignored (Table 16). R/W RS DB7 0 1 0 DB0 0 SQ5 SQ4 SQ3 SQ2 SQ1 SQ0 Figure 14 Scroll Control Register 3 R/W RS DB7 0 1 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 Figure 15 RAM Address Register 74 DB0 HD66730/HD66731 Table 15 DDRAM Address Allocation Displayed Lines 1-Line Display (NL1/0 = 00) 2-Line Display (NL1/0 = 01) 4-Line Display (NL1/0 = 00) First line H'00 to H'4F H'00 to H'27 H'00 to H'13 Second line — H'40 to H'67 H'20 to H'33 Third line — — H'40 to H'53 Fourth line — — H'60 to H'73 Table 16 CGRAM Address Allocation Displayed Character CGRAM Address First character H'00 to H'19 Second character H'20 to H'39 Third character H'40 to H'59 Fourth character H'60 to H'79 Fifth character H'80 to H'99 Sixth character H'A0 to H'B9 Seventh character H'C0 to H'D9 Eighth character H'E0 to H'F9 Table 17 SEGRAM Address Allocation Displayed Segment SEGRAM Address SEG1 to SEG6 H'0 SEG7 to SEG12 H'1 SEG13 to SEG18 H'2 SEG19 to SEG24 H'3 SEG25 to SEG30 H'4 SEG31 to SEG36 H'5 SEG37 to SEG42 H'6 SEG43 to SEG48 H'7 SEG49 to SEG54 H'8 SEG55 to SEG60 H'9 SEG61 to SEG66 H'A SEG67 to SEG72 H'B SEG73 to SEG78 H'C SEG79 to SEG84 H'D SEG85 to SEG90 H'E SEG91 to SEG96 H'F Note: SEG72 to SEG96 are driven by extension drivers. 75 HD66730/HD66731 RAM Data Register (R9) This register (Figure 16) stores 8-bit data that is written to or read from the DDRAM, CGRAM, or SEGRAM at the address indicated by the RAM address counter (RAC). The RAM selection bit (RM1/0) selects the RAM (DDRAM, CGRAM, SEGRAM). After the said RAM is accessed, RAM address is automatically incremented (decremented) by 1 according to the I/D bit. Note that RAM selection bits (RM1/0) and RAM address register (R8) must be set before reading. If not, the first data read is invalid. If read instructions continue to be executed, however, data will be read correctly from the second read. Test Register (RF) This is a test register (Figure 17) and must be set to H'00 at all times. This register is automatically cleared (H'00) by reset input; however, it must be cleared by software after power-on if the reset pin is not used. R/W RS DB7 0/1 DB0 1 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 Figure 16 RAM Data Register R/W RS DB7 0 1 0 DB0 0 0 0 0 0 Figure 17 Test Register 76 0 0 HD66730/HD66731 Table 18 Instruction Registers Code Execution Clock Cycle Reg. Index No. (Hex) Register R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description IR — Index (IDR) 0 0 — — — ID3 ID2 SR — Status (STR) 1 0 BF NF1 NF0 — LF3 LF2 LF1 LF0 R0 0 Entry mode (EMR) 0 1 0 0 0 0 I/D R1 1 Function 0 set (FSR) 1 0 BST EXT2 EXT1 DT1 DT0 0 R2 2 Cursor control (CCR) 0 1 0 0 0 0 CHM C CM1 CM0 Designates cursor-on 12 (C) and cursor display mode(CM1/0). Executes cursor home (CHM) instruction. R3 3 Display 0 control 1 (DCR1) 1 0 0 0 0 0 ST DC R4 4 Display 0 control 2 (DCR2) 1 0 0 NC1 NC0 0 0 NL1 NL0 R5 5 Scroll 0 control 1 (SCR1) 1 0 SN1 SN0 0 SL3 SL2 SL1 SL0 R6 6 Scroll 0 control 2 (SCR2) 1 0 0 PS1 PS0 SE4 SE3 SE2 SE1 Designates partial 12 scroll columns (PS1/0) and scroll display line enable(SE1 to SE4). R7 7 Scroll 0 control 3 (SCR3) 1 0 0 SQ5 SQ4 SQ3 SQ2 SQ1 SQ0 Sets the number of dots to be scrolled (SQR0 to SQR5). — 0 ID1 ID0 Designates the 12 register number of the instruction register to access. ID = 0000: R0 to 1001: R9 Indicates the busy flag 0 (BF), display read line position (NF1/0), display read rasterrow position(NL0 to NL3). RM1 RM0 Designates RAM address in crementation or decrementation (I/D) and RAM selection (RM1/0). 12 DCL Clears display (DCL) DCL = 1: and initializes the 492 DDRAM address. Other: 12 Selects duty drive ratio(DT1/0), enables extension driver (EXT2/1) and sets the booster operation on. DS Designates standby mode (ST), character display on (DC), and segment display on (DS). 12 Sets the number of 12 display characters(NC1/0) and display lines(NL1/0). Sets the display start line (SN1/0) and start raster-row (ST0 to ST3). 12 12 77 HD66730/HD66731 Table 18 Instruction Registers (cont) Reg. Index No. (Hex) Register R/W RS Code DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description Execution Clock Cycle R8 8 RAM 0 address (RAR) 1 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 Resets the address address counter for DDRAM/CGRAM/ SEGRAM. RAM is selected by RM1/0. 12 R9 9 RAM data (RDR) 0/1 1 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 Writes or reads data to and from DDRAM/CGRAM/ SEGRAM. RAM is selected by RM1/0. 12 RF F Test (TSR) 0 1 0 12 0 0 0 0 0 0 0 This is a test register. Set 00 in this register. Note: The execution time depends on the input or oscillation frequency. BF = 1: NF1/0: LF0 to LF3: ID= 1: = 0: RM1/0: BST = 1: EXT2 = 1: EXT1 = 1: DT1/0: DCL = 1: CHM = 1: C = 1: CM1/0: ST = 1: DC = 1: DS = 1: NC1/0: NL1/0: SN1/0: SL0 to SL3: PS1/0: SE1 to SE4: SQ0 to SQ5: RA0 to RA7: RD0 to RD7: 78 Internal processing being performed Position of display read line Position of display read raster-row Address increment Address decrement RAM selection (00/01: DDRAM. (10: GGRAM, 11: SEGRAM) Booster on Common driver extension enable Segment driver extension enable Duty ratio (00: 1/14, 01: 1/27, 10: 1/40, 11: 1/53) Executes display-clear instruction Executes cursor-home instruction Cursor on Designates cursor mode (00: 12th raster-row, 01: blinking, 10: white/black inverse) Standby mode Character display on Segment display on Sets the number of display characters (6 to 40 characters) Sets the number of display lines (00: 1 line, 01: 2 lines, 11: 4 lines) Designates the line to start displaying (00: first line, 01: second line, 10: third line, 11: fourth line) Designates scroll starting raster-row(0000: first raster-row, 1100: 13th raster-row) Designates partial scroll (00: all columns scroll. 01: the leftmost column fixed, 10: the two leftmost columns fixed, 11: the three leftmost columns fixed) Designates which line to scroll (SE = 1: enables the first line to be scrolled, etc.) Number of dots to scroll (0 to 48 dots) RAM address RAM data HD66730/HD66731 Reset Function The HD66730/1 is reset by setting the RESET pin to low level. During reset, the system performs nextcontrol-register setting and executes instructions. The busy flag (BF) therefore indicates a busy state (BF = 1) at this time, which means that only the index register and status register can be accessed. Display clear (DDRAM reset) is performed automatically by reset input. Since more than 1,000 clocks of execution cycles are needed to initialize the DDRAM, the reset period must be set to more than this number. Note that if the reset input conditions specified in Electrical Characteristics are not satisfied, the HD66730/1 will not operate correctly, and reset should be performed by software. Initialization of Instruction Register Function 1. Index Register: IR The index register cannot be initialized by reset. After reset release, the index register must be set to access a control register. 2. Status register: SR BF = 1: Busy state 3. Entry mode register: R0 I/D = 1: +1 (incrementation) RM1/0 = 00: DDRAM selection 4. Function set register: R1 BST = 0: Booster off EXT2/1 = 11: Driver extension enable DT1/0 = 11: 1/53 duty drive DCL = 1: Display-clear execution Note: At least 1,000 clock cycles of execution time is needed to clear the DDRAM. 79 HD66730/HD66731 5. Cursor control register: R2 CHM = 1: Cursor home execution C = 0: Cursor display off CM1/0 = 00: 12th raster-row cursor display mode 6. Display control register 1: R3 ST = 0: Standby mode clear DC = 0: Character display off DS = 0: Segment display off 7. Display control register 2: R4 NC1/0 = 00: 6-column display mode NL1/0 = 00: 1-line display mode 8. Scroll control register 1: R5 SN1/0 = 00: Starts displaying from the first line. SL3 to SL0 = 0000: Starts displaying from the first raster-row. 9. Scroll control register 2: R6 PS1/0 = 00: Partial scroll release SE4 to SE1 = 0000: Disables dot scrolling for all lines. 10. Scroll control register 3: R7 SQ5 to SQ0 = 000000: Number of dots to be scrolled = 0 11. RAM address register: R8 RAM address register is automatically incremented during reset when display-clear is executed. Note that after reset is released, this register must be reset by software before accessing RAM. 80 HD66730/HD66731 Initial Setting of Pin Functions 1. Bus/serial interface The input level of pin IM selects the 8-bit bus or serial interface. For an 8-bit bus interface, data is written into the index register or read from the status register according to the level of pin R/W. Note that pin RS must be held low during this time. For serial interface, data is written into the index register according to bit R/W. Note that bit RS must be 0 during this time. During reset, only the index register and status register can be set and RAM cannot be accessed. 2. LCD driver output Since segment drivers (pins SEG1 to SEG71/119) are in a display-off state during reset, they output non-selective levels (V2/V3 level) during reset. At this time, a 4-line 6-character display alternates its current. Common drivers (pins COM1 to COM24/53 and COMS) output non-selective levels (V1/V4 level) during reset, and alternate its current for a 4-line 6-character display. Note: Pins COM25/COMD of HD66730 are grounded (0V) during reset. When pin COM25 is used without expanding drivers to the common side, display may be performed using the liquid crystal drive voltage. In this case, adjust the liquid crystal voltage during reset. 3. Extension driver interface output (HD66730) Since bits EXT2/1 are 11 during reset, extension is performed to both segment side and common side. Pin CL2 outputs the oscillation (operation) frequency clock. Pins CL1 and M output signals in a cycle corresponding to a 4-line 6-character display size. In addition, pins SEGD and COM25/COMD output low (ground level) since the display is turned off. 4. Booster output The operation of the internal booster stops because bit BST becomes 0 during reset. Note: The potential of pins V5OUT2 and V5OUT3 increases by about +0.7 V with respect to GND level when the booster stops. When using external polarized capacitors, make sure that no reverse bias occurs. 81 HD66730/HD66731 Interfacing to the MPU The HD66730/1 enters 8-bit bus interface mode when the IM pin is set high. The HD66730/1 can interface with the MPU via an I/O port. Use the serial interface when there are restraints in the bus wiring width. Instruction is executed when data is written into the control register. In this case, only the status register can be read (busy check, etc.). In this case, check the busy flag when accessing (polling), or insert an interval considering the execution time and perform the next access when the internal process has completely finished. The instruction execution time depends on the HD66730/1 operation frequency. When using the internal oscillation circuit of the HD66730/1, the instruction time will change as the oscillation frequency does. Figure 18 shows an example of an 8-bit data transfer timing sequence. Figure 19 shows an example of interface between HD66730/1 and 8-bit microcomputers. RS R/W E Internal signal DB7 DB6 to DB0 Internal operation (busy) Data Busy Control register write Not Busy Busy Busy flag check Busy flag check Busy flag check Index register write Figure 18 Example of an 8-bit Data Transfer Timing Sequence H8/325 E RS R/W C0 C1 C2 A0 to A7 8 HD66730 HD66731 DB0 to DB7 I/O port interface Figure 19 Example of Interfacing with 8-Bit Microcomputers 82 Data HD66730/HD66731 Transferring Serial Data The HD66730/1 enters serial interface mode when the IM pin is set low. A three-line clock-synchronous transfer method is used. The HD66730/1 receives serial input data (SID) and transmits serial output data (SOD) by synchronizing with a transfer clock (SCLK) sent from the master side. When the HD66730/1 interfaces with several chips, chip select pin (CS*) must be used. The transfer clock (SCLK) input is activated by making chip select (CS*) low. In addition, the transfer counter of the HD66730/1 can be reset and serial transfer synchronized by making chip select (CS*) high. Here, since the data which was being sent at reset is cleared, restart the transfer from the first bit of this data. In a minimum system where a single HD66730/1 interfaces to a single MPU, an interface can be constructed from the transfer clock (SCLK) and serial input data (SID). In this case, chip select (CS*) should be fixed to low. The transfer clock (SCLK) is independent of operational clock (CLK) of the HD66730/1. However, when several instructions are continuously transferred, the instruction execution time determined by the operational clock (CLK) (see Continuous Transfer) must be considered since the HD66730/1 does not have an internal transmit/receive buffer. Figure 20 shows the basic procedure for transferring serial data. To begin with, transfer the start byte. By receiving five consecutive bits of 1 (synchronizing bit string) at the beginning of the start byte, the transfer counter of the HD66730/1 is reset and serial transfer is synchronized. The 2 bits following the synchronizing bit string (5 bits) specify transfer direction (R/W bit) and register select (RS bit). Be sure to transfer 0 in the 8th bit. After receiving the start byte, instructions are received and the data/busy flag is transmitted. When the transfer direction and register select remain the same, data can be continuously transmitted or received. The transfer protocol is described in detail in the following. 83 HD66730/HD66731 a) Serial data input (receiving) CS* (input) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 0 0 0 17 18 19 20 21 22 23 24 0 0 0 0 SCLK (input) SID (input) 1 1 1 1 1 R/W RS 0 D0 D1 D2 D3 Synchronizing bit string D4 D5 D6 D7 Lower data Upper data 1st byte 2nd byte Start byte Instruction b) Serial data output (transmitting) CS* (input) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 0 0 0 0 0 0 SCLK (input) SID (input) 1 1 1 1 1 R/W RS SOD (output) 0 0 D0 D1 D2 D3 D4 D5 D6 D7 Synchronizing bit string Start byte Lower data Upper data Status/data read Figure 20 Basic Procedure for Transferring Serial Data 84 HD66730/HD66731 • Receiving (write) After receiving the start synchronizing bit string, the R/W bit (= 0), and the RS bit in the start byte, an 8-bit instruction is received in 2 bytes: the lower 4 bits of the instruction are placed in the LSB of the first byte, and the higher 4 bits of the instruction are placed in the LSB of the second byte. Be sure to transfer 0 in the following 4 bits of each byte. When instructions are received with R/W bit and RS bit unchanged, continuous transfer is possible (see Continuous Transfer in the following). • Transmitting (read) After receiving the synchronizing bit string, the R/W bit (= 0), and the RS bit in the start byte, 8-bit read data is transmitted from pin SOD in the same way as receiving. When read data is transmitted with R/W bit and RS bit unchanged, continuous transfer is possible (see Continuous Transfer in the following). The status register (SR) is read when the RS bit is 0. RAM data is read out when the RS bit is set to 1 after designating RAM data register (R9) with the index register (IR). Bits RM1/0 of entry mode register (R0) select the RAM. When reading RAM data, an interval longer than the RAM reading time must be taken after the start byte has been accepted and before the first data has been read out. During transmission (data output), the SID input is continuously monitored for a start synchronizing bit string (11111). Once this has been detected, the R/W and RS bits are received. Accordingly, 0 must always be input to SID when transmitting data continuously. • Continuous Transfer When instructions are received with the R/W bit and RS bit unchanged, continuous receive is possible without inserting a start byte between instructions. After receiving the last bit (the 8th bit in the 2nd byte) of an instruction, the system begins to execute it. To execute the next instruction, the instruction execution time of the HD66730/1 must be considered. If the last bit (the 8th bit in the 2nd byte) of the next instruction is received during execution of the previous instruction, the instruction will be ignored. In addition, if the next unit of data is read before read execution of previous data is completed for RAM data, normal data is not sent. To transfer data normally, the busy flag must be checked. However, if the amount of wiring used for transmission needs to be reduced, or if the burden of polling on the CPU needs to be lightened, transfer can be performed without reading the busy flag. In this case, insert a transfer wait between instructions so that the current instruction has time to complete execution. Figure 21 shows the procedure for continuous data transfer. 85 HD66730/HD66731 i) Continuous data write by polling processing SCLK (input) SID (input) Start byte Instruction (1) 1st byte 2nd byte Start byte Instruction (2) 1st byte 2nd byte Start byte SOD (output) Busy read Instruction (1) execution time Instruction waiting time (not busy state) ii) Continuous data write by CPU wait insert Wait SCLK (input) SID (input) Start byte Instruction (1) 1st byte 2nd byte Wait Instruction (2) 1st byte 2nd byte Instruction (1) execution time Instruction (3) 1st byte 2nd byte Instruction (2) execution time Instruction (3) execution time iii) Continuous data write by CPU wait insert SCLK (input) SID (input) Wait Wait Wait Start byte SOD (output) Data read (1) RAM data read time (1) Data read (2) RAM data read time (2) RAM data read time (3) Figure 21 Procedure for Continuous Data Transfer 86 HD66730/HD66731 Combined Display of Full-Size and Half-Size Characters The HD66730/1 performs display from the left edge of the display combining 12-dot full-size (character size: 11 × 12 dots) and 6-dot half-size characters (character size: 6 × 12 dots). There will be a one-dot space between these fonts. The most significant bit in the data (8 bits) in DDRAM is allocated to the designation bit indicating a fullsize or half-size character. When this MSB is 0, the full-size character is selected, and when 1, the half-size character is selected. When the full-size character is selected, 2 bytes of DDRAM are linked and used as a 16-bit code (Figure 22). In this case, the lower byte is written into the smaller DDRAM address. 12 bits of this 16-bit code are used as character codes. Up to 4096 character codes can be specified. In addition, two of the remaining four bits can be allocated to a display-attribute code and can designate white/black inverted display for individual characters (refer to Display Attribute Designation). Table 18 shows the relationship between the 16-bit designated JIS code and the HD66730/1 12-bit character code. 8-bit data designating half-size characters are used as an 8-bit code (Figure 23). Specifically, 7 bits of the 8-bit half-size characters become the character codes, so that a total of 128 characters can be displayed (alphanumeric characters and symbols can be displayed as half-size characters). User fonts can be displayed using the CGRAM. Special symbols not included in the internal CGROM or the JIS Level-2 Kanji Set can be displayed as needed. Since the display font size of the CGRAM is 12 × 13 dots, CGRAM fonts can be displayed to the right, left, top or bottom, in order to be used to display doublesize characters or graphics. Note that the display-attribute code (A1/A0) designation that is to be written into the DDRAM is ignored when the CGRAM is used. In this case, bits 6 and 7 in the CGRAM are used for display-attribute-code designation. Refer to CGRAM for details. Table 19 Relationship between JIS Codes and HD66730 Character Codes • JIS first byte code: b1 to b7 (7 bits) • JIS second byte code: a1 to a7 (7 bits) • CGRAM address for user fonts: u0 to u2 (3 bits) Character Code Arrangement of HD66730 JIS b7 b6 b5 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 Non-kanji 0 1 0 a7 a6 b3 b2 b1 0 0 a5 a4 a3 a2 a1 Level 1 kanji 0 1 1 b7 b4 b3 b2 b1 a7 a6 a5 a4 a3 a2 a1 Level 1 kanji 1 0 0 b7 b4 b3 b2 b1 a7 a6 a5 a4 a3 a2 a1 User font — — — 0 0 0 0 0 0 0 0 0 u2 u1 u0 Upper byte Lower byte 87 HD66730/HD66731 Full-size character format 0 A1 A0 Display attribute code 0 C11 C10 C9 C8 Upper byte Display attribute code: A1/A0 (2 bits) Upper character code MSB C7 C6 C5 C4 C3 C2 C1 C0 Lower byte Lower character code Figure 22 Full-Size Character Codes Half-size character format 1 C6 C5 C4 C3 C2 C1 C0 Character code MSB LSB Character code: C6 to C0 (7 bits) Figure 23 Half-Size Character Codes 88 LSB Character code: C11 to C0 (12 bits) HD66730/HD66731 An example of displaying full-size and half-size characters together is described here. Full-size character display conforms to JIS (16 bits). Perform code conversion (16 bits → 12 bits) according to the relationship between the 16-bit JIS code and the HD66730/1 12-bit character code and write two-byte character data to the DDRAM (write the lower byte to the smaller DDRAM address). The example is shown in Table 19. When displaying a half-size character, refer to Table 5 the HD66730/1 Halfsize Font List and write one-byte character data into the DDRAM. The example is shown in Table 20. Figure 24 shows how to set data to the DDRAM when performing a 2-line display and Figure 25 shows the resulting liquid crystal display. Table 20 Example of Full-Size Font Conversion Displayed Character Table 21 JIS Code (First/Second Byte) Character Code (C11 to C0) 45/6C (Hex) AEC (Hex) 35/7E (Hex) 2FE (Hex) 45/54 (Hex) AD4 (Hex) 3E/2E (Hex) 72E (Hex) 4A/3F (Hex) D3F (Hex) 3B/54 (Hex) 5D4 (Hex) 4B/5C (Hex) DDC (Hex) 44/2E (Hex) A2C (Hex) 24/4E (Hex) A0E (Hex) Example of Half-Size Font Code Display Character Character Code (C0 to C11) 1 31 (Hex) 2 32 (Hex) 0 30 (Hex) , 2C (Hex) M 4D (Hex) C 43 (Hex) 89 HD66730/HD66731 0: Full-size designation 1: Half-size designation Address 1st-line data Address 2nd-line data 00 (Hex) 01 (Hex) 02 (Hex) 03 (Hex) 04 (Hex) 05 (Hex) 06 (Hex) 07 (Hex) 08 (Hex) 09 (Hex) 0A (Hex) (Hex) 0000 1010 1111 1110 0000 0010 1101 0100 0000 1010 0010 1110 0000 0111 0011 1111 0000 1101 1101 0100 0000 0101 40 41 42 43 44 45 46 47 48 49 4A 4B (Hex) 1101 1100 (Hex) 0000 1101 (Hex) 0010 1110 (Hex) 0000 1010 (Hex) 1011 0001 (Hex) 0000 1110 (Hex) 0000 1010 (Hex) 1011 0010 (Hex) 1011 0000 (Hex) 1010 1100 (Hex) 1100 1101 , Figure 24 Example of DDRAM Character Code (2-Line Display Mode) Figure 25 Example of Liquid Crystal Display 90 0B 1110 1100 (Hex) 1100 0011 HD66730/HD66731 Display Attribute Designation The HD66730/1 allocates 12 bits of the full-size 16-bit code character to an abbreviated character code and 2 bits to a display-attribute code (Figure 26). White/black inverted display, blinking display, and white/black inverted blinking display can be designated for each full-size character (Table 21). Display attribute control is performed for a 12 × 13 dot matrix unit that includes a 11 × 12 dot full-size character and a column of dots to the right and a row of dots to the bottom (Figure 27). The blinking cycle for blinking display and white/black inverted blinking display is 64 frames. Blinking display is performed by changing the display pattern every 32 frames. Since the 8-bit code designated for half-size characters cannot accommodate a display attribute, they will always be displayed normally. Table 22 Display Attribute Designation A1 A0 Display State 0 0 Normal display 0 1 White/black inverted display 1 0 Blinking display 1 1 White/black inverted blinking display 0 A1 A0 Attribute code 0 C11 C10 C9 C8 Upper character code C7 C6 C5 C4 C3 C2 C1 C0 Lower character code Figure 26 Full-Size Code Format 91 HD66730/HD66731 a) Example of normal display Normal display DDRAM code 1110 1100 0000 1010 b) Example of white/black inverted display White/black inverted display DDRAM code 1110 1100 0010 1010 c) Example of blinking display Blink display DDRAM code 1110 1100 Alternates display by 32 frames 0100 1010 d) Example of white/black inverted blinking display White/black inverted blinking display DDRAM code 1110 1100 Alternates display by 32 frames 0110 1010 Figure 27 Setting Codes in the DDRAM and Display Examples 92 HD66730/HD66731 Horizontal Smooth Scroll Data shown on the display can be scrolled horizontally to the left for a specified number of dots (Figure 28). The number of dots are set in scroll control register 3 (SCR3: R7), and the display lines to be scrolled are designated by the display line enable bits (SE1/SE2/SE3/SE4) in scroll control register 2 (SCR2: R6). Because the number of dots that can be set for scrolling here is 48, scrolling for more than this number can be achieved by shifting to the left by four characters of character code data in DDRAM for the scroll display line in question, rewriting the characters, and then scrolling again. When rewriting DDRAM while displaying characters, however, character output will momentarily breakdown, and the display may flicker. In this case, first check which display lines are currently being displayed by referring to NF1/0 (line 1 to the line 4) and display raster-rows LF0 to LF3 (raster-row 1 to raster-row 13) in the status register, and then rewrite a DDRAM line that is not being displayed. Keep in mind that scroll display line enable bits (SE1 to SE4) can be used to designate those display lines for which horizontal smooth scroll is desired. In partial scroll, one to three leftmost characters on the display as specified by the partial scroll bits (PS1/0) of the scroll control register 2 (SCR: R6) are fixed and the remaining characters undergo a smooth scroll to perform partial smooth scroll. When performing horizontal smooth scroll, the number of characters to be displayed (NC1/0: R4) must be at least 4 characters more than the number of characters actually displayed on the liquid crystal display. For example, set 10 or more display characters (NC1/0) for a single-chip 6-character display. 93 HD66730/HD66731 Performs no shift • SCR3 = “00” (Hex) Shifts to the left by one dot • SCR3 = “01” (Hex) Shifts to the left by two dots • SCR3 = “02” (Hex) Shifts to the left by ten dots • SCR3 = “0A” (Hex) Shifts to the left by 48 dots • SCR3 = “30” (Hex) Figure 28 Example of Horizontal Smooth Scroll Display 94 HD66730/HD66731 Examples of Register Setting R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 0 0 0 0 1 1 0 Index register set (R6 designation) 2 0 1 0 0 0 1 0 0 1 0 Enables scroll (scrolls only the second line) 3 0 0 0 0 0 0 0 1 1 1 Index register set (R7 designation) 4 0 1 0 0 0 0 0 0 0 1 Shifts the second line to the left by one dot 0 0 1 0 Shifts the second line to the left by two dots 0 0 1 1 Shifts the second line to the left by three dots 0 0 0 0 Shifts the second line to the left by 48 dots* CPU Wait 5 0 1 1 0 0 0 CPU Wait 6 0 1 1 0 0 0 CPU Wait 51 0 1 1 0 1 1 Note: The number of dots that can be specified for scrolling is 48. Scrolling for more than this number can be achieved by rewriting DDRAM data and scrolling again from dot 0. Note that the number of characters shown on the LCD and the number of scroll characters must be less than the number of maximum display characters (1-line display mode: 40 characters, 2-line display mode: 20 characters, 4-line display mode: 10 characters). Figure 29 Example of Executing Smooth Scroll to the Left 95 HD66730/HD66731 R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 0 0 0 0 1 1 0 Index register set (R6 designation) 2 0 1 0 0 0 1 0 0 1 0 Enables scroll (scrolls only the second line) 3 0 0 0 0 0 0 0 1 1 1 Index register set (R7 designation) 4 0 1 1 0 1 1 0 0 0 0 Shifts the second line to the left by 48 dots* 1 1 1 1 Shifts the second line to the left by 47 dots 0 0 0 1 Shifts the second line to the left by one dot 0 0 0 0 Perform no shift CPU Wait 5 0 1 1 0 1 0 CPU Wait 49 0 1 1 1 0 0 CPU Wait 51 0 1 1 0 0 0 Note: The number of dots that can be specified for scrolling is 48. Rewrite 48 dots (4 characters) of data inside the DDRAM and shift them to the right before scrolling. Scrolling for more than this number can be achieved by rewriting the data of DDRAM and begin scrolling from dot 48 again. Note that the number of characters shown on the LCD and the number of scroll characters must be less than the number of maximum display characters (1-line display mode: 40 characters, 2-line display mode: 20 characters, 4-line display mode: 10 characters). Figure 30 Example of Executing Smooth Scroll to the Right 96 HD66730/HD66731 Partial Smooth Scroll Partial smooth scroll displays one to three leftmost characters as fixed while the remaining ones undergo a horizontal smooth scroll in the left and right direction. Specifically, the number of leftmost characters to be fixed is specified by the partial scroll bits (PS1/0) in the scroll control register 2 (SCR2: R6). For example, when bits PS1/0 are 10, the two leftmost characters are fixed; when 11, the three leftmost characters are fixed. Although half-size characters can be displayed in a fixed display area, they must be displayed in evennumbered groups of two, four or six characters. Figure 31 shows an example of smooth scroll performed in a display when bits PS1/0 are set to 10. The two leftmost characters ( ) are displayed as fixed, and the remaining four characters undergo a smooth scroll. Perform no shift • PS1/0 = “10” • SCR3 = “00” (Hex) Shifts to the left by one dot • PS1/0 = “10” • SCR3 = “01” (Hex) Shifts to the left by two dots • PS1/0 = “10” • SCR3 = “02” (Hex) Shifts to the left by three dots • PS1/0 = “10” • SCR3 = “03” (Hex) Shifts to the left by 16 dots • PS1/0 = “10” • SCR3 = “0A” (Hex) Shifts to the left by 32 dots • PS1/0 = “10” • SCR3 = “20” (Hex) Figure 31 Example of Partial Smooth Scroll Display 97 HD66730/HD66731 Vertical Smooth Scroll Vertical smooth scroll up and down can be performed by setting the number of display lines (NL1/0: R4) to a value greater than the actual number of liquid crystal display lines, which can be set by the duty drive ratio (DT1/0: R1) to 1/14 (1-line display), 1/27 (2-line display), 1/40 (3-line display), or 1/53 (4-line display). The display line setting (NL1/0: R4), which controls the display, can select 1-line display mode, 2-line display mode, or 4-line display mode. For example, to perform normal vertical smooth scroll for a 3-line liquid crystal display with a duty ratio of 1/40, set the number of display lines (NL1/0: R4) to 4 lines. Note that if vertical smooth scroll is performed when the number of actual liquid display lines is the same as the number of set display lines, the display line that has scrolled out of the display will appear again from the bottom (or the top) (this function is called lap-around). In a 4-line crystal liquid display, only the lap-around function can be performed. Vertical smooth scroll is controlled by incrementing or decrementing the display line (SN1/0), which indicates which line to start from, and the display raster-row (SL0 to SL3). For example, when performing smooth scroll up, the display raster-row (SL0 to SL3) is incremented from 0000 to 1100 in order to scroll 12 raster-rows. Moreover, by incrementing the display line (SN1/0) and then incrementing the display raster-row from 0000 to 1100 again, a total of 25 raster-rows can be scrolled. Since the DDRAM is only 80 bytes, its data must be rewritten when performing continuous scroll exceeding this capacity. 98 HD66730/HD66731 Performs no scroll • SN1/0 = “00” • SL3 to 0 = “0000” 1-line scroll • SN1/0 = “00” • SL3 to 0 = “0001” 2-line scroll • SN1/0 = “00” • SL3 to 0 = “0010” 7-line scroll • SN1/0 = “00” • SL3 to 0 = “0111” 12-line scroll • SN1/0 = “00” • SL3 to 0 = “1100” Figure 32 Example of Vertical Smooth Scroll Display 99 HD66730/HD66731 Examples of Register Setting (2-Line Liquid Crystal Drive: DT1/0 = 01, 4-Line Display Mode: NL1/0 = 11) R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 2 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 Index register set (R5 designation) 0 0 0 1 Scrolls one raster-row up (Begins display from the second raster-row of the first line) 0 0 1 0 Scrolls two raster-rows up (Begins display from the third raster-row of the first line) 0 0 1 1 Scrolls three raster-rows up (Begins display from the fourth raster-row of the first line) 1 1 0 0 Scrolls 12 raster-rows up (Begins display from the 13th raster-row of the first line) 0 0 0 0 Scrolls 13 raster-rows up (Begins display from the first raster-row of the second line and displays the second and third lines) 1 1 0 0 0 0 0 0 CPU Wait 3 0 1 0 0 0 0 CPU Wait 4 0 1 0 0 0 0 CPU Wait 13 0 1 0 0 0 0 CPU Wait 14 0 1 0 0 1 0 CPU Wait 26 0 1 0 0 1 0 Scrolls 25 raster-rows up (Begins display from the 13th raster-row of the second line) CPU Wait 27 0 1 0 1 0 0 CPU Wait Scrolls 26 raster-rows up (Begins display from the first raster-row of the third line and displays the third and fourth lines) Note: The DDRAM has 80 bytes. For a 4-line display mode, a 4-line 10-character/line display can therefore be performed. Although the line and raster-row for scrolling can be designated as desired, the first raster-row of the first line will be displayed after displaying raster-row 13 of line 4. Figure 33 Example of Performing Smooth Scroll Up 100 HD66730/HD66731 R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 0 0 0 0 1 0 1 Index register set (R5 designation) 2 0 1 0 1 1 0 1 1 0 0 Scrolls one raster-row down (Begins display from the 13th raster-row of the fourth line) 1 0 1 1 Scrolls two raster-rows down (Begins display from the 12th raster-row of the fourth line) 1 0 1 0 Scrolls three raster-rows down (Begins display from the 11th raster-row of the fourth line) 0 0 0 0 Scrolls 13 raster-rows down (Begins display from the first raster-row of the fourth line) 1 1 0 0 Scrolls 14 raster-rows down (Begins display from the third raster-row of the 13th line) 0 0 0 0 Scrolls 26 raster-rows down (Begins display from the third raster-row of the first line) CPU Wait 3 0 1 0 1 1 0 CPU Wait 4 0 1 0 1 1 0 CPU Wait 14 0 1 0 1 1 0 CPU Wait 15 0 1 0 1 0 0 CPU Wait 27 0 1 0 1 0 0 Note: The DDRAM has 80 bytes. For a 4-line display mode, a 4-line 10-character/line display can therefore be performed. Although the line and raster-row for scrolling can be designated as desired, the first raster-row of the first line will be displayed after displaying raster-row 13 of line 4. Figure 34 Example of Performing Smooth Scroll Down 101 HD66730/HD66731 Extension Driver LSI Interface (HD66730) The HD66730 can interface with extension drivers using extension driver interface signals CL1, CL2, D, and M output from the HD66730, increasing the number of display characters (Figure 35). Although the liquid crystal driver voltage that drives the booster of the HD66730 can also be used as the driver power supply of extension drivers, the output voltage drop of the booster increases as the load of the booster increases. b) Using extension driver a) Single-chip operation COM1 to COM25 2-line/6-character display HD66730 CL1 CL2 D M HD66730 SEG1 to SEG71 COM1 to COM25 2-line/12-character display SEG1 to SEG71 SEG1 to SEG72 M D CL2 CL1 Y1 to Y73 HD66002 Figure 35 HD66730 and Extension Driver LSI Connection 102 HD66730/HD66731 Interfacing with the Liquid Crystal Panel By connecting the HD66730 to extension drivers, the display can be expanded up to a 1-line/40-character, 2-line/20-character, or a 4-line/10-character display configuration. Bits DT1/0 set the duty drive ratio and bits NC1/0 set the number of characters per line. In addition, bits NL1/0 sets the number of display lines during display read control. Table 22 shows the relationship between the number of characters actually displayed on the liquid crystal panel and the corresponding number of extension drivers needed. Table 23 Relationship between the Number of Liquid Crystal Display Characters and Extension Drivers Number of Display Characters per Line Display Lines 6 10 12 16 20 40 Duty Characters Characters Characters Characters Characters Characters Drive 1 line (0/0) (2/0) (2/0) (3/0) (5/0) (11/0) 1/14 2 lines (0/0) (2/0) (2/0) (3/0) (5/0) Display disabled 1/27 3 lines (0/1) (2/1) Display disabled Display disabled Display disabled Display disabled 1/40 4 lines (0/1) (2/1) Display disabled Display disabled Display disabled Display disabled 1/53 Notes: 1. Numbers in parentheses = (number of extension segment drivers/number of common drivers) 2. This is an example when using the 40 output extension drivers, and when Nh represents display characters and Nd extension driver outputs, the number of extension drivers needed can generally be calculated as follows: [Number of extension drivers] = (12 * Nh – 71 – 1)/Nd] ↑ 3. The right-edge segment (space between characters) is not displayed in 6-character or 16character display. 4. Horizontal smooth scroll cannot be performed during an 1-line/40-character, 2-line/20-character, 3-line/10-character, or 4-line/10-character display. 103 HD66730/HD66731 Example of Interfacing with a 1-Line Display Panel 1 HD66730 6 COM1 COM2 COM12 COMS ± + − × ÷ = ≠ SEG1 SEG2 SEG12 SEG71 Note: The rightmost dot-column space of the 6th character cannot be displayd. Figure 36 Example of 1-Line/6-Character + 71-Segment Display (Using 1/14 Duty) HD66730 1 6 7 12 COM1 COM2 COM12 COMS ± + − × ÷ = ≠ SEG1 SEG2 SEG12 SEG71 COM14 COM15 COM25 Note: 1. The above figure shows how a liquid crystal panel can be arranged into a 1-line/12-character display while operating the HD66730 in 2-line/6-character display mode. Although the duty ratio becomes high, extension drivers will not be needed. COM13 for spaces between display lines will not be needed. Figure 37 Example of 1-Line/12-Character + 71-Segment Display (Using 1/27 Duty) 104 HD66730/HD66731 Example of Interfacing with a 2-Line Display Panel HD66730 1 6 COM1 COM2 COM12 COM13 COM14 COM25 COMS ± + − × ÷ = ≠ SEG1 SEG2 SEG12 SEG71 Note: 1. When performing vertical smooth scroll, or displaying double-size characters or graphic figures by the CGRAM, COM13 can be used for spaces between lines. Display can be performed continuously vertically. Figure 38 Example of 2-Line/6-Character + 71-Segment Display (Using 1/27 Duty) 105 HD66730/HD66731 1 6 COMS COM1 COM2 COM19 HD66731 ± + – × ÷ = ≠ SEG1 SEG2 SEG12 SEG72 COM20 COM39 COM40 Note: COMS and COM40 output the same. Figure 39 Example of 3-Line/6-Character + 72-Segment Display (Using 1/40 Duty) 106 RS R/W E DB4~DB7 DB0~DB3 V5 V4 V3 V2 V1 OSC2 OSC1 RS COM1 R/W ~COM25 E DB4~DB7 COMS DB0~DB3 SEG1 ~SEG71 CL1 CL2 M D VCC HD66730 GND 26 Rf com24 com25 com1 com2 com3 CL1 D 71 2 3 4 VCC VCC VEE GND D1R E SHL HD66002 (1) Y80, Y79,…Y2, Y1 80 seg.240 seg.239 seg.238 seg.237 1 seg.2 239 D0L CAR VCC Open VCC VEE GND D1R E SHL HD66002 (2) Open Open CAR D0L (Latch clock) (Shift clock) Y80, Y79,…Y2, Y1 77 seg.1 240 19-character 2line LCD panel (228 × 25 dot + 96 segments) 1/27 Duty seg.3 238 Notes: 1. The resistance of R depends on the type of the LCD panel used (Usually 2 kΩ to 10 kΩ). 2. To stabilize the power supply, place two 0.1-µF capacitors near each LCD driver: one between the VCC and GND pins, and the other between the VCC and VEE. VEE (–7V) R R 2×R R R VCC (+3V) GND (0V) V5 V1 V2 V3 V4 CL2 seg1 seg2 seg3 Input waveform timechart V1 V3 V4 V2 CL1 CL2 M D2R, D3L TEST1 TEST2 FCS seg226 seg227 seg228 V1 V3 V4 V2 CL1 CL2 M D2R, D3L TEST1 TEST2 FCS MPU HD66730/HD66731 Interfacing between HD66730 and HD66002 Figure 40 Example of Display Extension Curcuit 107 HD66730/HD66731 Oscillator Figure 41 shows the optimal value of the oscillation frequency or the external clock frequency depends on the duty drive ratio setting (DT1/0), number of display lines (NL1/0), and the number of display characters (NC1/0) in the HD66730/1. The oscillation frequency or the external clock frequency must be adjusted according to the frame frequency of the liquid crystal drive. 1) When an external clock is used Clock 2) When an internal oscillator is used OSC1 OSC1 Rf HD66730 HD66731 OSC2 HD66730 HD66731 Note: The oscillator frequency can be adjusted by an oscillator resistor (Rf). Refer to Electrical Characteristics for the relationship between the oscillator resistor (Rf) and the oscillator frequency. If Rf is increased or power supply voltage is decreased, the oscillator frequency decreases. Figure 41 Oscillator Connections 108 HD66730/HD66731 Relationship between the Oscillation Frequency and the Liquid Crystal Display Frame Frequency Figures 42 to 45 and Tables 24 to 27 show the oscillation frequency and the external clock frequency for various registor settings when the frame frequency is 80 Hz. 1-line selection period 1 2 3 4 13 14 1 2 3 13 14 VCC V1 COM1 V4 V5 1 frame (Number of dots per screen) 1 frame (Number of dots per screen) Figure 42 Frame Frequency (1/14 Duty Cycle) 109 HD66730/HD66731 Table 24 1/14 Duty Drive Number of Display Lines: 1-Line Display (NL1/0 Set Value): (00) Number of display characters 6 characters 20 characters 40 characters (NC1/0 set value) (00) (01) (11) 1-line selection period (dot) 72 dots 240 dots 480 dots Number of dots per screen (dot) 1008 dots 3360 dots 6720 dots Oscillation frequency (kHz)* 70 235 475 Number of Display Lines: 2-line Display (NL1/0 Set Value): (01) Number of display characters 6 characters 20 characters 40 characters (NC1/0 set value) (00) (01) (11) 1-line selection period (dot) 72 dots 120 dots 240 dots Number of dots per screen (dot) 1008 dots 1680 dots 3360 dots Oscillation frequency (kHz)* 70 120 235 Number of Display Lines: 4-Line Display (NL1/0 Set Value): (11) Number of display characters 6 characters 10 characters (NC1/0 set value) (00) (01) 1-line selection period (dot) 72 dots 120 dots Number of dots per screen (dot) 1008 dots 1680 dots Oscillation frequency (kHz)* 70 120 Note: 110 * The frequencies in Table 23 are examples when the frame frequency is set to 70 Hz. Adjust the oscillation frequency so that a optimum frame frequency can be obtained. HD66730/HD66731 1/27 Duty Cycle (DT1/0 = 01: 2-Line Drive) 1-line selection period 1 2 3 4 26 27 1 2 3 26 27 VCC V1 COM1 V4 V5 1 frame (Number of dots per screen) 1 frame (Number of dots per screen) Figure 43 Frame Frequency (1/27 Duty Cycle) Table 25 1/27 Duty Drive Number of Display Lines: 2-Line Display (NL1/0 Set Value): (01) Number of display characters 6 characters 10 characters 20 characters (NC1/0 set value) (00) (01) (11) 1-line selection period (dot) 72 dots 120 dots 240 dots Number of dots per screen (dot) 1944 dots 3240 dots 6480 dots Oscillation frequency (kHz)* 135 225 475 Number of Display Lines: 4-Line Display (NL1/0 Set Value): (11) Number of display characters 6 characters 10 characters (NC1/0 set value) (00) (01) 1-line selection period (dot) 72 dots 120 dots Number of dots per screen (dot) 1944 dots 3240 dots Oscillation frequency (kHz)* 135 225 Note: * The frequencies in Table 24 are examples when the frame frequency is set to 70 Hz. Adjust the oscillation frequency so that an optimum frame frequency can be obtained. 111 HD66730/HD66731 1/40 Duty Cycle (DT1/0 = 10: 3-Line Drive) 1-line selection period 1 2 3 4 39 40 1 2 3 39 40 VCC V1 COM1 V4 V5 1 frame 1 frame (Number of dots per screen) (Number of dots per screen) Figure 44 Frame Frequency (1/40 Duty Cycle) Table 26 1/40 Duty Drive Number of Display Lines: 4-Line Display (NL1/0 set value): (11) Number of display characters 6 characters 10 characters (NC1/0 set value) (00) (01) 1-line selection period (dot) 72 dots 120 dots Number of dots per screen (dot) 2880 dots 4800 dots Oscillation frequency (kHz)* 200 335 Note: 112 * The frequencies in Table 25 are examples when the frame frequency is set to 70 Hz. Adjust the oscillation frequency so that an optimum frame frequency can be obtained. HD66730/HD66731 1/53 Duty Cycle (DT1/0 = 11: 4-Line Drive) 1-line selection period 1 2 3 4 52 53 1 2 3 52 53 VCC V1 COM1 V4 V5 1 frame (Number of dots per screen) 1 frame (Number of dots per screen) Figure 45 Frame Frequency (1/53 Duty Cycle) Table 27 1/53 Duty Drive Number of Display Lines: 4-line Display (11) (NL1/0 Setting Value): (00) (01) Number of display characters 6 characters 10 characters (NC1/0 setting value) (00) (01) 1-line selection period (dot) 72 dots 120 dots Number of dots per screen (dot) 3816 dots 6360 dots Oscillation frequency (kHz)* 265 445 Note: * The frequencies in Table 26 are examples when the frame frequency is to 80 Hz. Adjust the oscillation frequency so that an optimum frame frequency can be obtained. 113 HD66730/HD66731 Power Supply for Liquid Crystal Display Drive The HD66730/1 incorporates a booster for raising the LCD voltage two or three times that of the reference voltage input below VCC (Figure 48). A two or three times boosted voltage can be obtained by externally attaching two or three 1-µF capacitors. If the LCD panel is large and needs a large amount of drive current, the values of bleeder resistors that generate the V1 to V5 potential are made smaller. However, the load current in the booster and the voltage drop increases in this case. We recommend setting the resistance value of each bleeder larger than 4.7 kΩ and to hold down the DC load current to 0.4 mA if using a booster circuit. An external power supply should supply LCD voltage if the DC load current exceeds 0.7 mA (Figure 49). Refer to Electrical Characteristics showing the relationship between the load current and booster voltage output. Table 27 shows the duty factor and bleeder resistor value for power supply for liquid crystal display drive. Table 28 Duty Factor and Bleeder Resistor Value for Power Supply for Liquid Crystal Display Drive Item Data Drive lines (DT1/0 setting value) 1 2 3 4 Duty factor 1/14 1/27 1/40 1/53 Bias 1/4.7 1/6.2 1/7.3 1/8.3 R1 R R R R R0 R*0.7 R*2.2 R*3.3 R*4.3 Bleeder resistance value Note: * R changes depending on the size of a liquid crystal panel. Normally, R must be 4.7 kΩ to 20 kΩ. Adjust R to the optimum value with the consumption current and display picture quality. VCC R1 VCC V1 R1 V2 R0 V3 R1 V4 R1 V5 VR VEE Figure 46 Example of Power Supply for Liquid Crystal Display Drive (with External Power Supply) 114 HD66730/HD66731 (Double boosting) (Triple boosting) VCC VCC Vci Thermistor GND VCC V1 V2 GND C1 C2 1 µF + V5OUT2 V5OUT3 1 µF + GND V3 V4 V5 R1 Vci Thermistor GND R1 R0 V1 V2 GND 1 µF R1 R1 VCC 1 µF + V5OUT2 V5OUT3 + 1 µF C1 C2 V3 V4 V5 R1 R1 R0 R1 R1 + GND Notes: 1. The reference voltage input (Vci) must be set below the power supply (VCC). 2. Current that flows into reference voltage input (Vci) is 2-3 times larger than the load current flowing through bleeder resistors. Note that a reference voltage drop occurs due to the current flowing into the Vci input when a reference voltage (Vci) is generated by resistor division. 3. The amount of output voltage (V5OUT2/V5OUT3) drop of a booster circuit also increases as the load current flowing through bleeder resistors increases. Thus, set the bleeder resistance as large as possible (4.7 kΩ or greater) without affecting display picture quality. 4. Adjust the reference voltage input (Vci) according to the fluctuation of booster characteristics because the output voltage (V5OUT2/V5OUT3) drop depends on the load current, operation temperature, operation frequency, capacitance of external capacitors, and manufacturing tolerance. Refer to Electrical Characteristics for details. 5. Adjust the reference voltage input (Vci) so that the output voltage (V5OUT2/V5OUT3) after boosting will not exceed the absolute maximum rating of liquid crystal power supply voltage (15V). 6. Make sure that you connect polarized capacitors correctly. Figure 47 Example of Power Supply for Liquid Crystal Display Drive (with Internal Booster) 115 HD66730/HD66731 VCC VCC VCC Vci GND 1µF 1µF + R1 GND R0 C2 V3 V5OUT2 V4 V5OUT3 GND 1µF Vci GND V2 C1 + R1 V1 GND 1µF R1 1µF R1 V5 R1 V2 + R0 C2 V3 V5OUT2 V4 V5OUT3 V5 R1 R1 GND 1µF • R1= 4.7kΩ to 15kΩ + R1 V1 C1 + • R1= 15kΩ to 47kΩ • C0= 0.1µF to 0.5µF + i) Example of normal power supply C0 + + + + VCC ii) Example of low power supply Figure 48 Example of Power Supply for Low Power Consumption VCC VCC VCC Vci Rth V1 GND GND 1µF V2 C1 + V3 C2 V5OUT2 1µF V5OUT3 + GND 1µF + GND VCC V4 V5 R1 Vci R1 GND R0 V1 GND 1µF R1 C1 + C2 V5OUT2 R1 1µF VCC V5OUT3 V2 V3 V4 V5 R1 Vci R1 GND V1 GND 1µF R0 R1 GND + C2 V5OUT2 1µF Rth 1µF + C1 R1 + GND V5OUT3 + V2 V3 V4 V5 R1 R1 1µF + GND Rth R0 Ra R1 R1 Rb GND Figure 49 Example of Temperature Compensation Circuit 116 VCC HD66730/HD66731 Absolute Maximum Ratings (HD66730)* Item Symbol Value Unit Notes Power supply voltage (1) VCC –0.3 to +7.0 V 1 Power supply voltage (2) VCC–V5 –0.3 to +17.0 V 1, 2 Input voltage Vt –0.3 to VCC + 0.3 V 1 Operating temperature Topr –30 to +75 °C Storage temperature Tstg –55 to +125 °C Note: * 4 If the LSI is used above these absolute maximum ratings, it may become permanently damaged. Using the LSI within the following electrical characteristic limits is strongly recommended for normal operation. If these electrical characteristic conditions are also exceeded, the LSI will malfunction and cause poor reliability. Absolute Maximum Ratings (HD66731)* Item Symbol Value Unit Notes Power supply voltage (1) VCC –0.3 to +7.0 V 1 Power supply voltage (2) VCC–V5 –0.3 to +17.0 V 1, 2 Input voltage Vt –0.3 to VCC + 0.3 V 1 Operating temperature Topr –40 to +85 °C Storage temperature Tstg –55 to +110 °C Note: * 4 If the LSI is used above these absolute maximum ratings, it may become permanently damaged. Using the LSI within the following electrical characteristic limits is strongly recommended for normal operation. If these electrical characteristic conditions are also exceeded, the LSI will malfunction and cause poor reliability. 117 HD66730/HD66731 DC Characteristics (VCC = 2.4 V to 5.5 V, Ta = –30 to +75°C*3) Item Symbol Min Typ Max Unit Input high voltage (1) (except OSC1) VIH1 0.7V CC — VCC V Input low voltage (1) (except OSC1) VIL1 –0.3 — 0.2V CC V VCC = 2.4 to 3.0V –0.3 — 0.6 V VCC = 3.0 to 4.5V Input high voltage (2) (OSC1) VIH2 0.7V CC — VCC V 15 Input low voltage (2) (OSC1) VIL2 — — 0.2V CC V 15 Output high voltage (1) (D0–D7) VOH1 0.75V CC — — V –I OH = 0.1 mA 7 Output low voltage (1) (D0–D7) VOL1 — — 0.2V CC V I OL = 0.1 mA 7 Output high voltage (2) (except D0–D7) VOH2 0.8V CC — — V –I OH = 0.04 mA 8 Output low voltage (2) (except D0–D7) VOL2 — — 0.2V CC V I OL = 0.04 mA 8 Driver ON resistance (COM) RCOM — 2 20 kΩ ±Id = 0.05 mA, VLCD = 4V 13 Driver ON resistance (SEG) RSEG — 2 30 kΩ ±Id = 0.05 mA, VLCD = 4V 13 I/O leakage current I LI –1 — 1 µA VIN = 0 to VCC 9 Pull-up MOS current (RESET* pin) –I p 5 50 120 µA VCC = 3V VIN = 0V Power supply current I CC1 — 150 300 µA Rf oscillation, external clock VCC = 3V, f OSC = 215 kHz I CC2 — 25 — µA Sleep mode VCC = 3V f OSC = 215 kHz VLCD 3.0 — 15.0 V VCC–V5 LCD voltage 118 Test Condition Notes 5, 6 5, 6 10, 14 16 HD66730/HD66731 Booster Characteristics Item Symbol Min Typ Max Unit Test Condition Notes* Output voltage (V5OUT2 pin) VUP2 8.2 8.9 — V VCC = Vci = 4.5V, I o = 0.25 mA, C = 1 µF, f OSC = 215 kHz, Ta = 25°C 18 Output voltage (V5OUT3 pin) VUP3 7.2 7.8 — V VCC = Vci = 2.7V, I o = 0.25 mA, C = 1 µF, f OSC = 215 kHz, Ta = 25°C 18 Input voltage VCi 1.0 — 5.0 V Vci ≤ VCC 18, 19 AC Characteristics (VCC = 2.4V to 5.5V, Ta = –30 to +75°C*3) Clock Characteristics (V CC = 2.7 V to 5.5 V, Ta = –30 to +75°C*3) Item External clock operation Rf oscillation Symbol Min External clock frequency f cp Typ Max Unit Test Condition Notes* 80 215 350 kHz VCC = 2.4 to 2.7V 11 80 215 550 kHz VCC = 2.7 to 5.5V External clock duty Duty 45 50 55 % External clock rise time t rcp — — 0.2 µs External clock fall time t rcp — — 0.2 µs Clock oscillation frequency (HD66730) f OSC 110 150 200 kHz Rf = 150 kΩ, VCC = 3V 12 Clock oscillation frequency (HD66731) f OSC 150 215 275 kHz Rf = 91 kΩ, VCC = 3V 12 119 HD66730/HD66731 System Interface Timing Characteristics (1) (VCC = 2.4V to 4.5V, Ta = –30 to +75°C*3) Bus Write Operation Item Symbol Min Typ Max Unit Test Condition Enable cycle time t CYCE 500 — — ns Figure 50 Enable pulse width (high level) PWEH 250 — — VCC = 2.4 to 3.0V Enable rise/fall time t Er, t Ef 150 — — VCC = 3.0 to 4.5V — — 20 Figure 50 Address set-up time (RS, R/W to E) t AS 80 — — Address hold time t AH 20 — — Data set-up time t DSW 140 — — Data hold time tH 30 — — Bus Read Operation Item Symbol Min Typ Max Unit Test Condition Enable cycle time t CYCE 1000 — — ns Figure 51 Enable pulse width (high level) PWEH 450 — — Enable rise/fall time t Er, t Ef — — 25 Address set-up time (RS, R/W to E) t AS 60 — — Address hold time t AH 20 — — Data delay time t DDR — — 360 Data hold time t DHR 5 — — Serial Interface Operation Item Symbol Min Typ Max Unit Test Condition Serial clock cycle time t SCYC 1 — 20 µs Figure 52 Serial clock (high level width) t SCH 400 — — ns Serial clock (low level width) t SCL 400 — — Serial clock rise/fall time t scr , t scf — — 50 Chip select set-up time t CSU 60 — — Chip select hold time t CH 200 — — Serial input data set-up time t SISU 200 — — Serial input data hold time t SIH 200 — — Serial output data delay time t SOD — — 360 Serial output data hold time t SOH 5 — — 120 HD66730/HD66731 System Interface Timing Characteristics (2) (VCC = 4.5V to 5.5V, Ta = –30 to +75°C*3) Bus Write Operation Item Symbol Min Typ Max Unit Test Condition Enable cycle time t CYCE 500 — — ns Figure 50 Enable pulse width (high level) PWEH 150 — — Enable rise/fall time t Er, t Ef — — 20 Address set-up time (RS, R/W to E) t AS 40 — — Address hold time t AH 30 — — Data set-up time t DSW 80 — — Data hold time tH 30 — — Item Symbol Min Typ Max Unit Test Condition Enable cycle time t CYCE 500 — — ns Figure 51 Enable pulse width (high level) PWEH 230 — — Enable rise/fall time t Er, t Ef — — 20 Address set-up time (RS, R/W to E) t AS 40 — — Address hold time t AH 30 — — Data delay time t DDR — — 160 Data hold time t DHR 5 — — Item Symbol Min Typ Max Unit Test Condition Serial clock cycle time t SCYC 0.5 — 20 µs Figure 52 Serial clock (high level width) t SCH 200 — — ns Serial clock (low level width) t SCL 200 — — Serial clock rise/fall time t scr , t scf — — 50 Chip select set-up time t CSU 60 — — Chip select hold time t CH 100 — — Serial input data set-up time t SISU 100 — — Serial input data hold time t SIH 100 — — Serial output data delay time t SOD — — 160 Serial output data hold time t SOH 5 — — Bus Read Operation Serial Interface Sequence 121 HD66730/HD66731 HD66730 Segment Extension Signal Timing Characteristics (VCC = 2.4V to 5.5V, Ta = –30 to +75°C*3) Item Symbol Min Typ Max Unit Test Condition High level t CWH 800 — — ns Figure 53 Low level t CWL 800 — — Clock set-up time t CSU 500 — — Data set-up time t SU 300 — — Data hold time t DH 300 — — M delay time t DM –1000 — 1000 COMD set-up time t DSU 300 t ct1 — — 700 Pins except t ct2 COMD — — 200 Clock pulse width Clock rise/fall time COMD Reset Timing Characteristics (VCC = 2.4V to 5.5V, Ta = –30 to +75°C*3) Item Symbol Min Typ Max Unit Test Condition Reset low-level width t RES 10 — — ms Figure 54 122 HD66730/HD66731 Electrical Characteristics Notes 1. All voltage values are referred to GND = 0V. If the LSI is used above the absolute maximum ratings, it may become permanently damaged. Using the LSI within the electrical characteristic is strongly recommended to ensure normal operation. If these electrical characteristic are exceeded, the LSI may malfunction or exhibit poor reliability. 2. VCC ≥ V5 must be maintained. When the COM25/COMD pin is used as a extention driver interface signal (COMD), GND ≥ V5 must be maintained. 3. For die products, specified at 75°C. 4. For die products, specified by the die shipment specification. 5. The following four circuits are I/O pin configurations except for liquid crystal display output. Input pin Pin: E/SCLK, RS/CS*, RW/SID, IM, Input pin Pins: RESET* VCC VCC VCC PMOS PMOS Output pin Pins: CL1, CL2, M, SEGD (HD66730) TESTD (HD66731) VCC PMOS PMOS NMOS NMOS (Pull-up MOS) NMOS I/O Pin Pins: DB0/SOD to DB7 VCC VCC (Input circuit) (Pull-up MOS) PMOS PMOS Input enable NMOS VCC NMOS PMOS Output enable Data NMOS (Output circuit: tristate) 6. 7. 8. 9. Applies to input pins and I/O pins, excluding the OSC1 pin. Applies to I/O pins. Applies to output pins of HD66730. Current flowing through pull-up MOSs, excluding output drive MOSs. 123 HD66730/HD66731 10. Input/output current is excluded. When input is at an intermediate level with CMOS, the excessive current flows through the input circuit to the power supply. To avoid this from happening, the input level must be fixed high or low. 11. Applies only to external clock operation. Th Oscillator Tl OSC1 Open 0.7 VCC 0.5 VCC 0.3 VCC OSC2 t rcp Duty = t fcp Th × 100% Th + Tl 12. Applies only to the internal oscillator operation using oscillation resistor Rf. Recommended registor value OSC1 Rf: 150kΩ±2% (When VCC = 3V to 4V) Rf: 180kΩ±2% (When VCC = 4V to 5V) Rf OSC2 Since oscillation frequency varies depending on OSC1 and OSC2 terminal capacitance,wiring length to these pins should be minimized. 200 fOSC (kHz) 150 100 VCC = 5V (typ.) VCC = 3V (typ.) 50 0 100 150 200 300 400 500 Rf (kΩ) 124 600 700 800 HD66730/HD66731 13. RCOM is the resistance between the power supply pins (V CC, V1, V4, V5) and each common signal pin (COM0 to COM25/COM53). RSEG is the resistance between the power supply pins (VCC, V2, V3, V5) and each segment signal pin (SEG1 to SEG71/SEG119). 14. The following graphs show the relationship between operation frequency and current consumption (referential data). VCC = 5V 0.9 0.8 0.8 0.7 0.7 typ.(Normal display) 0.5 0.4 0.3 0.2 typ.(Sleep mode) 0.6 ICC (mA) 0.6 ICC (mA) VCC = 3V 0.9 0.5 0.4 0.2 0.1 0.1 0.0 0.0 0 100 200 300 400 500 typ.(Normal display) 0.3 typ.(Sleep mode) 0 100 200 300 400 500 fOSC or fCP (kHz) fOSC or fCP (kHz) 15. Applies to the OSC1 pin. 16. Each COM and SEG output voltage is within ±0.15V of the LCD voltage (V CC, V1, V2, V3, V4, V5) when there is no load. 17. The TEST pin must be fixed to ground, and the IM pin must also be connected to VCC or ground. 18. Booster characteristics test circuits are shown below. (Double boosting) VCC (Triple boosting) Rload Vci + V5OUT2 + V5OUT3 GND IO C1 1 µF 1 µF Rload Vci IO C1 C2 VCC + C2 V5OUT2 + 1 µF + 1 µF V5OUT3 GND 1 µF 125 HD66730/HD66731 VUP2=VCC –V5OUT2 VUP3=VCC –V5OUT3 11 10 9 8 7 6 5 4 Boosting three times Boosting twice typ. VUP3(V) VUP2(V) (i) VUP2,VUP3 vs Vci 2.0 3.0 4.0 Vci (V) 5.0 15 14 13 12 11 10 9 8 7 6 typ. 2.0 3.0 4.0 Vci (V) 5.0 Test condition : Vci=VCC, fcp=140kHz, Ta=25° C Test condition : Vci=VCC, fcp=140kHz, Ta=25°C (ii) VUP2, VUP3 vs Ta Boosting twice Boosting three times 9.5 8.5 typ. 8.5 8.0 7.5 -60 8.0 VUP3(V) VUP2(V) 9.0 -20 0 20 60 7.5 7.0 6.5 -60 100 typ. -20 0 20 Ta (°C) 60 100 Ta (°C) Test condition : Vci=VCC=2.7V, Rf=150kΩ IO=0.1mA Test condition : Vci=VCC=4.5V, Rf=180kΩ IO=0.1mA (iii) VUP2, VUP3 vs Capacitance Boosting twice Boosting three times typ. 8.5 8.0 VUP3(V) VUP2(V) 9.0 8.0 7.5 typ. 7.5 7.0 6.5 7.0 0.5 1.0 C (µF) 6.0 0.5 1.5 1.0 C (µF) 1.5 Test condition : Vci=VCC=2.7V, Rf=150kΩ IO=0.1mA Test condition : Vci=VCC=4.5V,Rf=180kΩ IO=0.1mA (iv) VUP2, VUP3 vs IO Boosting three times 8.0 typ. 7.5 7.0 6.5 6.0 0.0 0.5 1.0 IO (mA) 1.5 2.0 Test condition : Vci=VCC=4.5V,Rf=180kΩ Ta=25°C 19. Vci ≤ VCC must be maintained. 126 VUP3(V) VUP2(V) Boosting twice 9.0 8.5 8.0 7.0 6.0 5.0 4.0 3.0 2.0 0.0 typ. 0.5 1.0 IO (mA) 1.5 2.0 Test condition : Vci=VCC=2.7V, Rf=150kΩ Ta=25°C HD66730/HD66731 Load Circuits AC Characteristics Test Load Circuits Data bus: DB0 to DB7, SOD Segment extension signals: CL1, CL2, SEGD, M, COMD Test point Test point 50 pF 30 pF 127 HD66730/HD66731 Timing Characteristics RS VIH1 VIL1 VIH1 VIL1 t AH t AS R/W VIL1 VIL1 t AH PWEH t Ef VIH1 VIL1 E VIH1 VIL1 t Er VIL1 tH t DSW VIH1 VIL1 DB0 to DB7 VIH1 VIL1 Valid data tCYCE Figure 50 Bus Write Operation RS VIH1 VIL1 VIH1 VIL1 t AH t AS R/W VIH1 VIH1 PWEH t AH t Ef E VIL1 VIH1 VIH1 VIL1 VIL1 t Er t DHR t DDR DB0 to DB7 VOH1 VOL1 Valid data tCYCE Figure 51 Bus Read Operation 128 VOH1 VOL1 HD66730/HD66731 tSCYC CS* VIL1 VIL1 tCSU tSCr VIH1 VIL1 SCLK tSCf tSCH VIL1 VIH1 VIL1 tSISU tSIH VIH1 VIL1 SID tCH tSCL VIH1 VIL1 VIH1 VIL1 tSOD tSOH VOH1 VOL1 SOD VOH1 VOL1 Figure 52 Serial Interface Timing t ct VOH2 CL1 VOH2 VOL2 t CWH t CWH CL2 VOH2 VOL2 t CWL t ct t CSU VOH2 VOL2 SEGD t DH t SU M VOL2 t DSU t DM VOH2 COMD Figure 53 Interface Timing with Extension Driver 129 HD66730/HD66731 tRES RESET* VIL1 VIL1 Figure 54 Reset Timing 2.7V/4.5V*2 VCC 0.2V 0.2V 0.2V tOFF*1 trcc 0.1 ms ≤ trcc ≤ 10 ms tOFF ≥ 1 ms Notes: 1. tOFF compensates for the power oscillation period caused by momentary power supply oscillations. 2. Specified at 4.5V for 5-volt operation, and at 2.7V for 3-volt operation. Figure 55 Power Supply Sequence 130