AVAGO HCPL-6751 Hermetically sealed, low if, wide vcc, high gain optocoupler Datasheet

6N140A,* HCPL-675X, 83024, HCPL-570X, HCPL-177K, 5962-89810,
HCPL-573X, HCPL-673X, 5962-89785, 5962-98002
Hermetically Sealed, Low IF, Wide VCC,
High Gain Optocouplers
Data Sheet
*See matrix for available extensions.
Description
Features
These units are single, dual, and quad channel, hermetically sealed optocouplers. The products are capable of
operation and storage over the full military temperature
range and can be purchased as either standard product
or with full MIL-PRF-38534 Class Level H or K testing or
from the appropriate DLA Drawing. All devices are manufactured and tested on a MIL-PRF-38534 certified line
and are included in the DLA Qualified Manufacturers List
QML-38534 for Hybrid Microcircuits.
 Dual marked with device part number and DLA
drawing number
 Manufactured and tested on a MIL-PRF-38534 Certified
Line
 QML-38534, Class H and K
 Five hermetically sealed package configurations
 Performance guaranteed over full military temperature
range: -55°C to +125°C
 Low input current requirement: 0.5 mA
 High current transfer ratio: 1500% typical @ IF = 0.5 mA
 Low output saturation voltage: 0.11 V typical
 1500 Vdc withstand test voltage
 High radiation immunity
 6N138/9, HCPL-2730/31 function compatibility
 Reliability data
Each channel contains a GaAsP light emitting diode which
is optically coupled to an integrated high gain photon
detector. The high gain output stage features an open
collector output providing both lower saturation voltage
and higher signaling speed than possible with conventional photo-Darlington optocouplers. The shallow depth
and small junctions offered by the IC process provides
better radiation immunity than conventional photo transistor optocouplers.
The supply voltage can be operated as low as 2.0 V without
adversely affecting the parametric performance.
These devices have a 300% minimum CTR at an input
current of only 0.5 mA making them ideal for use in low
input current applications such as MOS, CMOS, low power
logic interfaces or line receivers. Compatibility with high
voltage CMOS logic systems is assured by specifying ICCH
and IOH at 18 Volts.
Applications















Military and aerospace
High reliability systems
Telephone ring detection
Microprocessor system interface
Transportation, medical, and life critical systems
Isolated input line receiver
EIA RS-232-C line receiver
Voltage level shifting
Isolated input line receiver
Isolated output line driver
Logic ground isolation
Harsh industrial environments
Current loop receiver
System test equipment isolation
Process control input/output isolation
The connection of a 0.1 F bypass capacitor between VCC and GND is recommended.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Upon special request, the following device selections can
be made: CTR minimum of up to 600% at 0.5 mA, and
lower output leakage current levels to 100 A.
Functional Diagram
Multiple Channel Devices Available
1
8
2
7
3
6
4
5
Package styles for these parts are 8 and 16 pin DIP through
hole (case outlines P and E respectively), 16 pin DIP flat
pack (case outline F), and leadless ceramic chip carrier
(case outline 2). Devices may be purchased with a variety
of lead bend and plating options. See Selection Guide
table for details. Standard Military Drawing (SMD) parts
are available for each package and lead style.
Because the same electrical die (emitters and detectors)
are used for each channel of each device listed in this data
sheet, absolute maximum ratings, recommended operating
conditions, electrical specifications, and performance characteristics shown in the figures are similar for all parts
except as noted. Additionally, the same package assembly
processes and materials are used in all devices. These similarities justify the use of a common data base for die related
reliability and certain limited radiation test results.
Truth Table
(Positive Logic)
Input
Output
On (H)
L
Off (L)
H
Selection Guide-Package Styles and Lead Configuration Options
Package
16 pin DIP
8 pin DIP
8 pin DIP
16 pin Flat Pack
20 Pad LCCC
Lead Style
Channels
Common Channel Wiring
Avago Part # & Options
Commercial
MIL-PRF-38534 Class H
MIL-PRF-38534 Class K
Standard Lead Finish
Solder Dipped*
Butt Cut/Gold Plate
Gull Wing/Soldered*
Crew Cut/Gold Plate
Class H SMD Part #
Through Hole
4
VCC, GND
Through Hole
1
None
Through Hole
2
VCC, GND
Unformed Leads
4
VCC, GND
Surface Mount
2
None
6N140A[1]
6N140A/883B
HCPL-177K
Gold Plate
Option #200
Option #100
Option #300
Option #600
HCPL-5700
HCPL-5701
HCPL-570K
Gold Plate
Option #200
Option #100
Option #300
Option #600
HCPL-5730
HCPL-5731
HCPL-573K
Gold Plate
Option #200
Option #100
Option #300
Option #600
HCPL-6750
HCPL-6751
HCPL-675K
Gold Plate
HCPL-6730
HCPL-6731
HCPL-673K
Solder Pads*
None
8302401EC
8302401EA
8302401YC
8302401YA
8302401XA
8302401ZC
8302401ZA
59628981001PC
8981001PA
8981001YC
8981001YA
8981001XA
Available
Available
59628978501PC
8978501PA
8978501YC
8978501YA
8978501ZA
Available
Available
None
8302401FC
5962-
59629800201KEC
9800201KEA
9800201KYC
9800201KYA
9800201KXA
9800201KZC
9800201KZA
59628981002KPC
8981002KPA
8981002KYC
8981002KYA
8981002KXA
Available
Available
59628978503KPC
8978503KPA
8978503KYC
8978503KYA
8978503KZA
Available
Available
59629800201KFC
Prescript for all below
Gold Plate
Solder Dipped*
Butt Cut/Gold Plate
Butt Cut/Soldered*
Gull Wing/Soldered*
Crew Cut/Gold Plate
Crew Cut/Soldered*
Class K SMD Part #
Prescript for all below
Gold Plate
Solder Dipped*
Butt Cut/Gold Plate
Butt Cut/Soldered*
Gull Wing/Soldered*
Crew Cut/Gold Plate
Crew Cut/Soldered*
*Solder contains lead.
Note:
1. JEDEC registered part.
2
89785022A
59628978504K2A
Functional Diagrams
16 pin DIP
8 pin DIP
8 pin DIP
16 pin Flat Pack
20 Pad LCCC
Through Hole
Through Hole
Through Hole
Unformed Leads
Surface Mount
4 Channels
1 Channel
2 Channels
4 Channels
2 Channels
15
1
16
8
1
8
1
VCC2
16
1
VO2
19
2
15
3
14
4
13
2
7
2
7
2
3
6
3
6
3
4
5
4
5
15
15
20
14
14
2
GND2
VCC1
13
12
10
3
13
4
GND1
VO1
7
5
12
5
12
6
11
6
11
7
10
7
10
8
9
8
9
8
Note: All DIP and flat pack devices have common VCC and ground. LCCC (leadless ceramic chip carrier) package has isolated channels with separate
VCC and ground connections.
Outline Drawings
16 Pin DIP Through Hole, 4 Channels
20.06 (0.790)
20.83 (0.820)
8.13 (0.320)
MAX.
0.89 (0.035)
1.65 (0.065)
4.45 (0.175)
MAX.
0.51 (0.020)
MIN.
3.81 (0.150)
MIN.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
0.20 (0.008)
0.33 (0.013)
7.36 (0.290)
7.87 (0.310)
Note: Dimensions in Millimeters (Inches)
Leaded Device Marking
Avago LOGO
Avago P/N
DLA SMD*
DLA SMD*
PIN ONE/
ESD IDENT
A QYYWWZ
XXXXXX
XXXXXXX
XXX XXX
t 50434
*QUALIFIED PARTS ONLY
3
Leadless Device Marking
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
COUNTRY OF MFR.
Avago CAGE CODE*
Avago LOGO
Avago P/N
PIN ONE/
ESD IDENT
COUNTRY OF MFR.
A QYYWWZ
XXXXXX
t XXXX
XXXXXX
XXX 50434
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
DLA SMD*
DLA SMD*
Avago CAGE CODE*
Outline Drawings (continued)
16 Pin Flat Pack, 4 Channels
7.24 (0.285)
6.99 (0.275)
2.29 (0.090)
MAX.
1.27 (0.050)
REF.
11.13 (0.438)
10.72 (0.422)
0.46 (0.018)
0.36 (0.014)
8.13 (0.320)
MAX.
2.85 (0.112)
MAX.
0.88 (0.0345)
MIN.
0.89 (0.035)
0.69 (0.027)
5.23
(0.206)
MAX.
0.31 (0.012)
0.23 (0.009)
9.02 (0.355)
8.76 (0.345)
Note: Dimensions in Millimeters (Inches)
20 Terminal LCCC Surface Mount, 2 Channels
8 Pin DIP Through Hole, 1 and 2 Channel
8.70 (0.342)
9.10 (0.358)
9.40 (0.370)
9.91 (0.390)
0.76 (0.030)
1.27 (0.050)
4.95 (0.195)
5.21 (0.205)
1.78 (0.070)
2.03 (0.080)
1.02 (0.040) (3 PLCS)
1.14 (0.045)
1.40 (0.055)
8.70 (0.342)
9.10 (0.358)
4.95 (0.195)
5.21 (0.205)
TERMINAL 1 IDENTIFIER
2.16 (0.085)
0.64
(0.025)
(20 PLCS)
0.51 (0.020)
MIN.
3.81 (0.150)
MIN.
0.51 (0.020)
1.52 (0.060)
2.03 (0.080)
Note: Dimensions in Millimeters (Inches).
Solder Thickness 0.127 (0.005) Max.
4
7.16 (0.282)
7.57 (0.298)
4.32 (0.170)
MAX.
METALIZED
CASTILLATIONS (20 PLCS)
1.78 (0.070)
2.03 (0.080)
8.13 (0.320)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
Note: Dimensions in Millimeters (Inches).
0.20 (0.008)
0.33 (0.013)
7.36 (0.290)
7.87 (0.310)
Hermetic Optocoupler Options
Option
Description
100
Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below for details).
4.32 (0.170)
MAX.
0.51 (0.020)
MIN.
1.14 (0.045)
1.40 (0.055)
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
4.32 (0.170)
MAX.
0.51 (0.020)
MIN.
1.14 (0.045)
1.40 (0.055)
0.20 (0.008)
0.33 (0.013)
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
7.36 (0.290)
7.87 (0.310)
Note: Dimensions in Millimeters (Inches).
200
Lead finish is solder dipped rather than gold plated. This option is available on commercial and hi-rel product in 8 and
16 pin DIP. DLA Drawing part numbers contain provisions for lead finish. All leadless chip carrier devices are delivered
with solder dipped terminals as a standard feature.
300
Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is available on
commercial and hi-rel product in 8 and 16 pin DIP (see drawings below for details). This option has solder dipped
leads.
4.57 (0.180)
MAX.
0.51 (0.020)
MIN.
1.40 (0.055)
1.65 (0.065)
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
4.57 (0.180)
MAX.
0.51 (0.020)
MIN.
1.40 (0.055)
1.65 (0.065)
4.57 (0.180)
MAX.
0.20 (0.008)
0.33 (0.013)
5° MAX.
9.65 (0.380)
9.91 (0.390)
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
1.07 (0.042)
1.32 (0.052)
Note: Dimensions in Millimeters (Inches).
600
Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below for details). Contact factory for the availability of this
option on DLA part types.
3.81 (0.150)
MIN.
MAX.
0.51 (0.020)
MIN.
0.20 (0.008)
0.33 (0.013)
2.29 (0.090)
2.79 (0.110)
1.14 (0.045)
1.25 (0.049)
Note: Dimensions in Millimeters (Inches).
Solder contains lead.
5
3.81 (0.150)
MAX.
7.36 (0.290)
7.87 (0.310)
0.51 (0.020)
MIN.
2.29 (0.090)
2.79 (0.110)
1.02 (0.040)
TYP.
Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
TS
-65
+150
°C
Operating Temperature
TA
-55
+125
°C
Case Temperature
TC
+170
°C
Junction Temperature
TJ
+175
°C
260 for 10 sec
°C
40
mA
Lead Solder Temperature
Notes
Output Current (each channel)
IO
Output Voltage (each channel)
VO
-0.5
20
V
1
Supply Voltage
VCC
-0.5
20
V
1
Output Power Dissipation (each channel)
50
mW
2
Peak Input Current (each channel, <1 ms duration)
20
mA
Average Input Current (each channel)
IF
10
mA
Reverse Input Voltage (each channel)
VR
5
V
Package Power Dissipation (each channel)
PD
200
mW
3
8 Pin Ceramic DIP Single Channel Schematic
ANODE
2
IF
VCC
8
ICC
+
VF
CATHODE
–
IO 6
3
5
VO
GND
ESD Classification
(MIL-STD-883, Method 3015)
HCPL-5700/01/0K and 6730/31/3K
(
), Class 2
6N140A, 6N140A/883B, HCPL-177K,
HCPL-6750/51/5K and HCPL-5730/31/3K
(Dot), Class 3
Recommended Operating Conditions
Parameter
Symbol
Input Voltage, Low Level (Each Channel)
VF(OFF)
Input Current, High Level (Each Channel)
IF(ON)
Supply Voltage
Output Voltage
6
Min.
Max.
Units
0.8
V
0.5
5
mA
VCC
2.0
18
V
VO
2.0
18
V
Electrical Characteristics, TA = -55°C to +125°C, unless otherwise specified
Min.
Typ.**
1, 2, 3
300
1500
IF = 1.6 mA, VO = 0.4 V,
VCC = 4.5 V
300
1000
IF =5 mA, VO = 0.4 V,
VCC = 4.5 V
200
500
Parameter
Symbol
Test Conditions
Current Transfer
Ratio
CTR*
IF = 0.5 mA, VO = 0.4 V,
VCC = 4.5 V
Logic Low Output
Voltage
VOL
Logic
High
Supply
Current
IF = 0.5 mA, IOL = 1.5 mA,
VCC = 4.5 V
1, 2, 3
3
4, 5
V
2
4
0.4
4, 16
IF =5 mA, IOL = 10 mA,
VCC = 4.5 V
0.16
0.4
4
0.001
250
A
4
250
A
4, 6
1.0
2
mA
15
Dual
Channel
IF1 =IF2 = 1.6 mA,
VCC = 18 V
1.0
4
Quad
Channel
IF1 = IF2 =IF3 =IF4 =1.6 mA,
VCC = 18 V
1.7
4
Single
ICCH*
Channel
and LCCC
IF =0 mA, VCC = 18 V
0.001
20
Dual
Channel
IF1 =IF2 = 0 mA,
VCC = 18 V
40
Quad
Channel
IF1 = IF2 =IF3 =IF4 =0 mA,
VCC = 18 V
40
IF = 1.6 mA
1, 2, 3
1
1.0
1.7
1.7
3
1.8
1, 2, 3
Quad
Channel
1, 2
1.0
3
IR = 10 A
1, 2, 3
Input-Output
II-O*
Insulation Leakage
Current
≤65% Relative Humidity
TA =25°C, t = 5 s,
VI-O = 1500 VDC
1
Capacitance
Between
Input-Output
f= 1 MHz, TA =25°C
4
* For JEDEC registered parts.
** All typical values are at VCC = 5 V, TA = 25°C.
1.4
2
LCCC
CI-O
%
0.13
1, 2, 3
BVR*
Note
IF = 1.6 mA, IOL = 4.8 mA,
VCC = 4.5 V
IF =1.6 mA, VCC = 18 V
Input Reverse
Breakdown
Voltage
Fig.
0.4
Single
ICCL*
Channel
and LCCC
VF*
Units
0.11
1, 2, 3
Single
Input
Forward and Dual
Voltage Channel
7
Max.
IF =2 A, VO = 18 V,
VCC = 18 V
Logic High Output IOH*
Current
IOHX
Logic
Low
Supply
Current
Limits
Group A[13]
Subgroup
1.4
1.8
1.4
1.7
4
A
V
15
1
4
1.8
5
V
4
1.0
A
7, 12
4
pF
4, 8
14, 17
Electrical Characteristics (cont), TA = -55°C to +125°C, unless otherwise specified
Parameter
Symbol
Propagation Delay tPHL*
Time to Logic Low
at Output
tPHL
tPHL*
Propagation Delay tPLH*
Time to Logic High
at Output
tPLH
tPLH*
Group A[13]
Subgroup
Test Conditions
Limits
Min.
Typ.**
Max.
Units
Fig.
Note
s
5, 6,
7, 8
4
IF = 0.5 mA, RL = 4.7 k,
VCC =5 V
9, 10, 11
30
100
IF = 1.6 mA, RL = 1.5 k,
VCC =5 V
9, 10, 11
5
30
4, 16
IF =5 mA, RL = 680 ,
VCC =5 V
9
2
5
4, 17
10, 11
10
9, 10, 11
10
4, 16
s
IF = 0.5 mA, RL = 4.7 k,
VCC =5 V
9, 10, 11
17
60
IF = 1.6 mA, RL = 1.5 k,
VCC =5 V
9, 10, 11
14
50
4, 16
IF =5 mA, RL = 680 ,
VCC =5 V
9
8
20
4, 17
10, 11
30
9, 10, 11
30
5, 6,
7, 8
4
4, 16
Common Mode
Transient
Immunity at Low
Output Level
|CML|
VCC =5 V, IF = 1.6 mA
RL =1.5 k
|VCM|= 25 VP-P[17]
|VCM|= 50 VP-P[16]
9, 10, 11
500
1000
V/s
9
4, 10
11, 14
Common Mode
Transient
Immunity at High
Output Level
|CMH|
VCC =5 V, IF =0 mA
RL =1.5 k
|VCM|= 25 VP-P[17]
|VCM|= 50 VP-P[16]
9, 10, 11
500
1000
V/s
9
4, 10
11, 14
* For JEDEC registered parts.
** All typical values are at VCC = 5 V, TA = 25°C.
Typical Characteristics, TA = 25°C, VCC = 5 V
Parameter
Sym.
Typ.
Units
Test Conditions
Note
Input Capacitance
CIN
60
pF
VF =0 V, f = 1 MHz
4
Input Diode Temperature
Coefficient
VF/TA
-1.8
mV/°C
IF = 1.6 mA
4
Resistance (Input-Output)
RI-O
1012

VI-O = 500 V
4, 8
Capacitance (Input-Output)
CI-O
2.0
pF
f = 1 MHz
4, 8
Input-Input Leakage Current
II-I
0.5
nA
Relative Humidity = ≤65%,
VI-I = 500 V, t = 5 s
9
Resistance (Input-Input)
RI-I
1012

VI-I = 500 V
9
Capacitance (Input-Input)
CI-I
1.0
pF
f = 1 MHz
9
Dual and Quad Channel Product Only
8
Notes:
1. GND Pin should be the most negative voltage at the detector side.
Keeping VCC as low as possible, but greater than 2.0 V, will provide
lowest total IOH over temperature.
2. Output power is collector output power plus total supply power for
the single channel device. For the dual channel device, output power
is collector output power plus one half the total supply power. For
the quad channel device, output power is collector output power
plus one fourth of total supply power. Derate at 1.66 mW/°C above
110°C.
3. Derate IF at 0.33 mA/°C above 110°C.
4. Each channel.
5. CURRENT TRANSFER RATIO is defined as the ratio of output collector
current, IO, to the forward LED input current, IF, times 100%.
6. IOHX is the leakage current resulting from channel to channel optical
crosstalk. IF = 2 μA for channel under test. For all other channels,
IF = 10 mA.
7. All devices are considered two-terminal devices; measured between
all input leads or terminals shorted together and all output leads or
terminals shorted together.
8. Measured between each input pair shorted together and all output
connections for that channel shorted together.
9. Measured between adjacent input pairs shorted together for each
multi-channel device.
10. CML is the maximum rate of rise of the common mode voltage that
can be sustained with the output voltage in the logic low state
(VO < 0.8 V). CMH is the maximum rate of fall of the common mode
voltage that can be sustained with the output voltage in the logic
high state (VO > 2.0 V).
9
11. In applications where dV/dt may exceed 50,000 V/s (such as
a static discharge) a series resistor, RCC, should be included to
protect the detector ICs from destructively high surge currents. The
recommended value is:
1 (V)
RCC = ————— k
0.15 IF (mA)
for single channel;
1 (V)
RCC = ————— k
0.3 IF (mA)
for dual channel;
1 (V)
RCC = ————— k
0.6 IF (mA)
for quad channel.
12. This is a momentary withstand test, not an operating condition.
13. Standard parts receive 100% testing at 25°C (Subgroups 1 and
9). SMD and 883B parts receive 100% testing at 25,125, and -55°C
(Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).
14. Parameters tested as part of device initial characterization and
after design and process changes. Parameters guaranteed to limits
specified for all lots not specifically tested.
15. The HCPL-6730, HCPL-6731, and HCPL-673K dual channel parts
function as two independent single channel units. Use the single
channel parameter limits.
16. Not required for 6N140A, 6N140A/883B, HCPL-177K, HCPL6750/51/5K, 8302401, and 5962-9800201 types.
17. Required for 6N140A, 6N140A/883B, HCPL-177K, HCPL-6750/51/5K,
8302401, and 5962-9800201 types.
Figure 1. Input Diode Forward Current vs. Forward
Voltage.
Figure 2. Normalized DC Transfer Characteristics.
Figure 3. Normalized Current Transfer Ratio vs.
Input Diode Forward Current.
Figure 4. Normalized Supply Current vs. Input
Diode Forward Current.
Figure 5. Propagation Delay to Logic Low vs. Input
Pulse Period.
Figure 6. Propagation Delay vs. Temperature.
Figure 7. Propagation Delay vs. Input Diode
Forward Current.
10
PULSE GEN.
ZO = 50 
tr, tf = 50 ns
f = 100 Hz
tPULSE = 0.5ms
RCC *
IF
IF MONITOR
Rm
1
8
2
7
3
6
4
5
56 
1.0 F
IF
+5 V
RL
RCC *
B
1
8
2
7
3
6
A
VO
CL**
VFF
4
VCC
R1
R2
1
8
2
7
3
6
4
5
R2 MAY BE OMITTED
IF ADDITIONAL FANOUT
IS NOT USED.
Figure 10. Recommended Drive Circuitry Using TTL Open-Collector Logic.
11
VCM
–
* SEE NOTE 11
Figure 8. Switching Test Circuit (f, tP not JEDEC registered).
2.4  VF
IF
VCC  VF  IF R2
R1 ≤
IF + ILEAK
+5 V
RL
PULSE GEN.
* SEE NOTE 11
** CL INCLUDES PROBE AND STRAY WIRING CAPACITANCE.
R2 ≥
1.0 F
5
+
ILEAK
56 
Figure 9. Test Circuit for Transient Immunity and Typical Waveforms.
VO
MIL-PRF-38534 Class H, Class K, and
DLA SMD Test Program
Avago’s Hi-Rel Optocouplers are in compliance with MILPRF-38534 Class H and K. Class H and Class K devices are
also in compliance with DLA drawings 83024, 5962-89785,
5962-89810, and 5962-98002.
Testing consists of 100% screening and quality conformance inspection to MIL-PRF-38534.
VCC + 18 V
(EACH INPUT)
+
VIN
–
1
8
2
7
3
6
4
5
VOC
0.01 F
(EACH OUTPUT)
CONDITIONS: IF = 10 mA
IO = 40 mA
TA = +125°C
* ALL CHANNELS TESTED SIMULTANEOUSLY.
Figure 11. Operating Circuit for Burn-In and Steady State Life Tests.
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved. Obsoletes 5968-9400E
AV02-1766EN - October 2, 2012
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