HCPL-4504/J454/0454, HCNW4504 High CMR, High Speed Optocouplers Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Features Description The HCPL-4504 and HCPL-0454 contain a GaAsP LED while the HCPL-J454 and HCNW4504 contain an AlGaAs LED. The LED is optically coupled to an integrated high gain photo detector. The HCPL-4504 series has short propagation delays and high CTR. The HCPL-4504 series also has a guaranteed propagation delay difference (tPLH-tPHL). These features make the HCPL-4504 series an excellent solution to IPM inverter dead time and other switching problems. The CTR, propagation delay, and CMR are specified both for TTL and IPM conditions which are provided for ease of application. These single channel, diode-transistor optocouplers are available in 8-Pin DIP, SO-8, and Widebody package configurations. An insulating layer between a LED and an integrated photodetector provide electrical insulation between input and output. Separate connections for the photodiode bias and output-transistor collector increase the speed up to a hundred times that of a conventional phototransistor coupler by reducing the base collector capacitance. Functional Diagram • Short propagation delays for TTL and IPM applications • 15 kV/μs minimum Common Mode Transient immunity at VCM = 1500 V for TTL/load drive • High CTR at TA = 25°C >25% for HCPL-4504/0454 >23% for HCNW4504 >19% for HCPL-J454 • Electrical specifications for common IPM applications • TTL compatible • Open collector output • Safety approval: UL recognized – 3750 V rms/1min. for HCPL-4504/0454/J454 – 5000 V rms/1min. for HCPL-4504 Option 020 and HCNW4504 CSA approved IEC/EN/DIN EN 60747-5-2 approved – VIORM = 560 Vpeak for HCPL-0454 Option 060 – VIORM = 630 Vpeak for HCPL-4504 Option 060 – VIORM = 891 Vpeak for HCPL-J454 – VIORM = 1414 Vpeak for HCNW4504 Applications 8 VCC NC 1 ANODE 2 7 NC CATHODE 3 6 VO TRUTH TABLE LED VO LOW ON HIGH OFF 5 GND NC 4 A 0.1 μF bypass capacitor between pins 5 and 8 is recommended. Schematic ICC 8 VCC IF + ANODE 2 VF CATHODE IO – 6 • Inverter circuits and Intelligent Power Module (IPM) interfacing: High Common Mode Transient immunity (> 10 kV/μs for an IPM load/drive) and (tPLH - tPHL) Specified (see Power Inverter Dead Time section) • Line receivers: Short propagation delays and low input-output capacitance • High speed logic ground isolation: TTL/TTL, TTL/ CMOS, TTL/LSTTL • Replaces pulse transformers: Save board space and weight • Analog signal ground isolation: Integrated photodetector provides improved linearity over phototransistors VO 3 SHIELD 5 GND CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Ordering Information HCPL-0454, HCPL-4504 and HCPL-J454 are UL Recognized with 3750 Vrms for 1 minute per UL1577. HCNW4504 is UL Recognized with 5000 Vrms for 1 minute per UL1577. HCPL-0454, HCPL-4504, HCPL-J454 and HCNW4504 are approved under CSA Component Acceptance Notice #5, File CA 88324. Part Number HCPL-4504 HCPL-J454 HCPL-0454 HCNW4504 Option RoHS non RoHS Compliant Compliant Package Surface Mount Gull Wing -000E no option -300E #300 X X -500E #500 X X -020E #020 -320E #320 X X -520E #520 X X -060E #060 -360E #360 X X -560E #560 X X -000E no option -300E #300 X X Tape & Reel UL 1577 5000 Vrms/ 1 Minute rating IEC/EN/DIN EN 60747-5-2 Quantity 50 per tube 300 mil DIP-8 50 per tube X X 1000 per reel X 50 per tube X 50 per tube X 1000 per reel X 300 mil DIP-8 X 50 per tube X 50 per tube X 1000 per reel X 50 per tube X 50 per tube -400E NA X X X 50 per tube -500E #500 X X X X 1000 per reel -600E NA X X X X 750 per reel -000E no option X -500E #500 -060E #060 -560E #560 -000E no option -300E #300 -500E #500 SO-8 100 per tube X X X X 400 mil Widebody DIP-8 1500 per reel X X X X X X X 100 per tube X 1500 per reel X X 42 per tube X X 42 per tube X X 750 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: HCPL-4504-560E to order product of 300 mil DIP Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-2 Safety Approval and RoHS compliant. Example 2: HCPL-4504 to order product of 300 mil DIP package in Tube packaging and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since July 15, 2001 and RoHS compliant will use ‘–XXXE.’ 2 Package Outline Drawings HCPL-4504 Outline Drawing 7.62 ± 0.25 (0.300 ± 0.010) 9.65 ± 0.25 (0.380 ± 0.010) 8 TYPE NUMBER 7 6 5 6.35 ± 0.25 (0.250 ± 0.010) OPTION CODE* DATE CODE A XXXXZ YYWW RU 1 2 3 4 UL RECOGNITION 1.78 (0.070) MAX. 1.19 (0.047) MAX. + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002) 5° TYP. 3.56 ± 0.13 (0.140 ± 0.005) 4.70 (0.185) MAX. 0.51 (0.020) MIN. 2.92 (0.115) MIN. DIMENSIONS IN MILLIMETERS AND (INCHES). 0.65 (0.025) MAX. 1.080 ± 0.320 (0.043 ± 0.013) * MARKING CODE LETTER FOR OPTION NUMBERS "L" = OPTION 020 "V" = OPTION 060 OPTION NUMBERS 300 AND 500 NOT MARKED. 2.54 ± 0.25 (0.100 ± 0.010) NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. HCPL-4504 Gull Wing Surface Mount Option 300 Outline Drawing LAND PATTERN RECOMMENDATION 9.65 ± 0.25 (0.380 ± 0.010) 8 7 6 1.016 (0.040) 5 6.350 ± 0.25 (0.250 ± 0.010) 1 2 3 10.9 (0.430) 4 1.27 (0.050) 1.19 (0.047) MAX. 1.780 (0.070) MAX. 9.65 ± 0.25 (0.380 ± 0.010) 7.62 ± 0.25 (0.300 ± 0.010) 3.56 ± 0.13 (0.140 ± 0.005) 1.080 ± 0.320 (0.043 ± 0.013) 0.635 ± 0.25 (0.025 ± 0.010) 0.635 ± 0.130 2.54 (0.025 ± 0.005) (0.100) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES). NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. 3 2.0 (0.080) + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002) 12° NOM. Package Outline Drawings HCPL-J454 Outline Drawing 7.62 ± 0.25 (0.300 ± 0.010) 9.80 ± 0.25 (0.386 ± 0.010) 8 7 6 5 6.35 ± 0.25 (0.250 ± 0.010) TYPE NUMBER DATE CODE A XXXX YYWW RU 1 2 3 UL RECOGNITION 4 1.78 (0.070) MAX. 1.19 (0.047) MAX. 5 TYP. 3.56 ± 0.13 (0.140 ± 0.005) 4.70 (0.185) MAX. + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002) 0.51 (0.020) MIN. 2.92 (0.115) MIN. 0.65 (0.025) MAX. 1.080 ± 0.320 (0.043 ± 0.013) 2.54 ± 0.25 (0.100 ± 0.010) DIMENSIONS IN MILLIMETERS AND (INCHES). OPTION NUMBERS 300 AND 500 NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX. HCPL-J454 Gull Wing Surface Mount Option 300 Outline Drawing LAND PATTERN RECOMMENDATION 9.80 ± 0.25 (0.386 ± 0.010) 8 7 6 1.016 (0.040) 5 6.350 ± 0.25 (0.250 ± 0.010) 1 2 3 10.9 (0.430) 4 1.27 (0.050) 1.19 (0.047) MAX. 1.780 (0.070) MAX. 9.65 ± 0.25 (0.380 ± 0.010) 7.62 ± 0.25 (0.300 ± 0.010) 3.56 ± 0.13 (0.140 ± 0.005) 1.080 ± 0.320 (0.043 ± 0.013) 0.635 ± 0.25 (0.025 ± 0.010) 0.635 ± 0.130 2.54 (0.025 ± 0.005) (0.100) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES). NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX. 4 2.0 (0.080) + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002) 12° NOM. HCPL-J454-400E/600E Widelead Gullwing Surface Mount Outline Drawing LAND PATTERN RECOMMENDATION 9.80 ±0.25 0.386 ±0.010 1.016 0.040 TYPE NUMBER 12.9 0.508 A XXXX DATE CODE 6.35 ±0.25 0.250 ±0.010 YYWW RU 1.27 0.050 UL RECOGNITION 2.0 0.08 [0.65] 0.025 MAX [11.75 0.25] 0.460 0.010 [1.19] 0.047 MAX. 7.62 ±0.51 0.300 ±0.020 [0.20] 0.008 [0.33] 0.013 3.56 ±0.13 0.140 ±0.005 [0.152] 0.006 [0.406] 0.016 [1.080] 0.320 0.043 0.013 2.54 0.100 BSC 0.625 ±0.254 0.025 ±0.010 30° NOM. LEAD COPLANARITY MAXIMUM: [0.102] 0.004 DIMENSIONS IN [MILLIMETERS] INCHES OPTION NUMBERS 400 AND 600 NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX. HCPL-0454 Outline Drawing (8-Pin Small Outline Package) LAND PATTERN RECOMMENDATION 8 7 6 5 5.994 ± 0.203 (0.236 ± 0.008) XXX YWW 3.937 ± 0.127 (0.155 ± 0.005) 7.49 (0.295) TYPE NUMBER (LAST 3 DIGITS) DATE CODE PIN ONE 1 2 3 0.406 ± 0.076 (0.016 ± 0.003) 4 1.9 (0.075) 1.270 BSC (0.050) 0.64 (0.025) * 5.080 ± 0.127 (0.200 ± 0.005) 3.175 ± 0.127 (0.125 ± 0.005) 7 45 X 0.432 (0.017) 0~7 0.228 ± 0.025 (0.009 ± 0.001) 1.524 (0.060) 0.203 ± 0.102 (0.008 ± 0.004) * TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH) 5.207 ± 0.254 (0.205 ± 0.010) 0.305 MIN. (0.012) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX. NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX. 5 HCNW4504 Outline Drawing (8-Pin Widebody Package) 11.00 MAX. (0.433) 11.15 ± 0.15 (0.442 ± 0.006) 8 7 6 9.00 ± 0.15 (0.354 ± 0.006) 5 TYPE NUMBER A HCNWXXXX DATE CODE YYWW 1 2 3 4 10.16 (0.400) TYP. 1.55 (0.061) MAX. 7° TYP. + 0.076 0.254 - 0.0051 + 0.003) (0.010 - 0.002) 5.10 MAX. (0.201) 3.10 (0.122) 3.90 (0.154) 0.51 (0.021) MIN. 2.54 (0.100) TYP. 1.78 ± 0.15 (0.070 ± 0.006) 0.40 (0.016) 0.56 (0.022) DIMENSIONS IN MILLIMETERS (INCHES). NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. HCNW4504 Gull Wing Surface Mount Option 300 Outline Drawing 11.15 ± 0.15 (0.442 ± 0.006) 8 7 6 LAND PATTERN RECOMMENDATION 5 9.00 ± 0.15 (0.354 ± 0.006) 1 2 3 13.56 (0.534) 4 1.3 (0.051) 2.29 (0.09) 12.30 ± 0.30 (0.484 ± 0.012) 1.55 (0.061) MAX. 11.00 MAX. (0.433) 4.00 MAX. (0.158) 1.78 ± 0.15 (0.070 ± 0.006) 2.54 (0.100) BSC 0.75 ± 0.25 (0.030 ± 0.010) 1.00 ± 0.15 (0.039 ± 0.006) + 0.076 0.254 - 0.0051 + 0.003) (0.010 - 0.002) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES). NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. 6 7° NOM. Solder Reflow Temperature Profile 300 PREHEATING RATE 3 °C + 1 °C/–0.5 °C/SEC. REFLOW HEATING RATE 2.5 °C ± 0.5 °C/SEC. 200 PEAK TEMP. 245 °C PEAK TEMP. 240 °C TEMPERATURE (°C) 2.5 C ± 0.5 °C/SEC. 30 SEC. 160 °C 150 °C 140 °C PEAK TEMP. 230 °C SOLDERING TIME 200 °C 30 SEC. 3 °C + 1 °C/–0.5 °C 100 PREHEATING TIME 150 °C, 90 + 30 SEC. 50 SEC. TIGHT TYPICAL LOOSE ROOM TEMPERATURE 0 50 0 100 150 TIME (SECONDS) NOTE: NON-HALIDE FLUX SHOULD BE USED. Recommended Pb-Free IR Profile tp Tp TEMPERATURE TL Tsmax TIME WITHIN 5 °C of ACTUAL PEAK TEMPERATURE 15 SEC. * 260 +0/-5 °C 217 °C 150 - 200 °C RAMP-UP 3 °C/SEC. MAX. RAMP-DOWN 6 °C/SEC. MAX. Tsmin ts PREHEAT 60 to 180 SEC. tL 60 to 150 SEC. 25 t 25 °C to PEAK TIME NOTES: THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX. Tsmax = 200 °C, Tsmin = 150 °C NOTE: NON-HALIDE FLUX SHOULD BE USED. * RECOMMENDED PEAK TEMPERATURE FOR WIDEBODY 400mils PACKAGE IS 245 °C 7 200 250 Regulatory Information The devices contained in this data sheet have been approved by the following agencies: Agency/Standard Underwriters Laboratories (UL) HCPL-4504 HCPL-J454 HCPL-0454 HCNW4504 UL1577 3750 Vrms / 1 minute, Option 020 5000 Vrms / 1 minute 3750 Vrms / 1 minute 3750 Vrms / 1 minute 5000 Vrms / 1 minute Component Acceptance Notice #5 3750 Vrms / 1 minute, Option 020 5000 Vrms / 1 minute 3750 Vrms / 1 minute 3750 Vrms / 1 minute 5000 Vrms / 1 minute Option 060 VIORM = 630 Vpeak VIORM = 891 Vpeak Option 060 VIORM = 560 Vpeak VIORM = 1414 Vpeak Recognized under UL1577, Component Recognition Program, Category FPQU2, File E55361 Canadian Standards Association (CSA) File CA88324 IEC/EN/DIN EN 60747-5-2 Approved under: IEC 60747-5-2:1997 + A1:2002 EN 60747-5-2:2001 + A1:2002 DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01 Insulation and Safety Related Specifications Value HCPLHCPL-J454 J454 All other -400E/-600E options Parameter Symbol HCPL4504 Minimum External Air Gap (External Clearance) L(101) 7.1 8.0 Minimum External Tracking (External Creepage) L(102) 7.4 Minimum Internal Plastic Gap (Internal Clearance) Minimum Internal Tracking (Internal Creepage) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI HCPL0454 HCNW 4504 Units Conditions 7.4 4.9 9.6 mm Measured from input terminals to output terminals, shortest distance through air. 8.0 8.0 4.8 10.0 mm Measured from input terminals to output terminals, shortest distance path along body. 0.08 0.5 0.5 0.08 1.0 mm Through insulation distance, conductor to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity. NA NA NA NA 4.0 mm Measured from input terminals to output terminals, along internal cavity. ≥175 ≥175 ≥175 ≥175 ≥200 Volts DIN IEC 112/VDE 0303 Part 1 IIIa IIIa IIIa IIIa IIIa All Avago data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. For 8 Material Group (DIN VDE 0110, 1/89, Table 1) creepage, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered. There are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending on factors such as pollution degree and insulation level. IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics Description Symbol Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage ≤150 V rms for rated mains voltage ≤300 V rms for rated mains voltage ≤450 V rms for rated mains voltage ≤600 V rms for rated mains voltage ≤1000 V rms HCPL-0454 HCPL-4504 OPTION 060 OPTION 060 HCPL-J454 HCNW4504 I-IV I-III I-IV I-IV I-III I-IV I-IV I-III I-III I-IV I-IV I-IV I-IV I-III Unit Climatic Classification 55/100/21 55/100/21 55/100/21 55/85/21 Pollution Degree (DIN VDE 0110/1.89) 2 2 2 2 VIORM 560 630 891 1414 V peak VPR 1050 1181 1670 2652 V peak VPR 840 945 1336 2121 V peak VIOTM 4000 6000 6000 8000 V peak Case Temperature TS 150 175 175 150 °C Input Current IS,INPUT 150 230 400 400 mA Output Power PS,OUTPUT 600 600 600 700 mW RS ≥109 ≥109 ≥109 ≥109 Ω Maximum Working Insulation Voltage Input to Output Test Voltage, Method b* VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial Discharge < 5 pC Input to Output Test Voltage, Method a* VIORM x 1.5 = VPR, Type and Sample Test, tm = 60 sec, Partial Discharge < 5 pC Highest Allowable Overvoltage* (Transient Overvoltage, tini = 10 sec) Safety Limiting Values - Maximum Values Allowed in the Event of a Failure, also see Thermal Derating curve Insulation Resistance at TS, VIO = 500 V *Refer to the optocoupler section of the Designer's Catalog, under regulatory information (IEC/EN/DIN EN 60747-5-2) for a detailed description of Method a and Method b partial discharge test profiles. NOTE: These optocouplers are suitable for "safe electrical isolation" only within the safety limit data. Maintenance of the safety data shall be ensured by means of protective circuits. NOTE: Insulation Characteristics are per IEC/EN/DIN EN 60747-5-2. NOTE: Surface mount classification is Class A in accordance with CECC 00802. 9 Absolute Maximum Ratings Parameter Symbol Storage Temperature TS Operating Temperature TA Average Forward Input Current IF(AVG) Peak Forward Input Current (50% duty cycle, 1 ms pulse width) IF(PEAK) Peak Transient Input Current (≤1 μs pulse width, 300 pps) Reverse LED Input Voltage (Pin 3-2) Input Power Dissipation Average Output Current (Pin 6) IF(TRANS) VR PIN Device Min. Max. Units -55 125 °C HCPL-4504 HCPL-0454 HCPL-J454 -55 100 °C HCNW4504 -55 85 25 mA 1 HCPL-4504 HCPL-0454 50 mA 2 HCPL-J454 HCNW4504 40 HCPL-4504 HCPL-0454 1 HCPL-J454 HCNW4504 0.1 HCPL-4504 HCPL-0454 5 HCPL-J454 HCNW4504 3 HCPL-4504 HCPL-0454 45 HCPL-J454 HCNW4504 40 IO(AVG) A V mW 8 mA Peak Output Current IO(PEAK) 16 mA Supply Voltage (Pin 8-5) VCC -0.5 30 V Output Voltage (Pin 6-5) VO -0.5 20 V Output Power Dissipation PO Lead Solder Temperature (Through-Hole Parts Only) 1.6 mm below seating plane, 10 seconds TLS Up to seating plane, 10 seconds Reflow Temperature Profile 10 TRP Note 100 mW HCPL-4504 HCPL-J454 260 °C HCNW4504 260 HCPL-0454, Option 300 , Option 500, Option 400E & Option 600E. See Package Outline Drawings section 3 4 Electrical Specifications (DC) Over recommended temperature (TA = 0°C to 70°C) unless otherwise specified. See note 12. Parameter Symbol Device Min. Current Transfer Ratio CTR HCPL-4504 HCPL-0454 HCPL-J454 19 37 13 39 23 19 HCNW4504 Current Transfer Ratio CTR HCPL-4504 HCPL-0454 HCPL-J454 HCNW4504 Logic Low Output Voltage VOL Typ.* Max. Units Test Conditions 25 32 60 % TA = 25°C 21 34 60 TA = 25°C 29 60 TA = 25°C 31 63 26 35 65 22 37 21 43 16 45 % TA = 25°C 65 TA = 25°C Logic Low Supply Current ICCL Logic High Supply Current ICCH Input Forward Voltage VF 5 IF = 12 mA, VCC = 4.5 V 1, 2, 4 5 VO = 0.4 V VO = 0.4 V VO = 0.4 V VO = 0.5 V 33 65 35 68 HCPL-4504 HCPL-0454 0.2 0.4 HCPL-J454 0.2 TA = 25°C VO = 0.4 V VO = 0.5 V V TA = 25°C 0.5 IO = 4.0 mA IO = 3.3 mA 0.4 TA = 25°C IF = 16 mA, VCC = 4.5 V IO = 3.6 mA IO = 3.0 mA 0.4 TA = 25°C 0.5 IOH 1, 2, 4 VO = 0.5 V 0.5 Logic High Output Current IF = 16 mA, VCC = 4.5 V VO = 0.4 V VO = 0.5 V 25 0.2 Note VO = 0.5 V 21 HCNW4504 VO = 0.4 V VO = 0.5 V Fig. IO = 3.6 mA IO = 3.0 mA 0.003 0.5 0.01 1 50 200 0.02 1 μA TA = 25°C VO = VCC = 5.5 V TA = 25°C VO = VCC = 15 V IF = 0 mA 5 50 HCPL-4504 HCPL-0454 HCNW4504 HCPL-J454 Input Reverse Breakdown Voltage IF = 16 mA, VO = Open, VCC = 15 V 12 μA TA = 25°C 12 V TA = 25°C IF = 16 mA TA = 25°C IF = 16 mA 70 2 BVR Temperature Coefficient of Forward Voltage ∆VF ∆TA Input Capacitance CIN HCPL-4504 HCPL-0454 *All typicals at TA = 25°C. 1.5 1.7 IF = 0 mA, VO = Open, VCC = 15 V 1.8 HCPL-J454 HCNW4504 1.45 HCPL-4504 HCPL-0454 5 HCPL-J454 HCNW4504 3 1.59 1.35 1.85 1.95 V IR = 10 μA IR = 100 μA HCPL-4504 HCPL-0454 -1.6 HCPL-J454 HCNW4504 -1.4 HCPL-4504 HCPL-0454 60 HCPL-J454 HCNW4504 11 μA 70 mV/°C IF = 16 mA pF f = 1 MHz, VF = 0 V 3 AC Switching Specifications Over recommended temperature (TA = 0°C to 70°C) unless otherwise specified. Parameter Symbol Propagation Delay Time to Logic Low at Output tPHL Device tPHL Propagation Delay Time to Logic High at Output Min. 0.2 HCPLJ454 0.05 Others 0.1 Max. Units Test Conditions 0.2 0.3 μs TA = 25°C 0.2 0.5 0.5 0.7 μs Fig. Note Pulse: f = 20 kHz, Duty Cycle = 10%, IF = 16 mA, VCC = 5.0 V, RL = 1.9 kΩ, CL = 15 pF, V THHL = 1.5 V 6, 8, 9 9 TA = 25°C Pulse: f = 10 kHz, Duty Cycle = 50%, IF = 12 mA, VCC = 15.0 V, RL = 20 kΩ, CL = 100 pF, V THHL = 1.5 V 6, 10-14 10 μs TA = 25°C Pulse: f = 20 kHz, Duty Cycle = 10%, IF = 16 mA, VCC = 5.0 V, RL = 1.9 kΩ, CL = 15 pF, V THLH = 1.5 V 6, 8, 9 9 μs TA = 25°C Pulse: f = 10 kHz, Duty Cycle = 50%, IF = 12 mA, VCC = 15.0 V, RL = 20 kΩ, CL = 100 pF, V THLH = 2.0 V 6, 10-14 10 μs TA = 25°C Pulse: f = 10 kHz, Duty Cycle = 50%, IF = 12 mA, VCC = 15.0 V, RL = 20 kΩ, CL = 100 pF, VTHHL = 1.5 V, VTHLH = 2.0 V 6, 10-14 17 TA = 25°C VCM = 1500 VP-P VCC = 5.0 V, RL = 1.9 kΩ, CL = 15 pF, IF = 0 mA 7 7, 9 VCC = 15.0 V, RL = 20 kΩ, CL = 100 pF, IF = 0 mA 7 8, 10 VCC = 5.0 V, RL = 1.9 kΩ, CL = 15 pF, IF = 16 mA 7 7, 9 VCC = 15.0 V, RL = 20 kΩ, CL = 100 pF, IF = 12 mA 7 8, 10 VCC = 15.0 V, RL = 20 kΩ, CL = 100 pF, IF = 16 mA 7 8, 10 1.0 0.3 0.5 0.3 0.7 0.3 0.8 1.1 0.2 0.8 1.4 tPLH tPLH Typ. Propagation Delay Difference Between Any 2 Parts tPLHtPHL -0.4 0.3 0.9 -0.7 0.3 1.3 Common Mode Transient Immunity at Logic High |CMH| 15 30 kV/μs |CMH| 15 30 kV/μs |CML| 15 30 kV/μs HCPLJ454 15 30 kV/μs Others 10 30 kV/μs Level Output Common Mode Transient Immunity at Logic Low Level Output |CML| |CML| *All typicals at TA = 25°C. 12 15 TA = 25°C VCM = 1500 VP-P Package Characteristics Over recommended temperature (TA = 0°C to 25°C) unless otherwise specified. Parameter Symbol Device Min. Input-Output Momentary Withstand Voltage† VISO HCPL-4504 HCPL-0454 3750 HCPL-J454 3750 HCPL-4504 Option 020 5000 6, 11, 15 HCNW4504 5000 6, 15, 16 Input-Output Resistance RI-O Max. 1012 HCPL-4504 HCPL-0454 HCPL-J454 HCNW4504 Typ.* 1012 Units Test Conditions V rms RH ≤50%, t = 1 min., TA = 25°C Ω 1013 CI-O Note 6, 13, 16 6, 14, 16 6 TA = 25°C 1011 Capacitance (Input-Output) VI-O = 500 Vdc Figure TA = 100°C HCPL-4504 HCPL-0454 0.6 HCPL-J454 0.8 HCNW4504 0.5 pF f = 1 MHz 6 0.6 All typicals at TA = 25°C.. †The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics Table (if applicable), your equipment level safety specification or Avago Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.” Notes: 1. Derate linearly above 70°C free-air temperature at a rate of 0.8 mA/°C (8-Pin DIP). Derate linearly above 85°C free-air temperature at a rate of 0.5 mA/°C (SO-8). 2. Derate linearly above 70°C free-air temperature at a rate of 1.6 mA/°C (8-Pin DIP). Derate linearly above 85°C free-air temperature at a rate of 1.0 mA/°C (SO-8). 3. Derate linearly above 70°C free-air temperature at a rate of 0.9 mW/°C (8-Pin DIP). Derate linearly above 85°C free-air temperature at a rate of 1.1 mW/°C (SO-8). 4. Derate linearly above 70°C free-air temperature at a rate of 2.0 mW/°C (8-Pin DIP). Derate linearly above 85°C free-air temperature at a rate of 2.3 mW/°C (SO-8). 5. CURRENT TRANSFER RATIO in percent is defined as the ratio of output collector current, IO, to the forward LED input current, IF, times 100. 6. Device considered a two-terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7, and 8 shorted together. 7. Under TTL load and drive conditions: Common mode transient immunity in a Logic High level is the maximum tolerable (positive) dVCM/dt on the leading edge of the common mode pulse, VCM, to assure that the output will remain in a Logic High state (i.e., VO > 2.0 V). Common mode transient immunity in a Logic Low level is the maximum tolerable (negative) dVCM/dt on the trailing edge of the common mode pulse signal, VCM, to assure that the output will remain in a Logic Low state (i.e., VO < 0.8 V). 8. Under IPM (Intelligent Power Module) load and LED drive conditions: Common mode transient immunity in a Logic High level is the maximum tolerable dVCM/dt on the leading edge of the common mode pulse, VCM, to assure that the output will remain in a Logic High state (i.e., VO > 3.0 V). Common mode transient immunity in a Logic Low level is the maximum tolerable dVCM/dt on the trailing edge of the common mode pulse signal, VCM, to assure that the output will remain in a Logic Low state (i.e., VO < 1.0 V). 9. The 1.9 kΩ load represents 1 TTL unit load of 1.6 mA and the 5.6 kΩ pull-up resistor. 10. The RL = 20 kΩ, CL = 100 pF load represents an IPM (Intelligent Power Module) load. 11. See Option 020 data sheet for more information. 12. Use of a 0.1 μF bypass capacitor connected between Pins 5 and 8 is recommended. 13. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥4500 V rms for 1 second (leakage detection current limit, Ii-o ≤5 μA). 14. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥4500 V rms for 1 second (leakage detection current limit, Ii-o ≤ 5 μA). 15. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥6000 V rms for 1 second (leakage detection current limit, Ii-o ≤5 μA). 16. This test is performed before the 100% Production test shown in the VDE 0884 Insulation Related Characteristics Table, if applicable. 17. The difference between tPLH and tPHL between any two devices (same part number) under the same test condition. (See Power Inverter Dead Time and Propagation Delay Specifications section.) 13 HCPL-4504/0454 25 mA 5 20 mA 15 mA 10 mA IF = 5 mA 0 40 mA 20 35 mA 30 mA 25 mA 15 20 mA 15 mA 10 10 mA 5 0 20 10 TA = 25° C VCC = 5.0 V IO – OUTPUT CURRENT – mA IO – OUTPUT CURRENT – mA IO – OUTPUT CURRENT – mA 35 mA 30 mA 0 HCNW4504 HCPL-J454 25 40 mA TA = 25°C 10 VCC = 5.0 V IF = 5 mA 0 5 VO – OUTPUT VOLTAGE – V 10 15 20 TA = 25°C 20 VCC = 5.0 V 18 12 40 mA 35 mA 30 mA 25 mA 10 20 mA 8 15 mA 16 14 6 10 mA 4 2 0 IF = 5 mA 0 20 10 VO – OUTPUT VOLTAGE – V VO – OUTPUT VOLTAGE – V HCPL-J454 HCNW4504 1.0 0.5 0.0 NORMALIZED IF = 16 mA VO = 0.4 V VCC = 5.0 V TA = 25°C 0 2 4 6 8 10 12 14 16 18 20 22 24 26 2.0 NORMALIZED IF = 16 mA VO = 0.4 V VCC = 5.0 V TA = 25° C 1.5 1.0 0.5 0 0 5 10 15 20 25 IF – INPUT CURRENT – mA IF – INPUT CURRENT – mA HCPL-4504/0454 HCPL-J454/HCNW4504 IF TA = 25°C + VF – 10 IF – FORWARD CURRENT – mA IF – FORWARD CURRENT – mA 1000 100 1.0 0.1 0.01 0.001 1.1 1.2 1.3 1.4 1.5 VF – FORWARD VOLTAGE – VOLTS Figure 3. Input current vs. forward voltage. 14 1.6 TA = 25°C 100 IF + VF – 10 1.0 0.1 0.01 0.001 1.2 1.3 1.4 1.5 1.6 VF – FORWARD VOLTAGE – VOLTS NORMALIZED IF = 16 mA VO = 0.4 V VCC = 5.0 V TA = 25°C 2.0 1.6 1.2 0.8 0.4 0 0 5 10 15 20 IF – INPUT CURRENT – mA Figure 2. Current transfer ratio vs. input current. 1000 NORMALIZED CURRENT TRANSFER RATIO NORMALIZED CURRENT TRANSFER RATIO HCPL-4504/0454 1.5 NORMALIZED CURRENT TRANSFER RATIO Figure 1. DC and pulsed transfer characteristics. 1.7 25 0.9 NORMALIZED I F = 16 mA VO = 0.4 V VCC = 5.0 V TA = 25°C 0.8 0.7 0.6 -60 -40 -20 0 20 40 60 80 100 120 HCPL-J454 NORMALIZED CURRENT TRANSFER RATIO 1.0 NORMALIZED CURRENT TRANSFER RATIO NORMALIZED CURRENT TRANSFER RATIO HCPL-4504/0454 1.1 1.05 1.0 NORMALIZED IF = 16 mA VO = 0.4 V VCC = 5.0 V TA = 25° C 0.95 0.9 0.85 -60 -40 -20 0 20 40 60 80 100 HCNW4504 1.05 NORMALIZED I F = 16 mA VO = 0.4 V VCC = 5.0 V TA = 25°C 1.0 0.95 0.9 0.85 -60 -40 -20 0 IOH – LOGIC HIGH OUTPUT CURRENT – nA Figure 4. Current transfer ratio vs. temperature. 10 4 10 3 IF = 0 mA VO = VCC = 5.0 V 10 2 10 1 10 0 10 -1 10-2 -60 -40 -20 0 20 40 60 80 100 120 TA – TEMPERATURE – °C Figure 5. Logic high output current vs. temperature. IF 0 VCC VO VTHHL PULSE GEN. ZO = 50 Ω t r = 5 ns IF VTHLH VOL 8 2 7 3 6 VCC RL VO 4 5 CL RM t PLH t PHL 1 0.1µF I F MONITOR Figure 6. Switching test circuit. VCM 90% 0V 90% 10% 1 8 2 7 3 6 10% A tf B VO 4 VO 5 CL VFF VO RL 0.1µF VCC SWITCH AT A: IF = 0 mA VOL SWITCH AT B: IF = 12 mA, 16 mA VCM + – PULSE GEN. Figure 7. Test circuit for transient immunity and typical waveforms. 15 VCC IF tr 20 40 60 80 100 120 TA – TEMPERATURE – °C TA – TEMPERATURE – °C TA – TEMPERATURE – °C HCPL-4504/0454 HCPL-J454/HCNW4504 0.50 0.25 0.20 IF = 10 mA IF = 16 mA 0.15 0.10 -60 -40 -20 0 tPLH 0.30 t PHL 0.25 0.20 IF = 10 mA IF = 16 mA 0.15 0.10 -60 -40 -20 0 20 40 60 80 100 120 1.4 VCC = 5.0 V 0.45 RL = 1.9 kΩ CL = 15 pF 0.40 V THHL = VTHLH = 1.5 V 10% DUTY CYCLE 0.35 TA – TEMPERATURE – °C tp – PROPAGATION DELAY – µs tp – PROPAGATION DELAY – µs tPLH tp – PROPAGATION DELAY – µs 0.50 VCC = 5.0 V 0.45 RL = 1.9 kΩ CL = 15 pF 0.40 V THHL = VTHLH = 1.5 V 10% DUTY CYCLE 0.35 t PHL 0.30 VCC = 5.0 V TA = 25° C CL = 15 pF 1.0 VTHHL = VTHLH = 1.5 V 10% DUTY CYCLE 1.2 0.6 2 4 6 0.6 0.5 tPHL 0.4 0.4 IF = 10 mA IF = 16 mA 0.2 0.0 0 5 10 15 20 25 30 35 40 45 50 RL – LOAD RESISTANCE – kΩ Figure 12. Propagation delay time vs. load resistance. 16 t PLH 0.6 0.5 tPHL 0.4 0 20 40 60 80 100 120 TA – TEMPERATURE – °C Figure 11. Propagation delay time vs. temperature. tp – PROPAGATION DELAY – µs tp – PROPAGATION DELAY – µs t PLH IF = 10 mA IF = 16 mA 0.7 0.3 -60 -40 -20 20 40 60 80 100 120 1.2 3.5 t PHL 0.6 0 VCC = 15.0 V 1.0 RL = 20 kΩ CL = 100 pF 0.9 VTHHL = 1.5 V VTHLH = 2.0 V 0.8 50% DUTY CYCLE TA – TEMPERATURE – °C 1.8 0.8 t PLH 50% DUTY CYCLE RL– LOAD RESISTANCE – kΩ VCC = 15.0 V 1.6 TA = 25° C CL = 100 pF 1.4 VTHHL = 1.5 V 1.2 VTHLH = 2.0 V 50% DUTY CYCLE 1.0 8 10 12 14 16 18 20 6 HCPL-J454/HCNW4504 0.7 0.3 -60 -40 -20 8 10 12 14 16 18 20 Figure 10. Propagation delay time vs. load resistance. 4 1.1 IF = 10 mA IF = 16 mA tp – PROPAGATION DELAY – µs VCC = 15.0 V 1.0 RL = 20 kΩ CL = 100 pF 0.9 V THHL = 1.5 V VTHLH = 2.0 V 0.8 VCC = 15.0 V 3.0 TA = 25° C RL = 20 kΩ 2.5 VTHHL = 1.5 V VTHLH = 2.0 V 2.0 50% DUTY CYCLE t PLH t PHL 1.5 1.0 0.5 0.0 IF = 10 mA IF = 16 mA 0 100 200 300 400 500 600 700 800 900 1000 CL – LOAD CAPACITANCE – pF Figure 13. Propagation delay time vs. load capacitance. tp – PROPAGATION DELAY – µs 0 IF = 10 mA IF = 16 mA tp – PROPAGATION DELAY – µs tp – PROPAGATION DELAY – µs t PHL 2 RL – LOAD RESISTANCE – kΩ HCPL-4504/0454 t PLH 0 Figure 9. Propagation delay time vs. load resistance. 1.1 VCC = 5.0 V TA = 25° C CL = 100 pF VTHHL = 1.5 V VTHLH = 2.0 V 50% DUTY CYCLE IF = 10 mA IF = 16 mA 0.2 TA – TEMPERATURE – °C Figure 8. Propagation delay time vs. temperature. 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 t PHL 0.4 0.0 20 40 60 80 100 120 tPLH 0.8 TA = 25° C RL = 20 kΩ CL = 100 pF VTHHL = 1.5 V VTHLH = 2.0 V 50% DUTY CYCLE 1.1 1.0 0.9 0.8 0.7 t PLH 0.6 0.5 0.4 0.3 t PHL IF = 10 mA IF = 16 mA 0.2 10 11 12 13 14 15 16 17 18 19 20 VCC – SUPPLY VOLTAGE – V Figure 14. Propagation delay time vs. supply voltage. PS (mW) IS (mA) for HCPL-4504 OPTION 060 IS (mA) for HCPL-J454 700 600 500 400 300 (230) 200 100 0 0 25 50 75 100 125 150 175 200 OUTPUT POWER – PS, INPUT CURRENT – IS OUTPUT POWER – PS, INPUT CURRENT – IS HCPL-4504 OPTION 060/HCPL-J454 800 1000 HCPL-0454 OPTION 060/HCNW4504 PS (mW) for HCNW4504 IS (mA) for HCNW4504 PS (mW) for HCPL-0454 OPTION 060 IS (mA) for HCPL-0454 OPTION 060 900 800 700 600 500 400 300 200 (150) 100 0 0 25 50 75 100 125 150 175 TS – CASE TEMPERATURE – °C TS – CASE TEMPERATURE – °C Figure 15. Thermal derating curve, dependence of safety limiting valve with case temperature per IEC/EN/DIN EN 60747-5-2. +HV + HCPL-4504/0454/J454 8 HCNW4504 LED 1 2 7 6 3 OUT 1 BASE/GATE DRIVE CIRCUIT Q1 BASE/GATE DRIVE CIRCUIT Q2 5 + HCPL-4504/0454/J454 8 HCNW4504 LED 2 2 7 6 3 OUT 2 5 –HV Figure 16. Typical power inverter. 17 Figure 17. LED delay and dead time diagram. Power Inverter Dead Time and Propagation Delay Specifications The HCPL-4504/0454/J454 and HCNW4504 include a specification intended to help designers minimize “dead time” in their power inverter designs. The new “propagation delay difference” specification (tPLH - tPHL) is useful for determining not only how much optocoupler switching delay is needed to prevent “shoot-through” current, but also for determining the best achievable worst-case dead time for a given design. When inverter power transistors switch (Q1 and Q2 in Figure 17), it is essential that they never conduct at the same time. Extremely large currents will flow if there is any overlap in their conduction during switching transitions, potentially damaging the transistors and even the surrounding circuitry. This “shoot-through” current is eliminated by delaying the turn-on of one transistor (Q2) long enough to ensure that the opposing transistor (Q1) has completely turned off. This delay introduces a small amount of “dead time” at the output of the inverter during which both transistors are off during switching transitions. Minimizing this dead time is an important design goal for an inverter designer. 18 The amount of turn-on delay needed depends on the propagation delay characteristics of the optocoupler, as well as the characteristics of the transistor base/gate drive circuit. Considering only the delay characteristics of the optocoupler (the characteristics of the base/gate drive circuit can be analyzed in the same way), it is important to know the minimum and maximum turn-on (tPHL) and turnoff (tPLH) propagation delay specifications, preferably over the desired operating temperature range. The importance of these specifications is illustrated in Figure 17. The waveforms labeled “LED1”, “LED2”, “OUT1”, and “OUT2” are the input and output voltages of the optocoupler circuits driving Q1 and Q2 respectively. Most inverters are designed such that the power transistor turns on when the optocoupler LED turns on; this ensures that both power transistors will be off in the event of a power loss in the control circuit. Inverters can also be designed such that the power transistor turns off when the optocoupler LED turns on; this type of design, however, requires additional fail-safe circuitry to turn off the power transistor if an over-current condition is detected. The timing illustrated in Figure 17 assumes that the power transistor turns on when the optocoupler LED turns on. The LED signal to turn on Q2 should be delayed enough so that an optocoupler with the very fastest turn-on propagation delay (tPHLmin) will never turn on before an optocoupler with the very slowest turn-off propagation delay (tPLHmax) turns off. To ensure this, the turn-on of the optocoupler should be delayed by an amount no less than (tPLHmax - tPHLmin), which also happens to be the maximum data sheet value for the propagation delay difference specification, (tPLH - tPHL). The HCPL-4504/0454/J454 and HCNW4504 specify a maximum (tPLH - tPHL) of 1.3 μs over an operating temperature range of 0-70°C. Although (tPLH-tPHL)max tells the designer how much delay is needed to prevent shoot-through current, it is insufficient to tell the designer how much dead time a design will have. Assuming that the optocoupler turn-on delay is exactly equal to (tPLH - tPHL)max, the minimum dead time is zero (i.e., there is zero time between the turnoff of the very slowest optocoupler and the turn-on of the very fastest optocoupler). Calculating the maximum dead time is slightly more complicated. Assuming that the LED turn-on delay is still exactly equal to (tPLH - tPHL)max, it can be seen in Figure 17 that the maximum dead time is the sum of the maximum difference in turn-on delay plus the maximum difference in turnoff delay, This expression can be rearranged to obtain [(tPLHmax-tPHLmin)-(tPHLmin-tPHLmax)], and further rearranged to obtain [(tPLH-tPHL)max-(tPLH-tPHL)min], which is the maximum minus the minimum data sheet values of (tPLH-tPHL). The difference between the maximum and minimum values depends directly on the total spread in propagation delays and sets the limit on how good the worst-case dead time can be for a given design. Therefore, optocouplers with tight propagation delay specifications (and not just shorter delays or lower pulsewidth distortion) can achieve short dead times in power inverters. The HCPL-4504/0454/J454 and HCNW4504 specify a minimum (tPLH - tPHL) of -0.7 μs over an operating temperature range of 0-70°C, resulting in a maximum dead time of 2.0 μs when the LED turn-on delay is equal to (tPLH-tPHL)max, or 1.3 μs. It is important to maintain accurate LED turn-on delays because delays shorter than (tPLH - tPHL)max may allow shoot-through currents, while longer delays will increase the worst-case dead time. [(tPLHmax-tPLHmin)+(tPHLmax-tPHLmin)]. For product information and a complete list of distributors, please go to our website: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved. Obsoletes AV01-0552EN AV02-0867EN - January 4, 2010