Fairchild HCPL2630V High speed 10mbit/s logic gate optocoupler Datasheet

Single-Channel: 6N137, HCPL2601, HCPL2611
Dual-Channel: HCPL2630, HCPL2631
High Speed 10MBit/s Logic Gate Optocouplers
Features
Description
■
■
■
■
■
■
■
■
The 6N137, HCPL2601, HCPL2611 single-channel and
HCPL2630, HCPL2631 dual-channel optocouplers
consist of a 850 nm AlGaAS LED, optically coupled to a
very high speed integrated photo-detector logic gate with
a strobable output. This output features an open collector, thereby permitting wired OR outputs. The coupled
parameters are guaranteed over the temperature range
of -40°C to +85°C. A maximum input signal of 5mA will
provide a minimum output sink current of 13mA (fan out
of 8).
Very high speed – 10 MBit/s
Superior CMR – 10 kV/µs
Double working voltage-480V
Fan-out of 8 over -40°C to +85°C
Logic gate output
Strobable output
Wired OR-open collector
U.L. recognized (File # E90700)
Applications
An internal noise shield provides superior common
mode rejection of typically 10kV/µs. The HCPL2601 and
HCPL2631 has a minimum CMR of 5kV/µs. The
HCPL2611 has a minimum CMR of 10kV/µs.
■ Ground loop elimination
■ LSTTL to TTL, LSTTL or 5-volt CMOS
■ Line receiver, data transmission
■ Data multiplexing
■ Switching power supplies
■ Pulse transformer replacement
■ Computer-peripheral interface
Schematics
Package Outlines
8 VCC
N/C 1
8
8 VCC
+ 1
1
VF1
+ 2
7 VE
_ 2
6 VO
_
7 V01
VF
_
8
3
V
5 GND
N/C 4
6N137
HCPL2601
HCPL2611
6 V02
3
8
1
1
F2
5 GND
+ 4
HCPL2630
HCPL2631
A 0.1µF bypass capacitor must be connected between pins 8 and 5(1).
©2005 Fairchild Semiconductor Corporation
6N137, HCPL2601, HCPL2611, HCPL2630, HCPL2631 Rev. 1.0.7
Truth Table (Positive Logic)
Input
Enable
Output
H
H
L
L
H
H
H
L
H
L
L
H
H
NC
L
L
NC
H
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Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 — High Speed 10MBit/s Logic Gate Optocouplers
August 2008
Symbol
Parameter
Value
Units
TSTG
Storage Temperature
-55 to +125
°C
TOPR
Operating Temperature
-40 to +85
°C
TSOL
Lead Solder Temperature
260 for 10 sec
°C
mA
EMITTER
IF
DC/Average Forward
Single Channel
50
Input Current
Dual Channel (Each Channel)
30
VE
Enable Input Voltage Not to Exceed
VCC by more than 500mV
Single Channel
5.5
V
VR
Reverse Input Voltage
Each Channel
5.0
V
PI
Power Dissipation
Single Channel
100
mW
Dual Channel (Each Channel)
45
DETECTOR
Supply Voltage
VCC
(1 minute max)
7.0
V
50
mA
IO
Output Current
Dual Channel (Each Channel)
50
VO
Output Voltage
Each Channel
7.0
V
PO
Collector Output
Single Channel
85
mW
Power Dissipation
Dual Channel (Each Channel)
60
Single Channel
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Min.
Max.
Units
IFL
Input Current, Low Level
0
250
µA
IFH
Input Current, High Level
*6.3
15
mA
VCC
Supply Voltage, Output
4.5
5.5
V
VEL
Enable Voltage, Low Level
0
0.8
V
VEH
Enable Voltage, High Level
2.0
VCC
V
TA
Low Level Supply Current
-40
+85
°C
N
Fan Out (TTL load)
8
*6.3mA is a guard banded value which allows for at least 20% CTR degradation. Initial input current threshold value
is 5.0mA or less.
©2005 Fairchild Semiconductor Corporation
6N137, HCPL2601, HCPL2611, HCPL2630, HCPL2631 Rev. 1.0.7
www.fairchildsemi.com
2
Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 — High Speed 10MBit/s Logic Gate Optocouplers
Absolute Maximum Ratings (TA = 25°C unless otherwise specified)
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Individual Component Characteristics
Symbol
Parameter
Test Conditions
Min.
Typ.*
Max.
Unit
1.8
V
EMITTER
VF
Input Forward Voltage
IF = 10mA
BVR
Input Reverse Breakdown
Voltage
IR = 10µA
CIN
Input Capacitance
VF = 0, f = 1MHz
Input Diode Temperature
Coefficient
IF = 10mA
ICCH
High Level Supply Current
VCC = 5.5V, IF = 0mA,
VE = 0.5V
Single Channel
7
10
Dual Channel
10
15
ICCL
Low Level Supply Current
Single Channel
VCC = 5.5V,
IF = 10mA
9
13
Dual Channel
VE = 0.5V
IEL
Low Level Enable Current
VCC = 5.5V, VE = 0.5V
IEH
High Level Enable Current
VCC = 5.5V, VE = 2.0V
VEH
High Level Enable Voltage
VCC = 5.5V, IF = 10mA
TA = 25°C
∆VF / ∆TA
1.4
1.75
5.0
V
60
pF
-1.4
mV/°C
DETECTOR
VEL
Low Level Enable Voltage
VCC = 5.5V, IF = 10mA
mA
mA
14
21
-0.8
-1.6
mA
-0.6
-1.6
mA
2.0
V
(3)
0.8
V
Switching Characteristics (TA = -40°C to +85°C, VCC = 5V, IF = 7.5mA unless otherwise specified)
Symbol
TPLH
TPHL
AC Characteristics
Test Conditions
Propagation Delay
Time to Output HIGH
Level
RL = 350Ω,
CL = 15pF(4) (Fig. 12)
Propagation Delay
Time to Output LOW
Level
TA = 25°C(5)
|TPHL–TPLH| Pulse Width Distortion
TA = 25°C
Min.
Typ.*
20
45
Max. Unit
75
ns
100
25
45
RL = 350Ω, CL = 15pF (Fig. 12)
75
ns
100
(RL = 350Ω, CL = 15pF (Fig. 12)
3
35
ns
tr
Output Rise Time
(10–90%)
RL = 350Ω, CL = 15pF
(Fig. 12)
50
ns
tf
Output Rise Time
(90–10%)
RL = 350Ω, CL = 15pF(7) (Fig. 12)
12
ns
tELH
Enable Propagation
Delay Time to Output
HIGH Level
IF = 7.5mA, VEH = 3.5V, RL = 350Ω, CL = 15pF(8)
(Fig. 13)
20
ns
tEHL
Enable Propagation
Delay Time to Output
LOW Level
IF = 7.5mA, VEH = 3.5V, RL = 350Ω, CL = 15pF(9)
(Fig. 13)
20
ns
Common Mode
Transient Immunity
(at Output HIGH Level)
TA = 25°C, |VCM| = 50V 6N137, HCPL2630
(Peak), IF = 0mA,
HCPL2601, HCPL2631
VOH (Min.) = 2.0V,
RL = 350Ω(10) (Fig. 14)
10,000
V/µs
Common Mode
Transient Immunity
(at Output LOW Level)
RL = 350Ω, IF = 7.5mA, 6N137, HCPL2630
VOL (Max.) = 0.8V,
HCPL2601, HCPL2631
TA = 25°C(11) (Fig. 14)
|CMH|
|VCM| = 400V
|CML|
HCPL2611
|VCM| = 400V
©2005 Fairchild Semiconductor Corporation
6N137, HCPL2601, HCPL2611, HCPL2630, HCPL2631 Rev. 1.0.7
(6)
HCPL2611
5000
10,000
10,000
15,000
V/µs
10,000
5000
10,000
10,000
15,000
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Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 — High Speed 10MBit/s Logic Gate Optocouplers
Electrical Characteristics (TA = 0 to 70°C unless otherwise specified)
Transfer Characteristics (TA = -40 to +85°C unless otherwise specified)
Symbol
DC Characteristics
Test Conditions
Min.
Typ.*
Max.
Unit
100
µA
IOH
HIGH Level Output Current
VCC = 5.5V, VO = 5.5V,
IF = 250µA, VE = 2.0V(2)
VOL
LOW Level Output Current
VCC = 5.5V, IF = 5mA, VE = 2.0V,
ICL = 13mA(2)
.35
0.6
V
IFT
Input Threshold Current
VCC = 5.5V, VO = 0.6V, VE = 2.0V,
IOL = 13mA
3
5
mA
Max.
Unit
1.0*
µA
Isolation Characteristics (TA = -40°C to +85°C unless otherwise specified.)
Symbol
II-O
Characteristics
Test Conditions
Min.
Typ.*
Input-Output Insulation
Leakage Current
Relative humidity = 45%,
TA = 25°C, t = 5s,
VI-O = 3000 VDC(12)
VISO
Withstand Insulation Test
Voltage
RH < 50%, TA = 25°C,
II-O ≤ 2µA, t = 1 min.(12)
RI-O
Resistance (Input to Output)
VI-O = 500V(12)
1012
Ω
Capacitance (Input to Output)
1MHz(12)
0.6
pF
CI-O
f=
2500
VRMS
*All Typicals at VCC = 5V, TA = 25°C
Notes:
1. The VCC supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic
or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible
to the package VCC and GND pins of each device.
2. Each channel.
3. Enable Input – No pull up resistor required as the device has an internal pull up resistor.
4. tPLH – Propagation delay is measured from the 3.75mA level on the HIGH to LOW transition of the input current
pulse to the 1.5 V level on the LOW to HIGH transition of the output voltage pulse.
5. tPHL – Propagation delay is measured from the 3.75mA level on the LOW to HIGH transition of the input current
pulse to the 1.5 V level on the HIGH to LOW transition of the output voltage pulse.
6. tr – Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse.
7. tf – Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse.
8. tELH – Enable input propagation delay is measured from the 1.5V level on the HIGH to LOW transition of the input
voltage pulse to the 1.5V level on the LOW to HIGH transition of the output voltage pulse.
9. tEHL – Enable input propagation delay is measured from the 1.5V level on the LOW to HIGH transition of the input
voltage pulse to the 1.5V level on the HIGH to LOW transition of the output voltage pulse.
10. CMH – The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the
HIGH state (i.e., VOUT > 2.0V). Measured in volts per microsecond (V/µs).
11. CML – The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the
LOW output state (i.e., VOUT < 0.8V). Measured in volts per microsecond (V/µs).
12. Device considered a two-terminal device: Pins 1, 2, 3 and 4 shorted together, and Pins 5, 6, 7 and 8 shorted
together.
©2005 Fairchild Semiconductor Corporation
6N137, HCPL2601, HCPL2611, HCPL2630, HCPL2631 Rev. 1.0.7
www.fairchildsemi.com
4
Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 — High Speed 10MBit/s Logic Gate Optocouplers
Electrical Characteristics (Continued)
Fig. 2 Input Diode Forward Voltage
vs. Forward Current
Conditions:
IF = 5 mA
VE = 2 V
VCC = 5.5V
0.7
0.6
IOL = 12.8 mA
0.5
IOL = 16mA
0.4
0.3
IOL = 6.4mA
0.2
IOL = 9.6mA
0.1
30
16
10
IF – FORWARD CURRENT (mA)
VOL – LOW LEVEL OUTPUT VOLTAGE (V)
Fig.1 Low Level Output Voltage vs. Ambient Temperature
0.8
1
0.1
0.01
0.001
0.0
-40
-20
0
20
40
60
80
0.9
1.0
1.1
TA – AMBIENT TEMPERATURE (°C)
IOL – LOW LEVEL OUTPUT CURRENT (mA)
TP – PROPAGATION DELAY (ns)
VCC = 5 V
100
RL = 4 kΩ (TPLH)
80
60
RL = 1 kΩ (TPLH)
40
0
RL = 350 Ω (TPLH)
5
7
RL = 1 kΩ
RL = 4 kΩ (TPHL)
RL = 350 kΩ
9
11
13
15
50
1.5
1.6
IF = 15mA
IF = 10mA
40
IF = 5mA
35
30
Conditions:
VCC = 5 V
VE = 2 V
VOL = 0.6 V
25
20
-40
-20
0
20
40
60
80
TA – AMBIENT TEMPERATURE (°C)
Fig. 6 Output Voltage vs. Input Forward Current
Fig. 5 Input Threshold Current
vs. Ambient Temperature
6
Conditions:
VCC = 5.0 V
VO = 0.6 V
VO – OUTPUT VOLTAGE (V)
IFT – INPUT THRESHOLD CURRENT (mA)
1.4
45
IF – FORWARD CURRENT (mA)
4
1.3
Fig. 4 Low Level Output Current
vs. Ambient Temperature
Fig.3 Switching Time vs. Forward Current
120
20
1.2
VF – FORWARD VOLTAGE (V)
3
RL = 350Ω
RL = 1kΩ
2
RL = 4kΩ
5
RL = 350Ω
4
RL = 4kΩ
RL = 1kΩ
3
2
1
1
-40
0
-20
0
20
40
60
0
80
©2005 Fairchild Semiconductor Corporation
6N137, HCPL2601, HCPL2611, HCPL2630, HCPL2631 Rev. 1.0.7
1
2
3
4
5
6
IF - FORWARD CURRENT (mA)
TA – AMBIENT TEMPERATURE (°C)
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Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 — High Speed 10MBit/s Logic Gate Optocouplers
Typical Performance Curves
Fig. 8 Rise and Fall Time vs. Temperature
Fig. 7 Pulse Width Distortion vs. Temperature
600
RL = 4 kΩ
Tr/Tf – RISE AND FALL TIME (ns)
PWD – PULSE WIDTH DISTORTION (ns)
80
60
Conditions:
IF = 7.5mA
VCC = 5A
40
20
RL = 1 kΩ
0
-60
RL = 350Ω
-40
-20
0
20
40
60
80
RL = 4 kΩ (tr)
500
400
Conditions:
IF = 7.5 mA
VCC = 5 V
300
200
RL = 1 kΩ (tr)
100
RL = 350Ω (tr)
0
-60
100
-40
-20
TA – TEMPERATURE (°C)
Fig. 9 Enable Propagation Delay vs. Temperature
40
60
20
80
100
Fig. 10 Switching Time vs. Temperature
120
TP – PROPAGATION DELAY (ns)
TE – ENABLE PROPAGATION DELAY (ns)
(tf)
TA – TEMPERATURE (°C)
120
100
RL = 4 kΩ (TELH)
80
60
40
RL = 1 kΩ (TELH)
RL = 350Ω (TELH)
20
0
-60
0
RL = 1 kΩ
RL = 4 kΩ
RL = 350Ω
RL = 350Ω
RL = 1 kΩ
RL = 4 kΩ
-40
-20
0
20
40
60
RL = 4 kΩ TPLH
100
80
60
RL = 1 kΩ TPLH
40
RL = 350Ω TPLH
RL = 1 kΩ
RL = 4 kΩ
RL = 350Ω
(TEHL)
80
20
-60
100
-40
-20
TA – TEMPERATURE (°C)
0
20
40
60
TPHL
80
100
TA – TEMPERATURE (°C)
IOH – HIGH LEVEL OUTPUT CURRENT (µA)
Fig. 11 High Level Output Current
vs. Temperature
20
Conditions:
VCC = 5.5 V
VO = 5.5 V
VE = 2.0 V
IF = 250 µA
15
10
5
0
-60
-40
-20
0
20
40
60
80
100
TA – TEMPERATURE (°C)
©2005 Fairchild Semiconductor Corporation
6N137, HCPL2601, HCPL2611, HCPL2630, HCPL2631 Rev. 1.0.7
www.fairchildsemi.com
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Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 — High Speed 10MBit/s Logic Gate Optocouplers
Typical Performance Curves (Continued)
Pulse
Generator
tr = 5ns
Z O = 50Ω
+5V
IF = 7.5 mA
1
VCC
IF = 3.75 mA
8
Input
(IF )
7
Output
(VO )
t PHL
2
Input
Monitor
(I F)
.1 µf
bypass
RL
Output
(VO )
6
3
CL
47
4
GND
tPLH
1.5 V
90%
Output
(VO )
10%
5
tf
tr
Fig. 12 Test Circuit and Waveforms for tPLH, tPHL, tr and tf
Pulse
Generator
tr = 5ns
Z O = 50Ω
Input
Monitor
(V E)
+5V
3.0 V
Input
(VE )
VCC
1
8
1.5 V
t EHL
7.5 mA
7
2
.1 µf
bypass
RL
1.5 V
Output
(VO )
6
3
t ELH
Output
(VO )
CL
4
GND
5
Fig. 13 Test Circuit tEHL and tELH
©2005 Fairchild Semiconductor Corporation
6N137, HCPL2601, HCPL2611, HCPL2630, HCPL2631 Rev. 1.0.7
www.fairchildsemi.com
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Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 — High Speed 10MBit/s Logic Gate Optocouplers
Test Circuits
VCC
IF
A
1
8
2
7
3
6
+5V
.1 µf
bypass
350Ω
B
VFF
4
GND
Output
(VO)
5
VCM
Pulse Gen
Peak
VCM
0V
CM H
5V
Switching Pos. (A), IF = 0
VO
VO (Min)
VO (Max)
Switching Pos. (B), I F = 7.5 mA
VO
0.5 V
CM L
Fig. 14 Test Circuit Common Mode Transient Immunity
©2005 Fairchild Semiconductor Corporation
6N137, HCPL2601, HCPL2611, HCPL2630, HCPL2631 Rev. 1.0.7
www.fairchildsemi.com
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Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 — High Speed 10MBit/s Logic Gate Optocouplers
Test Circuits (Continued)
Through Hole
0.4" Lead Spacing
PIN 1
ID.
4
3
2
PIN 1
ID.
1
4
3
2
1
0.270 (6.86)
0.250 (6.35)
5
6
7
0.270 (6.86)
0.250 (6.35)
8
5
6
0.070 (1.78)
0.045 (1.14)
0.020 (0.51) MIN
0.200 (5.08)
0.140 (3.55)
0.154 (3.90)
0.120 (3.05)
0.022 (0.56)
0.016 (0.41)
7
8
0.390 (9.91)
0.370 (9.40)
SEATING PLANE
SEATING PLANE
0.390 (9.91)
0.370 (9.40)
0.016 (0.40)
0.008 (0.20)
0.100 (2.54) TYP
0.070 (1.78)
0.045 (1.14)
0.004 (0.10) MIN
0.200 (5.08)
0.140 (3.55)
15° MAX
0.154 (3.90)
0.120 (3.05)
0.300 (7.62)
TYP
0.022 (0.56)
0.016 (0.41)
0.016 (0.40)
0.008 (0.20)
0.100 (2.54) TYP
Surface Mount
0° to 15°
0.400 (10.16)
TYP
8-Pin DIP – Land Pattern
0.390 (9.91)
0.370 (9.40)
4
3
2
1
0.070 (1.78)
PIN 1
ID.
0.060 (1.52)
0.270 (6.86)
0.250 (6.35)
5
6
7
0.100 (2.54)
8
0.295 (7.49)
0.070 (1.78)
0.045 (1.14)
0.020 (0.51)
MIN
0.022 (0.56)
0.016 (0.41)
0.100 (2.54)
TYP
Lead Coplanarity : 0.004 (0.10) MAX
0.415 (10.54)
0.300 (7.62)
TYP
0.030 (0.76)
0.016 (0.41)
0.008 (0.20)
0.045 (1.14)
0.315 (8.00)
MIN
0.405 (10.30)
MAX.
Note:
All dimensions are in inches (millimeters)
©2005 Fairchild Semiconductor Corporation
6N137, HCPL2601, HCPL2611, HCPL2630, HCPL2631 Rev. 1.0.7
www.fairchildsemi.com
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Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 — High Speed 10MBit/s Logic Gate Optocouplers
Package Dimensions
Option
Example Part Number
Description
S
6N137S
SD
6N137SD
W
6N137W
0.4" Lead Spacing
V
6N137V
VDE0884
WV
6N137WV
VDE0884; 0.4” Lead Spacing
SV
6N137SV
VDE0884; Surface Mount
SDV
6N137SDV
Surface Mount Lead Bend
Surface Mount; Tape and Reel
VDE0884; Surface Mount; Tape and Reel
Marking Information
1
V
3
2601
2
XX YY T1
6
4
5
Definitions
1
Fairchild logo
2
Device number
3
VDE mark (Note: Only appears on parts ordered with VDE option –
See order entry table)
4
Two digit year code, e.g., ‘03’
5
Two digit work week ranging from ‘01’ to ‘53’
6
Assembly package code
©2005 Fairchild Semiconductor Corporation
6N137, HCPL2601, HCPL2611, HCPL2630, HCPL2631 Rev. 1.0.7
www.fairchildsemi.com
10
Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 — High Speed 10MBit/s Logic Gate Optocouplers
Ordering Information
12.0 ± 0.1
4.90 ± 0.20
4.0 ± 0.1
Ø1.55 ± 0.05
4.0 ± 0.1
0.30 ± 0.05
1.75 ± 0.10
7.5 ± 0.1
13.2 ± 0.2
10.30 ± 0.20
Ø1.6 ± 0.1
10.30 ± 0.20
0.1 MAX
16.0 ± 0.3
User Direction of Feed
Reflow Profile
Temperature (°C)
300
215 C, 10–30 s
250
225 C peak
200
150
Time above 183C, 60–150 sec
100
50
Ramp up = 3C/sec
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Time (Minute)
• Peak reflow temperature: 225C (package surface temperature)
• Time of temperature higher than 183C for 60–150 seconds
• One time soldering reflow is recommended
©2005 Fairchild Semiconductor Corporation
6N137, HCPL2601, HCPL2611, HCPL2630, HCPL2631 Rev. 1.0.7
www.fairchildsemi.com
11
Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 — High Speed 10MBit/s Logic Gate Optocouplers
Tape Specifications
PDP SPM™
Power-SPM™
PowerTrench®
Programmable Active Droop™
QFET®
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Definition of Terms
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Definition
Datasheet contains the design specifications for product development. Specifications may change in
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Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild
Semiconductor reserves the right to make changes at any time without notice to improve design.
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes
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Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The
datasheet is for reference information only.
Rev. I35
©2005 Fairchild Semiconductor Corporation
6N137, HCPL2601, HCPL2611, HCPL2630, HCPL2631 Rev. 1.0.7
www.fairchildsemi.com
12
Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 — High Speed 10MBit/s Logic Gate Optocouplers
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