Hitachi HD404449 Hd404449 sery Datasheet

HD404449 Series
Rev. 6.0
Sept. 1998
Description
The HD404449 Series is a HMCS400-series microcomputer designed to increase program productivity
with large-capacity memory. Each microcomputer has four timers, two serial interfaces, A/D converter,
input capture circuit, 32-kHz oscillator for clock, and four low-power dissipation modes.
The HD404449 Series includes three chips: the HD404448 with 8-kword ROM; the HD404449 with 16kword ROM; and HD4074449 with 16-kword PROM (ZTAT version).
The HD4074449 is a PROM version (ZTAT microcomputer). A program can be written to the PROM by
a PROM writer, which can dramatically shorten system development periods and smooth the process from
debugging to mass production. (The ZTAT version is 27256-compatible.)
ZTAT: Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd.
Features
• 8,192-word × 10-bit ROM (HD404448)
16,384-word × 10-bit ROM (HD404449 and HD4074449)
• 1,152-digit × 4-bit RAM
• 64 I/O pins, including 10 high-current pins (15 mA, max)
• Four timer/counters
• Eight-bit input capture circuit
• Three timer outputs (including two PWM outputs)
• Two event counter inputs (including one double-edge function)
• Two clock-synchronous 8-bit serial interfaces
• A/D converter (4-channel × 8-bit)
• Built-in oscillators
 Main clock: 4-MHz ceramic oscillator or crystal (an external clock is also possible)
 Subclock: 32.768-kHz crystal
• Eleven interrupt sources
 Four by external sources, including two double-edge function
 Seven by internal sources
HD404449 Series
• Subroutine stack up to 16 levels, including interrupts
• Four low-power dissipation modes
 Subactive mode
 Standby mode
 Watch mode
 Stop mode
• One external input for transition from stop mode to active mode
• Instruction cycle time: 1 µs (fOSC = 4 MHz)
• Two operating modes
 MCU mode (HD404448, HD404449)
 MCU/PROM mode (HD4074449)
Ordering Information
Type
Product Name
Model Name
ROM (Words)
Package
Mask ROM
HD404448
HD404448H
8,192
80-pin plastic QFP (FP-80A)
HD404448TF
HD404449
HD404449H
80-pin plastic QFP (TFP-80F)
16,384
HD404449TF
ZTAT
HD4074449
HD4074449H
HD4074449TF
2
80-pin plastic QFP (FP-80A)
80-pin plastic QFP (TFP-80F)
16,384
80-pin plastic QFP (FP-80A)
80-pin plastic QFP (TFP-80F)
HD404449 Series
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
AN1
AN0
AVCC
VCC
RC3
RC2
RC1
RC0
RB3
RB2
RB1
RB0
RA3
RA2
RA1
RA0
R93
R92
R91
R90
Pin Arrangement
FP-80A
TFP-80F
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
R83
R82
R81
R80
R73
R72
R71
R70
R63
R62
R61
R60
R53/SO2
R52/SI2
R51/SCK2
R50
R43/SO1
R42/SI1
R41/SCK1
R40/EVND
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
D10
D11
D12/STOPC
D13/INT0
R00/INT1
R01/INT2
R02/INT3
R03
R10
R11
R12
R13
R20
R21
R22
R23
R30/TOB
R31/TOC
R32/TOD
R33/EVNB
AN2
AN3
AVSS
TEST
OSC1
OSC2
RESET
X1
X2
GND
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
(Top view)
3
HD404449 Series
Pin Description
Item
Symbol
Pin Number I/O
Function
Power supply
VCC
77
Applies power voltage
GND
10
Connected to ground
Test
TEST
4
I
Used for factory testing only: Connect this pin to V CC
Reset
RESET
7
I
Resets the MCU
Oscillator
OSC 1
5
I
Input/output pins for the internal oscillator circuit:
Connect them to a ceramic oscillator, crystal, or
connect OSC 1 to an external oscillator circuit
OSC 2
6
O
X1
8
I
X2
9
O
D0–D 11
11–22
I/O Input/output pins addressed by individual bits; pins
D0–D 9 are high-current pins that can each supply up to
15 mA
D12, D13
23, 24
I
R0 0–RC3
25–76
I/O Input/output pins addressable in 4-bit units
INT0, INT1,
24–27
I
Input pins for external interrupts
Input pin for transition from stop mode to active mode
Port
Interrupt
Used for a 32.768-kHz crystal for clock purposes. If
not to be used, fix the X1 pin to V CC and leave the X2
pin open.
Input pins addressable by individual bits
INT2, INT3
Stop clear
STOPC
23
I
Serial
SCK 1, SCK 2
42, 46
I/O Serial clock input/output pin
interface
SI 1, SI 2
43, 47
I
Serial receive data input pin
SO1, SO2
44, 48
O
Serial transmit data output pin
TOB, TOC, TOD 37–39
O
Timer output pins
EVNB, EVND
40, 41
I
Event count input pins
AVCC
78
Power pin for A/D converter: Connect it to the same
potential as V CC, as physically close to the VCC pin as
possible
AVSS
3
Ground for AV CC: Connect it to the same potential as
GND, as physically close to the GND pin as possible
AN 0–AN 3
79, 80, 1, 2
Timer
A/D converter
4
I
Analog input pins for A/D converter
HD404449 Series
RESET
TEST
STOPC
OSC1
OSC2
X1
X2
VCC
GND
Block Diagram
System control
External
interrupt
W
(2 bits)
Timer
A
TOC
Timer
C
EVND
TOD
Timer
D
SI 1
SO 1
SCK 1
Serial
interface
1
SI2
SO2
SCK2
Serial
interface
2
AVCC
AVSS
AN0
AN1
AN2
AN3
A/D
converter
X
(4 bits)
SPX
(4 bits)
Y
(4 bits)
Internal address bus
Timer
B
Internal data bus
EVNB
TOB
D port
RAM
(1,152 × 4 bits)
SPY
(4 bits)
ALU
CPU
ST
CA
(1 bit) (1 bit)
A
(4 bits)
B
(4 bits)
SP
(10 bits)
Instruction
decoder
PC
(14 bits)
ROM
(16,384 × 10 bits)
(8,192 × 10 bits)
RC port RB port RA port R9 port R8 port R7 port R6 port R5 port R4 port R3 port R2 port R1 port R0 port
INT 0
INT 1
INT 2
INT 3
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D 10
D 11
D 12
D 13
R0 0
R0 1
R0 2
R0 3
R1 0
R1 1
R1 2
R1 3
R2 0
R2 1
R2 2
R2 3
R3 0
R3 1
R3 2
R3 3
R4 0
R4 1
R4 2
R4 3
R5 0
R5 1
R5 2
R5 3
R6 0
R6 1
R6 2
R6 3
R7 0
R7 1
R7 2
R7 3
R8 0
R8 1
R8 2
R8 3
R9 0
R9 1
R9 2
R9 3
RA0
RA1
RA2
RA3
RB 0
RB 1
RB 2
RB 3
RC 0
RC 1
RC 2
RC 3
High current
pins
: Data bus
: Signal line
5
HD404449 Series
Memory Map
ROM Memory Map
The ROM memory map is shown in figure 1 and described below.
0
$0000
Vector address
$000F
15
16
$0010
Zero-page subroutine
(64 words)
63
$003F
64
$0040
Pattern
(4,096 words)
$0FFF
4,095
$1000
4,096
HD404448
Program
(8,192 words)
8,191
$1FFF
8,192
$2000
0
JMPL instruction
1 (Jump to RESET, STOPC routine)
JMPL instruction
2
(Jump to INT0 routine)
3
JMPL instruction
4
(Jump to INT1 routine)
5
6
7
8
9
10
11
12
13
14
15
JMPL instruction
(Jump to timer A routine)
$0000
$0001
$0002
$0003
$0004
$0005
JMPL instruction
(Jump to timer D, A/D routine)
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
JMPL instruction
(Jump to serial 1, serial 2 routine)
$000E
$000F
JMPL instruction
(Jump to timer B, INT2 routine)
JMPL instruction
(Jump to timer C, INT3 routine)
HD404449, HD4074449
Program
(16,384 words)
16,383
$3FFF
Figure 1 ROM Memory Map
Vector Address Area ($0000–$000F): Reserved for JMPL instructions that branch to the start addresses
of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the
vector address.
Zero-Page Subroutine Area ($0000–$003F): Reserved for subroutines. The program branches to a
subroutine in this area in response to the CAL instruction.
Pattern Area ($0000–$0FFF): Contains ROM data that can be referenced with the P instruction.
Program Area ($0000–$1FFF (HD404448), $0000–$3FFF (HD404449, HD4074449)): Used for
program coding.
RAM Memory Map
The MCU contains a 1,152-digit × 4-bit RAM area consisting of a memory register area, a data area, and a
stack area. In addition, an interrupt control bits area, special register area, and register flag area are mapped
onto the same RAM memory space as a RAM-mapped register area outside the above areas. The RAM
memory map is shown in figure 2 and described as follows.
6
HD404449 Series
0
$000
RAM-mapped registers
64
Memory registers (MR)
80
$040
$050
Not used
$090
144
Data (464 digits × 2)
V = 0 (bank 0)
V = 1 (bank 1)
Note
$260
608
Data (144 digits)
752
960
$2F0
Not used
$3C0
Stack (64 digits)
$3FF
1023
$090
Data
(464 digits)
V=0
(bank = 0)
Data
(464 digits)
V=1
(bank = 1)
$25F
Note: The data area has two banks:
bank 0 (V = 0) to bank 1 (V = 1)
R:
Read only
W:
Write only
R/W: Read/Write
* Two registers are mapped
0
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
63
(DCD0)
(DCD1)
(DCD2)
W
W
W
(DCR0)
(DCR1)
(DCR2)
(DCR3)
(DCR4)
(DCR5)
(DCR6)
(DCR7)
(DCR8)
(DCR9)
(DCRA)
(DCRB)
(DCRC)
W
W
W
W
W
W
W
W
W
W
W
W
W
$000
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
$00F
$010
$011
$012
$013
$014
$015
$016
$017
$018
$019
$01A
$01B
$01C
$01D
$01E
$01F
$020
$023
$024
$025
$026
$027
$028
$029
$02A
$02B
$02C
$02D
$02E
$02F
$030
$031
$032
$033
$034
$035
$036
$037
$038
$039
$03A
$03B
$03C
R/W
$03F
Interrupt control bits area
(PMRA)
Port mode register A
Serial mode register 1A (SM1A)
Serial data register 1 lower (SR1L)
Serial data register 1 upper (SR1U)
Timer mode register A
(TMA)
Timer mode register B1
(TMB1)
(TRBL/TWBL)
Timer B
(TRBU/TWBU)
(MIS)
Miscellaneous register
Timer mode register C1 (TMC1)
(TRCL/TWCL)
Timer C
(TRCU/TWCU)
Timer mode register D1 (TMD1)
(TRDL/TWDL)
Timer D
(TRDU/TWDU)
Timer mode register B2
(TMB2)
Timer mode register C2 (TMC2)
Timer mode register D2 (TMD2)
A/D data register
(AMR)
A/D data register lower
(ADRL)
A/D data register upper (ADRU)
W
W
R/W
R/W
W
W
R/W
R/W
W
W
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
W
R
R
Not used
Serial mode register 2A
Serial mode register 2B
Serial data register 2 lower
Serial data register 2 upper
Not used
(SM2A) W
(SM2B) W
(SR2L) R/W
(SR2U) R/W
Register flag area
Port mode register B
Port mode register C
(PMRB)
(PMRC)
Detection edge select register 1 (ESR1)
Detection edge select register 2 (ESR2)
Serial mode register 1B (SM1B)
System clock select register (SSR)
W
W
W
W
W
W
Not used
Port D0 –D 3 DCR
Port D4 –D 7 DCR
Port D8 and D11 DCR
Not used
Port R0 DCR
Port R1 DCR
Port R2 DCR
Port R3 DCR
Port R4 DCR
Port R5 DCR
Port R6 DCR
Port R7 DCR
Port R8 DCR
Port R9 DCR
Port RA DCR
Port RB DCR
Port RC DCR
Not used
V register
*
on the same area.
10
11
Timer read register B lower (TRBL) R Timer write register B lower (TWBL) W $00A
Timer read register B upper (TRBU) R Timer write register B upper (TWBU) W $00B
14 Timer read register C lower (TRCL) R Timer write register C lower (TWCL) W $00E
15 Timer read register C upper (TRCU) R Timer write register C upper (TWCU) W $00F
17 Timer read register D lower (TRDL) R Timer write register D lower (TWDL) W $011
18 Timer read register D upper (TRDU) R Timer write register D upper (TWDU) W $012
Figure 2 RAM Memory Map
7
HD404449 Series
RAM-Mapped Register Area ($000–$03F):
• Interrupt Control Bits Area ($000–$003)
This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit
manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the
instructions can be used for each bit. Limitations on using the instructions are shown in figure 4.
• Special Function Register Area ($004–$01F, $024–$03F)
This area is used as mode registers and data registers for external interrupts, serial interface 1, serial
interface 2, timer/counters, A/D converter, and as data control registers for I/O ports. The structure is
shown in figures 2 and 5. These registers can be classified into three types: write-only (W), read-only
(R), and read/write (R/W). RAM bit manipulation instructions cannot be used for these registers.
• Register Flag Area ($020–$023)
This area is used for the DTON, WDON, and other register flags and interrupt control bits (figure 3).
These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and
TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using
the instructions are shown in figure 4.
Memory Register (MR) Area ($040–$04F): Consisting of 16 addresses, this area (MR0–MR15) can be
accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6.
Data Area ($090–$2EF): 464 digits from $090 to $25F have two banks, which can be selected by setting
the bank register (V: $03F). Before accessing this area, set the bank register to the required value (figure
7). The area from $260 to $2EF is accessed without setting the bank register.
Stack Area ($3C0–$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and
carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a
16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save
conditions are shown in figure 6.
The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can
only be restored by the RTNI instruction. Any unused space in this area is used for data storage.
8
HD404449 Series
Bit 3
Bit 2
Bit 1
Bit 0
0
IM0
(IM of INT0)
IF0
(IF of INT0)
RSP
(Reset SP bit)
IE
(Interrupt
enable flag)
$000
1
IMTA
(IM of timer A)
IFTA
(IF of timer A)
IM1
(IM of INT1)
IF1
(IF of INT1)
$001
2
IMTC
(IM of timer C)
IFTC
(IF of timer C)
IMTB
(IM of timer B)
IFTB
(IF of timer B)
$002
3
IMS1
(IM of serial
interface 1)
IFS1
(IF of serial
interface 1)
IMTD
(IM of timer D)
IFTD
(IF of timer D)
$003
Interrupt control bits area
Bit 3
Bit 2
Bit 1
Bit 0
32
DTON
(Direct transfer
on flag)
ADSF
(A/D start flag)
WDON
(Watchdog
on flag)
LSON
(Low speed
on flag)
$020
33
RAME
(RAM enable
flag)
Not used
ICEF
(Input capture
error flag)
ICSF
(Input capture
status flag)
$021
34
IM3
(IM of INT3)
IF3
(IF of INT3)
IM2
(IM of INT2)
IF2
(IF of INT2)
$022
35
IMS2
(IM of serial
interface 2)
IFS2
(IF of serial
interface 2)
IMAD
(IM of A/D)
IFAD
(IF of A/D)
$023
IF:
IM:
IE:
SP:
Interrupt request flag
Interrupt mask
Interrupt enable flag
Stack pointer
Register flag area
Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas
9
HD404449 Series
IE
IM
LSON
IF
ICSF
ICEF
RAME
RSP
WDON
ADSF
DTON
Not used
SEM/SEMD
REM/REMD
TM/TMD
Allowed
Allowed
Allowed
Not executed
Allowed
Allowed
Not executed
Allowed
Allowed
Not executed in active mode
Used in subactive mode
Not executed
Allowed
Not executed
Inhibited
Inhibited
Inhibited
Allowed
Allowed
Allowed
Not executed
Inhibited
Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation.
The REM or REMD instuction must not be executed for ADSF during A/D conversion.
DTON is always reset in active mode.
If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,
the value in ST becomes invalid.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
10
HD404449 Series
Bit 3
Bit 2
PMRA $004
R52/SI2
R53/SO2
SM1A $005
R41/SCK1
$000
$003
Bit 1
Bit 0
Interrupt control bits area
R42/SI1
R43/SO1
Serial transmit clock speed selection 1
SR1L $006
Serial data register 1 (lower digit)
SR1U $007
Serial data register 1 (upper digit)
TMA $008
*1
TMB1 $009
*2
Clock source selection (timer A)
Clock source selection (timer B)
Timer B register (lower digit)
TRBL/TWBL $00A
Timer B register (upper digit)
TRBU/TWBU $00B
MIS $00C
*3
TMC1 $00D
*2
R43/SO1 PMOS control
Interrupt frame period selection
Clock source selection (timer C)
TRCL/TWCL $00E
Timer C register (lower digit)
TRCU/TWCU $00F
Timer C register (upper digit)
TMD1 $010
Timer D register (lower digit)
Timer D register (upper digit)
TRDU/TWDU $012
TMB2 $013
TMC2 $014
TMD2 $015
AMR $016
Clock source selection (timer D)
*2
TRDL/TWDL $011
Not used
Not used
Not used
Timer-B output mode selection
Timer-C output mode selection
Timer-D output mode selection
*4
Analog channel selection
Not used
ADRL $017
A/D data register (lower digit)
ADRU $018
A/D data register (upper digit)
*5
Not used
SM2A $01B
R51/SCK2
SM2B $01C
Not used
Serial transmit clock speed selection 2
*6
R53/SO2 PMOS control
*7
SR2L $01D
Serial data register 2 (lower digit)
SR2U $01E
Serial data register 2 (upper digit)
Not used
$020
Register flag area
$023
PMRB $024
Not used
R02/INT3
R01/INT2
R00/INT1
PMRC $025
D13/INT0
D12/STOPC
R40/EVND
R33/EVNB
ESR1 $026
INT3 detection edge selection
ESR2 $027
EVND detection edge selection
SM1B $028
Not used
Not used
*8
*9
*10
*11
*12
Not used
DCD0 $02C
Port D3 DCR
Port D2 DCR
Port D1 DCR
Port D0 DCR
DCD1 $02D
Port D7 DCR
Port D6 DCR
Port D5 DCR
Port D4 DCR
DCD2 $02E
Port D11 DCR
Port D10 DCR
Port D9 DCR
Port D8 DCR
SSR $029
INT2 detection edge selection
Not used
Not used
Not used
DCR0 $030
Port R03 DCR
Port R02 DCR
Port R01 DCR
Port R00 DCR
DCR1 $031
Port R13 DCR
Port R12 DCR
Port R11 DCR
Port R10 DCR
DCR2 $032
Port R23 DCR
Port R22 DCR
Port R21 DCR
Port R20 DCR
DCR3 $033
Port R33 DCR
Port R32 DCR
Port R31 DCR
Port R30 DCR
DCR4 $034
Port R43 DCR
Port R42 DCR
Port R41 DCR
Port R40 DCR
DCR5 $035
Port R53 DCR
Port R52 DCR
Port R51 DCR
Port R50 DCR
DCR6 $036
Port R63 DCR
Port R62 DCR
Port R61 DCR
Port R60 DCR
DCR7 $037
Port R73 DCR
Port R72 DCR
Port R71 DCR
Port R70 DCR
DCR8 $038
Port R83 DCR
Port R82 DCR
Port R81 DCR
Port R80 DCR
DCR9 $039
Port R93 DCR
Port R92 DCR
Port R91 DCR
Port R90 DCR
DCRA $03A
Port RA3 DCR
Port RA2 DCR
Port RA1 DCR
Port RA0 DCR
DCRB $03B
Port RB3 DCR
Port RB2 DCR
Port RB1 DCR
Port RB0 DCR
DCRC $03C
Port RC3 DCR
Port RC2 DCR
Port RC1 DCR
Not used
Port RC0 DCR
V $03F
Not used
Not used
Not used
*13
Notes:
1. Timer-A/time-base
2. Auto-reload on/off
3. Pull-up MOS control
4. Input capture selection
5. A/D conversion time
6. SO2 ouput control in idle states
7. Serial clock source selection 2
8. SO1 output level control in idle states
9. Serial clock source selection 1
10. 32-kHz oscillation stop
11. 32-kHz oscillation division ratio
12. System clock selection
13. Bank 0, 1 selection
Figure 5 Special Function Register Area
11
HD404449 Series
Memory registers
MR(0) $040
64
MR(1) $041
65
MR(2) $042
66
MR(3)
$043
67
MR(4)
$044
68
MR(5)
$045
69
MR(6)
$046
70
MR(7)
$047
71
MR(8)
$048
72
MR(9)
$049
73
MR(10) $04A
74
MR(11) $04B
75
MR(12) $04C
76
MR(13) $04D
77
MR(14) $04E
78
MR(15) $04F
79
Stack area
Level 16
Level 15
Level 14
Level 13
Level 12
Level 11
Level 10
Level 9
Level 8
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
1023 Level 1
960
$3C0
$3FF
Bit 3
Bit 2
Bit 1
Bit 0
1020
ST
PC13
PC 12
PC11
$3FC
1021
PC 10
PC9
PC 8
PC7
$3FD
1022
CA
PC6
PC 5
PC4
$3FE
1023
PC 3
PC2
PC 1
PC0
$3FF
PC13 –PC0 : Program counter
ST: Status flag
CA: Carry flag
Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position
Bank register (V: $03F)
Bit
3
2
1
0
Initial value
—
—
—
0
Read/Write
—
—
—
R/W
Bit name
V0
Not used Not used Not used
V0
Bank area selection
0
Bank 0 is selected
1
Bank 1 is selected
Note: After reset, the value in the bank register is 0, and therefore bank 0 is
selected.
Figure 7 Bank Register (V)
12
HD404449 Series
Functional Description
Registers and Flags
The MCU has nine registers and two flags for CPU operations. They are shown in figure 8 and described
below.
3
Accumulator
0
(A)
Initial value: Undefined, R/W
3
B register
Initial value: Undefined, R/W
0
(B)
1
W register
Initial value: Undefined, R/W
0
(W)
3
X register
Initial value: Undefined, R/W
Y register
Initial value: Undefined, R/W
0
(X)
3
0
(Y)
3
SPX register
Initial value: Undefined, R/W
0
(SPX)
3
SPY register
Initial value: Undefined, R/W
0
(SPY)
0
Carry
Initial value: Undefined, R/W
(CA)
0
Status
Initial value: 1, no R/W
(ST)
13
Program counter
Initial value: 0,
no R/W
0
(PC)
9
Stack pointer
Initial value: $3FF, no R/W
1
5
1
1
1
0
(SP)
Figure 8 Registers and Flags
Accumulator (A), B Register (B): Four-bit registers used to hold the results from the arithmetic logic unit
(ALU) and transfer data between memory, I/O, and other registers.
W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for
indirect RAM addressing. The Y register is also used for D-port addressing.
13
HD404449 Series
SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers.
Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is
affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an
interrupt and popped from the stack by the RTNI instruction—but not by the RTN instruction.
Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare
instruction, not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the
BR, BRL, CAL, and CALL instructions. The contents of ST remain unchanged until the next arithmetic,
compare, or bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is
read, regardless of whether the instruction is executed or skipped. The contents of ST are pushed onto the
stack during an interrupt and popped from the stack by the RTNI instruction—but not by the RTN
instruction.
Program Counter (PC): 14-bit binary counter that points to the ROM address of the instruction being
executed.
Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is
initialized to $3FF by MCU reset. It is decremented by 4 when data is pushed onto the stack, and
incremented by 4 when data is popped from the stack. The top four bits of the SP are fixed at 1111, so a
stack can be used up to 16 levels.
The SP can be initialized to $3FF in another way: by resetting the RSP bit with the REM or REMD
instruction.
Reset
The MCU is reset by inputting a high-level voltage to the RESET pin. At power-on or when stop mode is
cancelled, RESET must be high for at least one tRC to enable the oscillator to stabilize. During operation,
RESET must be high for at least two instruction cycles.
Initial values after MCU reset are listed in table 1.
14
HD404449 Series
Table 1
Initial Values After MCU Reset
Item
Abbr.
Initial
Value
Program counter
(PC)
$0000
Indicates program execution point from start
address of ROM area
Status flag
(ST)
1
Enables conditional branching
Stack pointer
(SP)
$3FF
Stack level 0
Interrupt
Interrupt enable flag
flags/mask
(IE)
0
Inhibits all interrupts
Interrupt request flag
(IF)
0
Indicates there is no interrupt request
Interrupt mask
(IM)
1
Prevents (masks) interrupt requests
Port data register
(PDR)
All bits 1 Enables output at level 1
Data control register
(DCD0–
DCD2)
All bits 0 Turns output buffer off (to high impedance)
(DCR0–
DCRC)
All bits 0
Port mode register A
(PMRA)
0000
Refer to description of port mode register A
Port mode register B
(PMRB)
- 000
Refer to description of port mode register B
Port mode register C
(PMRC)
0000
Refer to description of port mode register C
Detection edge select
register 1
(ESR1)
0000
Disables edge detection
Detection edge select
register 2
(ESR2)
00 - -
Disables edge detection
Timer mode register A
(TMA)
0000
Refer to description of timer mode register A
Timer mode register B1
(TMB1)
0000
Refer to description of timer mode register B1
Timer mode register B2
(TMB2)
- - 00
Refer to description of timer mode register B2
Timer mode register C1
(TMC1)
0000
Refer to description of timer mode register C1
Timer mode register C2
(TMC2)
- 000
Refer to description of timer mode register C2
Timer mode register D1
(TMD1)
0000
Refer to description of timer mode register D1
Timer mode register D2
(TMD2)
0000
Refer to description of timer mode register D2
Serial mode register 1A
(SM1A)
0000
Refer to description of serial mode register 1A
Serial mode register 1B
(SM1B)
- - 00
Refer to description of serial mode register 1B
Serial mode register 2A
(SM2A)
0000
Refer to description of serial mode register 2A
Serial mode register 2B
(SM2B)
- 000
Refer to description of serial mode register 2B
Prescaler S
(PSS)
$000
—
Prescaler W
(PSW)
$00
—
I/O
Timer/
counters,
serial
interface
Contents
15
HD404449 Series
Abbr.
Initial
Value
Contents
Timer counter A
(TCA)
$00
—
Timer counter B
(TCB)
$00
—
Timer counter C
(TCC)
$00
—
Timer counter D
(TCD)
$00
—
Timer write register B
(TWBU,
TWBL)
$X0
—
Timer write register C
(TWCU,
TWCL)
$X0
—
Timer write register D
(TWDU,
TWDL)
$X0
—
000
—
(AMR)
00 - 0
Refer to description of A/D mode register
(LSON)
0
Refer to description of operating modes
Item
Timer/
counters,
serial
interface
Octal counter
A/D
A/D mode register
Bit register Low speed on flag
Others
Watchdog timer on flag
(WDON) 0
Refer to description of timer C
A/D start flag
(ADSF)
0
Refer to description of A/D converter
Direct transfer on flag
(DTON)
0
Refer to description of operating modes
Input capture status flag
(ICSF)
0
Refer to description of timer D
Input capture error flag
(ICEF)
0
Refer to description of timer D
Miscellaneous register
(MIS)
0000
Refer to description of operating modes, and
oscillator circuit
System clock select
register bits 2–0
(SSR2–
SSR0)
00 -
Refer to description of operating modes, and
oscillator circuit
Bank register
(V)
---0
Refer to description of RAM memory map
Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table.
2. X indicates invalid value. – indicates that the bit does not exist.
16
HD404449 Series
Item
Abbr.
Carry flag
(CA)
Accumulator
(A)
B register
(B)
W register
(W)
X/SPX register
(X/SPX)
Y/SPY register
(Y/SPY)
Status After
Status After
Cancellation of Stop Cancellation of Stop
Mode by STOPC Input Mode by MCU Reset
Pre-stop-mode values are not guaranteed;
values must be initialized by program
Status After all Other
Types of Reset
Pre-stop-mode values
are not guaranteed;
values must be
initialized by program
Serial data register (SRL, SRU)
A/D data register
(ADRL,
ADRU)
RAM
RAM enable flag
Pre-stop-mode values are retained
(RAME)
Port mode register (PMRC12)
1 bit 2
1
0
0
Pre-stop-mode values
are retained
0
0
System clock
(SSR3)
select register bit 3
Interrupts
The MCU has 11 interrupt sources: four external signals (INT0 , INT1, INT 2, INT 3), four timer/counters
(timers A, B, C, and D), two serial interfaces (serial 1, serial 2), and A/D converter.
An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt
source, and an interrupt enable flag (IE) controls the entire interrupt process.
Some vector addresses are shared by two different interrupts. They are timer B and INT 2, timer C and
INT 3, timer D and A/D converter, and serial interface 1 and serial interface 2. So the type of request that
has occurred must be checked at the beginning of interrupt processing.
Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 and $022 to $023 in RAM are
reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions.
The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag
(IE) and the IF to 0 and the interrupt mask (IM) to 1.
A block diagram of the interrupt control circuit is shown in figure 9, interrupt priorities and vector
addresses are listed in table 2, and interrupt processing conditions for the 11 interrupt sources are listed in
table 3.
17
HD404449 Series
An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the
interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to
that interrupt source.
The interrupt processing sequence is shown in figure 10 and an interrupt processing flowchart is shown in
figure 11. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The
IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack
during the second and third cycles, and the program jumps to the vector address to execute the instruction
in the third cycle.
Program the JMPL instruction at each vector address, to branch the program to the start address of the
interrupt program, and reset the IF by a software instruction within the interrupt program.
Table 2
Vector Addresses and Interrupt Priorities
Reset/Interrupt
Priority
Vector Address
RESET, STOPC*
—
$0000
INT0
1
$0002
INT1
2
$0004
Timer A
3
$0006
Timer B, INT2
4
$0008
Timer C, INT3
5
$000A
Timer D, A/D
6
$000C
Serial 1, Serial 2
7
$000E
Note: * The STOPC interrupt request is valid only in stop mode
18
HD404449 Series
$ 000,0
IE
INT0 interrupt
Sequence control
• Push PC/CA/ST
• Reset IE
• Jump to vector
address
$ 000,2
IF0
$ 000,3
IM0
Vector
address
Priority control logic
INT1 interrupt
$ 001,0
IF1
$ 001,1
IM1
Timer A interrupt
$ 001,2
IFTA
$ 001,3
IMTA
Timer B interrupt
Timer C interrupt
Timer D interrupt
$ 002,0
IFTB
$ 022,0
IF2
INT2 interrupt
$ 002,1
IMTB
$ 022,1
IM2
$ 002,2
IFTC
$ 022,2
IF3
INT3 interrupt
$ 002,3
IMTC
$ 022,3
IM3
$ 003,0
IFTD
$ 023,0
IF
A/D interrupt
A/D
$ 023,1
IM
A/D
$ 023,2
Serial 2 interrupt
IFS2
$ 003,1
IMTD
$ 003,2
Serial 1 interrupt
IFS1
$ 003,3
$ 023,3
IMS2
IMS1
Note: $m,n is RAM address $m, bit number n.
Figure 9 Interrupt Control Circuit
19
HD404449 Series
Table 3
Interrupt Processing and Activation Conditions
Interrupt Source
Interrupt
Control Bit
INT0
INT1
Timer A
Timer B or Timer C or Timer D or Serial 1 or
INT3
A/D
Serial 2
INT2
IE
1
1
1
1
1
1
1
IF0 IM0
1
0
0
0
0
0
0
.
.
IF1 IM1
*
1
0
0
0
0
0
.
IFTA IMTA
*
*
1
0
0
0
0
.
*
*
*
1
0
0
0
*
*
*
*
1
0
0
*
*
*
*
*
1
0
*
*
*
*
*
*
1
IFTB IMTB
.
+ IF2 IM2
IFTC . IMTC
.
+ IF3 IM3
IFTD . IMTD
.
+ IFAD IMAD
IFS1 . IMS1
.
+ IFS2 IMS2
Note: Bits marked * can be either 0 or 1. Their values have no effect on operation.
Instruction cycles
1
2
3
4
5
6
Instruction
execution*
Interrupt
acceptance
Stacking
IE reset
Vector address
generation
Execution of JMPL
instruction at vector address
Note: *The stack is accessed and the IE reset after the instruction
is executed, even if it is a two-cycle instruction.
Figure 10 Interrupt Processing Sequence
20
Execution of
instruction at
start address
of interrupt
routine
HD404449 Series
Power on
RESET = 1?
Yes
No
Interrupt
request?
No
Yes
No
IE = 1?
Yes
Reset MCU
Accept interrupt
Execute instruction
IE ← 0
Stack ← (PC)
Stack ← (CA)
Stack ← (ST)
PC ←(PC) + 1
PC← $0002
Yes
INT0
interrupt?
No
PC← $0004
Yes
INT1
interrupt?
No
PC← $0006
Yes
Timer-A
interrupt?
No
PC← $0008
Yes
Timer-B/INT2
interrupt?
No
PC ← $000A
Yes
Timer-C/INT3
interrupt?
No
PC ← $000C
Yes
Timer-D/A-D
interrupt?
No
PC ← $000E
(Serial 1, serial 2 interrupt)
Figure 11 Interrupt Processing Flowchart
21
HD404449 Series
Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt
processing and set by the RTNI instruction, as listed in table 4.
Table 4
Interrupt Enable Flag (IE: $000, Bit 0)
IE
Interrupt Enabled/Disabled
0
Disabled
1
Enabled
External Interrupts (INT0, INT1, INT2, INT3): Four external interrupt signals.
External Interrupt Request Flags (IF0, IF1, IF2, IF3: $000, $001, $022): IF0 and IF1 are set at the
falling edge of signals input to INT0 and INT1, and IF2 and IF3 are set at the rising or falling edge of signals
input to INT2 and INT 3, as listed in table 5. The INT2 and INT 3 interrupt edges are selected by the detection
edge select registers (ESR1, ESR2: $026, $027) as shown in figures 12 and 13.
Table 5
External Interrupt Request Flags (IF0–IF3: $000, $001, $022)
IF0–IF3
Interrupt Request
0
No
1
Yes
Detection edge selection register 1 (ESR1: $026)
Bit
3
2
0
1
Initial value
0
0
0
0
Read/Write
W
W
W
W
ESR13
ESR12
ESR11
ESR10
Bit name
INT3 detection edge
ESR13
ESR12
0
0
No detection
1
Falling-edge detection
0
Rising-edge detection
1
Double-edge detection*
1
INT2 detection edge
ESR11
ESR10
0
0
No detection
1
Falling-edge detection
0
Rising-edge detection
1
Double-edge detection*
1
Note: *Both falling and rising edges are detected.
Figure 12 Detection Edge Selection Register 1 (ESR1)
22
HD404449 Series
Detection edge selection register 2 (ESR2: $027)
Bit
3
2
1
0
Initial value
0
0
—
—
Read/Write
W
W
—
—
Bit name
ESR23
ESR22 Not used Not used
EVND detection edge
ESR23
ESR22
0
0
No detection
1
Falling-edge detection
0
Rising-edge detection
1
Double-edge detection*
1
Note: *Both falling and rising edges are detected.
Figure 13 Detection Edge Selection Register 2 (ESR2)
External Interrupt Masks (IM0, IM1, IM2, IM3: $000, $001, $022): Prevent (mask) interrupt requests
caused by the corresponding external interrupt request flags, as listed in table 6.
Table 6
External Interrupt Masks (IM0–1M3: $000, $001, $022)
IM0–IM3
Interrupt Request
0
Enabled
1
Disabled (Masked)
Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in
table 7.
Table 7
Timer A Interrupt Request Flag (IFTA: $001, Bit 2)
IFTA
Interrupt Request
0
No
1
Yes
23
HD404449 Series
Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the
timer A interrupt request flag, as listed in table 8.
Table 8
Timer A Interrupt Mask (IMTA: $001, Bit 3)
IMTA
Interrupt Request
0
Enabled
1
Disabled (Masked)
Timer B Interrupt Request Flag (IFTB: $002, Bit 0): Set by overflow output from timer B, as listed in
table 9.
Table 9
Timer B Interrupt Request Flag (IFTB: $002, Bit 0)
IFTB
Interrupt Request
0
No
1
Yes
Timer B Interrupt Mask (IMTB: $002, Bit 1): Prevents (masks) an interrupt request caused by the
timer B interrupt request flag, as listed in table 10.
Table 10
Timer B Interrupt Mask (IMTB: $002, Bit 1)
IMTB
Interrupt Request
0
Enabled
1
Disabled (Masked)
Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in
table 11.
Table 11
Timer C Interrupt Request Flag (IFTC: $002, Bit 2)
IFTC
Interrupt Request
0
No
1
Yes
24
HD404449 Series
Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the
timer C interrupt request flag, as listed in table 12.
Table 12
Timer C Interrupt Mask (IMTC: $002, Bit 3)
IMTC
Interrupt Request
0
Enabled
1
Disabled (Masked)
Timer D Interrupt Request Flag (IFTD: $003, Bit 0): Set by overflow output from timer D, or by the
rising or falling edge of signals input to EVND when the input capture function is used, as listed in table
13.
Table 13
Timer D Interrupt Request Flag (IFTD: $003, Bit 0)
IFTD
Interrupt Request
0
No
1
Yes
Timer D Interrupt Mask (IMTD: $003, Bit 1): Prevents (masks) an interrupt request caused by the
timer D interrupt request flag, as listed in table 14.
Table 14
Timer D Interrupt Mask (IMTD: $003, Bit 1)
IMTD
Interrupt Request
0
Enabled
1
Disabled (Masked)
Serial Interrupt Request Flags (IFS1: $003, Bit 2; IFS2: $023, Bit 2) Set when data transfer is
completed or when data transfer is suspended, as listed in table 15.
Table 15
Serial Interrupt Request Flag (IFS1: $003, Bit 2; IFS2: $023, Bit 2)
IFS1, IFS2
Interrupt Request
0
No
1
Yes
25
HD404449 Series
Serial Interrupt Masks (IMS1: $003, Bit 3; IMS2: $023, Bit 3): Prevents (masks) an interrupt request
caused by the serial interrupt request flag, as listed in table 16.
Table 16
Serial Interrupt Mask (IMS1: $003, Bit 3; IMS2: $023, Bit 3)
IMS1, IMS2
Interrupt Request
0
Enabled
1
Disabled (Masked)
A/D Interrupt Request Flag (IFAD: $023, Bit 0): Set at the completion of A/D conversion, as listed in
table 17.
Table 17
A/D Interrupt Request Flag (IFAD: $023, Bit 0)
IFAD
Interrupt Request
0
No
1
Yes
A/D Interrupt Mask (IMAD: $023, Bit 1): Prevents (masks) an interrupt request caused by the A/D
interrupt request flag, as listed in table 18.
Table 18
A/D Interrupt Mask (IMAD: $023, Bit 1)
IMAD
Interrupt Request
0
Enabled
1
Disabled (Masked)
26
HD404449 Series
Operating Modes
The MCU has five operating modes as shown in table 19. The operations in each mode are listed in tables
20 and 21. Transitions between operating modes are shown in figure 14.
Active Mode: All MCU functions operate according to the clock generated by the system oscillators OSC1
and OSC2.
Table 19
Operating Modes and Clock Status
Mode Name
Active
Standby
Stop
Watch
Subactive*2
SBY instruction STOP
STOP
Activation method RESET
instruction when instruction when
cancellation,
TMA3 = 0
TMA3 = 1
interrupt
request, STOPC
cancellation in
stop mode,
STOP/SBY
instruction in
subactive mode
(when direct
transfer is
selected)
INT0 or timer A
interrupt request
from watch
mode
Status System
oscillator
OP
OP
Stopped
Stopped
Stopped
Subsystem OP
oscillator
OP
OP*1
OP
OP
Cancellation
method
RESET input,
STOP/SBY
instruction
RESET input,
RESET input,
RESET input,
RESET input,
interrupt request STOPC input in INT0 or timer A STOP/SBY
stop mode
interrupt request instruction
Note: OP implies in operation
1. Operating or stopping the oscillator can be selected by setting bit 3 of the system clock select
register (SSR: $029).
2. Subactive mode is an optional function; specify it on the function option list.
27
HD404449 Series
Table 20
Operations in Low-Power Dissipation Modes
Function
Stop Mode
Watch Mode
Standby Mode
Subactive Mode*2
CPU
Reset
Retained
Retained
OP
RAM
Retained
Retained
Retained
OP
Timer A
Reset
OP
OP
OP
Timer B
Reset
Stopped
OP
OP
Timer C
Reset
Stopped
OP
OP
Timer D
Reset
Stopped
OP
OP
OP
OP
Stopped
OP
Stopped
Retained
Retained
OP
Serial 1, 2
Reset
A/D
Reset
I/O
Reset*
Stopped*
1
3
Note: OP implies in operation
1. Output pins are at high impedance.
2. Subactive mode is an optional function specified on the function option list.
3. Transmission/reception is activated if a clock is input in external clock mode. However, all
interrupts stop.
Table 21
I/O Status in Low-Power Dissipation Modes
Output
Input
Standby mode,
watch mode
Stop mode
Active mode,
subactive mode
D0–D 11
Retained
High impedance
Input enabled
D12–D 13
—
—
Input enabled
R0–RC
Retained or output of
peripheral functions
High impedance
Input enabled
28
HD404449 Series
Reset by
RESET input or
by watchdog timer
Stop mode
(TMA3 = 0, SSR3 = 0)
RAME = 0
RAME = 1
RESET1
RESET2
STOPC
STOPC
STOP
Oscillate
Oscillate
Stop
fcyc
fcyc
Stop
Oscillate
Stop
Stop
Stop
Active
mode
Standby mode
fOSC:
fX:
ø CPU:
ø CLK:
ø PER:
fOSC:
fX:
ø CPU:
ø CLK:
ø PER:
SBY
Interrupt
fOSC:
fX:
ø CPU:
ø CLK:
ø PER:
Oscillate
Oscillate
fcyc
fcyc
fcyc
(TMA3 = 0, SSR3 = 1)
STOP
fOSC:
fX:
ø CPU:
ø CLK:
ø PER:
Stop
Stop
Stop
Stop
Stop
(TMA3 = 0)
Watch mode
(TMA3 = 1)
fOSC:
fX:
ø CPU:
ø CLK:
ø PER:
Oscillate
Oscillate
Stop
fW
fcyc
SBY
Interrupt
fOSC:
fX:
ø CPU:
ø CLK:
ø PER:
Oscillate
Oscillate
fcyc
fW
fcyc
(TMA3 = 1, LSON = 0)
STOP
INT0,
timer A*1
fOSC:
fX:
ø CPU:
ø CLK:
ø PER:
Stop
Oscillate
Stop
fW
Stop
*3
fOSC:
fX:
Main oscillation frequency
Suboscillation frequency
for time-base
fOSC/4
fcyc:
fSUB:
fX/8 or fX/4
(software selectable)
fW:
fX/8
ø CPU: System clock
ø CLK: Clock for time-base
ø PER: Clock for other
peripheral functions
LSON: Low speed on flag
DTON: Direct transfer on flag
*2
Subactive
mode
fOSC:
fX:
ø CPU:
ø CLK:
ø PER:
STOP
Stop
Oscillate
fSUB
fW
fSUB
Notes: 1.
2.
3.
4.
*4
INT0,
timer A*1
(TMA3 = 1, LSON = 1)
fOSC:
fX:
ø CPU:
ø CLK:
ø PER:
Stop
Oscillate
Stop
fW
Stop
Interrupt source
STOP/SBY (DTON = 1, LSON = 0)
STOP/SBY (DTON = 0, LSON = 0)
STOP/SBY (DTON = Don’t care, LSON = 1)
Figure 14 MCU Status Transitions
29
HD404449 Series
Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction
execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the
D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and
serial interface continue to operate. The power dissipation in this mode is lower than in active mode
because the CPU stops.
The MCU enters standby mode when the SBY instruction is executed in active mode.
Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input,
the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next
instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is
0, the interrupt request is left pending and normal instruction execution continues. A flowchart of
operation in standby mode is shown in figure 15.
Stop
Standby
Watch
Oscillator: Stop
Suboscillator: Active/Stop
Peripheral clocks: Stop
All other clocks: Stop
Oscillator: Active
Peripheral clocks: Active
All other clocks: Stop
Oscillator: Stop
Suboscillator: Active
Peripheral clocks: Stop
All other clocks: Stop
No
RESET = 1?
Yes
RESET = 1?
No
Yes
IF0 • IM0 = 1?
No
No
STOPC = 0?
Yes
IF1 • IM1 = 1?
No
Yes
Yes
IFTA • IMTA
= 1?
Yes
RAME = 1
No
IFTB •
IMTB + IF2 •
IM2 = 1?
RAME = 0
Yes
No
IFTC •
IMTC + IF3 •
IM3 = 1?
Yes
No
IFTD •
IMTD + IFAD •
IMAD = 1?
Yes
(SBY
only)
(SBY
only)
Restart
processor clocks
(SBY
only)
(SBY
only)
Restart
processor clocks
Execute
next instruction
No
Reset MCU
IF = 1,
IM = 0, and
IE = 1?
Yes
Execute
next instruction
Figure 15 MCU Operation Flowchart
30
Accept interrupt
No
IFS1•
IMS1 + IFS2 •
IMS2 = 1?
(SBY
only)
Yes
No
,
HD404449 Series
Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power
dissipation in this mode is the least of all modes. The OSC1 and OSC2 oscillator stops. Operation of the
X1 and X2 oscillator can be selected by setting bit 3 of the system clock select register (SSR: $029;
operating: SSR3 = 0, stop: SSR3 = 1) (figure 26). The MCU enters stop mode if the STOP instruction is
executed in active mode when bit 3 of timer mode register A (TMA: $008) is set to 0 (TMA3 = 0) (figure
41).
Stop mode is terminated by a RESET input or a STOPC input as shown in figure 16. RESET or STOPC
must be applied for at least one t RC to stabilize oscillation (refer to the AC Characteristics section). When
the MCU restarts after stop mode is cancelled, all RAM contents before entering stop mode are retained,
but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register,
carry flag, and serial data register cannot be guaranteed.
Stop mode
Oscillator
Internal
clock
RESET
STOPC
tres
STOP instruction execution
tres ≥ tRC (stabilization period)
Figure 16 Timing of Stop Mode Cancellation
Watch Mode: In watch mode, the clock function (timer A) using the X1 and X2 oscillator operates but
other function operations stop. Therefore, the power dissipation in this mode is the second least to stop
mode, and this mode is convenient when only clock display is used. In this mode, the OSC 1 and OSC2
oscillator stops, but the X1 and X2 oscillator operates. The MCU enters watch mode if the STOP
instruction is executed in active mode when TMA3 = 1, or if the STOP or SBY instruction is executed in
subactive mode.
Watch mode is terminated by a RESET input or a timer-A/INT0 interrupt request. For details of RESET
input, refer to the Stop Mode section. When terminated by a timer-A/INT0 interrupt request, the MCU
enters active mode if LSON is 0, or subactive mode if LSON is 1. After an interrupt request is generated,
the time required to enter active mode is tRC for a timer A interrupt, and TX (where T + tRC < TX < 2T + tRC)
for an INT0 interrupt, as shown in figure 17.
Operation during mode transition is the same as that at standby mode cancellation (figure 15).
31
HD404449 Series
Oscillation
stabilization period
Active mode
Watch mode
Active mode
Interrupt strobe
INT0
Interrupt request
generation
T
(During the transition
from watch mode to
active mode only)
T
t RC
Tx
Interrupt frame length
T:
t RC : Oscillation stabilization period
Figure 17 Interrupt Frame
Subactive Mode: The OSC1 and OSC2 oscillator stops and the MCU operates with a clock generated by
the X1 and X2 oscillator. In this mode, functions other than A/D conversion operate. However, because
the operating clock is slow, the power dissipation becomes low, next to watch mode.
The CPU instruction execution speed can be selected as 244 µs or 122 µs by setting bit 2 (SSR2) of the
system clock select register (SSR: $029). Note that the SSR2 value must be changed in active mode. If the
value is changed in subactive mode, the MCU may malfunction.
When the STOP or SBY instruction is executed in subactive mode, the MCU enters either watch or active
mode, depending on the statuses of the low speed on flag (LSON: $020, bit 0) and the direct transfer on
flag (DTON: $020, bit 3).
Subactive mode is an optional function that the user must specify on the function option list.
Interrupt Frame: In watch and subactive modes, øCLK is applied to timer A and the INT0 circuit. Prescaler
W and timer A operate as the time-base and generate the timing clock for the interrupt frame. Three
interrupt frame lengths (T) can be selected by setting the miscellaneous register (MIS: $00C) (figure 18).
In watch and subactive modes, the timer-A/INT0 interrupt is generated synchronously with the interrupt
frame. The interrupt request is generated synchronously with the interrupt strobe timing except during
transition to active mode. The falling edge of the INT0 signal is input asynchronously with the interrupt
frame timing, but it is regarded as input synchronously with the second interrupt strobe clock after the
falling edge. An overflow and interrupt request in timer A is generated synchronously with the interrupt
strobe timing.
32
HD404449 Series
Miscellaneous register (MIS: $00C)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
MIS3
MIS2
MIS1
MIS0
Bit name
MIS3
MIS2
Buffer control.
Refer to figure 38.
MIS1
MIS0
0
0
T*1
tRC*1
0.24414 ms 0.12207 ms
Oscillation circuit conditions
External clock input
0.24414 ms*2
0
1
15.625 ms
1
0
125 ms
1
1
Not used
7.8125 ms
Ceramic oscillator or crystal
62.5 ms
—
Notes: 1. The values of T and tRC are applied when a 32.768-kHz crystal oscillator is used.
2. The value is applied only when direct transfer operation is used.
Figure 18 Miscellaneous Register (MIS)
Direct Transition from Subactive Mode to Active Mode: Available by controlling the direct transfer on
flag (DTON: $020, bit 3) and the low speed on flag (LSON: $020, bit 0). The procedures are described
below:
• Set LSON to 0 and DTON to 1 in subactive mode.
• Execute the STOP or SBY instruction.
• The MCU automatically enters active mode from subactive mode after waiting for the MCU internal
processing time and oscillation stabilization time (Figure 19).
Notes: 1. The DTON flag ($020, bit 3) can be set only in subactive mode. It is always reset in active
mode.
2. The transition time (TD) from subactive mode to active mode:
tRC < TD < T + tRC
33
HD404449 Series
STOP/SBY instruction execution
Subactive mode
MCU internal
processing period
Oscillation
stabilization
time
Active mode
(Set LSON = 0, DTON = 1)
Interrupt strobe
Direct transfer
completion timing
T
t RC
Interrupt frame length
T:
t RC : Oscillation stabilization period
Figure 19 Direct Transition Timing
Stop Mode Cancellation by STOPC : The MCU enters active mode from stop mode by a STOPC input
as well as by RESET. In either case, the MCU starts instruction execution from the starting address
(address 0) of the program. However, the value of the RAM enable flag (RAME: $021, bit 3) differs
between cancellation by STOPC and by RESET. When stop mode is cancelled by RESET, RAME = 0;
when cancelled by STOPC, RAME = 1. RESET can cancel all modes, but STOPC is valid only in stop
mode; STOPC input is ignored in other modes. Therefore, when the program requires to confirm that stop
mode has been cancelled by STOPC (for example, when the RAM contents before entering stop mode are
used after transition to active mode), execute the TEST instruction on the RAM enable flag (RAME) at the
beginning of the program.
MCU Operation Sequence: The MCU operates in the sequences shown in figures 20 to 22. It is reset by
an asynchronous RESET input, regardless of its status.
The low-power mode operation sequence is shown in figure 22. With the IE flag cleared and an interrupt
flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is
cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY
instruction, make sure all interrupt flags are cleared or all interrupts are masked.
34
HD404449 Series
Power on
RESET = 1 ?
No
Yes
RAME = 0
MCU
operation
cycle
Reset MCU
Figure 20 MCU Operating Sequence (Power On)
35
HD404449 Series
MCU operation
cycle
IF = 1?
No
Instruction
execution
Yes
SBY/STOP
instruction?
Yes
No
IM = 0 and
IE = 1?
Yes
IE ← 0
Stack ← (PC),
(CA),
(ST)
No
Low-power mode
operation cycle
IF:
IM:
IE:
PC:
CA:
ST:
PC ← Next
location
PC ← Vector
address
Interrupt request flag
Interrupt mask
Interrupt enable flag
Program counter
Carry flag
Status flag
Figure 21 MCU Operating Sequence (MCU Operation Cycle)
36
HD404449 Series
Low-power mode
operation cycle
IF = 1 and
IM = 0?
No
Yes
Standby/Watch
mode
Stop mode
*
No
IF = 1 and
IM = 0?
Yes
No
STOPC = 0?
Yes
Hardware NOP
execution
Hardware NOP
execution
RAME = 1
PC ← Next
Iocation
PC ← Next
Iocation
Reset MCU
Instruction
execution
MCU operation
cycle
Note: * For IF and IM operation, refer to figure 15.
Figure 22 MCU Operating Sequence (Low-Power Mode Operation)
Note: When the MCU is in watch mode or subactive mode, if the high level period before the falling edge
of INT0 is shorter than the interrupt frame, INT0 is not detected. Also, if the low level period after
the falling edge of INT 0 is shorter than the interrupt frame, INT 0 is not detected.
Edge detection is shown in figure 23. The level of the INT0 signal is sampled by a sampling clock.
When this sampled value changes to low from high, a falling edge is detected.
In figure 24, the level of the INT0 signal is sampled by an interrupt frame. In (a) the sampled value
is low at point A, and also low at point B. Therefore, a falling edge is not detected. In (b), the
sampled value is high at point A, and also high at point B. A falling edge is not detected in this
case either.
37
HD404449 Series
When the MCU is in watch mode or subactive mode, keep the high level and low level period of
INT 0 longer than interrupt frame.
INT0
Sampling
High
Low
Low
Figure 23 Edge Detection
INT0
INT0
Interrupt
frame
Interrupt
frame
A: Low
B: Low
(a) High level period
Figure 24 Sampling Example
38
A: High
B: High
(b) Low level period
HD404449 Series
Internal Oscillator Circuit
A block diagram of the clock generation circuit is shown in figure 25. As shown in table 22, a ceramic
oscillator or crystal oscillator can be connected to OSC1 and OSC2, and a 32.768-kHz oscillator can be
connected to X1 and X2. The system oscillator can also be operated by an external clock. Bit 1 (SSR1) of
the system clock select register (SSR: $029) must be selected according to the frequency of the oscillator
connected to OSC1 and OSC2 (figure 26).
Note: If the system clock select register (SSR: $029) setting does not match the oscillator frequency,
subsystems using the 32.768-kHz oscillation will malfunction.
LSON
OSC2
1/4
System fOSC
division
oscillator
circuit
fcyc
tcyc
Timing
generator
circuit
OSC1
fX
X1
Subsystem
oscillator
øCPU
CPU with ROM,
RAM, registers,
flags, and I/O
øPER
Peripheral
function
interrupt
System
clock
selection
fSUB
1/8 or 1/4
Timing
division tsubcyc generator
circuitNote
circuit
TMA3
X2
1/8
division
circuit
fW
tWcyc
Timing
generator
circuit
Time-base
clock øCLK
selection
Time-base
interrupt
Note: 1/8 or 1/4 division ratio can be selected by setting bit 2 of the system
clock select register (SSR: $029).
Figure 25 Clock Generation Circuit
39
HD404449 Series
System clock select register (SSR: $029)
Bit
3
2
1
0
Initial value
0
0
0
—
Read/Write
W
W
W
—
SSR3
SSR2
SSR1
Not used
Bit name
SSR2
32-kHz oscillation division
ratio selection
0
fSUB = fX/8
1
fSUB = fX/4
SSR3
SSR1
System clock selection
0
0.4 to 1.0 MHz
1
1.6 to 4.0 MHz
32-kHz oscillation stop
0
Oscillation operates in stop mode
1
Oscillation stops in stop mode
Figure 26 System Clock Select Register
D0
GND
X2
X1
RESET
OSC2
OSC1
TEST
AVSS
GND
Figure 27 Typical Layouts of Crystal and Ceramic Oscillator
40
HD404449 Series
Table 22
Oscillator Circuit Examples
Circuit Configuration
External clock
operation
Circuit Constants
External
oscillator
OSC 1
Open
OSC 2
Ceramic oscillator
(OSC1, OSC 2)
Ceramic oscillator: CSA4.00MG (Murata)
C1
Rf = 1 MΩ ± 20%
OSC1
Ceramic
oscillator
C1 = C2 = 30 pF ± 20%
Rf
OSC2
C2
GND
Rf = 1 MΩ ± 20%
C1
Crystal oscillator
(OSC1, OSC 2)
C1 = C2 = 10–22 pF ± 20%
OSC1
Crystal
oscillator
Crystal: Equivalent to circuit shown below
Rf
C0 = 7 pF max
OSC2
RS = 100 Ω max
C2
GND
L
CS RS
OSC1
OSC2
C0
C1
Crystal oscillator
(X1, X2)
Ceramic: 32.768 kHz: MX38T
X1
(Nippon Denpa Kogyo)
Crystal
oscillator
C1 = C2 = 20 pF ± 20%
RS: 14 kΩ
X2
C0: 1.5 pF
C2
GND
L
CS RS
X1
X2
C0
Notes: 1. Since the circuit constants change depending on the crystal or ceramic resonator and stray
capacitance of the board, the user should consult with the crystal or ceramic oscillator
manufacturer to determine the circuit parameters.
2. Wiring among OSC1, OSC 2, X1, X2, and elements should be as short as possible, and must not
cross other wiring (see figure 27).
3. If the 32.768-kHz crystal oscillator is not used, the X1 pin must be fixed to GND and X2 must be
open.
41
HD404449 Series
Input/Output
The MCU has 64 input/output pins (D 0–D 11, R00–RC 3) and 2 input pins (D12, D13). The features are
described below.
• 10 pins (D0–D9) are high-current input/output pins.
• The D12, D13, R00–R0 2, and R3 0–R5 3 input/output pins are multiplexed with peripheral function pins
such as for the timers or serial interface. For these pins, the peripheral function setting is done prior to
the D or R port setting. Therefore, when a peripheral function is selected for a pin, the pin function and
input/output selection are automatically switched according to the setting.
• Input or output selection for input/output pins and port or peripheral function selection for multiplexed
pins are set by software.
• Peripheral function output pins are CMOS output pins. Only the R43/SO1 and R5 3/SO 2 pins can be set to
NMOS open-drain output by software.
• In stop mode, the MCU is reset, and therefore peripheral function selection is cancelled. Input/output
pins are in high-impedance state.
• Each input/output pin has a built-in pull-up MOS, which can be individually turned on or off by
software.
I/O buffer configuration is shown in figure 28, programmable I/O circuits are listed in table 23, and I/O pin
circuit types are shown in table 24.
Table 23
Programmable I/O Circuits
MIS3 (Bit 3 of MIS)
0
DCD, DCR
0
PDR
0
1
0
1
0
1
0
1
PMOS
—
—
—
On
—
—
—
On
NMOS
—
—
On
—
—
—
On
—
—
—
—
—
—
On
—
On
CMOS buffer
Pull-up MOS
Note: — indicates off status.
42
1
1
0
1
HD404449 Series
HLT
Pull-up control signal
VCC
Pull-up
MOS
MIS3
VCC
Buffer control signal
DCD, DCR
Output data
PDR
Input data
Input control signal
Figure 28 I/O Buffer Configuration
43
HD404449 Series
Table 24
Circuit Configurations of I/O Pins
I/O Pin Type
Circuit
Input/output pins
Pins
VCC
VCC
Pull-up control signal
Buffer control
signal
HLT
D0–D 11 , R0 0–R0 3
MIS3
R1 0–R1 3, R20–R2 3
DCD, DCR
R5 0–R5 2, R60–R6 3
Output data
PDR
RB 0–RB 3, RC0–RC3
Input control signal
HLT
VCC
R7 0–R7 3, R80–R8 3
R9 0–R9 3, RA0–RA 3
Input data
VCC
R3 0–R3 3, R40–R4 2
Pull-up control signal
Buffer control
signal
R4 3, R53
MIS3
DCR
MIS2, SM2B2
PDR
Output data
Input data
Input control signal
Input data
Input pins
D12, D13
Input control signal
Peripheral
Input/ output
function pins pins
VCC
HLT
VCC
Pull-up control signal
MIS3
Output data
Input data
Output pins
VCC
SCK 1 , SCK 2
SCK 1 , SCK 2
HLT
VCC
Pull-up control signal
Output data
VCC
Output data
44
MIS2, SM2B2
SO 1 , SO 2
HLT
Pull-up control signal
SO1, SO2
MIS3
PMOS control
signal
VCC
SCK 1, SCK 2
MIS3
TOB, TOC, TOD
TOB, TOC, TOD
HD404449 Series
I/O Pin Type
Circuit
Input pins
Pins
SI 1, SI 2, INT1,
VCC
HLT
MIS3
PDR
Input data
Input data
INT2, INT3,
EVNB, EVND
SI1, SI2,, INT1, etc
INT0 , STOPC
INT0, STOPC
Notes: 1. The MCU is reset in stop mode, and peripheral function selection is cancelled. The HLT signal
becomes low, and input/output pins enter high-impedance state.
2. The HLT signal is 1 in watch and subactive modes.
D Port (D 0–D13): Consist of 12 input/output pins and 2 input pins addressed by one bit. D0–D11 are highcurrent I/O pins, and D12 and D13 are input-only pins.
Pins D0–D 11 are set by the SED and SEDD instructions, and reset by the RED and REDD instructions.
Output data is stored in the port data register (PDR) for each pin. All pins D0–D13 are tested by the TD and
TDD instructions.
The on/off statuses of the output buffers are controlled by D-port data control registers (DCD0–DCD2:
$02C–$02E) that are mapped to memory addresses (figure 29).
Pins D 12 and D13 are multiplexed with peripheral function pins STOPC and INT0, respectively. The
peripheral function modes of these pins are selected by bits 2 and 3 (PMRC2, PMRC3) of port mode
register C (PMRC: $025) (figure 30).
R Ports (R0 0–RC3): 52 input/output pins addressed in 4-bit units. Data is input to these ports by the LAR
and LBR instructions, and output from them by the LRA and LRB instructions. Output data is stored in the
port data register (PDR) for each pin. The on/off statuses of the output buffers of the R ports are controlled
by R-port data control registers (DCR0–DCRC: $030–$03C) that are mapped to memory addresses (figure
29).
Pins R00–R02 are multiplexed with peripheral pins INT1–INT 3, respectively. The peripheral function modes
of these pins are selected by bits 0–2 (PMRB0–PMRB2) of port mode register B (PMRB: $024) (figure
31).
Pins R30–R32 are multiplexed with peripheral pins TOB, TOC, and TOD, respectively. The peripheral
function modes of these pins are selected by bits 0 and 1 (TMB20, TMB21) of timer mode register B2
(TMB2: $013), bits 0–2 (TMC20–TMC22) of timer mode register C2 (TMC2: $014), and bits 0–3
(TMD20–TMD23) of timer mode register D2 (TMD2: $015) (figures 32, 33, and 34).
Pins R33 and R40 are multiplexed with peripheral pins EVNB and EVND, respectively. The peripheral
function modes of these pins are selected by bits 0 and 1 (PMRC0, PMRC1) of port mode register C
(PMRC: $025) (figure 30).
Pins R41–R43 are multiplexed with peripheral pins SCK 1, SI1, and SO1, respectively. The peripheral
function modes of these pins are selected by bit 3 (SM1A3) of serial mode register 1A (SM1A: $005), and
bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004), as shown in figures 35 and 36.
45
HD404449 Series
Ports R51–R5 3 are multiplexed with peripheral function pins SCK 2, SI2, SO2, respectively. The function
modes of these pins can be selected by individual pins, by 2A setting bit 3 (SM2A3) of serial mode register
2A (SM2A: $01B), and bits 2 and 3 (PMRA2, PMRA3) of port mode register A (PMRA: $004) (figures 36
and 37).
Pull-Up MOS Transistor Control: A program-controlled pull-up MOS transistor is provided for each
input/output pin other than input-only pins D 12 and D13 . The on/off status of all these transistors is
controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off status of an individual
transistor can also be controlled by the port data register (PDR) of the corresponding pin—enabling on/off
control of that pin alone (table 23 and figure 38).
The on/off status of each transistor and the peripheral function mode of each pin can be set independently.
How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be
connected to V CC to prevent LSI malfunctions due to noise. These pins must either be pulled up to VCC by
their pull-up MOS transistors or by resistors of about 100 kΩ.
46
HD404449 Series
Data control register
(DCD0 to 2: $02C to $02E)
(DCR0 to C: $030 to $03C)
DCD0, DCD1
Bit
3
2
1
0
Initial value
0
0
0
0
W
W
W
W
Read/Write
Bit name
DCD03, DCD02, DCD01, DCD00,
DCD13 DCD12 DCD11 DCD10
DCD2
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
Bit name
W
W
W
W
DCD23
DCD22
DCD21
DCD20
3
2
1
0
DCR0 to DCRC
Bit
Initial value
0
0
0
0
Read/Write
W
W
W
W
Bit name
DCR03– DCR02– DCR01– DCR00–
DCRC3 DCRC2 DCRC1 DCRC0
All Bits
CMOS Buffer On/Off Selection
0
Off (high-impedance)
1
On
Correspondence between ports and DCD/DCR bits
Register Name
Bit 3
Bit 2
Bit 1
Bit 0
DCD0
D3
D2
D1
D0
DCD1
D7
D6
D5
D4
DCD2
D11
D10
D9
D8
DCR0
R03
R02
R01
R00
DCR1
R13
R12
R11
R10
DCR2
R23
R22
R21
R20
DCR3
R33
R32
R31
R30
DCR4
R43
R42
R41
R40
DCR5
R53
R52
R51
R50
DCR6
R63
R62
R61
R60
DCR7
R73
R72
R71
R70
DCR8
R83
R82
R81
R80
DCR9
R93
R92
R91
R90
DCRA
RA3
RA2
RA1
RA0
DCRB
RB3
RB2
RB1
RB0
DCRC
RC3
RC2
RC1
RC0
Figure 29 Data Control Registers (DCD, DCR)
47
HD404449 Series
Port mode register C (PMRC: $025)
Bit
3
2
1
0
Initial value
0
0
0
0
W
W
Read/Write
Bit name
W
PMRC3
PMRC2* PMRC1
W
PMRC0
PMRC0
R33/EVNB mode selection
0
R33
1
EVNB
PMRC1
R40/EVND mode selection
0
R40
1
EVND
PMRC2
D12/STOPC mode selection
0
D12
1
STOPC
PMRC3
D13/INT0 mode selection
0
D13
1
INT0
Note: *PMRC2 is reset to 0 only by RESET input. When STOPC is input in stop
mode, PMRC2 is not reset but retains its value.
Figure 30 Port Mode Register C (PMRC )
48
HD404449 Series
Port mode register B (PMRB: $024)
Bit
3
2
1
0
Initial value
—
0
0
0
—
W
W
W
Read/Write
Bit name
Not used PMRB2 PMRB1 PMRB0
PMRB0
R00/INT1 mode selection
0
R00
1
INT1
PMRB1
R01/INT2 mode selection
0
R01
1
INT2
PMRB2
R02/INT3 mode selection
0
R02
1
INT3
Figure 31 Port Mode Register B (PMRB)
Timer mode register B2 (TMB2: $013)
Bit
3
2
1
0
Initial value
—
—
0
0
Read/Write
—
—
R/W
R/W
Bit name
Not used Not used TMB21
TMB20
R30/TOB mode selection
TMB21
TMB20
0
0
R30
R30 port
1
TOB
Toggle output
0
TOB
0 output
1
TOB
1 output
1
Figure 32 Timer Mode Register B2 (TMB2)
49
HD404449 Series
Timer mode register C2 (TMC2: $014)
Bit
3
2
1
0
Initial value
—
0
0
0
Read/Write
—
R/W
R/W
R/W
TMC21
TMC20
Bit name
Not used TMC22
TMC22
TMC21
TMC20
0
0
0
R31
R31 port
1
TOC
Toggle output
0
TOC
0 output
1
TOC
1 output
0
—
Inhibited
TOC
PWM output
1
1
0
R31/TOC mode selection
1
1
0
1
Figure 33 Timer Mode Register C2 (TMC2)
50
HD404449 Series
Timer mode register D2 (TMD2: $015)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
TMD23
TMD22
TMD21
TMD20
Bit name
R32/TOD mode selection
TMD23
TMD22
TMD21
TMD20
0
0
0
0
R32
R32 port
1
TOD
Toggle output
0
TOD
0 output
1
TOD
1 output
0
—
Inhibited
1
1
0
1
1
0
1
1
Don't care Don't care Don't care
TOD
PWM output
R32
Input capture (R32 port)
Figure 34 Timer Mode Register D2 (TMD2)
51
HD404449 Series
Serial mode register 1A (SM1A: $005)
Bit
3
2
0
1
Initial value
0
0
0
0
Read/Write
W
W
W
W
SM1A3
SM1A2
SM1A1
SM1A0
Bit name
SM1A3
R41/SCK1
mode selection
0
R41
1
SCK1
SM1A2
SM1A1
SM1A0
SCK1
Clock source
Prescaler
division
ratio
0
0
0
Output
Prescaler
÷2048
1
Output
Prescaler
÷512
0
Output
Prescaler
÷128
1
Output
Prescaler
÷32
0
Output
Prescaler
÷8
1
Output
Prescaler
÷2
0
Output
System clock
—
1
Input
External clock
—
1
1
0
1
Figure 35 Serial Mode Register 1A (SM1A)
52
HD404449 Series
Port mode register A (PMRA: $004)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
Bit name
PMRA3
PMRA2 PMRA1 PMRA0
PMRA0
R43/SO1 mode selection
0
R43
1
SO1
PMRA1
R42/SI1 mode selection
0
R42
1
SI1
PMRA2
R53/SO2 mode selection
0
R53
1
SO2
PMRA3
R52/SI2 mode selection
0
R52
1
SI2
Figure 36 Port Mode Register A (PMRA)
53
HD404449 Series
Serial mode register 2A (SM2A: $01B)
Bit
3
2
0
1
Initial value
0
0
0
0
Read/Write
W
W
W
W
SM2A3
SM2A2
SM2A1
SM2A0
Bit name
SM2A3
R51/SCK2
mode selection
0
R51
1
SCK2
SM2A2
SM2A1
SM2A0
SCK2
Clock source
Prescaler
division
ratio
0
0
0
Output
Prescaler
÷2048
1
Output
Prescaler
÷512
0
Output
Prescaler
÷128
1
Output
Prescaler
÷32
0
Output
Prescaler
÷8
1
Output
Prescaler
÷2
0
Output
System clock
—
1
Input
External clock
—
1
1
0
1
Figure 37 Serial Mode Register 2A (SM2A)
Miscellaneous register (MIS: $00C)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
MIS3
MIS2
MIS1
MIS0
MIS2
CMOS buffer
on/off selection
for pin R43/SO1
Bit name
MIS3
Pull-up MOS
on/off selection
0
Off
0
On
1
On
1
Off
MIS1
tRC selection.
Refer to figure 18 in the
operation modes section.
Figure 38 Miscellaneous Register (MIS)
54
MIS0
HD404449 Series
Prescalers
The MCU has the following two prescalers, S and W.
The prescaler operating conditions are listed in table 25, and the prescaler output supply is shown in figure
39. The timer A–D input clocks except external events and the serial transmit clock except the external
clock are selected from the prescaler outputs, depending on corresponding mode registers.
Prescaler Operation
Prescaler S: 11-bit counter that inputs a system clock signal. After being reset to $000 by MCU reset,
prescaler S divides the system clock. Prescaler S keeps counting, except in stop, watch, and subactive
modes and at MCU reset.
Prescaler W: Five-bit counter that inputs the X1 input clock signal (32-kHz crystal oscillation) divided by
eight. After being reset to $00 by MCU reset, prescaler W divides the input clock. Prescaler W can be
reset by software.
Table 25
Prescaler Operating Conditions
Prescaler
Input Clock
Reset Conditions
Stop Conditions
Prescaler S
System clock (in active
and standby mode),
Subsystem clock (in
subactive mode)
MCU reset
MCU reset, stop mode,
watch mode
Prescaler W
32-kHz crystal oscillation
Software
MCU reset, stop mode
Subsystem
clock
fX /8
Prescaler W
fX /4 or fX /8
Timer A
Timer B
Timer C
System
clock
Clock
selector
Prescaler S
Timer D
Serial 1
Serial 2
Figure 39 Prescaler Output Supply
55
HD404449 Series
Timers
The MCU has four timer/counters (A to D).
•
•
•
•
Timer A:
Timer B:
Timer C:
Timer D:
Free-running timer
Multifunction timer
Multifunction timer
Multifunction timer
Timer A is an 8-bit free-running timer. Timers B–D are 8-bit multifunction timers, whose functions are
listed in table 26. The operating modes are selected by software.
Table 26
Timer Functions
Functions
Clock source
Timer functions
Timer outputs
Timer A
Timer B
Timer C
Timer D
Prescaler S
Available
Available
Available
Available
Prescaler W
Available
—
—
—
External event
—
Available
—
Available
Free-running
Available
Available
Available
Available
Time-base
Available
—
—
—
Event counter
—
Available
—
Available
Reload
—
Available
Available
Available
Watchdog
—
—
Available
—
Input capture
—
—
—
Available
Toggle
—
Available
Available
Available
0 output
—
Available
Available
Available
1 output
—
Available
Available
Available
PWM
—
—
Available
Available
Note: — means not available.
56
HD404449 Series
Timer A
Timer A Functions: Timer A has the following functions.
• Free-running timer
• Clock time-base
The block diagram of timer A is shown in figure 40.
1/4
fW
1/2
twcyc
2 fW
Timer A interrupt
request flag
(IFTA)
Prescaler W
(PSW)
÷2
÷8
÷ 16
÷ 32
32.768-kHz
oscillator
1/2 twcyc
Clock
Timer
counter A
(TCA) Overflow
System
clock
ø PER
÷2
÷4
÷8
÷ 32
÷ 128
÷ 512
÷ 1024
÷ 2048
Selector
Internal data bus
Selector
Selector
Prescaler S (PSS)
3
Timer mode
register A
(TMA)
Figure 40 Timer A Block Diagram
Timer A Operations:
• Free-running timer operation: The input clock for timer A is selected by timer mode register A (TMA:
$008).
Timer A is reset to $00 by MCU reset and incremented at each input clock. If an input clock is applied
to timer A after it has reached $FF, an overflow is generated, and timer A is reset to $00. The overflow
sets the timer A interrupt request flag (IFTA: $001, bit 2). Timer A continues to be incremented after
reset to $00, and therefore it generates regular interrupts every 256 clocks.
• Clock time-base operation: Timer A is used as a clock time-base by setting bit 3 (TMA3) of timer
mode register A (TMA: $008) to 1. The prescaler W output is applied to timer A, and timer A
generates interrupts at the correct timing based on the 32.768-kHz crystal oscillation. In this case,
prescaler W and timer A can be reset to $00 by software.
57
HD404449 Series
Registers for Timer A Operation: Timer A operating modes are set by the following registers.
• Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A’s operating mode
and input clock source as shown in figure 41.
Timer mode register A (TMA: $008)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
Bit name
W
W
W
W
TMA3
TMA2
TMA1
TMA0
Source
Input clock
TMA3 TMA2 TMA1 TMA0 prescaler frequency Operating mode
0
0
0
1
1
0
1
1
0
0
1
1
0
1
0
PSS
2048tcyc
1
PSS
1024tcyc
0
PSS
512tcyc
1
PSS
128tcyc
0
PSS
32tcyc
1
PSS
8tcyc
0
PSS
4tcyc
1
PSS
2tcyc
0
PSW
32tWcyc
1
PSW
16tWcyc
0
PSW
8tWcyc
1
PSW
2tWcyc
0
PSW
1/2tWcyc
1
Inhibited
Don't
care
Timer A mode
Time-base
mode
PSW and TCA reset
Notes: 1. tWcyc = 244.14 µs (when a 32.768-kHz crystal oscillator is used)
2. Timer counter overflow output period (seconds) = input clock period (seconds) × 256.
3. The division ratio must not be modified during time-base mode operation, otherwise
an overflow cycle error will occur.
Figure 41 Timer Mode Register A (TMA)
58
HD404449 Series
Timer B
Timer B Functions: Timer B has the following functions.
• Free-running/reload timer
• External event counter
• Timer output operation (toggle, 0, and 1 outputs)
The block diagram of timer B is shown in figure 42.
Timer B interrupt
request flag
(IFTB)
Timer output
control logic
TOB
Timer read register BU (TRBU)
Timer output control
Timer read
register BL
(TRBL)
Clock
System
clock
ø PER
÷ 2048
EVNB
÷2
÷4
÷8
÷ 32
÷ 128
÷ 512
Selector
Timer write
register BU
(TWBU)
Prescaler S (PSS)
Free-running/
Reload control
Timer write
register BL
(TWBL)
Internal data bus
Timer counter B
(TCB)
Overflow
3
Timer mode
register B1
(TMB1)
2
Timer mode
register B2
(TMB2)
Figure 42 Timer B Block Diagram
59
HD404449 Series
Timer B Operations:
• Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register B1 (TMB1: $009).
Timer B is initialized to the value set in timer write register B (TWBL: $00A, TWBU: $00B) by
software and incremented by one at each clock input. If an input clock is applied to timer B after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer B is
initialized to its initial value set in timer write register B; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.
The overflow sets the timer B interrupt request flag (IFTB: $002, bit 0). IFTB is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.
• External event counter operation: Timer B is used as an external event counter by selecting external
event input as the input clock source. In this case, pin R33/EVNB must be set to EVNB by port mode
register C (PMRC: $025).
Timer B is incremented by one at each falling edge of signals input to pin EVNB. Other operations are
basically the same as the free-running/ reload timer operation.
• Timer output operation: The following three output modes can be selected for timer B by setting timer
mode register B2 (TMB2: $013).
 Toggle
 0 output
 1 output
By selecting the timer output mode, pin R30/TOB is set to TOB. The output from TOB is reset low by
MCU reset.
 Toggle output: When toggle output mode is selected, the output level is inverted if a clock is input
after timer B has reached $FF. By using this function and reload timer function, clock signals can
be output at a required frequency for the buzzer. The output waveform is shown in figure 43.
 0 output: When 0 output mode is selected, the output level is pulled low if a clock is input after
timer B has reached $FF. Note that this function must be used only when the output level is high.
 1 output: When 1 output mode is selected, the output level is set high if a clock is input after timer
B has reached $FF. Note that this function must be used only when the output level is low.
60
HD404449 Series
Toggle output waveform (timers B, C, and D)
Free-running timer
256 clock cycles
256 clock cycles
Reload timer
(256 – N) clock cycles (256 – N) clock cycles
PWM output waveform (timers C and D)
T × (N + 1)
TMC13 = 0
TMD13 = 0
T
T × 256
TMC13 = 1
TMD13 = 1
T × (256 – N)
Note: The waveform is always fixed low when N = $FF.
T: Input clock period to counter (figures 52 and 59)
N: The value of the timer write register
Figure 43 Timer Output Waveform
Registers for Timer B Operation: By using the following registers, timer B operation modes are selected
and the timer B count is read and written.





Timer mode register B1 (TMB1: $009)
Timer mode register B2 (TMB2: $013)
Timer write register B (TWBL: $00A, TWBU: $00B)
Timer read register B (TRBL: $00A, TRBU: $00B)
Port mode register C (PMRC: $025)
• Timer mode register B1 (TMB1: $009): Four-bit write-only register that selects the freerunning/reload timer function, input clock source, and the prescaler division ratio as shown in figure 44.
It is reset to $0 by MCU reset.
61
HD404449 Series
Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register B1 write instruction. Setting timer B’s initialization by writing to timer
write register B (TWBL: $00A, TWBU: $00B) must be done after a mode change becomes valid.
Timer mode register B1 (TMB1: $009)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
TMB13
TMB12
TMB11
TMB10
Bit name
TMB13
Free-running/reload
timer selection
TMB12
TMB11
TMB10
0
Free-running timer
0
0
0
2048tcyc
1
Reload timer
1
512tcyc
0
128tcyc
1
32tcyc
0
8tcyc
1
4tcyc
0
2tcyc
1
R33/EVNB (External event input)
1
1
0
1
Input clock period and input
clock source
Figure 44 Timer Mode Register B1 (TMB1)
• Timer mode register B2 (TMB2: $013): Two-bit read/write register that selects the timer B output
mode as shown in figure 45. It is reset to $0 by MCU reset.
62
HD404449 Series
Timer mode register B2 (TMB2: $013)
Bit
3
2
1
0
Initial value
—
—
0
0
Read/Write
—
—
R/W
R/W
Bit name
Not used Not used TMB21
TMB20
TMB21
TMB20
0
0
R30
R30 port
1
TOB
Toggle output
0
TOB
0 output
1
TOB
1 output
1
R30/TOB mode selection
Figure 45 Timer Mode Register B2 (TMB2)
• Timer write register B (TWBL: $00A, TWBU: $00B): Write-only register consisting of the lower digit
(TWBL) and the upper digit (TWBU) as shown in figures 46 and 47. The lower digit is reset to $0 by
MCU reset, but the upper digit value is invalid.
Timer B is initialized by writing to timer write register B (TWBL: $00A, TWBU: $00B). In this case,
the lower digit (TWBL) must be written to first, but writing only to the lower digit does not change the
timer B value. Timer B is initialized to the value in timer write register B at the same time the upper
digit (TWBU) is written to. When timer write register B is written to again and if the lower digit value
needs no change, writing only to the upper digit initializes timer B.
Timer write register B (lower digit) (TWBL: $00A)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
Bit name
W
W
W
W
TWBL3
TWBL2
TWBL1
TWBL0
Figure 46 Timer Write Register B Lower Digit (TWBL)
Timer write register B (upper digit) (TWBU: $00B)
Bit
Initial value
Read/Write
Bit name
3
2
1
0
Undefined Undefined Undefined Undefined
W
W
W
W
TWBU3
TWBU2
TWBU1
TWBU0
Figure 47 Timer Write Register B Upper Digit (TWBU)
63
HD404449 Series
• Timer read register B (TRBL: $00A, TRBU: $00B): Read-only register consisting of the lower digit
(TRBL) and the upper digit (TRBU) that holds the count of the timer B upper digit (figures 48 and 49).
The upper digit (TRBU) must be read first. At this time, the count of the timer B upper digit is
obtained, and the count of the timer B lower digit is latched to the lower digit (TRBL). After this, by
reading TRBL, the count of timer B when TRBU is read can be obtained.
Timer read register B (lower digit) (TRBL: $00A)
Bit
Initial value
Read/Write
Bit name
3
2
1
0
Undefined Undefined Undefined Undefined
R
R
R
R
TRBL3
TRBL2
TRBL1
TRBL0
Figure 48 Timer Read Register B Lower Digit (TRBL)
Timer read register B (upper digit) (TRBU: $00B)
Bit
Initial value
Read/Write
Bit name
3
2
1
0
Undefined Undefined Undefined Undefined
R
R
R
R
TRBU3
TRBU2
TRBU1
TRBU0
Figure 49 Timer Read Register B Upper Digit (TRBU)
• Port mode register C (PMRC: $025): Write-only register that selects R33/EVNB pin function as shown
in figure 50. It is reset to $0 by MCU reset.
64
HD404449 Series
Port mode register C (PMRC: $025)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
Bit name
PMRC3
PMRC2 PMRC1 PMRC0
PMRC0
R33/EVNB mode selection
0
R33
1
EVNB
PMRC1
R40/EVND mode selection
0
R40
1
EVND
PMRC2
D12/STOPC mode selection
0
D12
1
STOPC
PMRC3
D13/INT0 mode selection
0
D13
1
INT0
Figure 50 Port Mode Register C (PMRC)
Timer C
Timer C Functions: Timer C has the following functions.
• Free-running/reload timer
• Watchdog timer
• Timer output operation (toggle, 0, 1, and PWM outputs)
The block diagram of timer C is shown in figure 51.
65
HD404449 Series
System
reset signal
Watchdog on
flag (WDON)
Timer C interrupt
request flag
(IFTC)
Watchdog timer
control logic
Timer output
control logic
TOC
Timer read register CU (TRCU)
Timer output
control
Timer read
register CL
(TRCL)
Timer counter C
(TCC)
Timer write
register CU
(TWCU)
÷2
÷4
÷8
÷32
÷128
÷512
÷1024
÷2048
Selector
System øPER
clock
Prescaler S (PSS)
Overflow
Free-running
/Reload control
Timer write
register CL
(TWCL)
Internal data bus
Clock
3
Timer mode
register C1
(TMC1)
3
Timer mode
register C2
(TMC2)
Figure 51 Timer C Block Diagram
Timer C Operations:
• Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register C1 (TMC1: $00D).
Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by
software and incremented by one at each clock input. If an input clock is applied to timer C after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is
initialized to its initial value set in timer write register C; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.
66
HD404449 Series
The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2). IFTC is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.
• Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program
routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of
control and an overflow is generated, the MCU is reset. Program run can be controlled by initializing
timer C by software before it reaches $FF.
• Timer output operation: The following four output modes can be selected for timer C by setting timer
mode register C2 (TMC2: $014).




Toggle
0 output
1 output
PWM output
By selecting the timer output mode, pin R31/TOC is set to TOC. The output from TOC is reset low by
MCU reset.




Toggle output: The operation is basically the same as that of timer-B’s toggle output.
0 output: The operation is basically the same as that of timer-B’s 0 output.
1 output: The operation is basically the same as that of timer-B’s 1 output.
PWM output: When PWM output mode is selected, timer C provides the variable-duty pulse output
function. The output waveform differs depending on the contents of timer mode register C1
(TMC1: $00D) and timer write register C (TWCL: $00E, TWCU: $00F). The output waveform is
shown in figure 43.
Registers for Timer C Operation: By using the following registers, timer C operation modes are selected
and the timer C count is read and written.




Timer mode register C1 (TMC1: $00D)
Timer mode register C2 (TMC2: $014)
Timer write register C (TWCL: $00E, TWCU: $00F)
Timer read register C (TRCL: $00E, TRCU: $00F)
• Timer mode register C1 (TMC1: $00D): Four-bit write-only register that selects the freerunning/reload timer function, input clock source, and prescaler division ratio as shown in figure 52. It
is reset to $0 by MCU reset.
Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register C1 write instruction. Setting timer C’s initialization by writing to timer
write register C (TWCL: $00E, TWCU: $00F) must be done after a mode change becomes valid.
• Timer mode register C2 (TMC2: $014): Three-bit read/write register that selects the timer C output
mode as shown in figure 53. It is reset to $0 by MCU reset.
67
HD404449 Series
• Timer write register C (TWCL: $00E, TWCU: $00F): Write-only register consisting of a lower digit
(TWCL) and an upper digit (TWCU) as shown in figures 54 and 55. The operation of timer write
register C is basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B).
• Timer read register C (TRCL: $00E, TRCU: $00F): Read-only register consisting of a lower digit
(TRCL) and an upper digit (TRCU) that holds the count of the timer C upper digit as shown in figures
56 and 57. The operation of timer read register C is basically the same as that of timer read register B
(TRBL: $00A, TRBU: $00B).
Timer mode register C1 (TMC1: $00D)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
TMC13
TMC12
TMC11
TMC10
Bit name
TMC13
Free-running/reload timer selection
0
Free-running timer
1
Reload timer
TMC11
TMC10
0
0
0
2048tcyc
1
1024tcyc
0
512tcyc
1
128tcyc
0
32tcyc
1
8tcyc
0
4tcyc
1
2tcyc
1
1
0
1
Figure 52 Timer Mode Register C1 (TMC1)
68
Input clock period
TMC12
HD404449 Series
Timer mode register C2 (TMC2: $014)
Bit
3
2
1
0
Initial value
—
0
0
0
Read/Write
—
R/W
R/W
R/W
Not used TMC22
TMC21
TMC20
TMC22
TMC21
TMC20
0
0
0
R31
R31 port
1
TOC
Toggle output
0
TOC
0 output
1
TOC
1 output
0
—
Inhibited
Bit name
1
1
0
R31/TOC mode selection
1
0
1
1
PWM output
TOC
Figure 53 Timer Mode Register C2 (TMC2)
Timer write register C (lower digit) (TWCL: $00E)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
Bit name
W
W
W
W
TWCL3
TWCL2
TWCL1
TWCL0
Figure 54 Timer Write Register C Lower Digit (TWCL)
Timer write register C (upper digit) (TWCU: $00F)
Bit
Initial value
Read/Write
Bit name
3
2
1
0
Undefined Undefined Undefined Undefined
W
W
W
W
TWCU3
TWCU2
TWCU1
TWCU0
Figure 55 Timer Write Register C Upper Digit (TWCU)
69
HD404449 Series
Timer read register C (lower digit) (TRCL: $00E)
Bit
Initial value
Read/Write
Bit name
3
2
1
0
Undefined Undefined Undefined Undefined
R
R
R
R
TRCL3
TRCL2
TRCL1
TRCL0
Figure 56 Timer Read Register C Lower Digit (TRCL)
Timer read register C (upper digit) (TRCU: $00F)
Bit
Initial value
Read/Write
Bit name
3
2
1
0
Undefined Undefined Undefined Undefined
R
R
R
R
TRCU3
TRCU2
TRCU1
TRCU0
Figure 57 Timer Read Register C Upper Digit (TRCU)
Timer D
Timer D Functions: Timer D has the following functions.
•
•
•
•
Free-running/reload timer
External event counter
Timer output operation (toggle, 0, 1, and PWM outputs)
Input capture timer
The block diagram for each operation mode of timer D is shown in figures 58 (A) and (B).
70
HD404449 Series
Timer D interrupt
request flag (IFTD)
Timer output
control logic
TOD
Timer read
register DU (TRDU)
Timer output
control
Timer read
register DL
(TRDL)
Clock
Timer write
register DU
(TWDU)
System
clock
øPER
÷2048
Edge
detection
logic
÷2
÷4
÷8
÷32
÷128
÷512
Selector
EVND
Overflow
Free-running/
Reload control
Timer write
register DL
(TWDL)
3
Prescaler S (PSS)
Internal data bus
Timer counter D
(TCD)
Timer mode
register D1
(TMD1)
3
Timer mode
register D2
(TMD2)
Edge detection control
2
Edge detection
selection register
2 (ESR2)
Figure 58 (A) Timer D Block Diagram (Free-Running/Reload Timer)
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HD404449 Series
Input capture
status flag (ICSF)
Input capture
error flag (ICEF)
Timer D interrupt
request flag (IFTD)
Error
control
logic
Timer read
register DU
(TRDU)
Timer read
register DL
(TRDL)
EVND
Edge
detection
logic
Read signal
Clock
Timer counter D
(TCD)
Overflow
Selector
System
clock
÷2048
÷2
÷4
÷8
÷32
÷128
÷512
3
Timer mode
register D1
(TMD1)
øPER
Prescaler S (PSS)
Timer mode
register D2
(TMD2)
Edge detection control
2
Edge detection
selection register
2 (ESR2)
Figure 58 (B) Timer D Block Diagram (Input Capture Timer)
72
Internal data bus
Input capture
timer control
HD404449 Series
Timer D Operations:
• Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register D1 (TMD1: $010).
Timer D is initialized to the value set in timer write register D (TWDL: $011, TWDU: $012) by
software and incremented by one at each clock input. If an input clock is applied to timer D after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer D is
initialized to its initial value set in timer write register D; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.
The overflow sets the timer D interrupt request flag (IFTD: $003, bit 0). IFTD is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.
• External event counter operation: Timer D is used as an external event counter by selecting the
external event input as an input clock source. In this case, pin R40/EVND must be set to EVND by port
mode register C (PMRC: $025).
Either falling or rising edge, or both falling and rising edges of input signals can be selected as the
external event detection edge by detection edge select register 2 (ESR2: $027). When both rising and
falling edges detection is selected, the time between the falling edge and rising edge of input signals
must be 2t cyc or longer.
Timer D is incremented by one at each detection edge selected by detection edge select register 2
(ESR2: $027). The other operation is basically the same as the free-running/reload timer operation.
• Timer output operation: The following four output modes can be selected for timer D by setting timer
mode register D2 (TMD2: $015).




Toggle
0 output
1 output
PWM output
By selecting the timer output mode, pin R32/TOD is set to TOD. The output from TOD is reset low by
MCU reset.




Toggle output: The operation is basically the same as that of timer-B’s toggle output.
0 output: The operation is basically the same as that of timer-B’s 0 output.
1 output: The operation is basically the same as that of timer-B’s 1 output.
PWM output: The operation is basically the same as that of timer-C’s PWM output.
• Input capture timer operation: The input capture timer counts the clock cycles between trigger edges
input to pin EVND.
Either falling or rising edge, or both falling and rising edges of input signals can be selected as the
trigger input edge by detection edge select register 2 (ESR2: $027).
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HD404449 Series
When a trigger edge is input to EVND, the count of timer D is written to timer read register D (TRDL:
$011, TRDU: $012), and the timer D interrupt request flag (IFTD: $003, bit 0) and the input capture
status flag (ICSF: $021, bit 0) are set. Timer D is reset to $00, and then incremented again. While
ICSF is set, if a trigger input edge is applied to timer D, or if timer D generates an overflow, the input
capture error flag (ICEF: $021, bit 1) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing
0.
By selecting the input capture operation, pin R3 2/TOD is set to R3 2 and timer D is reset to $00.
Registers for Timer D Operation: By using the following registers, timer D operation modes are selected
and the timer D count is read and written.






Timer mode register D1 (TMD1: $010)
Timer mode register D2 (TMD2: $015)
Timer write register D (TWDL: $011, TWDU: $012)
Timer read register D (TRDL: $011, TRDU: $012)
Port mode register C (PMRC: $025)
Detection edge select register 2 (ESR2: $027)
• Timer mode register D1 (TMD1: $010): Four-bit write-only register that selects the freerunning/reload timer function, input clock source, and the prescaler division ratio as shown in figure 59.
It is reset to $0 by MCU reset.
Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register D1 (TMD1: $010) write instruction. Setting timer D’s initialization by
writing to timer write register D (TWDL: $011, TWDU: $012) must be done after a mode change
becomes valid.
When selecting the input capture timer operation, select the internal clock as the input clock source.
• Timer mode register D2 (TMD2: $015): Four-bit read/write register that selects the timer D output
mode and input capture operation as shown in figure 60. It is reset to $0 by MCU reset.
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HD404449 Series
Timer mode register D1 (TMD1: $010)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
Bit name
TMD13
W
W
W
W
TMD13
TMD12
TMD11
TMD10
Free-running/reload timer selection
0
Free-running timer
1
Reload timer
Input clock period and
input clock source
TMD12
TMD11
TMD10
0
0
0
2048tcyc
1
512tcyc
0
128tcyc
1
32tcyc
0
8tcyc
1
4tcyc
0
2tcyc
1
R40/EVND (External event input)
1
1
0
1
Figure 59 Timer Mode Register D1 (TMD1)
• Timer write register D (TWDL: $011, TWDU: $012): Write-only register consisting of a lower digit
(TWDL) and an upper digit (TWDU) as shown in figures 61 and 62. The operation of timer write
register D is basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B).
• Timer read register D (TRDL: $011, TRDU: $012): Read-only register consisting of a lower digit
(TRDL) and an upper digit (TRDU) as shown in figures 63 and 64. The operation of timer read register
D is basically the same as that of timer read register B (TRBL: $00A, TRBU: $00B).
When the input capture timer operation is selected and if the count of timer D is read after a trigger is
input, either the lower or upper digit can be read first.
• Port mode register C (PMRC: $025): Write-only register that selects R40/EVND pin function as shown
in figure 50. It is reset to $0 by MCU reset.
• Detection edge select register 2 (ESR2: $027): Write-only register that selects the detection edge of
signals input to pin EVND as shown in figure 65. It is reset to $0 by MCU reset.
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HD404449 Series
Timer mode register D2 (TMD2: $015)
Bit
3
2
0
1
Initial value
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
TMD23
TMD22
TMD21
TMD20
Bit name
TMD23
TMD22
TMD21
TMD20
0
0
0
0
R32
R32 port
1
TOD
Toggle output
0
TOD
0 output
1
TOD
1 output
0
—
Inhibited
TOD
PWM output
R32
Input capture (R32 port)
1
1
0
R32/TOD mode selection
1
0
1
1
1
Don't care Don't care Don't care
Figure 60 Timer Mode Register D2 (TMD2)
Timer write register D (lower digit) (TWDL: $011)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
Bit name
W
W
W
W
TWDL3
TWDL2
TWDL1
TWDL0
Figure 61 Timer Write Register D Lower Digit (TWDL)
Timer write register D (upper digit) (TWDU: $012)
Bit
Initial value
Read/Write
Bit name
3
2
1
0
Undefined Undefined Undefined Undefined
W
W
W
W
TWDU3
TWDU2
TWDU1
TWDU0
Figure 62 Timer Write Register D Upper Digit (TWDU)
76
HD404449 Series
Timer read register D (lower digit) (TRDL: $011)
Bit
3
Initial value
2
1
0
Undefined Undefined Undefined Undefined
Read/Write
Bit name
R
R
R
R
TRDL3
TRDL2
TRDL1
TRDL0
Figure 63 Timer Read Register D Lower Digit (TRDL)
Timer read register D (upper digit) (TRDU: $012)
Bit
3
Initial value
2
0
1
Undefined Undefined Undefined Undefined
Read/Write
Bit name
R
R
R
R
TRDU3
TRDU2
TRDU1
TRDU0
Figure 64 Timer Read Register D Upper Digit (TRDU)
Detection edge register 2 (ESR2: $027)
Bit
3
2
1
0
Initial value
0
0
—
—
W
—
—
Read/Write
W
Bit name
ESR23
ESR22 Not used Not used
EVND detection edge
ESR23
ESR22
0
0
No detection
1
Falling-edge detection
0
Rising-edge detection
1
Double-edge detection*
1
Note: * Both falling and rising edges are detected.
Figure 65 Detection Edge Select Register 2 (ESR2)
Notes on Use
When using the timer output as PWM output, note the following point. From the update of the timer write
register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty
settings, as shown in table 27. The PWM output should therefore not be used until after the overflow
interrupt following the update of the timer write register. After the overflow, the PWM output will have the
set period and duty cycle.
77
HD404449 Series
Table 27
PWM Output Following Update of Timer Write Register
PWM Output
Mode
Timer Write Register is Updated during
High PWM Output
Timer write
register
updated to
value N
Free running
Timer Write Register is Updated during
Low PWM Output
Timer write
register
updated to
value N
Interrupt
request
T × (255 – N) T × (N + 1)
Interrupt
request
T × (N' + 1)
T × (255 – N)
Timer write
register
updated to
value N
Reload
T
Interrupt
request
T × (255 – N)
T
Timer write
register
updated to
value N
Interrupt
request
T
T × (255 – N)
78
T × (N + 1)
T
HD404449 Series
Serial Interface
The MCU has two channels of serial interface. The transfer and receive start instructions differ according
to the serial interface channel, but other functions are the same. The serial interface serially transfers or
receives 8-bit data, and includes the following features.
• Multiple transmit clock sources
 External clock
 Internal prescaler output clock
 System clock
• Output level control in idle states
Five registers, an octal counter, and a multiplexer are also configured for serial interfaces 1 and 2 as
follows.
Serial interface 1
•
•
•
•
•
•
•
Serial data register 1 (SR1L: $006, SR1U: $007)
Serial mode register 1A (SM1A: $005)
Serial mode register 1B (SM1B: $028)
Port mode register A (PMRA: $004)
Miscellaneous register (MIS: $00C)
Octal counter (OC)
Selector
Serial interface 2
•
•
•
•
•
•
Serial data register 2 (SR2L: $01D, SR2U: $01E)
Serial mode register 2A (SM2A: $01B)
Serial mode register 2B (SM2B: $01C)
Port mode register A (PMRA: $004)
Octal counter (OC)
Selector
The block diagram of serial interfaces 1 and 2 are shown in figure 66.
79
HD404449 Series
Serial interrupt
request flag
(IFS1, IFS2)
Octal counter
(OC1, OC2)
Idle control
logic
SO1 , SO2
SCK1 , SCK2
Transfer
control
1/2
1/2
System
clock
øPER
3
÷2048
÷8
÷32
÷128
÷512
÷2
Selector
Selector
SI1 , SI 2
Internal data bus
Serial data
register (SR1L/U,
SR2L/U)
Clock
I/O control
logic
Prescaler S (PSS)
Serial mode register
1A, 2A (SM1A,
SM2A)
Serial mode register
1B, 2B (SM1B,
SM2B)
Figure 66 Serial Interfaces 1 and 2 Block Diagram
Serial Interface Operation
Selecting and Changing the Operating Mode: Tables 28 (A) and 28 (B) list the serial interfaces’
operating modes. To select an operating mode, use one of these combinations of port mode register A
(PMRA: $004), serial mode register 1A (SM1A: $005), and serial mode register 2A (SM2A: $01B)
settings; to change the operating mode of serial interface 1, always initialize the serial interface internally
by writing data to serial mode register 1A; and to change the operating mode of serial interface 2, always
initialize the serial interface internally by writing data to serial mode register 2A. Note that serial interface
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HD404449 Series
1 is initialized by writing data to serial mode register 1A, and serial interface 2 is initialized by writing data
to serial mode register 2A. Refer to the following section Registers for Serial Interface for details.
Pin Setting: The R41/SCK 1 pin is controlled by writing data to serial mode register 1A (SM1A: $005).
The R5 1/SCK 2 pin is controlled by writing data to serial mode register 2A (SM2A: $01B). Pins R42/SI 1,
R4 3/SO 1, R5 2/SI 2, and R5 3/SO 2 are controlled by writing data to port mode register A (PMRA: $004). Refer
to the following section Registers for Serial Interface for details.
Transmit Clock Source Setting: The transmit clock source of serial interface 1 is set by writing data to
serial mode register 1A (SM1A: $005) and serial mode register 1B (SM1B: $028). The transmit clock
source of serial interface 2 is set by writing data to serial mode register 2A (SM2A: $01B) and serial mode
register 2B (SM2B: $01C). Refer to the following section Registers for Serial Interface for details.
Data Setting: Transmit data of serial interface 1 is set by writing data to serial data register 1 (SR1L:
$006, SR1U: $007). Transmit data of serial interface 2 is set by writing data to serial data register 2
(SR2L: $01D, SR2U: $01E). Receive data of serial interface 1 is obtained by reading the contents of serial
data register 1. Receive data of serial interface 2 is obtained by reading the contents of serial data register
2. The serial data is shifted by each serial interface transmit clock and is input from or output to an external
system.
The output level of the SO1 and SO2 pins is invalid until the first data of each serial interface is output after
MCU reset, or until the output level control in idle states is performed.
Transfer Control: Serial interface 1 is activated by the STS instruction. Serial interface 2 is activated by
a dummy read of serial mode register 2A (SM2A: $01B), which will be referred to as SM2A read. The
octal counter is reset to 000 by the STS instruction (serial interface 2 is SM2A read), and it increments at
the rising edge of the transmit clock for each serial interface. When the eighth transmit clock signal is
input or when serial transmission/reception is discontinued, the octal counter is reset to 000, the serial 1
interrupt request flag (IFS1: $003, bit 2) for serial interface 1 and serial 2 interrupt request flag (IFS2:
$023, bit 2) for serial interface 2 are set, and the transfer stops.
When the prescaler output is selected as the transmit clock of serial interface 1, the transmit clock
frequency is selected as 4t cyc to 8192tcyc by setting bits 0 to 2 (SM1A0–SM1A2) of serial mode register 1A
(SM1A: $005) and bit 0 (SM1B0) of serial mode register 1B (SM1B: $028) as listed in table 29. When the
prescaler output is selected as the transmit clock of serial interface 2, the transmit clock frequency is
selected as 4t cyc to 8192tcyc by setting bits 0 to 2 (SM2A0– SM2A2) of serial mode register 2A (SM2A:
$01B) and bit 0 (SM2B0) of serial mode register 2B (SM2B: $01C).
Note: To start serial interface 2, simply read serial mode register 2A by using the instruction that
compares serial mode register 2A (SM2A: $01B) with the accumulator.
Serial mode register 2A (SM2A: $01B) is a read-only register, so $0 can be read.
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HD404449 Series
Table 28 (A)
Serial Interface 1 Operating Modes
SM1A
PMRA
Bit 3
Bit 1
Bit 0
Operating Mode
1
0
0
Continuous clock output mode
1
Transmit mode
0
Receive mode
1
Transmit/receive mode
1
Table 28 (B)
Serial Interface 2 Operating Modes
SM2A
PMRA
Bit 3
Bit 3
Bit 2
Operating Mode
1
0
0
Continuous clock output mode
1
Transmit mode
0
Receive mode
1
Transmit/receive mode
1
Table 29
Serial Transmit Clock (Prescaler Output)
SM1B/
SM2B
SM1A/ SM2A
Bit 0
Bit 2
Bit 1
Bit 0
Prescaler Division Ratio
Transmit Clock Frequency
0
0
0
0
÷ 2048
4096t cyc
1
÷ 512
1024t cyc
0
÷ 128
256t cyc
1
÷ 32
64t cyc
0
÷8
16t cyc
1
÷2
4t cyc
0
÷ 4096
8192t cyc
1
÷ 1024
2048t cyc
0
÷ 256
512t cyc
1
÷ 64
128t cyc
0
÷ 16
32t cyc
1
÷4
8t cyc
1
1
1
0
0
0
1
1
82
0
HD404449 Series
Operating States: The serial interface has the following operating states; transitions between them are
shown in figure 67.




STS wait state (serial interface 2 is in SM2A read wait state)
Transmit clock wait state
Transfer state
Continuous clock output state (only in internal clock mode)
The operation state of serial interface 2 is the same as serial interface 1 except that the STS instruction of
serial interface 1 changes to SM2A read. The following shows the operation state of serial interface 1.
• STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 67). In STS
wait state, serial interface 1 is initialized and the transmit clock is ignored. If the STS instruction is then
executed (01, 11), serial interface 1 enters transmit clock wait state.
External clock mode
STS wait state
(Octal counter = 000,
transmit clock disabled)
SM1A write
00
MCU reset
06 SM1A write (IFS ← 1)
04
01
STS instruction
02 Transmit clock
Transmit clock wait state
(Octal counter = 000)
03
8 transmit clocks
Transfer state
(Octal counter = 000)
05
STS instruction (IFS ← 1)
Internal clock mode
STS wait state
(Octal counter = 000,
transmit clock disabled)
SM1A write
18
Continuous clock output state
(PMRA 0, 1 = 00)
10
13
SM1A write
8 transmit clocks
14
11
STS instruction
MCU reset
16
SM1A write (IFS ←1)
Transmit clock 17
12 Transmit clock
Transmit clock wait state
(Octal counter = 000)
Transfer state
(Octal counter = 000)
15
STS instruction (IFS ← 1)
Note: Refer to the Operating States section for the corresponding encircled numbers.
Figure 67 Serial Interface State Transitions
• Transmit clock wait state: Transmit clock wait state is the period between the STS execution and the
falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12)
increments the octal counter, shifts serial data register 1 (SR1L: $006, SR1U: $007), and enters the
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HD404449 Series
serial interface in transfer state. However, note that if continuous clock output mode is selected in
internal clock mode, the serial interface does not enter transfer state but enters continuous clock output
state (17).
The serial interface enters STS wait state by writing data to serial mode register 1A (SM1A: $005) (04,
14) in transmit clock wait state.
• Transfer state: Transfer state is the period between the falling edge of the first clock and the rising edge
of the eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction
sets the octal counter to 000, and the serial interface enters another state. When the STS instruction is
executed (05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait
state is entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode.
In internal clock mode, the transmit clock stops after outputting eight clocks.
In transfer state, writing data to serial mode register 1A (SM1A: $005) (06, 16) initializes serial
interface 1, and STS wait state is entered.
If the state changes from transfer to another state, the serial 1 interrupt request flag (IFS1: $003, bit 2) is
set by the octal counter that is reset to 000.
• Continuous clock output state (only in internal clock mode): Continuous clock output state is entered
only in internal clock mode. In this state, the serial interface does not transmit/receive data but only
outputs the transmit clock from the SCK 1 pin.
When bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004) are 00 in transmit clock
wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state.
If serial mode register 1A (SM1A: $005) is written to in continuous clock output mode (18), STS wait
state is entered.
Output Level Control in Idle States: When serial interface 1 is in STS instruction wait state and when
serial interface 2 is in SM2A read wait state and transmit clock state, the output of each serial output pin,
SO1 and SO2, can be controlled by setting bit 1 (SM1B1) of serial mode register 1B (SM1B: $028) to 0 or 1,
or bit 1 (SM2B1) of serial mode register 2B (SM2B: $01C) to 0 or 1. The output level control example of
serial interface 1 is shown in figure 68. Note that the output level cannot be controlled in transfer state.
84
,
HD404449 Series
Transmit clock
wait state
State
STS wait state
Transmit clock
wait state
Transfer state
STS wait state
MCU reset
Port selection
PMRA write
External clock selection
SM1A write
Output level control in
idle states
Dummy write for
state transition
Output level control in
idle states
SM1B write
Data write for transmission
SR1L, SR1U
write
STS instruction
SCK1 pin (input)
SO1 pin
Undefined
LSB
MSB
IFS1
External clock mode
Flag reset at transfer completion
Transmit clock
wait state
State
STS wait state
Transfer state
STS wait state
MCU reset
Port selection
PMRA write
Internal clock selection
SM1A write
Output level control in
idle states
SM1B write
Output level control in
idle states
Data write for transmission
SR1L, SR1U
write
STS instruction
SCK1 pin (input)
SO1 pin
Undefined
LSB
MSB
IFS1
Internal clock mode
Flag reset at transfer completion
Figure 68 Example of Serial Interface 1 Operation Sequence
85
HD404449 Series
Transmit Clock Error Detection (In External Clock Mode): Each serial interface will malfunction if a
spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit
clock error of this type can be detected as shown in figure 69.
If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse
by noise, the octal counter reaches 000, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set, and
transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is
entered. After the transfer is completed and IFS1 is reset, writing to serial mode register 1A (SM1A: $005)
changes the state from transfer to STS wait. At this time serial interface 1 is in the transfer state, and the
serial 1 interrupt request flag (IFS1: $003, bit 2) is set again, and therefore the error can be detected. The
same applies to serial interface 2.
Notes on Use:
• Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit
clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode
register 1A (SM1A: $005) and serial mode register 2A (SM2A: $01B) again.
• Serial 1 interrupt request flag (IFS1: $003, bit 2) and serial 2 interrupt request flag (IFS2: $023, bit 2)
set: For serial interface 1, if the state is changed from transfer state to another by writing to serial mode
register 1A (SM1A: $005) or executing the STS instruction during the first low pulse of the transmit
clock, the serial 1 interrupt request flag (IFS1: $003, bit 2) is not set. In the same way for serial
interface 2, if the state is changed from transfer state to another by writing to serial mode register 2A
(SM2A: $01B) or by executing the STS instruction during the first low pulse of the transmit clock, the
serial 2 interrupt request flag (IFS2: $023, bit 2) is not set. To set the serial 1 interrupt request flag
(IFS1: $003, bit 2), a serial mode register 1A (SM1A: $005) write or STS instruction execution must be
programmed to be executed after confirming that the SCK 1 pin is at 1, that is, after executing the input
instruction to port R4. To set the serial 2 interrupt request flag (IFS2: $023, bit 2), a serial mode
register 2A (SM2A: $01B) write or SM2A instruction execution must be programmed to be executed
after confirming that the SCK 2 pin is at 1, that is, after executing the input instruction to port R5.
86
HD404449 Series
Transfer completion
(IFS1 ← 1)
Interrupts inhibited
IFS1 ← 0
SM1A write
Yes
IFS1 = 1
Transmit clock
error processing
No
Normal
termination
Transmit clock error detection flowchart
Transmit clock
wait state
Transmit clock wait state
Transfer state
State
SCK 1 pin
(input)
1
2
Transfer state
Noise
3
4
5
6
7
8
Transfer state has been
entered by the transmit clock
error. When SM1A is written,
IFS1 is set.
SM1A
write
IFS1
Flag set because octal
counter reaches 000.
Flag reset at
transfer completion.
Transmit clock error detection procedures
Figure 69 Transmit Clock Error Detection
87
HD404449 Series
Registers for Serial Interface
The serial interface operation is selected, and serial data is read and written by the following registers.
For serial interface 1
• Serial mode register 1A (SM1A: $005)
• Serial mode register 1B (SM1B: $028)
• Serial data register 1
(SR1L: $006, SR1U: $007)
• Port mode register A (PMRA: $004)
• Miscellaneous register (MIS: $00C)
For serial interface 2
• Serial mode register 2A (SM2A: $01B)
• Serial mode register 2B (SM2B: $01C)
• Serial data register 2
(SR2L: $01D, SR2U: $01E)
• Port mode register A (PMRA: $004)
Serial Mode Register 1A (SM1A: $005): This register has the following functions (figure 70).
•
•
•
•
R4 1/SCK 1 pin function selection
Serial interface 1 transmit clock selection
Serial interface 1 prescaler division ratio selection
Serial interface 1 initialization
Serial mode register 1A (SM1A: $005) is a 4-bit write-only register. It is reset to $0 by MCU reset.
A write signal input to serial mode register 1A (SM1A: $005) discontinues the input of the transmit clock
to serial data register 1 (SR1L: $006, SR1U: $007) and the octal counter, and the octal counter is reset to
000. Therefore, if a write is performed during data transfer, the serial 1 interrupt request flag (IFS1: $003,
bit 2) is set.
Written data is valid from the second instruction execution cycle after the write operation, so the STS
instruction must be executed at least two cycles after that.
88
HD404449 Series
Serial mode register 1A (SM1A: $005)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
SM1A3
SM1A2
SM1A1
SM1A0
Bit name
SM1A3
R41/SCK1
mode selection
0
R41
1
SCK1
Prescaler
division ratio
SM1A2
SM1A1
SM1A0
SCK1
Clock source
0
0
0
Output
Prescaler
Refer to
table 29
0
Output
System clock
—
1
Input
External clock
—
1
1
0
1
1
0
0
1
1
Figure 70 Serial Mode Register 1A (SM1A)
Serial Mode Register 1B (SM1B: $028): This register has the following functions (figure 71).
• Serial interface 1 prescaler division ratio selection
• Serial interface 1 output level control in idle states
Serial mode register 1B (SM1B: $028) is a 2-bit write-only register. It cannot be written during data
transfer.
By setting bit 0 (SM1B0) of this register, the serial interface 1 prescaler division ratio is selected. Only bit
0 (SM1B0) can be reset to 0 by MCU reset. By setting bit 1 (SM1B1), the output level of the SO1 pin is
controlled in idle states of serial interface 1. The output level changes at the same time that SM1B1 is
written to.
89
HD404449 Series
Serial mode register 1B (SM1B: $028)
Bit
3
2
1
0
Initial value
—
—
Undefined
0
Read/Write
—
—
W
W
Bit name
Not used Not used SM1B1
SM1B1
Output level control in idle states
SM1B0
SM1B0
Transmit clock division ratio
0
Low level
0
Prescaler output divided by 2
1
High level
1
Prescaler output divided by 4
Figure 71 Serial Mode Register 1B (SM1B)
Serial Data Register 1 (SR1L: $006, SR1U: $007): This register has the following functions (figures 72
and 73)
• Serial interface 1 transmission data write and shift
• Serial interface 1 receive data shift and read
Writing data in this register is output from the SO1 pin, LSB first, synchronously with the falling edge of
the transmit clock; data is input, LSB first, through the SI1 pin at the rising edge of the transmit clock.
Input/output timing is shown in figure 74.
Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the
accuracy of the resultant data cannot be guaranteed.
Serial data register 1 (lower digit) (SR1L: $006)
Bit
3
Initial value
2
1
0
Undefined Undefined Undefined Undefined
Read/Write
R/W
R/W
R/W
R/W
Bit name
SR13
SR12
SR11
SR10
Figure 72 Serial Data Register 1 (SR1L)
90
HD404449 Series
Serial data register 1 (upper digit) (SR1U: $007)
Bit
Initial value
1
2
3
0
Undefined Undefined Undefined Undefined
Read/Write
R/W
R/W
R/W
R/W
Bit name
SR17
SR16
SR15
SR14
Figure 73 Serial Data Register 1 (SR1U)
Transmit clock
1
Serial output
data
2
3
4
5
6
LSB
7
8
MSB
Serial input data
latch timing
Figure 74 Serial Interface Output Timing
91
HD404449 Series
Port Mode Register A (PMRA: $004): This register has the following functions (figure 75).
•
•
•
•
R4 2/SI 1 pin function selection
R4 3/SO 1 pin function selection
R5 2/SI 2 pin function selection
R5 3/SO 2 pin function selection
Port mode register A (PMRA: $004) is a 4-bit write-only register, and is reset to $0 by MCU reset.
Port mode register A (PMRA: $004)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
Bit name
PMRA3
PMRA2 PMRA1 PMRA0
PMRA0
R43/SO1 mode selection
0
R43
1
SO1
PMRA1
R42/SI1 mode selection
0
R42
1
SI1
PMRA2
R53/SO2 mode selection
0
R53
1
SO2
PMRA3
R52/SI2 mode selection
0
R52
1
SI2
Figure 75 Port Mode Register A (PMRA)
92
HD404449 Series
Miscellaneous Register (MIS: $00C): This register has the following functions (figure 76).
• R4 3/SO 1 pin PMOS control
Miscellaneous register (MIS: $00C) is a 4-bit write-only register and is reset to $0 by MCU reset.
Miscellaneous register (MIS: $00C)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
MIS3
MIS2
MIS1
MIS0
Bit name
MIS1
MIS0
0
0
tRC
0.12207 ms
0.24414 ms*
1
MIS2
1
7.8125 ms
0
62.5 ms
1
Not used
R43/SO1 PMOS on/off selection
0
On
1
Off
MIS3
Pull-up MOS on/off selection
0
Off
1
On
Note: *This value is valid only for direct transfer operation.
Figure 76 Miscellaneous Register (MIS)
Serial Mode Register 2A (SM2A: $01B): This register has the following functions (figure 77).
•
•
•
•
R5 1/SCK 2 pin function selection
Serial interface 2 transmit clock selection
Serial interface 2 prescaler division ratio selection
Serial interface 2 initialization
Serial mode register 2A (SM2A: $01B) is a 4-bit write-only register. It is reset to $0 by MCU reset.
A write signal input to serial mode register 2A (SM2A: $01B) discontinues the input of the transmit clock
to serial data register 2 (SR2L: $01D, SR1U: $01E) and the octal counter, and the octal counter is reset to
93
HD404449 Series
000. Therefore, if a write is performed during data transfer, the serial 2 interrupt request flag (IFS2: $023,
bit 2) is set.
Written data is valid from the second instruction execution cycle after the write operation, so the SM2A
read instruction must be executed at least two cycles after that.
Serial mode register 2A (SM2A: $01B)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
SM2A3
SM2A2
SM2A1
SM2A0
Bit name
SM2A3
R51/SCK2
mode selection
0
R51
1
SCK2
Prescaler
division ratio
SM2A2
SM2A1
SM2A0
SCK2
Clock source
0
0
0
Output
Prescaler
Refer to
table 29
0
Output
System clock
—
1
Input
External clock
—
1
1
0
1
1
0
0
1
1
Figure 77 Serial Mode Register 2A (SM2A)
Serial Mode Register 2B (SM2B: $01C): This register has the following functions (figure 78).
• Serial interface 2 prescaler division ratio selection
• Serial interface 2 output level control in idle states
• R5 3/SO 2 pin PMOS control
Serial mode register 2B (SM2B: $01C) is a 3-bit write-only register. It cannot be written during serial
interface 2 data transfer. Bit 0 (SM2B0) and bit 2 (SM2B2) is reset to $0 by MCU reset.
By setting bit 0 (SM2B0) of this register, the serial interface 2 prescaler division ratio of serial interface 2 is
selected. By resetting bit 1 (SM2B1), the output level of the SO2 pin is controlled in idle states of serial
interface 2. The output level changes at the same time that SM2B1 is written to.
94
HD404449 Series
Serial mode register 2B (SM2B: $01C)
Bit
3
2
1
0
Initial value
—
0
Undefined
0
Read/Write
—
W
W
W
SM2B1
SM2B0
Bit name
SM2B2
Not used SM2B2
R53/SO2 PMOS
SM2B0
Transmit clock division ratio
0
On
0
Prescaler output divided by 2
1
Off
1
Prescaler output divided by 4
SM2B1
Output level control in idle states
0
Low level
1
High level
Figure 78 Serial Mode Register 2B (SM2B)
Serial Data Register 2 (SR2L: $01D, SR2U: $01E): This register has the following functions (figures 79
and 80).
• Serial interface 2 transmission data write and shift
• Serial interface 2 receive data shift and read
Writing data in this register is output from the SO2 pin, LSB first, synchronously with the falling edge of
the transmit clock; data is input, LSB first, through the SI2 pin at the rising edge of the transmit clock.
Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the
accuracy of the resultant data cannot be guaranteed.
Serial data register 2 (lower digit) (SR2L: $01D)
Bit
3
Initial value
2
1
0
Undefined Undefined Undefined Undefined
Read/Write
R/W
R/W
R/W
R/W
Bit name
SR23
SR22
SR21
SR20
Figure 79 Serial Data Register 2 (SR2L)
95
HD404449 Series
Serial data register 2 (upper digit) (SR2U: $01E)
Bit
3
Initial value
2
1
0
Undefined Undefined Undefined Undefined
Read/Write
R/W
R/W
R/W
R/W
Bit name
SR27
SR26
SR25
SR24
Figure 80 Serial Data Register 2 (SR2U)
96
HD404449 Series
A/D Converter
The MCU has a built-in A/D converter that uses a sequential comparison method with a resistor ladder. It
can measure four analog inputs with 8-bit resolution. As shown in the block diagram of figure 81, the A/D
converter has a 4-bit A/D mode register, a 1-bit A/D start flag, and a 4-bit plus 4-bit A/D data register.
Internal bus line (S2)
Internal bus line (S1)
4
4
A/D mode register
(AMR)
2
A/D start flag
(ADSF)
4
A/D data register
(ADRU, ADRL)
2
8
IFAD
AN 1
AN 2
AN 3
Selector
AN 0
A/D interrupt
request flag
+
Control logic
COMP
–
AVCC
AVSS
Encoder
D/A
8
Operating mode signal (set to 0 in stop mode,
watch mode, and subactive mode)
Figure 81 A/D Converter Block Diagram
A/D Mode Register (AMR: $016): Four-bit write-only register which selects the A/D conversion period
and indicates analog input pin information. Bit 0 of the A/D mode register selects the A/D conversion
period, and bits 2 and 3 select a channel, as shown in figure 82.
A/D Start Flag (ADSF: $020, Bit 2): One-bit flag that initiates A/D conversion when set to 1. At the
completion of A/D conversion, the converted data is stored in the A/D data register and the A/D start flag is
cleared. Refer to figure 86.
A/D Data Register (ADRL: $017, ADRU: $018): Eight-bit read-only register consisting of a 4-bit lower
digit and 4-bit upper digit. This register is not cleared by reset. After the completion of A/D conversion,
the resultant eight-bit data is held in this register until the start of the next conversion (figures 83, 84, and
85).
97
HD404449 Series
Note on Use: Use the SEM and SEMD instructions to write data to the A/D start flag (ADSF: $020, bit 2),
but make sure that the A/D start flag is not written to during A/D conversion. Data read from the A/D data
register (ADRL: $017, ADRU: $018) during A/D conversion cannot be guaranteed.
The A/D converter does not operate in the stop, watch, and subactive modes because of the OSC clock.
During these low-power dissipation modes, current through the resistor ladder is cut off to decrease the
power input.
A/D mode register (AMR: $016)
Bit
3
2
1
0
Initial value
0
0
—
0
Read/Write
W
W
—
W
Bit name
AMR3
AMR2 Not used
Analog input selection
AMR0
AMR3
AMR2
0
0
AN0
0
34tcyc
0
1
AN1
1
67tcyc
1
0
AN2
1
1
AN3
AMR0
Conversion time
Figure 82 A/D Mode Register (AMR)
ADRU: $018
3
2
1
ADRL: $017
0
3
1
0
MSB
LSB
Bit 7
Bit 0
Figure 83 A/D Data Registers
98
2
HD404449 Series
A/D data register (lower digit) (ADRL: $017)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
R
R
R
R
ADRL3
ADRL2
ADRL1
ADRL0
Bit name
Figure 84 A/D Data Register Lower Digit (ADRL)
A/D data register (upper digit) (ADRU: $018)
Bit
3
2
1
0
Initial value
1
0
0
0
Read/Write
R
R
R
R
ADRU3
ADRU2
Bit name
ADRU1 ADRU0
Figure 85 A/D Data Register Upper Digit (ADRU)
99
HD404449 Series
A/D start flag (ADSF: $020, bit 2)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
DTON
ADSF
WDON
LSON
Bit name
LSON
Refer to the description of operating
modes
WDON
Refer to the description of timers
ADSF (A/D start flag)
1
A/D conversion started
0
A/D conversion completed
DTON
Refer to the description of operating
modes
Figure 86 A/D Start Flag (ADSF)
100
HD404449 Series
Notes on Mounting
Assemble all parts including the HD404449 Series on a board, noting the points described below.
1. Connect layered ceramic type capacitors (about 0.1 µF) between AVCC and AVSS , between VCC and
GND, and between used analog pins and AVSS .
2. Connect unused analog pins to AVSS .
• When not using an A/D converter
VCC
AVCC
AN 0
0.1 µF
AN 1
AN 2
AN 3
AVSS
GND
• When using pins AN0 and AN1 but not using AN2 and AN3
AVCC
VCC
AN 0
AN 1
AN 2
AN 3
AVSS
GND
0.1 µF × 3
• When using all analog pins
VCC
AVCC
AN 0
AN 1
AN 2
AN 3
GND
AVSS
0.1 µF × 5
Figure 87 Example of Connections (1)
101
HD404449 Series
Between the VCC and GND lines, connect capacitors designed for use in ordinary power supply circuits.
An example connection is described in figure 88.
No resistors can be inserted in series in the power supply circuit, so the capacitors should be connected in
parallel. The capacitors are a large capacitance C1 and a small capacitance C2.
VCC
VCC
C1
GND
C2
GND
Figure 88 Example of Connections (2)
102
HD404449 Series
Programmable ROM (HD4074449)
The HD4074449 is a ZTAT microcomputer with built-in PROM that can be programmed in PROM
mode.
PROM Mode Pin Description
MCU Mode
PROM Mode
Pin No. Pin Name
I/O
Pin Name
1
AN 2
2
AN 3
3
AVSS
4
TEST
I
TEST
5
OSC 1
I
VCC
6
OSC 2
O
7
RESET
I
RESET
8
X1
I
GND
9
X2
O
10
GND
11
D0
I/O
CE
12
D1
I/O
OE
13
D2
I/O
14
D3
I/O
15
D4
16
D5
17
MCU Mode
I/O
PROM Mode
Pin No.
Pin Name
I/O
Pin Name
I/O
I
31
R1 2
I/O
A7
I
I
32
R1 3
I/O
A8
I
GND
33
R2 0
I/O
A0
I
34
R2 1
I/O
A10
I
35
R2 2
I/O
A11
I
36
R2 3
I/O
A12
I
37
R3 0/TOB
I/O
38
R3 1/TOC
I/O
39
R3 2/TOD
I/O
40
R3 3/EVNB
I/O
I
41
R4 0/EVND
I/O
I
42
R4 1/SCK 1
I/O
VCC
43
R4 2/SI1
I/O
VCC
44
R4 3/SO 1
I/O
I/O
45
R5 0
I/O
I/O
46
R5 1/SCK 2
I/O
D6
I/O
47
R5 2/SI2
I/O
18
D7
I/O
48
R5 3/SO 2
I/O
19
D8
I/O
49
R6 0
I/O
A1
I
20
D9
I/O
50
R6 1
I/O
A2
I
21
D10
I/O
A13
I
51
R6 2
I/O
A3
I
22
D11
I/O
A14
I
52
R6 3
I/O
A4
I
23
D12/STOPC I
A9
I
53
R7 0
I/O
O0
I/O
24
D13/INT0
I
VPP
54
R7 1
I/O
O1
I/O
25
R0 0/INT1
I/O
M0
I
55
R7 2
I/O
O2
I/O
26
R0 1/INT2
I/O
M1
I
56
R7 3
I/O
O3
I/O
27
R0 2/INT3
I/O
57
R8 0
I/O
O4
I/O
28
R0 3
I/O
58
R8 1
I/O
O5
I/O
29
R1 0
I/O
A5
I
59
R8 2
I/O
O6
I/O
30
R1 1
I/O
A6
I
60
R8 3
I/O
O7
I/O
I
I
GND
103
HD404449 Series
MCU Mode
PROM Mode
MCU Mode
PROM Mode
Pin No. Pin Name
I/O
Pin Name
I/O
Pin No.
Pin Name
I/O
Pin Name
61
R9 0
I/O
O4
I/O
71
RB 2
I/O
62
R9 1
I/O
O3
I/O
72
RB 3
I/O
63
R9 2
I/O
O2
I/O
73
RC0
I/O
64
R9 3
I/O
O1
I/O
74
RC1
I/O
65
RA 0
I/O
O0
I/O
75
RC2
I/O
66
RA 1
I/O
VCC
76
RC3
I/O
67
RA 2
I/O
77
VCC
VCC
68
RA 3
I/O
78
AVCC
VCC
69
RB 0
I/O
79
AN 0
I
70
RB 1
I/O
80
AN 1
I
Notes: 1. I/O: Input/output pin, I: Input pin, O: Output pin
2. Each of O0–O4 has two pins; before using, each pair must be connected together.
104
I/O
HD404449 Series
Programming the Built-In PROM
The MCU’s built-in PROM is programmed in PROM mode. PROM mode is set by pulling TEST, M0, and
M1 low, and RESET high as shown in figure 89. In PROM mode, the MCU does not operate, but it can be
programmed in the same way as any other commercial 27256-type EPROM using a standard PROM
programmer and an 80-to-28-pin socket adapter. Recommended PROM programmers and socket adapters
of the HD4074449 are listed in table 31.
Since an HMCS400-series instruction is ten bits long, the HMCS400-series MCU has a built-in conversion
circuit to enable the use of a general-purpose PROM programmer. This circuit splits each instruction into
five lower bits and five upper bits that are read from or written to consecutive addresses. This means that
if, for example, 16 kwords of built-in PROM are to be programmed by a general-purpose PROM
programmer, a 32-kbyte address space ($0000–$7FFF) must be specified.
Warnings
1. Always specify addresses $0000 to $7FFF when programming with a PROM programmer. If address
$8000 or higher is accessed, the PROM may not be programmed or verified correctly. Set all data in
unused addresses to $FF.
Note that the plastic-package version cannot be erased or reprogrammed.
2. Make sure that the PROM programmer, socket adapter, and LSI are aligned correctly (their pin 1
positions match), otherwise overcurrents may damage the LSI. Before starting programming, make
sure that the LSI is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the
programmer.
3. PROM programmers have two voltages (VPP): 12.5 V and 21 V. Remember that ZTAT devices
require a VPP of 12.5 V—the 21-V setting will damage them. 12.5 V is the Intel 27256 setting.
Programming and Verification
The built-in PROM of the MCU can be programmed at high speed without risk of voltage stress or damage
to data reliability.
Programming and verification modes are selected as listed in table 30.
For details of PROM programming, refer to the following section, Notes on PROM Programming.
Table 30
PROM Mode Selection
Pin
Mode
CE
OE
VPP
O0–O7
Programming
Low
High
VPP
Data input
Verification
High
Low
VPP
Data output
Programming inhibited
High
High
VPP
High impedance
105
HD404449 Series
Table 31
Recommended PROM Programmers and Socket Adapters
PROM Programmer
Socket Adapter
Manufacturer
Model Name
Manufacturer
Package
Model Name
DATA I/O Corp.
121B
Hitachi
FP-80A
HS444ESH01H
TFP-80F
HS4449ESN01H
FP-80A
HS444ESH01H
TFP-80F
HS4449ESN01H
29B
AVAL Corp.
PKW-1000
Hitachi
VCC
VCC
AVCC
VCC
VCC
RESET
TEST
M0
VPP
M1
O0 to O7
Data
O0 to O7
A0 to A14
Address
A0 to A14
VPP
HD4074449
VCC
OSC1
D2
D3
RA1
X1
AVSS
GND
Figure 89 PROM Mode Connections
106
OE
OE
CE
CE
HD404449 Series
Addressing Modes
RAM Addressing Modes
The MCU has three RAM addressing modes, as shown in figure 90 and described below.
W register
W1 W0
RAM address
X register
X3
X2
X1
Y register
X0
Y3
Y2
Y1
Y0
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Register Direct Addressing
1st word of Instruction
Opcode
2nd word of Instruction
d
RAM address
9
d8
d7
d6
d5
d4
d3
d2
d1
d0
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Direct Addressing
Instruction
Opcode
0
RAM address
0
0
1
m3 m2
0
m1
m0
0
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Memory Register Addressing
Figure 90 RAM Addressing Modes
Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used
as a RAM address. When the area from $090 to $25F is used, a bank must be selected by the bank register
(V: $03F).
Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains
the opcode, and the contents of the second word (10 bits) are used as a RAM address.
107
HD404449 Series
Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses
from $040 to $04F, are accessed with the LAMR and XMRA instructions.
ROM Addressing Modes and the P Instruction
The MCU has four ROM addressing modes, as shown in figure 91 and described below.
Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing
the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits
(PC 13–PC0) with 14-bit immediate data.
Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program
can branch to any address in the current page by executing the BR instruction. This instruction replaces the
eight low-order bits of the program counter (PC7–PC0) with eight-bit immediate data. If the BR instruction
is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next
physical page, as shown in figure 93. This means that the execution of the BR instruction on a page
boundary will make the program branch to the next page.
Note that the HMCS400-series cross macroassembler has an automatic paging feature for ROM pages.
Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000–
$003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data
are placed in the six low-order bits of the program counter (PC5–PC0), and 0s are placed in the eight highorder bits (PC13–PC6).
Table Data Addressing Mode: A program can branch to an address determined by the contents of fourbit immediate data, the accumulator, and the B register by executing the TBR instruction.
P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction
as shown in figure 92. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator
and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers.
If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and
R2 port output registers at the same time.
The P instruction has no effect on the program counter.
108
HD404449 Series
1st word of instruction
[JMPL]
[BRL]
[CALL]
Opcode
p3
Program counter
2nd word of instruction
p2
p1
p0
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Direct Addressing
Instruction
[BR]
Program counter
Opcode
b7
b6
b5
b4
b3
b2
b1
b0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Current Page Addressing
Instruction
[CAL]
0
Program counter
0
0
0
d5
Opcode
0
0
0
d4
d3
d2
d1
d0
0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Zero Page Addressing
Instruction
[TBR]
Opcode
p3
p2
p1
p0
B register
B3
0
Program counter
B2 B1
Accumulator
B0
A3
A2
A1
A0
0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Table Data Addressing
Figure 91 ROM Addressing Modes
109
HD404449 Series
Instruction
[P]
Opcode
p3
p2
p1
p0
B register
B3
0
B2 B1
Accumulator
B0
A3
A2
A1
A0
0
Referenced ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0
Address Designation
ROM data
RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Accumulator, B register
ROM data
B3
B2
B1
B0
A3 A
2
A1
A
0
If RO 8 = 1
RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Output registers R1, R2
R23 R22 R21 R20 R13 R12 R11 R10
If RO 9 = 1
Pattern Output
Figure 92 P Instruction
256 (n – 1) + 255
BR
AAA
256n
AAA
BBB
256n + 254
256n + 255
256 (n + 1)
NOP
BR
BR
BBB
AAA
NOP
Figure 93 Branching when the Branch Destination is on a Page Boundary
110
HD404449 Series
Absolute Maximum Ratings
Item
Symbol
Value
Unit
Supply voltage
VCC
–0.3 to +7.0
V
Programming voltage
VPP
–0.3 to +14.0
V
Pin voltage
VT
–0.3 to (VCC + 0.3) V
Total permissible input current
∑Io
100
mA
2
Total permissible output current
–∑Io
50
mA
3
Maximum input current
Io
4
mA
4, 5
30
mA
4, 6
7, 8
Maximum output current
–I o
4
mA
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +125
°C
Notes
1
Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal opera-tion
must be under the conditions stated in the electrical characteristics tables. If these conditions are
exceeded, the LSI may malfunction or its reliability may be affected.
1. Applies to D 13 (VPP) of the HD4074449.
2. The total permissible input current is the total of input currents simultaneously flowing in from all
the I/O pins to ground.
3. The total permissible output current is the total of output currents simultaneously flowing out from
VCC to all I/O pins.
4. The maximum input current is the maximum current flowing from each I/O pin to ground.
5. Applies to D 10 , D11, and R0–RC.
6. Applies to D 0–D 9.
7. The maximum output current is the maximum current flowing out from V CC to each I/O pin.
8. Applies to D 0–D 11 and R0–RC.
111
HD404449 Series
Electrical Characteristics
DC Characteristics (HD404448, HD404449: VCC = 2.7 to 6.0 V, GND = 0 V, T a = –20°C to +75°C;
HD4074449: V CC = 2.7 to 5.5 V, GND = 0 V, T a = –20°C to +75°C, unless otherwise specified)
Item
Symbol
Pin(s)
Min
Typ
Max
Unit
Test Condition
Notes
Input high
voltage
VIH
RESET, STOPC,
0.9V CC
—
VCC + 0.3
V
—
OSC 1
VCC – 0.3
—
VCC + 0.3
V
External clock
operation
RESET, STOPC,
–0.3
—
0.1V CC
V
—
OSC 1
–0.3
—
0.3
V
External clock
operation
SCK 1, SO1,
VCC – 1.0
—
—
V
–I OH = 0.5 mA
—
—
0.4
V
I OL = 0.4 mA
—
—
1.0
µA
Vin = 0 V to VCC
1
—
5
9
mA
VCC = 5.0 V,
2
INT0, INT1, INT2,
INT3, SCK 1, SI 1,
SCK 2, SI 2, EVNB,
EVND
Input low
voltage
VIL
INT0, INT1, INT2,
INT3, SCK 1, SI 1,
SCK 2, SI 2, EVNB,
EVND
Output high VOH
voltage
SCK 2, SO2,
TOB, TOC, TOD
Output low VOL
voltage
SCK 1, SO1,
SCK 2, SO2,
TOB, TOC, TOD
I/O leakage | IIL |
current
RESET, STOPC,
INT0, INT1, INT2,
INT3, SCK 1, SI 1,
SCK 2, SI 2, SO1,
SO2, EVNB,
EVND, OSC 1,
TOB, TOC, TOD
I CC1
Current
dissipation
in active
mode
VCC
I CC2
VCC
f OSC = 4 MHz
—
0.6
1.8
mA
VCC = 3.0 V,
f OSC = 800 kHz
112
2
HD404449 Series
Item
Symbol
Pin(s)
Min
Typ
Max
Unit
Test Condition
Notes
Current dissipation
in standby mode
I SBY1
VCC
—
1.2
3
mA
VCC = 5.0 V,
3
f OSC = 4 MHz
I SBY2
VCC
—
0.2
0.7
mA
VCC = 3.0 V,
3
f OSC = 800 kHz
Current dissipation
in subactive mode
I SUB
VCC
—
35
70
µA
VCC = 3.0 V,
4
32-kHz oscillator
—
70
150
µA
VCC = 3.0 V,
5
32-kHz oscillator
Current dissipation
in watch mode
I WTC
Current dissipation
in stop mode
I STOP
VCC
—
8
15
µA
VCC = 3.0 V,
6
32-kHz oscillator
Stop mode retaining VSTOP
voltage
VCC
—
1
10
µA
VCC = 3.0 V,
6
no 32-kHz oscillator
VCC
2
—
—
V
No 32-kHz oscillator
7
Notes: 1. Output buffer current is excluded.
2. I CC1 and I CC2 are the source currents when no I/O current is flowing while the MCU is in reset
state.
Test conditions:
MCU: Reset
Pins:
RESET at V CC (VCC – 0.3 V to VCC)
TEST at V CC (VCC – 0.3 V to VCC)
3. I SBY1 and I SBY2 are the source currents when no I/O current is flowing while the MCU timer is
operating.
Test conditions:
MCU: I/O reset
Serial interface stopped
Standby mode
Pins:
RESET at GND (0 V to 0.3 V)
TEST at V CC (VCC – 0.3 V to VCC)
4. Applies to HD404448 and HD404449.
5. Applies to HD4074449.
6. These are the source currents when no I/O current is flowing.
Test conditions:
Pins:
RESET at GND (0 V to 0.3 V)
TEST at V CC (VCC – 0.3 V to VCC)
D13 (VPP) at V CC (VCC – 0.3 V to VCC) for the HD4074449
7. RAM data retention.
113
HD404449 Series
I/O Characteristics for Standard Pins (HD404448, HD404449: VCC = 2.7 to 6.0 V, GND = 0 V, T a = –
20°C to +75°C; HD4074449: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise
specified)
Item
Symbol
Pin(s)
Min
Typ
Max
Unit
Test Condition
Notes
Input high
voltage
VIH
D10–D 13 ,
0.7V CC
—
VCC + 0.3 V
—
Input low
voltage
VIL
–0.3
—
0.3V CC
V
—
Output high
voltage
VOH
VCC – 1.0 —
—
V
–I OH = 0.5 mA
Output low
voltage
VOL
—
—
0.4
V
I OL = 0.4 mA
I/O leakage
current
IIL
—
—
1
µA
Vin = 0 V to VCC
1, 2
—
—
1
µA
Vin = 0 V to VCC
1, 3
D13
—
—
1
µA
Vin = VCC – 0.3 V to VCC 1, 3
D13
—
—
20
µA
Vin = 0 V to 0.3 V
D10, D11,
5
30
90
µA
VCC = 3.0 V,
R0–RC
D10–D 13 ,
R0–RC
D10, D11,
R0–RC
D10, D11,
R0–RC
D10–D 13 ,
R0–RC
D10–D 12 ,
R0–RC
Pull-up MOS –I PU
current
R0–RC
Notes: 1. Output buffer current is excluded.
2. Applies to HD404448 and HD404449.
3. Applies to HD4074449.
114
Vin = 0 V
1, 3
HD404449 Series
I/O Characteristics for High-Current Pins (HD404448, HD404449: VCC = 2.7 to 6.0 V, GND = 0 V, Ta
= –20°C to +75°C; HD4074449: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise
specified)
Item
Symbol
Pin(s)
Min
Typ
Max
Input high voltage
VIH
D0–D 9
0.7V CC
—
VCC + 0.3 V
—
Input low voltage
VIL
D0–D 9
–0.3
—
0.3V CC
V
—
Output high voltage VOH
D0–D 9
VCC – 1.0 —
—
V
–I OH = 0.5 mA
Output low voltage
D0–D 9
—
—
0.4
V
I OL = 0.4 mA
—
—
2.0
V
I OL = 15 mA,
VOL
Unit
Test Condition
Notes
VCC ≥ 4.5 V
IIL
D0–D 9
—
—
1
µA
Vin = 0 V to VCC
Pull-up MOS current –I PU
D0–D 9
5
30
90
µA
VCC = 3.0 V,
I/O leakage current
1
Vin = 0 V
Notes: 1. Output buffer current is excluded.
A/D Converter Characteristics (HD404448, HD404449: V CC = 2.7 to 6.0 V, GND = 0 V, Ta = –20°C to
+75°C; HD4074449: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified)
Item
Symbol
Pin(s)
Min
Typ
Analog power
voltage
AVCC
AVCC
VCC – 0.3 VCC
Analog input
voltage
AVin
AN 0–AN 3 AVSS
Current between
AVCC and AVSS
I AD
—
Analog input
capacitance
Max
Unit
Test Condition
Notes
VCC + 0.3 V
—
1
—
AVCC
V
—
—
50
150
µA
VCC = AVCC = 5.0 V
CA in
AN 0–AN 3 —
15
—
pF
—
Resolution
—
—
8
8
8
Bit
Number of inputs
—
—
0
—
4
Channel
—
Absolute accuracy —
—
—
—
± 2.0
LSB
Ta = 25°C,
VCC = 4.5 V to 5.5 V
Conversion time
—
—
34
Input impedance
—
AN 0–AN 3 1
—
67
t cyc
—
—
—
MΩ
f OSC = 1 MHz,
Vin = 0 V
Note:
1. AVCC ≥ 2.7 V
115
HD404449 Series
AC Characteristics (HD404448, HD404449: VCC = 2.7 to 6.0 V, GND = 0 V, T a = –20°C to +75°C;
HD4074449: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified)
Item
Symbol
Pin(s)
Min Typ
Max Unit
Test Condition
Notes
Clock oscillation
frequency
f OSC
OSC 1, OSC 2
0.4
4.0
MHz
1/4 division
1
X1, X2
—
32.768 —
kHz
—
t cyc
—
1.0
—
10
µs
—
t subcyc
—
—
244.14 —
µs
32-kHz oscillator,
Instruction cycle
time
1
1/8 division
—
122.07 —
µs
32-kHz oscillator,
1/4 division
Oscillation
stabilization time
(ceramic)
t RC
OSC 1, OSC 2
—
—
7.5
ms
—
2
Oscillation
stabilization time
(crystal)
t RC
OSC 1, OSC 2
—
—
40
ms
HD404448, HD404449
VCC=3.0 to 6.0V
HD4074449
VCC=3.5 to 5.5V
2
—
—
60
ms
—
2
X1, X2
—
—
3
s
Ta = –10°C to +60°C
3
External clock high t CPH
width
OSC 1
105 —
—
ns
—
4
External clock low t CPL
width
OSC 1
105 —
—
ns
—
4
External clock rise t CPr
time
OSC 1
—
—
20
ns
—
4
External clock fall
time
OSC 1
—
—
20
ns
—
4
INT0–INT3, EVNB, t IH
EVND high widths
INT0–INT3,
2
—
—
t cyc /
—
5
INT0–INT3, EVNB, t IL
EVND low widths
INT0–INT3,
—
5
RESET high width t RSTH
RESET
2
—
—
t cyc
—
6
STOPC low width
t STPL
STOPC
1
—
—
t RC
—
7
RESET fall time
t RSTf
RESET
—
—
20
ms
—
6
STOPC rise time
t STPr
STOPC
—
—
20
ms
—
7
116
t CPf
EVNB, EVND
t subcyc
2
—
—
EVNB, EVND
t cyc /
t subcyc
HD404449 Series
Item
Symbol
Pin(s)
Input capacitance
Cin
Min
Typ
Max
Unit
Test Condition
All pins except D13 —
—
15
pF
f = 1 MHz, Vin = 0 V
D13
—
15
pF
HD404448,
—
Notes
HD404449:
f = 1 MHz,
Vin = 0 V
—
—
180
pF
HD4074449:
f = 1 MHz,
Vin = 0 V
Notes: 1. If the 32.768-kHz oscillator is used for the subsystem oscillator, f OSC must be set as 0.4 MHz ≤
f OSC ≤ 1.0 MHz or 1.6 MHz ≤ fOSC ≤ 4.0 MHz, and bit 1 of the system clock selector register (SSR:
$029) must be set to 0 or 1, respectively.
2. The oscillation stabilization time is the period required for the oscillator to stabilize after V CC
reaches 2.7 V at power-on, or after RESET input goes high or STOPC input goes low when stop
mode is cancelled. At power-on or when stop mode is cancelled, RESET or STOPC must be
input for at least tRC to ensure the oscillation stabilization time. If using a ceramic oscillator,
contact its manufacturer to determine what stabilization time is required, since it will depend on
the circuit constants and stray capacitances. Set bits 0 and 1 (MIS0, MIS1) of the miscellaneous
register (MIS: $00C) according to the system oscillation of the oscillation stabilization time.
3. The oscillation stabilization time is the period required for the oscillator to stabilize after V CC
reaches 2.7 V at power-on, or after RESET input goes high or STOPC input goes low when the
32-kHz oscillator stops in stop mode and stop mode is cancelled. If using a crystal oscillator,
contact its manufacturer to determine what stabilization time is required, since it will depend on
the circuit constants and stray capacitances.
4. Refer to figure 94.
5. Refer to figure 95. The t cyc unit applies when the MCU is in standby or active mode. The tsubcyc
unit applies when the MCU is in watch or subactive mode.
6. Refer to figure 96.
7. Refer to figure 97.
117
HD404449 Series
Serial Interface Timing Characteristics (HD404448, HD404449: VCC = 2.7 to 6.0 V, GND = 0 V, Ta = –
20°C to +75°C; HD4074449: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise
specified)
During Transmit Clock Output
Item
Symbol Pin
Transmit clock cycle
time
t Scyc
Transmit clock high
width
Transmit clock low
width
Typ
Max
Unit
Test Condition
SCK 1, SCK 2 1.0
—
—
t cyc
Load shown in figure 99 1
t SCKH
SCK 1, SCK 2 0.5
—
—
t Scyc
Load shown in figure 99 1
t SCKL
SCK 1, SCK 2 0.5
—
—
t Scyc
Load shown in figure 99 1
Transmit clock rise time t SCKr
SCK 1, SCK 2 —
—
200
ns
Load shown in figure 99 1
Transmit clock fall time
SCK 1, SCK 2 —
—
200
ns
Load shown in figure 99 1
Serial output data delay t DSO
time
SO1, SO2
—
—
500
ns
Load shown in figure 99 1
Serial input data setup
time
t SSI
SI 1, SI 2
300
—
—
ns
—
1
Serial input data hold
time
t HSI
SI 1, SI 2
300
—
—
ns
—
1
Min
Typ
Max Unit
Test Condition
Note
Note:
t SCKf
Min
Note
1. Refer to figure 98.
During Transmit Clock Input
Item
Symbol Pin
Transmit clock cycle
time
t Scyc
SCK 1, SCK 2 1.0
—
—
t cyc
—
1
Transmit clock high
width
t SCKH
SCK 1, SCK 2 0.5
—
—
t Scyc
—
1
Transmit clock low
width
t SCKL
SCK 1, SCK 2 0.5
—
—
t Scyc
—
1
Transmit clock rise time t SCKr
SCK 1, SCK 2 —
—
200
ns
—
1
Transmit clock fall time
SCK 1, SCK 2 —
—
200
ns
—
1
Serial output data delay t DSO
time
SO1, SO2
—
—
500
ns
Load shown in figure 99 1
Serial input data setup
time
t SSI
SI 1, SI 2
300
—
—
ns
—
1
Serial input data hold
time
t HSI
SI 1, SI 2
300
—
—
ns
—
1
Note:
118
t SCKf
1. Refer to figure 98.
HD404449 Series
1/fCP
OSC1
VCC – 0.3 V
0.3 V
tCPL
tCPH
tCPr
tCPf
Figure 94 External Clock Timing
INT0 to INT3,
EVNB, EVND
0.9VCC
0.1VCC
tIH
tIL
Figure 95 Interrupt Timing
RESET
0.9VCC
0.1VCC
tRSTH
tRSTf
Figure 96 Reset Timing
STOPC
0.9VCC
tSTPL
0.1VCC
tSTPr
Figure 97 STOPC Timing
119
HD404449 Series
t Scyc
t SCKf
SCK 1 VCC – 2.0 V (0.9VCC )*
0.4 V (0.1VCC)*
SCK 2
t SCKr
t SCKL
t SCKH
t DSO
VCC – 0.5 V
0.4 V
SO1
SO2
t SSI
t HSI
0.9V CC
0.1VCC
SI1
SI2
Note: * VCC – 2.0 V and 0.4 V are the threshold voltages for transmit clock output, and
0.9VCC and 0.1VCC are the threshold voltages for transmit clock input.
Figure 98 Serial Interface Timing
VCC
RL = 2.6 kΩ
Test
point
C=
30 pF
R=
12 kΩ
1S2074 H
or equivalent
Figure 99 Timing Load Circuit
120
HD404449 Series
Notes on ROM Out
Please pay attention to the following items regarding ROM out.
On ROM out, fill the ROM area indicated below with 1s to create the same data size as a 16-kword version
(HD404449). A 16-kword data size is required to change ROM data to mask manufacturing data since the
program used is for a16-kword version.
This limitation applies when using an EPROM or a data base.
ROM 8-kword version:
HD404448
Address $2000–$3FFF
$0000
Vector address
$000F
$0010
Zero-page subroutine
(64 words)
$003F
$0040
Pattern & program
(8,192 words)
$1FFF
$2000
Not used
$3FFF
Fill this area with 1s
121
HD404449 Series
HD404448, HD404449 Option List
Please check off the appropriate applications and enter the necessary information.
Date of order
Customer
1. ROM size
Department
HD404448
8-kword
Name
HD404449
16-kword
ROM code name
LSI number
HD40444
2. Optional Functions
*
With 32-kHz CPU operation, with time-base for clock
*
Without 32-kHz CPU operation, with time-base for clock
Without 32-kHz CPU operation, without time-base
Note: * Options marked with an asterisk require a subsystem crystal oscillator (X1, X2).
3. ROM code media
Please specify the first type below (the upper bits and lower bits are mixed together), when using
the EPROM on-package microcomputer type (including ZTAT™ version).
EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits
are programmed to the same EPROM in alternating order (i.e., LULULU...).
EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are
programmed to different EPROMS.
4. Oscillator for OSC1 and OSC2
Ceramic oscillator
f=
MHz
Crystal oscillator
f=
MHz
External clock
f=
MHz
5. Stop mode
Used
Not used
6. Package
FP-80A
TFP-80F
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HD404449 Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
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Japan
: http://www.hitachi.co.jp/Sicd/indx.htm
For further information write to:
Hitachi Semiconductor
(America) Inc.
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Tel: <1> (408) 433-1990
Fax: <1>(408) 433-0223
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Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
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Electronic Components Group.
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Tun-Hwa North Road, Taipei (105)
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Fax: <886> (2) 2718-8180
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Telex: 40815 HITEC HX
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
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