Renesas HD64F36054 Renesas 16-bit single-chip microcomputer h8 family/h8/300h tiny sery Datasheet

REJ09B0026-0400
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
16
H8/36057Group, H8/36037Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8 Family/H8/300H Tiny Series
H8/36057
H8/36054
H8/36037
H8/36036
H8/36035
H8/36034
H8/36033
H8/36032
HD64F36057,
HD64336057,
HD64F36054,
HD64336054,
HD64F36037,
HD64336037,
HD64336036,
HD64336035,
HD64F36034,
HD64336034,
HD64336033,
HD64336032,
Rev.4.00
Revision Date: Mar. 15, 2006
HD64F36057G
HD64336057G
HD64F36054G
HD64336054G
HD64F36037G
HD64336037G
HD64336036G
HD64336035G
HD64F36034G
HD64336034G
HD64336033G
HD64336032G
Rev. 4.00 Mar. 15, 2006 Page ii of xxxii
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.
Rev. 4.00 Mar. 15, 2006 Page iii of xxxii
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product’s state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system’s
operation is not guaranteed if they are accessed.
Rev. 4.00 Mar. 15, 2006 Page iv of xxxii
Configuration of This Manual
This manual comprises the following items:
1.
2.
3.
4.
5.
6.
General Precautions on Handling of Product
Configuration of This Manual
Preface
Contents
Overview
Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 4.00 Mar. 15, 2006 Page v of xxxii
Preface
The H8/36057 Group and H8/36037 Group are single-chip microcomputers made up of the highspeed H8/300H CPU employing Renesas Technology-original architecture as their cores, and the
peripheral functions required to configure a system. The H8/300H CPU has an instruction set that
is compatible with the H8/300 CPU.
Target Users: This manual was written for users who will be using the H8/36057 Group and
H8/36037 Group in the design of application systems. Target users are expected to
understand the fundamentals of electrical circuits, logical circuits, and
microcomputers.
Objective:
This manual was written to explain the hardware functions and electrical
characteristics of the H8/36057 Group and H8/36037 Group to the target users.
Refer to the H8/300H Series Software Manual for a detailed description of the
instruction set.
Notes on reading this manual:
• In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions, and electrical characteristics.
• In order to understand the details of the CPU's functions
Read the H8/300H Series Software Manual.
• In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 21,
List of Registers.
Example:
Register name:
Bit order:
Rev. 4.00 Mar. 15, 2006 Page vi of xxxii
The following notation is used for cases when the same or a
similar function, e.g. serial communication interface, is
implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
The MSB is on the left and the LSB is on the right.
Notes:
When using an on-chip emulator (E7, E8) for H8/36057 and H8/36037 program development and
debugging, the following restrictions must be noted.
1. The NMI pin is reserved for the E7 or E8, and cannot be used.
2. Pins P85, P86, and P87 cannot be used. In order to use these pins, additional hardware must be
provided on the user board.
3. Area H'D000 to H'DFFF is used by the E7 or E8, and is not available to the user.
4. Area H'F780 to H'FB7F must on no account be accessed.
5. When the E7 or E8 is used, address breaks can be set as either available to the user or for use
by the E7 or E8. If address breaks are set as being used by the E7 or E8, the address break
control registers must not be accessed.
6. When the E7 or E8 is used, NMI is an input/output pin (open-drain in output mode), P85 and
P87 are input pins, and P86 is an output pin.
7. In on-board programming mode by boot mode, channel 1 (P21/RXD and P22/TXD) for SCI3
is used.
Related Manuals:
The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/
H8/36057 Group and H8/36037 Group manuals:
Document Title
Document No.
H8/36057 Group, H8/36037 Group Hardware Manual
This manual
H8/300H Series Software Manual
REJ09B0213
User's manuals for development tools:
Document Title
Document No.
H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor
User's Manual
REJ10B0058
H8S, H8/300 Series Simulator/Debugger User's Manual
REJ10B0211
H8S, H8/300 Series High-Performance Embedded Workshop 3 Tutorial
REJ10B0024
H8S, H8/300 Series High-Performance Embedded Workshop 3 User's Manual REJ10B0026
Rev. 4.00 Mar. 15, 2006 Page vii of xxxii
Application notes:
Document Title
Document No.
H8S, H8/300 Series C/C++ Compiler Package Application Note
TM
Single Power Supply F-ZTAT On-Board Programming
Rev. 4.00 Mar. 15, 2006 Page viii of xxxii
REJ05B0464
REJ05B0520
Contents
Section 1 Overview................................................................................................1
1.1
1.2
1.3
1.4
Features................................................................................................................................. 1
Internal Block Diagram......................................................................................................... 3
Pin Arrangement ................................................................................................................... 4
Pin Functions ........................................................................................................................ 5
Section 2 CPU........................................................................................................9
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Address Space and Memory Map ....................................................................................... 10
Register Configuration........................................................................................................ 14
2.2.1
General Registers................................................................................................ 15
2.2.2
Program Counter (PC) ........................................................................................ 16
2.2.3
Condition-Code Register (CCR)......................................................................... 16
Data Formats....................................................................................................................... 18
2.3.1
General Register Data Formats ........................................................................... 18
2.3.2
Memory Data Formats ........................................................................................ 20
Instruction Set ..................................................................................................................... 21
2.4.1
Table of Instructions Classified by Function ...................................................... 21
2.4.2
Basic Instruction Formats ................................................................................... 31
Addressing Modes and Effective Address Calculation....................................................... 32
2.5.1
Addressing Modes .............................................................................................. 32
2.5.2
Effective Address Calculation ............................................................................ 36
Basic Bus Cycle .................................................................................................................. 38
2.6.1
Access to On-Chip Memory (RAM, ROM)........................................................ 38
2.6.2
On-Chip Peripheral Modules .............................................................................. 39
CPU States .......................................................................................................................... 40
Usage Notes ........................................................................................................................ 42
2.8.1
Notes on Data Access to Empty Areas ............................................................... 42
2.8.2
EEPMOV Instruction.......................................................................................... 42
2.8.3
Bit-Manipulation Instruction .............................................................................. 42
Section 3 Exception Handling .............................................................................49
3.1
3.2
Exception Sources and Vector Address .............................................................................. 50
Register Descriptions.......................................................................................................... 52
3.2.1
Interrupt Edge Select Register 1 (IEGR1) .......................................................... 52
3.2.2
Interrupt Edge Select Register 2 (IEGR2) .......................................................... 53
3.2.3
Interrupt Enable Register 1 (IENR1) .................................................................. 54
Rev. 4.00 Mar. 15, 2006 Page ix of xxxii
3.3
3.4
3.5
3.2.4
Interrupt Enable Register 2 (IENR2) .................................................................. 55
3.2.5
Interrupt Flag Register 1 (IRR1)......................................................................... 55
3.2.6
Interrupt Flag Register 2 (IRR2)......................................................................... 57
3.2.7
Wakeup Interrupt Flag Register (IWPR) ............................................................ 57
Reset Exception Handling .................................................................................................. 59
Interrupt Exception Handling ............................................................................................. 60
3.4.1
External Interrupts .............................................................................................. 60
3.4.2
Internal Interrupts ............................................................................................... 61
3.4.3
Interrupt Handling Sequence .............................................................................. 62
3.4.4
Interrupt Response Time..................................................................................... 63
Usage Notes ........................................................................................................................ 65
3.5.1
Interrupts after Reset........................................................................................... 65
3.5.2
Notes on Stack Area Use .................................................................................... 65
3.5.3
Notes on Rewriting Port Mode Registers ........................................................... 65
Section 4 Address Break ..................................................................................... 67
4.1
4.2
Register Descriptions.......................................................................................................... 68
4.1.1
Address Break Control Register (ABRKCR) ..................................................... 68
4.1.2
Address Break Status Register (ABRKSR) ........................................................ 70
4.1.3
Break Address Registers (BARH, BARL).......................................................... 70
4.1.4
Break Data Registers (BDRH, BDRL) ............................................................... 70
Operation ............................................................................................................................ 71
Section 5 Clock Pulse Generators ....................................................................... 73
5.1
5.2
5.3
System Clock Generator ..................................................................................................... 74
5.1.1
Connecting Crystal Resonator ............................................................................ 74
5.1.2
Connecting Ceramic Resonator .......................................................................... 75
5.1.3
External Clock Input Method.............................................................................. 75
Prescaler.............................................................................................................................. 76
5.2.1
Prescaler S .......................................................................................................... 76
Usage Notes ........................................................................................................................ 76
5.3.1
Note on Resonators............................................................................................. 76
5.3.2
Notes on Board Design ....................................................................................... 76
Section 6 Power-Down Modes............................................................................ 77
6.1
Register Descriptions.......................................................................................................... 78
6.1.1
System Control Register 1 (SYSCR1) ................................................................ 78
6.1.2
System Control Register 2 (SYSCR2) ................................................................ 79
6.1.3
Module Standby Control Register 1 (MSTCR1) ................................................ 80
6.1.4
Module Standby Control Register 2 (MSTCR2) ................................................ 81
Rev. 4.00 Mar. 15, 2006 Page x of xxxii
6.2
6.3
6.4
6.5
Mode Transitions and States of LSI.................................................................................... 82
6.2.1
Sleep Mode ......................................................................................................... 84
6.2.2
Standby Mode ..................................................................................................... 84
6.2.3
Subsleep Mode.................................................................................................... 85
6.2.4
Subactive Mode .................................................................................................. 85
Operating Frequency in Active Mode................................................................................. 86
Direct Transition ................................................................................................................. 86
6.4.1
Direct Transition from Active Mode to Subactive Mode.................................... 86
6.4.2
Direct Transition from Subactive Mode to Active Mode.................................... 87
Module Standby Function................................................................................................... 87
Section 7 ROM ....................................................................................................89
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Block Configuration ........................................................................................................... 89
Register Descriptions.......................................................................................................... 91
7.2.1
Flash Memory Control Register 1 (FLMCR1).................................................... 91
7.2.2
Flash Memory Control Register 2 (FLMCR2).................................................... 92
7.2.3
Erase Block Register 1 (EBR1) .......................................................................... 93
7.2.4
Flash Memory Power Control Register (FLPWCR) ........................................... 94
7.2.5
Flash Memory Enable Register (FENR) ............................................................. 94
On-Board Programming Modes.......................................................................................... 95
7.3.1
Boot Mode .......................................................................................................... 96
7.3.2
Programming/Erasing in User Program Mode.................................................... 98
Flash Memory Programming/Erasing............................................................................... 100
7.4.1
Program/Program-Verify .................................................................................. 100
7.4.2
Erase/Erase-Verify............................................................................................ 103
7.4.3
Interrupt Handling when Programming/Erasing Flash Memory....................... 103
Program/Erase Protection ................................................................................................. 105
7.5.1
Hardware Protection ......................................................................................... 105
7.5.2
Software Protection........................................................................................... 105
7.5.3
Error Protection................................................................................................. 105
Programmer Mode ............................................................................................................ 106
Power-Down States for Flash Memory............................................................................. 106
Section 8 RAM ..................................................................................................109
Section 9 I/O Ports .............................................................................................111
9.1
Port 1................................................................................................................................. 111
9.1.1
Port Mode Register 1 (PMR1) .......................................................................... 112
9.1.2
Port Control Register 1 (PCR1) ........................................................................ 113
9.1.3
Port Data Register 1 (PDR1)............................................................................. 113
Rev. 4.00 Mar. 15, 2006 Page xi of xxxii
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.1.4
Port Pull-Up Control Register 1 (PUCR1)........................................................ 114
9.1.5
Pin Functions .................................................................................................... 114
Port 2................................................................................................................................. 116
9.2.1
Port Control Register 2 (PCR2) ........................................................................ 117
9.2.2
Port Data Register 2 (PDR2) ............................................................................ 117
9.2.3
Port Mode Register 3 (PMR3) .......................................................................... 118
9.2.4
Pin Functions .................................................................................................... 118
Port 5................................................................................................................................. 120
9.3.1
Port Mode Register 5 (PMR5) .......................................................................... 121
9.3.2
Port Control Register 5 (PCR5) ........................................................................ 122
9.3.3
Port Data Register 5 (PDR5) ............................................................................ 122
9.3.4
Port Pull-Up Control Register 5 (PUCR5)........................................................ 123
9.3.5
Pin Functions .................................................................................................... 123
Port 6................................................................................................................................. 126
9.4.1
Port Control Register 6 (PCR6) ........................................................................ 126
9.4.2
Port Data Register 6 (PDR6) ............................................................................ 127
9.4.3
Pin Functions .................................................................................................... 127
Port 7................................................................................................................................. 131
9.5.1
Port Control Register 7 (PCR7) ........................................................................ 132
9.5.2
Port Data Register 7 (PDR7) ............................................................................ 132
9.5.3
Pin Functions .................................................................................................... 133
Port 8................................................................................................................................. 135
9.6.1
Port Control Register 8 (PCR8) ........................................................................ 135
9.6.2
Port Data Register 8 (PDR8) ............................................................................ 136
9.6.3
Pin Functions .................................................................................................... 136
Port 9................................................................................................................................. 137
9.7.1
Port Control Register 9 (PCR9) ........................................................................ 137
9.7.2
Port Data Register 9 (PDR9) ............................................................................ 138
9.7.3
Pin Functions .................................................................................................... 138
Port B................................................................................................................................ 141
9.8.1
Port Data Register B (PDRB) ........................................................................... 141
Section 10 Timer B1.......................................................................................... 143
10.1
10.2
10.3
10.4
Features............................................................................................................................. 143
Input/Output Pin ............................................................................................................... 144
Register Descriptions........................................................................................................ 145
10.3.1
Timer Mode Register B1 (TMB1) .................................................................... 145
10.3.2
Timer Counter B1 (TCB1)................................................................................ 146
10.3.3
Timer Load Register B1 (TLB1) ...................................................................... 146
Operation .......................................................................................................................... 147
Rev. 4.00 Mar. 15, 2006 Page xii of xxxii
10.5
10.4.1
Interval Timer Operation .................................................................................. 147
10.4.2
Auto-Reload Timer Operation .......................................................................... 147
10.4.3
Event Counter Operation .................................................................................. 147
Timer B1 Operating Modes .............................................................................................. 148
Section 11 Timer V............................................................................................149
11.1
11.2
11.3
11.4
11.5
11.6
Features............................................................................................................................. 149
Input/Output Pins.............................................................................................................. 151
Register Descriptions........................................................................................................ 151
11.3.1
Timer Counter V (TCNTV) .............................................................................. 151
11.3.2
Time Constant Registers A and B (TCORA, TCORB) .................................... 152
11.3.3
Timer Control Register V0 (TCRV0) ............................................................... 152
11.3.4
Timer Control/Status Register V (TCSRV) ...................................................... 154
11.3.5
Timer Control Register V1 (TCRV1) ............................................................... 155
Operation .......................................................................................................................... 156
11.4.1
Timer V Operation............................................................................................ 156
Timer V Application Examples ........................................................................................ 159
11.5.1
Pulse Output with Arbitrary Duty Cycle........................................................... 159
11.5.2
Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input .......... 160
Usage Notes ...................................................................................................................... 161
Section 12 Timer Z ............................................................................................163
12.1
12.2
12.3
12.4
Features............................................................................................................................. 163
Input/Output Pins.............................................................................................................. 168
Register Descriptions........................................................................................................ 169
12.3.1
Timer Start Register (TSTR) ............................................................................ 170
12.3.2
Timer Mode Register (TMDR) ......................................................................... 171
12.3.3
Timer PWM Mode Register (TPMR) ............................................................... 172
12.3.4
Timer Function Control Register (TFCR)......................................................... 173
12.3.5
Timer Output Master Enable Register (TOER) ................................................ 175
12.3.6
Timer Output Control Register (TOCR) ........................................................... 176
12.3.7
Timer Counter (TCNT)..................................................................................... 177
12.3.8
General Registers A, B, C, and D (GRA, GRB, GRC, and GRD).................... 178
12.3.9
Timer Control Register (TCR).......................................................................... 179
12.3.10 Timer I/O Control Register (TIORA and TIORC)............................................ 180
12.3.11 Timer Status Register (TSR)............................................................................. 182
12.3.12 Timer Interrupt Enable Register (TIER) ........................................................... 184
12.3.13 PWM Mode Output Level Control Register (POCR) ....................................... 185
12.3.14 Interface with CPU ........................................................................................... 186
Operation .......................................................................................................................... 187
Rev. 4.00 Mar. 15, 2006 Page xiii of xxxii
12.5
12.6
12.4.1
Counter Operation ............................................................................................ 187
12.4.2
Waveform Output by Compare Match.............................................................. 191
12.4.3
Input Capture Function ..................................................................................... 195
12.4.4
Synchronous Operation..................................................................................... 198
12.4.5
PWM Mode ...................................................................................................... 200
12.4.6
Reset Synchronous PWM Mode....................................................................... 206
12.4.7
Complementary PWM Mode............................................................................ 210
12.4.8
Buffer Operation............................................................................................... 221
12.4.9
Timer Z Output Timing .................................................................................... 229
Interrupts........................................................................................................................... 232
12.5.1
Status Flag Set Timing...................................................................................... 232
12.5.2
Status Flag Clearing Timing ............................................................................. 234
Usage Notes ...................................................................................................................... 235
Section 13 Watchdog Timer.............................................................................. 245
13.1
13.2
13.3
Features............................................................................................................................. 245
Register Descriptions........................................................................................................ 246
13.2.1
Timer Control/Status Register WD (TCSRWD) .............................................. 246
13.2.2
Timer Counter WD (TCWD)............................................................................ 248
13.2.3
Timer Mode Register WD (TMWD) ................................................................ 248
Operation .......................................................................................................................... 249
Section 14 Serial Communication Interface 3 (SCI3)....................................... 251
14.1
14.2
14.3
14.4
14.5
Features............................................................................................................................. 251
Input/Output Pins.............................................................................................................. 254
Register Descriptions........................................................................................................ 254
14.3.1
Receive Shift Register (RSR) ........................................................................... 255
14.3.2
Receive Data Register (RDR)........................................................................... 255
14.3.3
Transmit Shift Register (TSR) .......................................................................... 255
14.3.4
Transmit Data Register (TDR).......................................................................... 255
14.3.5
Serial Mode Register (SMR) ............................................................................ 256
14.3.6
Serial Control Register 3 (SCR3) ..................................................................... 257
14.3.7
Serial Status Register (SSR) ............................................................................. 259
14.3.8
Bit Rate Register (BRR) ................................................................................... 261
Operation in Asynchronous Mode .................................................................................... 270
14.4.1
Clock................................................................................................................. 270
14.4.2
SCI3 Initialization............................................................................................. 271
14.4.3
Data Transmission ............................................................................................ 272
14.4.4
Serial Data Reception ....................................................................................... 274
Operation in Clocked Synchronous Mode ........................................................................ 278
Rev. 4.00 Mar. 15, 2006 Page xiv of xxxii
14.6
14.7
14.8
14.5.1
Clock................................................................................................................. 278
14.5.2
SCI3 Initialization............................................................................................. 278
14.5.3
Serial Data Transmission .................................................................................. 279
14.5.4
Serial Data Reception (Clocked Synchronous Mode)....................................... 281
14.5.5
Simultaneous Serial Data Transmission and Reception.................................... 283
Multiprocessor Communication Function......................................................................... 285
14.6.1
Multiprocessor Serial Data Transmission ......................................................... 286
14.6.2
Multiprocessor Serial Data Reception .............................................................. 287
Interrupts........................................................................................................................... 291
Usage Notes ...................................................................................................................... 292
14.8.1
Break Detection and Processing ....................................................................... 292
14.8.2
Mark State and Break Sending.......................................................................... 292
14.8.3 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only).................................................................. 292
14.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous
Mode ................................................................................................................. 293
Section 15 Controller Area Network for Tiny (TinyCAN) ...............................295
15.1
15.2
15.3
15.4
Features............................................................................................................................. 295
Input/Output Pins.............................................................................................................. 297
Register Descriptions........................................................................................................ 297
15.3.1
Test Control Register (TCR)............................................................................. 298
15.3.2
Master Control Register (MCR) ....................................................................... 300
15.3.3
TinyCAN Module Control Register (TCMR)................................................... 301
15.3.4
General Status Register (GSR) ......................................................................... 302
15.3.5
Bit Configuration Registers 0, 1 (BCR0, BCR1) .............................................. 304
15.3.6
Mailbox Configuration Register (MBCR) ........................................................ 306
15.3.7
Transmit Pending Register (TXPR).................................................................. 307
15.3.8
Transmit Pending Cancel Register (TXCR) ..................................................... 308
15.3.9
Transmit Acknowledge Register (TXACK) ..................................................... 308
15.3.10 Abort Acknowledge Register (ABACK) .......................................................... 309
15.3.11 Data Frame Receive Complete Register (RXPR) ............................................. 310
15.3.12 Remote Request Register (RFPR)..................................................................... 310
15.3.13 Unread Message Status Register (UMSR)........................................................ 311
15.3.14 TinyCAN Interrupt Registers 0, 1 (TCIRR0, TCIRR1).................................... 312
15.3.15 Mailbox Interrupt Mask Register (MBIMR)..................................................... 315
15.3.16 TinyCAN Interrupt Mask Registers 0, 1 (TCIMR0, TCIMR1) ........................ 315
15.3.17 Transmit Error Counter (TEC).......................................................................... 318
15.3.18 Receive Error Counter (REC) ........................................................................... 318
Message Data and Control ................................................................................................ 319
Rev. 4.00 Mar. 15, 2006 Page xv of xxxii
15.4.1
15.4.2
15.5
15.6
15.7
15.8
15.9
Message Control (MCn0, MCn4 to MCn7 [n = 0 to 3]) ................................... 319
Local Acceptance Filter Mask
(LAFMHn1, LAFMHn0, LAFMLn1, LAFMLn0 [n = 0 to 3]) ........................ 322
15.4.3
Message Data (MDn0 to MDn7 [n = 0 to 3]) ................................................... 323
Operation .......................................................................................................................... 324
15.5.1
TinyCAN Initial Settings .................................................................................. 324
15.5.2
Bit Timing......................................................................................................... 325
15.5.3
Message Transmission...................................................................................... 327
15.5.4
Message Reception ........................................................................................... 336
15.5.5
Reconfiguring Mailbox..................................................................................... 340
15.5.6
TinyCAN Standby Transition ........................................................................... 342
Interrupt Requests............................................................................................................. 344
Test Mode Settings ........................................................................................................... 345
CAN Bus Interface ........................................................................................................... 346
Usage Notes ...................................................................................................................... 347
Section 16 Synchronous Serial Communication Unit (SSU) ............................ 349
16.1
16.2
16.3
16.4
Features............................................................................................................................. 349
Continuous transmission and reception of serial data are enabled since both transmitter
and Input/Output Pins ....................................................................................................... 349
Register Descriptions........................................................................................................ 350
16.3.1
SS Control Register H (SSCRH) ...................................................................... 351
16.3.2
SS Control Register L (SSCRL) ....................................................................... 353
16.3.3
SS Mode Register (SSMR) ............................................................................... 354
16.3.4
SS Enable Register (SSER) .............................................................................. 355
16.3.5
SS Status Register (SSSR)................................................................................ 356
16.3.6
SS Receive Data Register (SSRDR) ................................................................. 358
16.3.7
SS Transmit Data Register (SSTDR)................................................................ 358
16.3.8
SS Shift Register (SSTRSR)............................................................................. 358
Operation .......................................................................................................................... 359
16.4.1
Transfer Clock .................................................................................................. 359
16.4.2
Relationship between Clock Polarity and Phase, and Data............................... 359
16.4.3
Relationship between Data Input/Output Pin and Shift Register ...................... 361
16.4.4
Communication Modes and Pin Functions ....................................................... 362
16.4.5
Operation in Clocked Synchronous Communication Mode ............................. 363
16.4.6
Operation in Four-Line Bus Communication Mode ......................................... 370
16.4.7
Initialization in Four-Line Bus Communication Mode..................................... 371
16.4.8
Serial Data Transmission .................................................................................. 372
16.4.9
Serial Data Reception ....................................................................................... 374
16.4.10 SCS Pin Control and Arbitration ...................................................................... 376
Rev. 4.00 Mar. 15, 2006 Page xvi of xxxii
16.5
16.4.11 Interrupt Requests ............................................................................................. 377
Usage Note........................................................................................................................ 378
Section 17 Subsystem Timer (Subtimer) ...........................................................379
17.1
17.2
17.3
17.4
17.5
Features............................................................................................................................. 379
Register Descriptions........................................................................................................ 381
17.2.1
Subtimer Control Register (SBTCTL) .............................................................. 381
17.2.2
Subtimer Counter (SBTDCNT) ........................................................................ 382
17.2.3
Ring Oscillator Prescaler Setting Register (ROPCR) ....................................... 382
Operation .......................................................................................................................... 383
17.3.1
SBTPS Division Ratio Setting .......................................................................... 383
Count Operation................................................................................................................ 387
Usage Notes ...................................................................................................................... 390
17.5.1
Clock Supply to Watchdog Timer .................................................................... 390
17.5.2
Writing to ROPCR............................................................................................ 390
Section 18 A/D Converter..................................................................................391
18.1
18.2
18.3
18.4
18.5
18.6
Features............................................................................................................................. 391
Input/Output Pins.............................................................................................................. 393
Register Descriptions........................................................................................................ 394
18.3.1
A/D Data Registers A to D (ADDRA to ADDRD) .......................................... 394
18.3.2
A/D Control/Status Register (ADCSR) ............................................................ 395
18.3.3
A/D Control Register (ADCR) ......................................................................... 396
Operation .......................................................................................................................... 397
18.4.1
Single Mode...................................................................................................... 397
18.4.2
Scan Mode ........................................................................................................ 397
18.4.3
Input Sampling and A/D Conversion Time ...................................................... 398
18.4.4
External Trigger Input Timing.......................................................................... 399
A/D Conversion Accuracy Definitions ............................................................................. 400
Usage Notes ...................................................................................................................... 402
18.6.1
Permissible Signal Source Impedance .............................................................. 402
18.6.2
Influences on Absolute Accuracy ..................................................................... 402
Section 19 Power-On Reset and Low-Voltage Detection Circuits
(Optional).........................................................................................403
19.1
19.2
19.3
Features............................................................................................................................. 404
Register Descriptions........................................................................................................ 405
19.2.1
Low-Voltage-Detection Control Register (LVDCR)........................................ 405
19.2.2
Low-Voltage-Detection Status Register (LVDSR)........................................... 407
Operation .......................................................................................................................... 408
Rev. 4.00 Mar. 15, 2006 Page xvii of xxxii
19.3.1
19.3.2
Power-On Reset Circuit .................................................................................... 408
Low-Voltage Detection Circuit......................................................................... 409
Section 20 Power Supply Circuit ...................................................................... 413
20.1
20.2
When Using Internal Power Supply Step-Down Circuit .................................................. 413
When Not Using Internal Power Supply Step-Down Circuit ........................................... 414
Section 21 List of Registers............................................................................... 415
21.1
21.2
21.3
Register Addresses (Address Order)................................................................................. 416
Register Bits ..................................................................................................................... 425
Register States in Each Operating Mode .......................................................................... 433
Section 22 Electrical Characteristics ................................................................. 441
22.1
22.2
22.3
22.4
22.5
Absolute Maximum Ratings ............................................................................................. 441
Electrical Characteristics (F-ZTATTM Version)................................................................. 442
22.2.1
Power Supply Voltage and Operating Ranges .................................................. 442
22.2.2
DC Characteristics ............................................................................................ 445
22.2.3
AC Characteristics ............................................................................................ 451
22.2.4
A/D Converter Characteristics.......................................................................... 456
22.2.5
Watchdog Timer Characteristics....................................................................... 457
22.2.6
Flash Memory Characteristics .......................................................................... 458
22.2.7
Power-Supply-Voltage Detection Circuit Characteristics (Optional) ............... 460
22.2.8
Power-On Reset Circuit Characteristics (Optional).......................................... 460
Electrical Characteristics (Masked ROM Version)........................................................... 461
22.3.1
Power Supply Voltage and Operating Ranges .................................................. 461
22.3.2
DC Characteristics ............................................................................................ 464
22.3.3
AC Characteristics ............................................................................................ 470
22.3.4
A/D Converter Characteristics.......................................................................... 475
22.3.5
Watchdog Timer Characteristics....................................................................... 476
22.3.6
Power-Supply-Voltage Detection Circuit Characteristics (Optional) ............... 477
22.3.7
Power-On Reset Circuit Characteristics (Optional).......................................... 477
Operation Timing.............................................................................................................. 478
Output Load Condition ..................................................................................................... 485
Appendix A Instruction Set ............................................................................... 487
A.1
A.2
A.3
A.4
Instruction List.................................................................................................................. 487
Operation Code Map......................................................................................................... 502
Number of Execution States ............................................................................................. 505
Combinations of Instructions and Addressing Modes ...................................................... 516
Rev. 4.00 Mar. 15, 2006 Page xviii of xxxii
Appendix B I/O Port Block Diagrams ...............................................................517
B.1
B.2
I/O Port Block Diagrams .................................................................................................. 517
Port States in Each Operating State .................................................................................. 544
Appendix C Product Code Lineup.....................................................................545
Appendix D Package Dimensions .....................................................................547
Main Revisions and Additions in this Edition .....................................................549
Index ....................................................................................................................553
Rev. 4.00 Mar. 15, 2006 Page xix of xxxii
Rev. 4.00 Mar. 15, 2006 Page xx of xxxii
Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram of F-ZTAT TM and Masked ROM Versions ............................ 3
Figure 1.2 Pin Arrangement of F-ZTATTM and Masked ROM Versions (FP-64K, FP-64A)......... 4
Section 2 CPU
Figure 2.1 Memory Map (1) ......................................................................................................... 11
Figure 2.1 Memory Map (2) ......................................................................................................... 12
Figure 2.1 Memory Map (3) ......................................................................................................... 13
Figure 2.2 CPU Registers ............................................................................................................. 14
Figure 2.3 Usage of General Registers ......................................................................................... 15
Figure 2.4 Relationship between Stack Pointer and Stack Area ................................................... 16
Figure 2.5 General Register Data Formats (1).............................................................................. 18
Figure 2.5 General Register Data Formats (2).............................................................................. 19
Figure 2.6 Memory Data Formats................................................................................................. 20
Figure 2.7 Instruction Formats...................................................................................................... 31
Figure 2.8 Branch Address Specification in Memory Indirect Mode ........................................... 35
Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 38
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)..................................... 39
Figure 2.11 CPU Operation States................................................................................................ 40
Figure 2.12 State Transitions ........................................................................................................ 41
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same
Address...................................................................................................................... 43
Section 3
Figure 3.1
Figure 3.2
Figure 3.3
Figure 3.4
Exception Handling
Reset Sequence............................................................................................................ 61
Stack Status after Exception Handling ........................................................................ 63
Interrupt Sequence....................................................................................................... 64
Port Mode Register Setting and Interrupt Request Flag Clearing Procedure .............. 65
Section 4
Figure 4.1
Figure 4.2
Figure 4.2
Address Break
Block Diagram of Address Break................................................................................ 67
Address Break Interrupt Operation Example (1)......................................................... 71
Address Break Interrupt Operation Example (2)......................................................... 72
Section 5
Figure 5.1
Figure 5.2
Figure 5.3
Figure 5.4
Clock Pulse Generators
Block Diagram of Clock Pulse Generators.................................................................. 73
Block Diagram of System Clock Generator ................................................................ 74
Typical Connection to Crystal Resonator.................................................................... 74
Equivalent Circuit of Crystal Resonator...................................................................... 74
Rev. 4.00 Mar. 15, 2006 Page xxi of xxxii
Figure 5.5 Typical Connection to Ceramic Resonator.................................................................. 75
Figure 5.6 Example of External Clock Input ................................................................................ 75
Figure 5.7 Example of Incorrect Board Design ............................................................................ 76
Section 6 Power-Down Modes
Figure 6.1 Mode Transition Diagram ........................................................................................... 82
Section 7
Figure 7.1
Figure 7.2
Figure 7.3
Figure 7.4
ROM
Flash Memory Block Configuration............................................................................ 90
Programming/Erasing Flowchart Example in User Program Mode............................ 99
Program/Program-Verify Flowchart ......................................................................... 101
Erase/Erase-Verify Flowchart ................................................................................... 104
Section 9
Figure 9.1
Figure 9.2
Figure 9.3
Figure 9.4
Figure 9.5
Figure 9.6
Figure 9.7
Figure 9.8
I/O Ports
Port 1 Pin Configuration............................................................................................ 111
Port 2 Pin Configuration............................................................................................ 116
Port 5 Pin Configuration............................................................................................ 120
Port 6 Pin Configuration............................................................................................ 126
Port 7 Pin Configuration............................................................................................ 131
Port 8 Pin Configuration............................................................................................ 135
Port 9 Pin Configuration............................................................................................ 137
Port B Pin Configuration........................................................................................... 141
Section 10 Timer B1
Figure 10.1 Block Diagram of Timer B1.................................................................................... 143
Section 11 Timer V
Figure 11.1 Block Diagram of Timer V ..................................................................................... 150
Figure 11.2 Increment Timing with Internal Clock .................................................................... 157
Figure 11.3 Increment Timing with External Clock................................................................... 157
Figure 11.4 OVF Set Timing ...................................................................................................... 157
Figure 11.5 CMFA and CMFB Set Timing................................................................................ 158
Figure 11.6 TMOV Output Timing ............................................................................................ 158
Figure 11.7 Clear Timing by Compare Match............................................................................ 158
Figure 11.8 Clear Timing by TMRIV Input ............................................................................... 159
Figure 11.9 Pulse Output Example ............................................................................................. 159
Figure 11.10 Example of Pulse Output Synchronized to TRGV Input....................................... 160
Figure 11.11 Contention between TCNTV Write and Clear ...................................................... 161
Figure 11.12 Contention between TCORA Write and Compare Match ..................................... 162
Figure 11.13 Internal Clock Switching and TCNTV Operation ................................................. 162
Rev. 4.00 Mar. 15, 2006 Page xxii of xxxii
Section 12
Figure 12.1
Figure 12.2
Figure 12.3
Figure 12.4
Timer Z
Timer Z Block Diagram .......................................................................................... 165
Timer Z (Channel 0) Block Diagram ...................................................................... 166
Timer Z (Channel 1) Block Diagram ...................................................................... 167
Example of Outputs in Reset Synchronous PWM Mode and Complementary
PWM Mode ............................................................................................................. 174
Figure 12.5 Accessing Operation of 16-Bit Register (between CPU and TCNT (16 Bits)) ....... 186
Figure 12.6 Accessing Operation of 8-Bit Register (between CPU and TSTR (8 Bits))............ 186
Figure 12.7 Example of Counter Operation Setting Procedure .................................................. 187
Figure 12.8 Free-Running Counter Operation ............................................................................ 188
Figure 12.9 Periodic Counter Operation..................................................................................... 189
Figure 12.10 Count Timing at Internal Clock Operation............................................................ 189
Figure 12.11 Count Timing at External Clock Operation (Both Edges Detected)...................... 190
Figure 12.12 Example of Setting Procedure for Waveform Output by Compare Match............ 191
Figure 12.13 Example of 0 Output/1 Output Operation ............................................................. 192
Figure 12.14 Example of Toggle Output Operation ................................................................... 193
Figure 12.15 Output Compare Timing........................................................................................ 194
Figure 12.16 Example of Input Capture Operation Setting Procedure ....................................... 195
Figure 12.17 Example of Input Capture Operation..................................................................... 196
Figure 12.18 Input Capture Signal Timing ................................................................................. 197
Figure 12.19 Example of Synchronous Operation Setting Procedure ........................................ 198
Figure 12.20 Example of Synchronous Operation...................................................................... 199
Figure 12.21 Example of PWM Mode Setting Procedure .......................................................... 201
Figure 12.22 Example of PWM Mode Operation (1) ................................................................. 202
Figure 12.23 Example of PWM Mode Operation (2) ................................................................. 203
Figure 12.24 Example of PWM Mode Operation (3) ................................................................. 204
Figure 12.25 Example of PWM Mode Operation (4) ................................................................. 205
Figure 12.26 Example of Reset Synchronous PWM Mode Setting Procedure........................... 207
Figure 12.27 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 1) ...... 208
Figure 12.28 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 0) ...... 209
Figure 12.29 Example of Complementary PWM Mode Setting Procedure................................ 212
Figure 12.30 Canceling Procedure of Complementary PWM Mode .......................................... 213
Figure 12.31 Example of Complementary PWM Mode Operation (1)....................................... 214
Figure 12.32 (1) Example of Complementary PWM Mode Operation
(TPSC2 = TPSC1 = TPSC0 = 0) (2)................................................................ 216
Figure 12.32 (2) Example of Complementary PWM Mode Operation
(Other than TPSC2 = TPSC1 = TPSC0) (3) .................................................... 217
Figure 12.33 Timing of Overshooting ........................................................................................ 218
Figure 12.34 Timing of Undershooting ...................................................................................... 218
Figure 12.35 Compare Match Buffer Operation......................................................................... 221
Rev. 4.00 Mar. 15, 2006 Page xxiii of xxxii
Figure 12.36 Input Capture Buffer Operation............................................................................. 221
Figure 12.37 Example of Buffer Operation Setting Procedure................................................... 222
Figure 12.38 Example of Buffer Operation (1)
(Buffer Operation for Output Compare Register) ................................................. 223
Figure 12.39 Example of Compare Match Timing for Buffer Operation ................................... 224
Figure 12.40 Example of Buffer Operation (2)
(Buffer Operation for Input Capture Register) ...................................................... 225
Figure 12.41 Input Capture Timing of Buffer Operation............................................................ 226
Figure 12.42 Buffer Operation (3)
(Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1)............ 227
Figure 12.43 Buffer Operation (4)
(Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1)............ 228
Figure 12.44 Example of Output Disable Timing of Timer Z by Writing to TOER .................. 229
Figure 12.45 Example of Output Disable Timing of Timer Z by External Trigger.................... 230
Figure 12.46 Example of Output Inverse Timing of Timer Z by Writing to TFCR ................... 230
Figure 12.47 Example of Output Inverse Timing of Timer Z by Writing to POCR................... 231
Figure 12.48 IMF Flag Set Timing when Compare Match Occurs ............................................ 232
Figure 12.49 IMF Flag Set Timing at Input Capture .................................................................. 233
Figure 12.50 OVF Flag Set Timing ............................................................................................ 233
Figure 12.51 Status Flag Clearing Timing.................................................................................. 234
Figure 12.52 Contention between TCNT Write and Clear Operations....................................... 235
Figure 12.53 Contention between TCNT Write and Increment Operations ............................... 236
Figure 12.54 Contention between GR Write and Compare Match............................................. 237
Figure 12.55 Contention between TCNT Write and Overflow................................................... 238
Figure 12.56 Contention between GR Read and Input Capture.................................................. 239
Figure 12.57 Contention between Count Clearing and Increment Operations by Input
Capture .................................................................................................................. 240
Figure 12.58 Contention between GR Write and Input Capture................................................. 241
Figure 12.59 When Compare Match and Bit Manipulation Instruction to TOCR Occur at the
Same Timing ......................................................................................................... 243
Section 13 Watchdog Timer
Figure 13.1 Block Diagram of Watchdog Timer ........................................................................ 245
Figure 13.2 Watchdog Timer Operation Example...................................................................... 249
Section 14
Figure 14.1
Figure 14.2
Figure 14.3
Serial Communication Interface 3 (SCI3)
Block Diagram of SCI3........................................................................................... 253
Data Format in Asynchronous Communication ...................................................... 270
Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits) ............. 270
Figure 14.4 Sample SCI3 Initialization Flowchart ..................................................................... 271
Rev. 4.00 Mar. 15, 2006 Page xxiv of xxxii
Figure 14.5 Example of SCI3 Transmission in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit) ........................................................................... 272
Figure 14.6 Sample Serial Transmission Data Flowchart (Asynchronous Mode)...................... 273
Figure 14.7 Example of SCI3 Reception in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit) ........................................................................... 274
Figure 14.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (1)...................... 276
Figure 14.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (2)...................... 277
Figure 14.9 Data Format in Clocked Synchronous Communication .......................................... 278
Figure 14.10 Example of SCI3 Transmission in Clocked Synchronous Mode........................... 279
Figure 14.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode) ................ 280
Figure 14.12 Example of SCI3 Reception in Clocked Synchronous Mode................................ 281
Figure 14.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)...................... 282
Figure 14.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
(Clocked Synchronous Mode)............................................................................... 284
Figure 14.15 Example of Inter-Processor Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A) .......................................... 286
Figure 14.16 Sample Multiprocessor Serial Transmission Flowchart ........................................ 287
Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 288
Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 289
Figure 14.18 Example of SCI3 Reception Using Multiprocessor Format
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).............................. 290
Figure 14.19 Receive Data Sampling Timing in Asynchronous Mode ...................................... 293
Section 15
Figure 15.1
Figure 15.2
Figure 15.3
Figure 15.4
Figure 15.5
Figure 15.6
Figure 15.7
Figure 15.8
Controller Area Network for Tiny (TinyCAN)
TinyCAN Block Diagram........................................................................................ 296
Standard Format and Extended Format ................................................................... 319
Message Data Configuration ................................................................................... 323
Reset Clearing Flowchart ........................................................................................ 324
CAN Bit Configuration ........................................................................................... 325
Transmission Request Flowchart............................................................................. 327
Internal Arbitration at Transmission Caused by TXCR/TXPR Setting................... 329
Internal Arbitration at Reception Caused by CAN Bus Arbitration Loss
(MBn in TXCR = 0 and DART = 0)........................................................................ 330
Figure 15.9 Internal Arbitration at Reception Caused by CAN Bus Arbitration Loss
(MBn in TXCR = 1) ................................................................................................ 331
Figure 15.10 Internal Arbitration at Reception Caused by CAN Bus Arbitration Loss
(DART = 1) ........................................................................................................... 332
Figure 15.11 Internal Arbitration at Error Detection (MBn in TXCR = 0 and DART = 0)........ 333
Figure 15.12 Internal Arbitration at Error Detection (MBn in TXCR = 1)................................. 334
Figure 15.13 Internal Arbitration at Error Detection (DART = 1).............................................. 335
Figure 15.14 Message Reception Flowchart............................................................................... 336
Rev. 4.00 Mar. 15, 2006 Page xxv of xxxii
Figure 15.15
Figure 15.16
Figure 15.17
Figure 15.18
Set Timing for Message Reception ....................................................................... 338
RXPR/RFPR Set/Clear Timing when Overrun/Overwrite Occurs........................ 339
Flowchart for Changing ID, MBCR, and LAFM of Receive Mailbox.................. 341
Flowchart for Transition between Active Mode and Standby Mode or Module
Standby Mode ....................................................................................................... 343
Figure 15.19 High-Speed CAN Bus Interface Using HA13721 ................................................. 346
Section 16 Synchronous Serial Communication Unit (SSU)
Figure 16.1 Block Diagram of SSU............................................................................................ 350
Figure 16.2 Relationship between Clock Polarity and Phase, and Data ..................................... 360
Figure 16.3 Relationship between Data Input/Output Pin and Shift Register ............................ 361
Figure 16.4 Initialization in Clocked Synchronous Communication Mode................................ 363
Figure 16.5 Example of Operation in Data Transmission .......................................................... 364
Figure 16.6 Sample Serial Transmission Flowchart ................................................................... 365
Figure 16.7 Example of Operation in Data Reception (MSS = 1) .............................................. 366
Figure 16.8 Sample Serial Reception Flowchart (MSS = 1)....................................................... 367
Figure 16.9 Sample Flowchart for Serial Transmit and Receive Operations.............................. 369
Figure 16.10 Initialization in Four-Line Bus Communication Mode ......................................... 371
Figure 16.11 Example of Operation in Data Transmission (MSS = 1)....................................... 373
Figure 16.12 Example of Operation in Data Reception (MSS = 1) ............................................ 375
Figure 16.13 Arbitration Check Timing ..................................................................................... 376
Figure 16.14 Procedures when Changing Output Level of Serial Data ...................................... 378
Section 17
Figure 17.1
Figure 17.2
Figure 17.3
Figure 17.4
Figure 17.5
Subsystem Timer (Subtimer)
Block Diagram of Subtimer .................................................................................... 380
Timing for On-Chip Oscillator................................................................................ 383
SBTPS Setting Flowchart........................................................................................ 385
Example of Subtimer Operation.............................................................................. 388
Count Operation Flowchart ..................................................................................... 389
Section 18
Figure 18.1
Figure 18.2
Figure 18.3
Figure 18.4
Figure 18.5
Figure 18.6
A/D Converter
Block Diagram of A/D Converter ........................................................................... 392
A/D Conversion Timing.......................................................................................... 398
External Trigger Input Timing ................................................................................ 399
A/D Conversion Accuracy Definitions (1).............................................................. 401
A/D Conversion Accuracy Definitions (2).............................................................. 401
Analog Input Circuit Example ................................................................................ 402
Section 19
Figure 19.1
Figure 19.2
Figure 19.3
Power-On Reset and Low-Voltage Detection Circuits (Optional)
Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit.... 404
Operational Timing of Power-On Reset Circuit...................................................... 409
Operational Timing of LVDR Circuit ..................................................................... 410
Rev. 4.00 Mar. 15, 2006 Page xxvi of xxxii
Figure 19.4 Operational Timing of LVDI Circuit....................................................................... 411
Figure 19.5 Timing for Operation/Release of Low-Voltage Detection Circuit .......................... 412
Section 20 Power Supply Circuit
Figure 20.1 Power Supply Connection when Internal Step-Down Circuit is Used .................... 413
Figure 20.2 Power Supply Connection when Internal Step-Down Circuit is Not Used ............. 414
Section 22
Figure 22.1
Figure 22.2
Figure 22.3
Figure 22.4
Figure 22.5
Figure 22.6
Figure 22.7
Figure 22.8
Electrical Characteristics
System Clock Input Timing..................................................................................... 478
RES Low Width Timing.......................................................................................... 478
Input Timing............................................................................................................ 478
SCK3 Input Clock Timing....................................................................................... 479
SCI Input/Output Timing in Clocked Synchronous Mode ...................................... 479
TinyCAN Input/Output Timing............................................................................... 480
SSU Input/Output Timing in Clocked Synchronous Mode ..................................... 480
SSU Input/Output Timing
(Four-Line Bus Communication Mode, Master, CPHS = 1) ................................... 481
Figure 22.9 SSU Input/Output Timing
(Four-Line Bus Communication Mode, Master, CPHS = 0) ................................... 482
Figure 22.10 SSU Input/Output Timing
(Four-Line Bus Communication Mode, Slave, CPHS = 1) ................................... 483
Figure 22.11 SSU Input/Output Timing
(Four-Line Bus Communication Mode, Slave, CPHS = 0) ................................... 484
Figure 22.12 Output Load Circuit............................................................................................... 485
Appendix B I/O Port Block Diagrams
Figure B.1 Port 1 Block Diagram (P17) ..................................................................................... 517
Figure B.2 Port 1 Block Diagram (P14, P16) ............................................................................. 518
Figure B.3 Port 1 Block Diagram (P15) ..................................................................................... 519
Figure B.4 Port 1 Block Diagram (P12, P11, P10) ..................................................................... 520
Figure B.5 Port 2 Block Diagram (P24, P23) ............................................................................. 521
Figure B.6 Port 2 Block Diagram (P22) ..................................................................................... 522
Figure B.7 Port 2 Block Diagram (P21) ..................................................................................... 523
Figure B.8 Port 2 Block Diagram (P20) ..................................................................................... 524
Figure B.9 Port 5 Block Diagram (P57, P56) ............................................................................. 525
Figure B.10 Port 5 Block Diagram (P55) ................................................................................... 526
Figure B.11 Port 5 Block Diagram (P54 to P55) ........................................................................ 527
Figure B.12 Port 6 Block Diagram (P67 to P60) ........................................................................ 528
Figure B.13 Port 7 Block Diagram (P76) ................................................................................... 529
Figure B.14 Port 7 Block Diagram (P75) ................................................................................... 530
Figure B.15 Port 7 Block Diagram (P74) ................................................................................... 531
Figure B.16 Port 7 Block Diagram (P72) ................................................................................... 532
Rev. 4.00 Mar. 15, 2006 Page xxvii of xxxii
Figure B.17
Figure B.18
Figure B.19
Figure B.20
Figure B.21
Figure B.22
Figure B.23
Figure B.24
Figure B.25
Figure B.26
Figure B.27
Port 7 Block Diagram (P71) ................................................................................... 533
Port 7 Block Diagram (P70) ................................................................................... 534
Port 8 Block Diagram (P87 to P85) ........................................................................ 535
Port 9 Block Diagram (P97) ................................................................................... 536
Port 9 Block Diagram (P96) ................................................................................... 537
Port 9 Block Diagram (P94, P95) ........................................................................... 538
Port 9 Block Diagram (P93) ................................................................................... 539
Port 9 Block Diagram (P92) ................................................................................... 540
Port 9 Block Diagram (P91) ................................................................................... 541
Port 9 Block Diagram (P90) ................................................................................... 542
Port B Block Diagram (PB7 to PB0) ...................................................................... 543
Appendix D Package Dimensions
Figure D.1 FP-64K Package Dimensions ................................................................................... 547
Figure D.2 FP-64A Package Dimensions ................................................................................... 548
Rev. 4.00 Mar. 15, 2006 Page xxviii of xxxii
Tables
Section 1 Overview
Table 1.1
Pin Functions ............................................................................................................ 5
Section 2 CPU
Table 2.1
Operation Notation ................................................................................................. 21
Table 2.2
Data Transfer Instructions....................................................................................... 22
Table 2.3
Arithmetic Operations Instructions (1) ................................................................... 23
Table 2.3
Arithmetic Operations Instructions (2) ................................................................... 24
Table 2.4
Logic Operations Instructions................................................................................. 25
Table 2.5
Shift Instructions..................................................................................................... 25
Table 2.6
Bit Manipulation Instructions (1)............................................................................ 26
Table 2.6
Bit Manipulation Instructions (2)............................................................................ 27
Table 2.7
Branch Instructions ................................................................................................. 28
Table 2.8
System Control Instructions.................................................................................... 29
Table 2.9
Block Data Transfer Instructions ............................................................................ 30
Table 2.10
Addressing Modes .................................................................................................. 32
Table 2.11
Absolute Address Access Ranges ........................................................................... 34
Table 2.12
Effective Address Calculation (1)........................................................................... 36
Table 2.12
Effective Address Calculation (2)........................................................................... 37
Section 3 Exception Handling
Table 3.1
Exception Sources and Vector Address .................................................................. 50
Table 3.2
Interrupt Wait States ............................................................................................... 63
Section 4 Address Break
Table 4.1
Access and Data Bus Used ..................................................................................... 69
Section 5 Clock Pulse Generators
Table 5.1
Crystal Resonator Parameters ................................................................................. 75
Section 6 Power-Down Modes
Table 6.1
Operating Frequency and Waiting Time................................................................. 79
Table 6.2
Transition Mode after SLEEP Instruction Execution and Transition Mode due to
Interrupt .................................................................................................................. 83
Table 6.3
Internal State in Each Operating Mode................................................................... 83
Section 7 ROM
Table 7.1
Setting Programming Modes .................................................................................. 95
Table 7.2
Boot Mode Operation ............................................................................................. 97
Rev. 4.00 Mar. 15, 2006 Page xxix of xxxii
Table 7.3
Table 7.4
Table 7.5
Table 7.6
Table 7.7
System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is
Possible................................................................................................................... 98
Reprogram Data Computation Table .................................................................... 102
Additional-Program Data Computation Table ...................................................... 102
Programming Time ............................................................................................... 102
Flash Memory Operating States............................................................................ 107
Section 10 Timer B1
Table 10.1
Pin Configuration.................................................................................................. 144
Table 10.2
Timer B1 Operating Modes .................................................................................. 148
Section 11 Timer V
Table 11.1
Pin Configuration.................................................................................................. 151
Table 11.2
Clock Signals to Input to TCNTV and Counting Conditions ............................... 153
Section 12 Timer Z
Table 12.1
Timer Z Functions ................................................................................................ 164
Table 12.2
Pin Configuration.................................................................................................. 168
Table 12.3
Initial Output Level of FTIOB0 Pin...................................................................... 200
Table 12.4
Output Pins in Reset Synchronous PWM Mode................................................... 206
Table 12.5
Register Settings in Reset Synchronous PWM Mode........................................... 206
Table 12.6
Output Pins in Complementary PWM Mode........................................................ 210
Table 12.7
Register Settings in Complementary PWM Mode................................................ 211
Table 12.8
Register Combinations in Buffer Operation ......................................................... 221
Section 14 Serial Communication Interface 3 (SCI3)
Table 14.1
Channel Configuration.......................................................................................... 252
Table 14.2
Pin Configuration.................................................................................................. 254
Table 14.3
Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...... 262
Table 14.3
Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ...... 264
Table 14.3
Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3) ...... 266
Table 14.4
Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 267
Table 14.5
Examples of BRR Settings for Various Bit Rates
(Clocked Synchronous Mode) (1)......................................................................... 268
Table 14.5
Examples of BRR Settings for Various Bit Rates
(Clocked Synchronous Mode) (2)......................................................................... 269
Table 14.6
SSR Status Flags and Receive Data Handling ...................................................... 275
Table 14.7
SCI3 Interrupt Requests........................................................................................ 291
Section 15 Controller Area Network for Tiny (TinyCAN)
Table 15.1
Pin Configuration.................................................................................................. 297
Table 15.2
Settable Values in BCR ........................................................................................ 325
Table 15.3
Settable Values for TSG1 and TSG2 in BCR1 ..................................................... 326
Rev. 4.00 Mar. 15, 2006 Page xxx of xxxii
Table 15.4
Table 15.5
Interrupt Requests ................................................................................................. 344
Test Mode Settings ............................................................................................... 345
Section 16 Synchronous Serial Communication Unit (SSU)
Table 16.1
Pin Configuration.................................................................................................. 349
Table 16.2
Relationship between Communication Modes and Input/Output Pins.................. 362
Table 16.3
Interrupt Requests ................................................................................................. 377
Section 17 Subsystem Timer (Subtimer)
Table 17.1
Example of Subclock Error................................................................................... 385
Section 18 A/D Converter
Table 18.1
Pin Configuration.................................................................................................. 393
Table 18.2
Analog Input Channels and Corresponding ADDR Registers .............................. 394
Table 18.3
A/D Conversion Time (Single Mode)................................................................... 399
Section 19 Power-On Reset and Low-Voltage Detection Circuits (Optional)
Table 19.1
LVDCR Settings and Select Functions................................................................. 406
Section 22 Electrical Characteristics
Table 22.1
Absolute Maximum Ratings ................................................................................. 441
Table 22.2
DC Characteristics (1)........................................................................................... 445
Table 22.2
DC Characteristics (2)........................................................................................... 450
Table 22.3
AC Characteristics ................................................................................................ 451
Table 22.4
Serial Communication Interface (SCI) Timing..................................................... 453
Table 22.5
Controller Area Network for Tiny (TinyCAN) Timing ........................................ 454
Table 22.6
Synchronous Communication Unit (SSU) Timing ............................................... 455
Table 22.7
A/D Converter Characteristics .............................................................................. 456
Table 22.8
Watchdog Timer Characteristics........................................................................... 457
Table 22.9
Flash Memory Characteristics .............................................................................. 458
Table 22.10
Power-Supply-Voltage Detection Circuit Characteristics................................. 460
Table 22.11
Power-On Reset Circuit Characteristics............................................................ 460
Table 22.12
DC Characteristics (1)....................................................................................... 464
Table 22.13
DC Characteristics (2)....................................................................................... 469
Table 22.14
AC Characteristics ............................................................................................ 470
Table 22.15
Serial Communication Interface (SCI) Timing................................................. 472
Table 22.16
Controller Area Network for Tiny (TinyCAN) Timing .................................... 473
Table 22.17
Synchronous Communication Unit (SSU) Timing ........................................... 474
Table 22.18
A/D Converter Characteristics .......................................................................... 475
Table 22.19
Watchdog Timer Characteristics....................................................................... 476
Table 22.20
Power-Supply-Voltage Detection Circuit Characteristics................................. 477
Table 22.21
Power-On Reset Circuit Characteristics............................................................ 477
Rev. 4.00 Mar. 15, 2006 Page xxxi of xxxii
Appendix A
Table A.1
Table A.2
Table A.2
Table A.2
Table A.3
Table A.4
Table A.5
Instruction Set
Instruction Set....................................................................................................... 489
Operation Code Map (1) ....................................................................................... 502
Operation Code Map (2) ....................................................................................... 503
Operation Code Map (3) ....................................................................................... 504
Number of States Required for Execution ............................................................ 506
Number of Cycles in Each Instruction.................................................................. 507
Combinations of Instructions and Addressing Modes .......................................... 516
Rev. 4.00 Mar. 15, 2006 Page xxxii of xxxii
Section 1 Overview
Section 1 Overview
1.1
Features
• High-speed H8/300H central processing unit with an internal 16-bit architecture
 Upward-compatible with H8/300 CPU on an object level
 Sixteen 16-bit general registers
 62 basic instructions
• Various peripheral functions
 Timer B1 (8-bit timer)
 Timer V (8-bit timer)
 Timer Z (16-bit timer)
 Watchdog timer
 SCI3 (asynchronous or clocked synchronous serial communication interface)
 TinyCAN (controller area network for Tiny)
 SSU (synchronous serial communication unit)
 Subsystem timer (subtimer)
 10-bit A/D converter
Rev. 4.00 Mar. 15, 2006 Page 1 of 556
REJ09B0026-0400
Section 1 Overview
• On-chip memory
Model
Standard
Version
On-Chip PowerOn Reset and
Low-Voltage
Detecting Circuit
Version
ROM
RAM
H8/36057F
HD64F36057
HD64F36057G
56 kbytes
3 kbytes
H8/36054F
HD64F36054
HD64F36054G
32 kbytes
2 kbytes
H8/36037F
HD64F36037
HD64F36037G
56 kbytes
3 kbytes
H8/36034F
HD64F36034
HD64F36034G
32 kbytes
2 kbytes
H8/36057
HD64336057
HD64336057G
56 kbytes
2 kbytes
H8/36054
HD64336054
HD64336054G
32 kbytes
2 kbytes
H8/36037
HD64336037
HD64336037G
56 kbytes
2 kbytes
H8/36036
HD64336036
HD64336036G
48 kbytes
2 kbytes
H8/36035
HD64336035
HD64336035G
40 kbytes
2 kbytes
H8/36034
HD64336034
HD64336034G
32 kbytes
2 kbytes
H8/36033
HD64336033
HD64336033G
24 kbytes
1 kbyte
H8/36032
HD64336032
HD64336032G
16 kbytes
1 kbyte
Product Classification
Flash memory version
TM
(F-ZTAT version)
Masked ROM version
• General I/O ports
 I/O pins: 45 I/O pins, including 8 large current ports (IOL = 20 mA, @VOL = 1.5 V)
 Input-only pins: 8 input pins (also used for analog input)
• Supports various power-down modes
Note: F-ZTATTM is a trademark of Renesas Technology Corp.
• Compact package
Package
Code
Body Size
Pin Pitch
LQFP-64
FP-64K
10.0 × 10.0 mm
0.5 mm
QFP-64
FP-64A
Rev. 4.00 Mar. 15, 2006 Page 2 of 556
REJ09B0026-0400
14.0 × 14.0 mm
0.8 mm
Section 1 Overview
Internal
oscillator
P57
P56
P55/WKP5/ADTRG
P54/WKP4
P53/WKP3
P52/WKP2
P51/WKP1
P50/WKP0
NMI
TEST
RES
VSS
VCC
Port 6
P76/TMOV
P75/TMCIV
P74/TMRIV
P72/TXD_2*2
P71/RXD_2*2
P70/SCK3_2*2
Port 1
P67/FTIOD1
P66/FTIOC1
P65/FTIOB1
P64/FTIOA1
P63/FTIOD0
P62/FTIOC0
P61/FTIOB0
P60/FTIOA0
Port 7
Data bus (lower)
RAM
ROM
SSU
TinyCAN
SCI3
Subtimer
SCI3_2*1
Timer Z
Watchdog
timer
Timer V
Timer B1
A/D converter
POR and
LVD*3
Port 8
P90/SCS
P91/SSCK
P92/SSO
P93/SSI
P94
P95
P96/HRxD
P97/HTxD
CPU
H8/300H
Port 2
P20/SCK3
P21/RXD
P22/TXD
P23
P24
System
clock
generator
Port 9
P10
P11
P12
P14/IRQ0
P15/IRQ1/TMIB1
P16/IRQ2
P17/IRQ3/TRGV
VCL
OSC1
OSC2
Internal Block Diagram
Port 5
P87
P86
P85
Data bus (upper)
Address bus
AVCC
Port B
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
1.2
Notes: 1. The SCI3_2 is incorporated only in the H8/36057.
2. The SCK3_2, RXD_2, and TXD_2 pins are not multiplexed in the H8/36037.
3. POR and LVD function is incorporated in the H8/36057G and H8/36037G.
Figure 1.1 Internal Block Diagram of F-ZTAT TM and Masked ROM Versions
Rev. 4.00 Mar. 15, 2006 Page 3 of 556
REJ09B0026-0400
Section 1 Overview
P62/FTIOC0
P61/FTIOB0
NMI
P60/FTIOA0
P64/FTIOA1
P65/FTIOB1
P66/FTIOC1
P67/FTIOD1
P85
P86
P87
P20/SCK3
P21/RXD
P22/TXD
P23
Pin Arrangement
P70/SCK3_2*2
1.3
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
52
29
P75/TMCIV
P16/IRQ2
53
28
P74/TMRIV
P17/IRQ3/TRGV
54
27
P57
P93/SSI
55
26
P56
P92/SSO
56
H8/36057 Group
25
P12
P91/SSCK
57
H8/36037 Group
24
P11
P90/SCS
58
Top View
23
P10
PB3/AN3
59
22
P55/WKP5/ADTRG
PB2/AN2
60
21
P54/WKP4
PB1/AN1
61
20
P53/WKP3
PB0/AN0
62
19
P52/WKP2
PB4/AN4
63
18
P97/HTxD
PB5/AN5
64
17
P96/HRxD
8
9 10 11 12 13 14 15 16
P95
7
P94
6
P51/WKP1
5
P50/WKP0
4
Vcc
3
OSC1
2
OSC2
1
Vss
P76/TMOV
P15/IRQ1/TMIB1
TEST
30
RES
51
VCL
P24
P14/IRQ0
NC*1
31
NC*1
P63/FTIOD0
50
AVcc
32
P72/TXD_2*2
PB7/AN7
49
PB6/AN6
P71/RXD_2*2
Notes: 1. Do not connect NC pins (these pins are not connected to the internal circuitry).
2. The SCK3_2, RXD_2, and TXD_2 pins are not multiplexed in the H8/36037.
Figure 1.2 Pin Arrangement of F-ZTATTM and Masked ROM Versions (FP-64K, FP-64A)
Rev. 4.00 Mar. 15, 2006 Page 4 of 556
REJ09B0026-0400
Section 1 Overview
1.4
Pin Functions
Table 1.1
Pin Functions
Pin No.
Type
Symbol
FP-64K
FP-64A
I/O
Functions
Power
source pins
VCC
12
Input
Power supply pin. Connect this pin to the
system power supply.
VSS
9
Input
Ground pin. Connect this pin to the system
power supply (0 V).
AVCC
3
Input
Analog power supply pin for the A/D converter.
When the A/D converter is not used, connect
this pin to the system power supply.
VCL
6
Input
Internal step-down power supply pin. Connect
a capacitor of around 0.1 µF between this pin
and the Vss pin for stabilization.
OSC1
11
Input
OSC2
10
Output
These pins connect with crystal or ceramic
resonator for the system clock, or can be used
to input an external clock.
Clock pins
See section 5, Clock Pulse Generators, for a
typical connection.
System
control
Interrupt
pins
RES
7
Input
Reset pin. The pull-up resistor (typ. 150 kΩ) is
incorporated. When driven low, the chip is
reset.
TEST
8
Input
Test pin. Connect this pin to Vss.
NMI
35
Input
Non-maskable interrupt request input pin. Must
be pulled-up with a resistor.
IRQ0 to
IRQ3
51 to 54
Input
External interrupt request input pins. Can
select the rising or falling edge.
WKP0 to
WKP5
13, 14,
19 to 22
Input
External interrupt request input pins. Can
select the rising or falling edge.
Timer B1
TMIB1
52
Input
External event input pin.
Timer V
TMOV
30
Output
This is an output pin for waveforms generated
by the output compare function.
TMCIV
29
Input
External event input pin.
TMRIV
28
Input
Counter reset input pin.
TRGV
54
Input
Counter start trigger input pin.
Rev. 4.00 Mar. 15, 2006 Page 5 of 556
REJ09B0026-0400
Section 1 Overview
Pin No.
Type
Symbol
FP-64K
FP-64A
I/O
Functions
Timer Z
FTIOA0
36
I/O
Output compare output/input capture
input/external clock input pin.
FTIOB0
34
I/O
Output compare output/input capture
input/PWM output pin.
FTIOC0
33
I/O
Output compare output/input capture
input/PWM sync output pin (at a reset,
complementary PWM mode).
FTIOD0
32
I/O
Output compare output/input capture
input/PWM output pin.
FTIOA1
37
I/O
Output compare output/input capture
input/PWM output pin (at a reset,
complementary PWM mode).
FTIOB1 to
FTIOD1
38 to 40
I/O
Output compare output/input capture
input/PWM output pins.
TXD,
TXD_2*
46, 50
Output
Transmit data output pins.
RXD,
RXD_2*
45, 49
Input
Receive data input pins.
SCK3,
SCK3_2*
44, 48
I/O
Clock I/O pins.
17
Input
Receive data input pin.
18
Output
Transmit data output pin.
58
I/O
Chip select I/O pin.
57
I/O
Clock I/O pin.
55
I/O
Transmit/receive data I/O pin.
56
I/O
Transmit/receive data I/O pin.
AN7 to AN0 2, 1,
59 to 64
Input
Analog input pins.
ADTRG
Input
Conversion start trigger input pin.
Serial communication
interface
(SCI)
Controller
HRXD
area network HTXD
for Tiny
(TinyCAN)
Synchronous SCS
serial commSSCK
unication unit
SSI
(SSU)
SSO
A/D
converter
22
Rev. 4.00 Mar. 15, 2006 Page 6 of 556
REJ09B0026-0400
Section 1 Overview
Pin No.
Type
Symbol
I/O ports
Note:
*
FP-64K
FP-64A
I/O
Functions
PB7 to PB0 1, 2,
59 to 64
Input
8-bit input ports.
P17 to P14, 51 to 54,
P12 to P10 23 to 25
I/O
7-bit I/O ports.
P24 to P20
31, 44 to 47 I/O
5-bit I/O ports.
P57 to P50
13, 14,
19 to 22,
26, 27
I/O
8-bit I/O ports.
P67 to P60
32 to 34,
I/O
36, 37 to 40
8-bit I/O ports.
P76 to P74, 28 to 30,
P72 to P70 48 to 50
I/O
6-bit I/O ports.
P87 to P85
41 to 43
I/O
3-bit I/O ports.
P97 to P90
15 to 18,
58 to 55
I/O
8-bit I/O ports.
The SCK3_2, RXD_2, and TXD_2 pins are not multiplexed in the H8/36037.
Rev. 4.00 Mar. 15, 2006 Page 7 of 556
REJ09B0026-0400
Section 1 Overview
Rev. 4.00 Mar. 15, 2006 Page 8 of 556
REJ09B0026-0400
Section 2 CPU
Section 2 CPU
This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with
the H8/300CPU, and supports only normal mode, which has a 64-kbyte address space.
• Upward-compatible with H8/300 CPUs
 Can execute H8/300 CPUs object programs
 Additional eight 16-bit extended registers
 32-bit transfer and arithmetic and logic instructions are added
 Signed multiply and divide instructions are added.
• General-register architecture
 Sixteen 16-bit general registers also usable as sixteen 8-bit registers and eight 16-bit
registers, or eight 32-bit registers
• Sixty-two basic instructions
 8/16/32-bit data transfer and arithmetic and logic instructions
 Multiply and divide instructions
 Powerful bit-manipulation instructions
• Eight addressing modes
 Register direct [Rn]
 Register indirect [@ERn]
 Register indirect with displacement [@(d:16,ERn) or @(d:24,ERn)]
 Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
 Absolute address [@aa:8, @aa:16, @aa:24]
 Immediate [#xx:8, #xx:16, or #xx:32]
 Program-counter relative [@(d:8,PC) or @(d:16,PC)]
 Memory indirect [@@aa:8]
• 64-kbyte address space
• High-speed operation
 All frequently-used instructions execute in one or two states
 8/16/32-bit register-register add/subtract : 2 states
 8 × 8-bit register-register multiply
: 14 states
 16 ÷ 8-bit register-register divide
: 14 states
 16 × 16-bit register-register multiply
: 22 states
 32 ÷ 16-bit register-register divide
: 22 states
Rev. 4.00 Mar. 15, 2006 Page 9 of 556
REJ09B0026-0400
Section 2 CPU
• Power-down state
 Transition to power-down state by SLEEP instruction
2.1
Address Space and Memory Map
The address space of this LSI is 64 kbytes, which includes the program area and the data area.
Figures 2.1 show the memory map.
Rev. 4.00 Mar. 15, 2006 Page 10 of 556
REJ09B0026-0400
Section 2 CPU
HD64F36054
HD64F36054G
HD64F36034
HD64F36034G
(Flash memory version)
HD64F36057
HD64F36057G
HD64F36037
HD64F36037G
(Flash memory version)
H'0000
H'0049
H'004A
Interrupt vector
H'0000
H'0049
H'004A
Interrupt vector
On-chip ROM
(32 kbytes)
H'7FFF
On-chip ROM
(56 kbytes)
Not used
H'DFFF
Not used
H'EC00
H'EFFF
On-chip RAM
(1 kbyte)
Not used
H'F600
H'F77F
H'F780
H'FB7F
H'FB80
H'FF7F
H'FF80
Internal I/O register
(1-kbyte work area
for flash memory
programming)
On-chip RAM
(2 kbytes)
(1-kbyte user area)
H'F600
H'F77F
H'F780
H'FB7F
H'FB80
H'FF7F
H'FF80
Internal I/O register
H'FFFF
Internal I/O register
(1-kbyte work area
for flash memory
programming)
On-chip RAM
(2 kbytes)
(1-kbyte user area)
Internal I/O register
H'FFFF
Figure 2.1 Memory Map (1)
Rev. 4.00 Mar. 15, 2006 Page 11 of 556
REJ09B0026-0400
Section 2 CPU
HD64336054G
HD64336054
(Masked ROM version)
HD64336057G
HD64336057
(Masked ROM version)
H'0000
H'0049
H'004A
Interrupt vector
H'0000
H'0049
H'004A
Interrupt vector
HD64336037G
HD64336037
(Masked ROM version)
H'0000
H'0049
H'004A
Interrupt vector
HD64336036G
HD64336036
(Masked ROM version)
H'0000
H'0049
H'004A
On-chip ROM
(32 kbytes)
Interrupt vector
On-chip ROM
(48 kbytes)
H'7FFF
On-chip ROM
(56 kbytes)
On-chip ROM
(56 kbytes)
H'BFFF
Not used
H'DFFF
Not used
H'EC00
H'EFFF
Not used
H'EC00
On-chip RAM
(1 kbyte)
H'EFFF
Not used
H'F600
H'F77F
Internal I/O register
On-chip RAM
(1 kbyte)
H'F600
H'F77F
On-chip RAM
(1 kbyte)
Internal I/O register
Internal I/O register
H'FFFF
On-chip RAM
(1 kbyte)
H'F600
H'F77F
Internal I/O register
On-chip RAM
(1 kbyte)
H'FB80
On-chip RAM
(1 kbyte)
H'FF7F
H'FF80
H'FFFF
Figure 2.1 Memory Map (2)
REJ09B0026-0400
Internal I/O register
Not used
Internal I/O register
Internal I/O register
Rev. 4.00 Mar. 15, 2006 Page 12 of 556
Not used
H'F600
H'F77F
Not used
H'FB80
On-chip RAM
(1 kbyte)
H'EFFF
H'FF7F
H'FF80
H'FFFF
H'EC00
Not used
Not used
H'FF7F
H'FF80
On-chip RAM
(1 kbyte)
H'EFFF
H'FB80
H'FB80
H'EC00
Not used
Not used
H'FF7F
H'FF80
Not used
H'DFFF
Internal I/O register
H'FFFF
Section 2 CPU
HD64336035G
HD64336035
(Masked ROM version)
H'0000
H'0049
H'004A
Interrupt vector
HD64336033G
HD64336033
(Masked ROM version)
HD64336034G
HD64336034
(Masked ROM version)
H'0000
H'0049
H'004A
Interrupt vector
H'0000
H'0049
H'004A
On-chip ROM
(24 kbytes)
On-chip ROM
(32 kbytes)
On-chip ROM
(40 kbytes)
Interrupt vector
HD64336032G
HD64336032
(Masked ROM version)
H'0000
H'0049
H'004A
Interrupt vector
On-chip ROM
(16 kbytes)
H'3FFF
H'5FFF
H'7FFF
H'9FFF
Not used
Not used
Not used
Not used
H'EC00
H'EFFF
On-chip RAM
(1 kbyte)
H'EC00
H'EFFF
Not used
H'F600
H'F77F
Internal I/O register
Not used
H'F600
H'F77F
Not used
H'FB80
Internal I/O register
H'F600
H'F77F
Not used
H'FF7F
H'FF80
Internal I/O register
On-chip RAM
(1 kbyte)
H'F600
H'F77F
Not used
H'FF7F
H'FF80
Internal I/O register
H'FFFF
Internal I/O register
Internal I/O register
Not used
H'FB80
H'FB80
H'FB80
On-chip RAM
(1 kbyte)
H'FF7F
H'FF80
H'FFFF
On-chip RAM
(1 kbyte)
On-chip RAM
(1 kbyte)
H'FF7F
H'FF80
Internal I/O register
On-chip RAM
(1 kbyte)
Internal I/O register
H'FFFF
H'FFFF
Figure 2.1 Memory Map (3)
Rev. 4.00 Mar. 15, 2006 Page 13 of 556
REJ09B0026-0400
Section 2 CPU
2.2
Register Configuration
The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers;
general registers and control registers. The control registers are a 24-bit program counter (PC), and
an 8-bit condition-code register (CCR).
General Registers (ERn)
15
0 7
0 7
0
ER0
E0
R0H
R0L
ER1
E1
R1H
R1L
ER2
E2
R2H
R2L
ER3
E3
R3H
R3L
ER4
E4
R4H
R4L
ER5
E5
R5H
R5L
ER6
E6
R6H
R6L
ER7
E7
R7H
R7L
(SP)
Control Registers (CR)
23
0
PC
7 6 5 4 3 2 1 0
CCR I UI H U N Z V C
[Legend]
SP:
PC:
CCR:
I:
UI:
Stack pointer
Program counter
Condition-code register
Interrupt mask bit
User bit
H:
U:
N:
Z:
V:
C:
Half-carry flag
User bit
Negative flag
Zero flag
Overflow flag
Carry flag
Figure 2.2 CPU Registers
Rev. 4.00 Mar. 15, 2006 Page 14 of 556
REJ09B0026-0400
Section 2 CPU
2.2.1
General Registers
The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally
identical and can be used as both address registers and data registers. When a general register is
used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates
the usage of the general registers. When the general registers are used as 32-bit registers or address
registers, they are designated by the letters ER (ER0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit registers designated by the letters RH (R0H to R7H) and RL (R0L
to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8-bit
registers.
The usage of each register can be selected independently.
• Address registers
• 32-bit registers
• 16-bit registers
• 8-bit registers
E registers (extended registers)
(E0 to E7)
ER registers
(ER0 to ER7)
RH registers
(R0H to R7H)
R registers
(R0 to R7)
RL registers
(R0L to R7L)
Figure 2.3 Usage of General Registers
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.4 shows the
relationship between the stack pointer and the stack area.
Rev. 4.00 Mar. 15, 2006 Page 15 of 556
REJ09B0026-0400
Section 2 CPU
Empty area
SP (ER7)
Stack area
Figure 2.4 Relationship between Stack Pointer and Stack Area
2.2.2
Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched, the least significant PC bit is regarded as 0). The PC is initialized when the
start address is loaded by the vector address generated during reset exception-handling sequence.
2.2.3
Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. The I bit is initialized to 1
by reset exception-handling sequence, but other bits are not initialized.
Some instructions leave flag bits unchanged. Operations can be performed on the CCR bits by the
LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching
conditions for conditional branch (Bcc) instructions.
For the action of each instruction on the flag bits, see appendix A.1, Instruction List.
Rev. 4.00 Mar. 15, 2006 Page 16 of 556
REJ09B0026-0400
Section 2 CPU
Bit
Bit Name
Initial
Value
R/W
Description
7
I
1
R/W
Interrupt Mask Bit
Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set to
1 at the start of an exception-handling sequence.
6
UI
Undefined R/W
User Bit
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions.
5
H
Undefined R/W
Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or
NEG.B instruction is executed, this flag is set to 1 if
there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or
NEG.W instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 11, and cleared to 0
otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L
instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 27, and cleared to 0 otherwise.
4
U
Undefined R/W
User Bit
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions.
3
N
Undefined R/W
Negative Flag
Stores the value of the most significant bit of data as a
sign bit.
2
Z
Undefined R/W
Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.
1
V
Undefined R/W
Overflow Flag
Set to 1 when an arithmetic overflow occurs, and
cleared to 0 at other times.
0
C
Undefined R/W
Carry Flag
Set to 1 when a carry occurs, and cleared to 0
otherwise. Used by:
•
Add instructions, to indicate a carry
•
Subtract instructions, to indicate a borrow
•
Shift and rotate instructions, to indicate a carry
The carry flag is also used as a bit accumulator by bit
manipulation instructions.
Rev. 4.00 Mar. 15, 2006 Page 17 of 556
REJ09B0026-0400
Section 2 CPU
2.3
Data Formats
The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two
digits of 4-bit BCD data.
2.3.1
General Register Data Formats
Figure 2.5 shows the data formats in general registers.
Data Type
General Register
Data Format
7
RnH
1-bit data
0
Don't care
7 6 5 4 3 2 1 0
7
1-bit data
RnL
4-bit BCD data
RnH
4-bit BCD data
RnL
Byte data
RnH
Don't care
7
4 3
Upper
0
7 6 5 4 3 2 1 0
0
Lower
Don't care
7
Don't care
7
4 3
Upper
0
Don't care
MSB
LSB
7
Byte data
RnL
Figure 2.5 General Register Data Formats (1)
REJ09B0026-0400
0
Don't care
MSB
Rev. 4.00 Mar. 15, 2006 Page 18 of 556
0
Lower
LSB
Section 2 CPU
Data Type
General
Register
Word data
Rn
Data Format
15
Word data
MSB
En
15
MSB
Longword
data
0
LSB
0
LSB
ERn
31
16 15
MSB
0
LSB
[Legend]
ERn: General register ER
En:
General register E
Rn:
General register R
RnH: General register RH
RnL: General register RL
MSB: Most significant bit
LSB: Least significant bit
Figure 2.5 General Register Data Formats (2)
Rev. 4.00 Mar. 15, 2006 Page 19 of 556
REJ09B0026-0400
Section 2 CPU
2.3.2
Memory Data Formats
Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and
longword data in memory, however word or longword data must begin at an even address. If an
attempt is made to access word or longword data at an odd address, an address error does not
occur, however the least significant bit of the address is regarded as 0, so access begins the
preceding address. This also applies to instruction fetches.
When ER7 (SP) is used as an address register to access the stack area, the operand size should be
word or longword.
Data Type
Address
Data Format
7
1-bit data
Address L
7
Byte data
Address L
MSB
Word data
Address 2M
MSB
0
6
5
4
3
2
Address 2N
0
LSB
LSB
Address 2M+1
Longword data
1
MSB
Address 2N+1
Address 2N+2
Address 2N+3
Figure 2.6 Memory Data Formats
Rev. 4.00 Mar. 15, 2006 Page 20 of 556
REJ09B0026-0400
LSB
Section 2 CPU
2.4
Instruction Set
2.4.1
Table of Instructions Classified by Function
The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each
functional category. The notation used in tables 2.2 to 2.9 is defined below.
Table 2.1
Operation Notation
Symbol
Description
Rd
General register (destination)*
Rs
General register (source)*
Rn
General register*
ERn
General register (32-bit register or address register)
(EAd)
Destination operand
(EAs)
Source operand
CCR
Condition-code register
N
N (negative) flag in CCR
Z
Z (zero) flag in CCR
V
V (overflow) flag in CCR
C
C (carry) flag in CCR
PC
Program counter
SP
Stack pointer
#IMM
Immediate data
disp
Displacement
+
Addition
–
Subtraction
×
Multiplication
÷
Division
∧
Logical AND
∨
Logical OR
⊕
Logical XOR
→
Move
¬
NOT (logical complement)
:3/:8/:16/:24
3-, 8-, 16-, or 24-bit length
Rev. 4.00 Mar. 15, 2006 Page 21 of 556
REJ09B0026-0400
Section 2 CPU
Note:
*
General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers/address register (ER0 to ER7).
Table 2.2
Data Transfer Instructions
Instruction
Size*
Function
MOV
B/W/L
(EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general register
and memory, or moves immediate data to a general register.
MOVFPE
B
(EAs) → Rd
Cannot be used in this LSI.
MOVTPE
B
Rs → (EAs)
Cannot be used in this LSI.
POP
W/L
@SP+ → Rn
Pops a general register from the stack. POP.W Rn is identical to
MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn.
PUSH
W/L
Rn → @–SP
Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP.
[Legend]
B: Byte
W: Word
L: Longword
Note: * Refers to the operand size.
Rev. 4.00 Mar. 15, 2006 Page 22 of 556
REJ09B0026-0400
Section 2 CPU
Table 2.3
Arithmetic Operations Instructions (1)
Instruction
Size*
Function
ADD
SUB
B/W/L
Rd ± Rs → Rd, Rd ± #IMM → Rd
Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register (immediate byte data
cannot be subtracted from byte data in a general register. Use the
SUBX or ADD instruction.)
ADDX
SUBX
B
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry on byte data in two general
registers, or on immediate data and data in a general register.
INC
DEC
B/W/L
Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2. (Byte operands
can be incremented or decremented by 1 only.)
ADDS
SUBS
L
Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.
DAA
DAS
B
Rd (decimal adjust) → Rd
Decimal-adjusts an addition or subtraction result in a general register by
referring to the CCR to produce 4-bit BCD data.
MULXU
B/W
Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers: either
8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
MULXS
B/W
Rd × Rs → Rd
Performs signed multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
DIVXU
B/W
Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either 16
bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits →
16-bit quotient and 16-bit remainder.
[Legend]
B: Byte
W: Word
L: Longword
Note: * Refers to the operand size.
Rev. 4.00 Mar. 15, 2006 Page 23 of 556
REJ09B0026-0400
Section 2 CPU
Table 2.3
Arithmetic Operations Instructions (2)
Instruction
Size*
Function
DIVXS
B/W
Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16 bits
÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder.
CMP
B/W/L
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general
register or with immediate data, and sets CCR bits according to the
result.
NEG
B/W/L
0 – Rd → Rd
Takes the two's complement (arithmetic complement) of data in a
general register.
EXTU
W/L
Rd (zero extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by padding with zeros on the
left.
EXTS
W/L
Rd (sign extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by extending the sign bit.
[Legend]
B: Byte
W: Word
L: Longword
Note: * Refers to the operand size.
Rev. 4.00 Mar. 15, 2006 Page 24 of 556
REJ09B0026-0400
Section 2 CPU
Table 2.4
Logic Operations Instructions
Instruction
Size*
Function
AND
B/W/L
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR
B/W/L
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR
B/W/L
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT
B/W/L
¬ (Rd) → (Rd)
Takes the one's complement (logical complement) of general register
contents.
[Legend]
B: Byte
W: Word
L: Longword
Note: * Refers to the operand size.
Table 2.5
Shift Instructions
Instruction
Size*
Function
SHAL
SHAR
B/W/L
Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
SHLL
SHLR
B/W/L
Rd (shift) → Rd
Performs a logical shift on general register contents.
ROTL
ROTR
B/W/L
Rd (rotate) → Rd
Rotates general register contents.
ROTXL
ROTXR
B/W/L
Rd (rotate) → Rd
Rotates general register contents through the carry flag.
[Legend]
B: Byte
W: Word
L: Longword
Note: * Refers to the operand size.
Rev. 4.00 Mar. 15, 2006 Page 25 of 556
REJ09B0026-0400
Section 2 CPU
Table 2.6
Bit Manipulation Instructions (1)
Instruction
Size*
Function
BSET
B
1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory operand to 1. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BCLR
B
0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to 0. The
bit number is specified by 3-bit immediate data or the lower three bits of
a general register.
BNOT
B
¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BTST
B
¬ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory operand and sets
or clears the Z flag accordingly. The bit number is specified by 3-bit
immediate data or the lower three bits of a general register.
BAND
B
C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIAND
B
C ∧ ¬ (<bit-No.> of <EAd>) → C
ANDs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BOR
B
C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIOR
B
C ∨ ¬ (<bit-No.> of <EAd>) → C
ORs the carry flag with the inverse of a specified bit in a general register
or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
[Legend]
B: Byte
Note: *
Refers to the operand size.
Rev. 4.00 Mar. 15, 2006 Page 26 of 556
REJ09B0026-0400
Section 2 CPU
Table 2.6
Bit Manipulation Instructions (2)
Instruction
Size*
Function
BXOR
B
C ⊕ (<bit-No.> of <EAd>) → C
XORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIXOR
B
C ⊕ ¬ (<bit-No.> of <EAd>) → C
XORs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BLD
B
(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to the
carry flag.
BILD
B
¬ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST
B
C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register or
memory operand.
BIST
B
¬ C → (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a
general register or memory operand.
The bit number is specified by 3-bit immediate data.
[Legend]
B: Byte
Note: *
Refers to the operand size.
Rev. 4.00 Mar. 15, 2006 Page 27 of 556
REJ09B0026-0400
Section 2 CPU
Table 2.7
Branch Instructions
Instruction
Size
Function
Bcc*
—
Branches to a specified address if a specified condition is true. The
branching conditions are listed below.
Mnemonic
Description
Condition
BRA(BT)
Always (true)
Always
BRN(BF)
Never (false)
Never
BHI
High
C∨Z=0
BLS
Low or same
C∨Z=1
BCC(BHS)
Carry clear
(high or same)
C=0
BCS(BLO)
Carry set (low)
C=1
BNE
Not equal
Z=0
BEQ
Equal
Z=1
BVC
Overflow clear
V=0
BVS
Overflow set
V=1
BPL
Plus
N=0
BMI
Minus
N=1
BGE
Greater or equal
N⊕V=0
BLT
Less than
N⊕V=1
BGT
Greater than
Z∨(N ⊕ V) = 0
BLE
Less or equal
Z∨(N ⊕ V) = 1
JMP
—
Branches unconditionally to a specified address.
BSR
—
Branches to a subroutine at a specified address.
JSR
—
Branches to a subroutine at a specified address.
RTS
—
Returns from a subroutine
Note:
*
Bcc is the general name for conditional branch instructions.
Rev. 4.00 Mar. 15, 2006 Page 28 of 556
REJ09B0026-0400
Section 2 CPU
Table 2.8
System Control Instructions
Instruction
Size*
Function
TRAPA
—
Starts trap-instruction exception handling.
RTE
—
Returns from an exception-handling routine.
SLEEP
—
Causes a transition to a power-down state.
LDC
B/W
(EAs) → CCR
Moves the source operand contents to the CCR. The CCR size is one
byte, but in transfer from memory, data is read by word access.
STC
B/W
CCR → (EAd)
Transfers the CCR contents to a destination location. The condition
code register size is one byte, but in transfer to memory, data is written
by word access.
ANDC
B
CCR ∧ #IMM → CCR
Logically ANDs the CCR with immediate data.
ORC
B
CCR ∨ #IMM → CCR
Logically ORs the CCR with immediate data.
XORC
B
CCR ⊕ #IMM → CCR
Logically XORs the CCR with immediate data.
NOP
—
PC + 2 → PC
Only increments the program counter.
[Legend]
B: Byte
W: Word
Note: *
Refers to the operand size.
Rev. 4.00 Mar. 15, 2006 Page 29 of 556
REJ09B0026-0400
Section 2 CPU
Table 2.9
Block Data Transfer Instructions
Instruction
Size
Function
EEPMOV.B
—
if R4L ≠ 0 then
Repeat @ER5+ → @ER6+,
R4L–1 → R4L
Until R4L = 0
else next;
EEPMOV.W
—
if R4 ≠ 0 then
Repeat @ER5+ → @ER6+,
R4–1 → R4
Until R4 = 0
else next;
Transfers a data block. Starting from the address set in ER5, transfers
data for the number of bytes set in R4L or R4 to the address location set
in ER6.
Execution of the next instruction begins as soon as the transfer is
completed.
Rev. 4.00 Mar. 15, 2006 Page 30 of 556
REJ09B0026-0400
Section 2 CPU
2.4.2
Basic Instruction Formats
H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op), a register field (r), an effective address extension (EA), and a condition field
(cc).
Figure 2.7 shows examples of instruction formats.
• Operation Field
Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.
• Register Field
Specifies a general register. Address registers are specified by 3 bits, and data registers by 3
bits or 4 bits. Some instructions have two register fields. Some have no register field.
• Effective Address Extension
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A24-bit
address or displacement is treated as a 32-bit data in which the first 8 bits are 0 (H'00).
• Condition Field
Specifies the branching condition of Bcc instructions.
(1) Operation field only
op
NOP, RTS, etc.
(2) Operation field and register fields
op
rm
rn
ADD.B Rn, Rm, etc.
(3) Operation field, register fields, and effective address extension
op
rn
rm
MOV.B @(d:16, Rn), Rm
EA(disp)
(4) Operation field, effective address extension, and condition field
op
cc
EA(disp)
BRA d:8
Figure 2.7 Instruction Formats
Rev. 4.00 Mar. 15, 2006 Page 31 of 556
REJ09B0026-0400
Section 2 CPU
2.5
Addressing Modes and Effective Address Calculation
The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the
generated 24-bit address, so the effective address is 16 bits.
2.5.1
Addressing Modes
The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses
a subset of these addressing modes. Addressing modes that can be used differ depending on the
instruction. For details, refer to appendix A.4, Combinations of Instructions and Addressing
Modes.
Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer
instructions can use all addressing modes except program-counter relative and memory indirect.
Bit-manipulation instructions use register direct, register indirect, or the absolute addressing mode
(@aa:8) to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions)
or immediate (3-bit) addressing mode to specify a bit number in the operand.
Table 2.10 Addressing Modes
No.
Addressing Mode
Symbol
1
Register direct
Rn
2
Register indirect
@ERn
3
Register indirect with displacement
@(d:16,ERn)/@(d:24,ERn)
4
Register indirect with post-increment
Register indirect with pre-decrement
@ERn+
@–ERn
5
Absolute address
@aa:8/@aa:16/@aa:24
6
Immediate
#xx:8/#xx:16/#xx:32
7
Program-counter relative
@(d:8,PC)/@(d:16,PC)
8
Memory indirect
@@aa:8
(1)
Register Direct—Rn
The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the
operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7
can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
Rev. 4.00 Mar. 15, 2006 Page 32 of 556
REJ09B0026-0400
Section 2 CPU
(2)
Register Indirect—@ERn
The register field of the instruction code specifies an address register (ERn), the lower 24 bits of
which contain the address of the operand on memory.
(3)
Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn)
A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn)
specified by the register field of the instruction, and the lower 24 bits of the sum the address of a
memory operand. A 16-bit displacement is sign-extended when added.
(4)
Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn
• Register indirect with post-increment—@ERn+
The register field of the instruction code specifies an address register (ERn) the lower 24 bits
of which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is
added to the address register contents (32 bits) and the sum is stored in the address register.
The value added is 1 for byte access, 2 for word access, or 4 for longword access. For the word
or longword access, the register value should be even.
• Register indirect with pre-decrement—@-ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instruction code, and the lower 24 bits of the result is the address of a memory operand.
The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for
word access, or 4 for longword access. For the word or longword access, the register value
should be even.
(5)
Absolute Address—@aa:8, @aa:16, @aa:24
The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24)
For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit
absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the
entire address space.
The access ranges of absolute addresses for this LSI are those shown in table 2.11, because the
upper 8 bits are ignored.
Rev. 4.00 Mar. 15, 2006 Page 33 of 556
REJ09B0026-0400
Section 2 CPU
Table 2.11 Absolute Address Access Ranges
Absolute Address
Access Range
8 bits (@aa:8)
H'FF00 to H'FFFF
16 bits (@aa:16)
H'0000 to H'FFFF
24 bits (@aa:24)
H'0000 to H'FFFF
(6)
Immediate—#xx:8, #xx:16, or #xx:32
The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an
operand.
The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit
number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a
vector address.
(7)
Program-Counter Relative—@(d:8, PC) or @(d:16, PC)
This mode is used in the BSR instruction. An 8-bit or 16-bit displacement contained in the
instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. The
PC value to which the displacement is added is the address of the first byte of the next instruction,
so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768
bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an
even number.
(8)
Memory Indirect—@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand. This memory operand contains a branch address.
The memory operand is accessed by longword access. The first byte of the memory operand is
ignored, generating a 24-bit branch address. Figure 2.8 shows how to specify branch address for in
memory indirect mode. The upper bits of the absolute address are all assumed to be 0, so the
address range is 0 to 255 (H'0000 to H'00FF).
Note that the first part of the address range is also the exception vector area.
Rev. 4.00 Mar. 15, 2006 Page 34 of 556
REJ09B0026-0400
Section 2 CPU
Specified
by @aa:8
Dummy
Branch address
Figure 2.8 Branch Address Specification in Memory Indirect Mode
Rev. 4.00 Mar. 15, 2006 Page 35 of 556
REJ09B0026-0400
Section 2 CPU
2.5.2
Effective Address Calculation
Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI,
the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address.
Table 2.12 Effective Address Calculation (1)
No
1
Addressing Mode and Instruction Format
op
2
Effective Address Calculation
Effective Address (EA)
Register direct(Rn)
rm
Operand is general register contents.
rn
Register indirect(@ERn)
0
31
23
0
23
0
23
0
23
0
General register contents
op
3
r
Register indirect with displacement
@(d:16,ERn) or @(d:24,ERn)
0
31
General register contents
op
r
disp
0
31
Sign extension
4
Register indirect with post-increment or
pre-decrement
•Register indirect with post-increment @ERn+
op
31
0
General register contents
r
•Register indirect with pre-decrement @-ERn
disp
1, 2, or 4
31
0
General register contents
op
r
1, 2, or 4
The value to be added or subtracted is 1 when the
operand is byte size, 2 for word size, and 4 for
longword size.
Rev. 4.00 Mar. 15, 2006 Page 36 of 556
REJ09B0026-0400
Section 2 CPU
Table 2.12 Effective Address Calculation (2)
No
5
Addressing Mode and Instruction Format
Effective Address Calculation
Effective Address (EA)
Absolute address
@aa:8
8 7
23
op
abs
0
H'FFFF
@aa:16
23
op
abs
16 15
0
Sign extension
@aa:24
op
0
23
abs
6
Immediate
#xx:8/#xx:16/#xx:32
op
7
Operand is immediate data.
IMM
0
23
Program-counter relative
PC contents
@(d:8,PC)/@(d:16,PC)
op
disp
23
0
Sign
extension
8
disp
23
0
Memory indirect @@aa:8
8 7
23
op
abs
0
abs
H'0000
15
0
Memory contents
[Legend]
r, rm,rn :
op :
disp :
IMM :
abs :
23
16 15
0
H'00
Register field
Operation field
Displacement
Immediate data
Absolute address
Rev. 4.00 Mar. 15, 2006 Page 37 of 556
REJ09B0026-0400
Section 2 CPU
2.6
Basic Bus Cycle
CPU operation is synchronized by a system clock (φ) or a subclock (φSUB). The period from a rising
edge of φ or φSUB to the next rising edge is called one state. A bus cycle consists of two states or
three states. The cycle differs depending on whether access is to on-chip memory or to on-chip
peripheral modules.
2.6.1
Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access
in byte or word size. Figure 2.9 shows the on-chip memory access cycle.
Bus cycle
T2 state
T1 state
φ or φ SUB
Internal address bus
Address
Internal read signal
Internal data bus
(read access)
Read data
Internal write signal
Internal data bus
(write access)
Write data
Figure 2.9 On-Chip Memory Access Cycle
Rev. 4.00 Mar. 15, 2006 Page 38 of 556
REJ09B0026-0400
Section 2 CPU
2.6.2
On-Chip Peripheral Modules
On-chip peripheral modules are accessed in two states, three states, or four states. The data bus
width is 8 bits or 16 bits depending on the register. For description on the data bus width and
number of accessing states of each register, refer to section 21.1, Register Addresses (Address
Order). Registers with 16-bit data bus width can be accessed by word size only. Registers with 8bit data bus width can be accessed by byte or word size. When a register with 8-bit data bus width
is accessed by word size, a bus cycle occurs twice. In two-state access, the operation timing is the
same as that for on-chip memory. Figure 2.10 shows the operation timing in the case of three-state
access to an on-chip peripheral module. In four-state access, the operation timing is such that a
wait cycle is inserted between the T2 and T3 states.
Bus cycle
T1 state
T2 state
T3 state
φ or φ SUB
Internal
address bus
Address
Internal
read signal
Internal
data bus
(read access)
Read data
Internal
write signal
Internal
data bus
(write access)
Write data
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)
Rev. 4.00 Mar. 15, 2006 Page 39 of 556
REJ09B0026-0400
Section 2 CPU
2.7
CPU States
There are four CPU states: the reset state, program execution state, program halt state, and
exception-handling state. The program execution state includes active mode and subactive mode.
For the program halt state, there are a sleep mode, standby mode, and sub-sleep mode. These
states are shown in figure 2.11. Figure 2.12 shows the state transitions. For details on program
execution state and program halt state, refer to section 6, Power-Down Modes. For details on
exception processing, refer to section 3, Exception Handling.
CPU state
Reset state
The CPU is initialized
Program
execution state
Active
(high speed) mode
The CPU executes successive program
instructions at high speed,
synchronized by the system clock
Subactive mode
The CPU executes
successive program
instructions at reduced
speed, synchronized
by the subclock
Program halt state
A state in which some
or all of the chip
functions are stopped
to conserve power
Sleep mode
Standby mode
Subsleep mode
Exceptionhandling state
A transient state in which the CPU changes
the processing flow due to a reset or an interrupt
Figure 2.11 CPU Operation States
Rev. 4.00 Mar. 15, 2006 Page 40 of 556
REJ09B0026-0400
Power-down
modes
Section 2 CPU
Reset cleared
Reset state
Exception-handling state
Reset occurs
Reset
occurs
Reset
occurs
Interrupt
source
Program halt state
Interrupt
source
Exceptionhandling
complete
Program execution state
SLEEP instruction executed
Figure 2.12 State Transitions
Rev. 4.00 Mar. 15, 2006 Page 41 of 556
REJ09B0026-0400
Section 2 CPU
2.8
Usage Notes
2.8.1
Notes on Data Access to Empty Areas
The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip
I/O registers areas available to the user. When data is transferred from CPU to empty areas, the
transferred data will be lost. This action may also cause the CPU to malfunction. When data is
transferred from an empty area to CPU, the contents of the data cannot be guaranteed.
2.8.2
EEPMOV Instruction
EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L,
which starts from the address indicated by R5, to the address indicated by R6. Set R4L and R6 so
that the end address of the destination address (value of R6 + R4L) does not exceed H'FFFF (the
value of R6 must not change from H'FFFF to H'0000 during execution).
2.8.3
Bit-Manipulation Instruction
The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in
byte units, manipulate the data of the target bit, and write data to the same address again in byte
units. Special care is required when using these instructions in cases where two registers are
assigned to the same address, or when a bit is directly manipulated for a port or a register
containing a write-only bit, because this may rewrite data of a bit other than the bit to be
manipulated.
(1)
Bit manipulation for two registers assigned to the same address
Example 1: Bit manipulation for the timer load register and timer counter
(Applicable for timer B1 in the H8/36057 Group and H8/36037 Group.)
Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same
address. When a bit-manipulation instruction accesses the timer load register and timer counter of
a reloadable timer, since these two registers share the same address, the following operations takes
place.
1. Data is read in byte units.
2. The CPU sets or resets the bit to be manipulated with the bit-manipulation instruction.
3. The written data is written again in byte units to the timer load register.
Rev. 4.00 Mar. 15, 2006 Page 42 of 556
REJ09B0026-0400
Section 2 CPU
The timer is counting, so the value read is not necessarily the same as the value in the timer load
register. As a result, bits other than the intended bit in the timer counter may be modified and the
modified value may be written to the timer load register.
Read
Count clock
Timer counter
Reload
Write
Timer load register
Internal data bus
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same
Address
Example 2: The BSET instruction is executed for port 5.
P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at
P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level
signal at P50 with a BSET instruction is shown below.
• Prior to executing BSET instruction
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR5
0
0
1
1
1
1
1
1
PDR5
1
0
0
0
0
0
0
0
• BSET instruction executed instruction
BSET
#0,
@PDR5
The BSET instruction is executed for port 5.
Rev. 4.00 Mar. 15, 2006 Page 43 of 556
REJ09B0026-0400
Section 2 CPU
• After executing BSET instruction
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR5
0
0
1
1
1
1
1
1
PDR5
0
1
0
0
0
0
0
1
• Description on operation
1. When the BSET instruction is executed, first the CPU reads port 5.
Since P57 and P56 are input pins, the CPU reads the pin states (low-level and high-level
input).
P55 to P50 are output pins, so the CPU reads the value in PDR5. In this example PDR5 has a
value of H'80, but the value read by the CPU is H'40.
2. Next, the CPU sets bit 0 of the read data to 1, changing the PDR5 data to H'41.
3. Finally, the CPU writes H'41 to PDR5, completing execution of BSET instruction.
As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level signal.
However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem, store a copy
of the PDR5 data in a work area in memory. Perform the bit manipulation on the data in the work
area, then write this data to PDR5.
• Prior to executing BSET instruction
MOV.B
MOV.B
MOV.B
#80,
R0L,
R0L,
R0L
@RAM0
@PDR5
The PDR5 value (H'80) is written to a work area in
memory (RAM0) as well as to PDR5.
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR5
0
0
1
1
1
1
1
1
PDR5
1
0
0
0
0
0
0
0
RAM0
1
0
0
0
0
0
0
0
Rev. 4.00 Mar. 15, 2006 Page 44 of 556
REJ09B0026-0400
Section 2 CPU
• BSET instruction executed
BSET
#0,
@RAM0
The BSET instruction is executed designating the PDR5
work area (RAM0).
• After executing BSET instruction
MOV.B
MOV.B
@RAM0, R0L
R0L, @PDR5
P57
The work area (RAM0) value is written to PDR5.
P56
P55
P54
P53
P52
P51
P50
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR5
0
0
1
1
1
1
1
1
PDR5
1
0
0
0
0
0
0
1
RAM0
1
0
0
0
0
0
0
1
(2)
Bit Manipulation in a Register Containing a Write-Only Bit
Example 3: BCLR instruction executed designating port 5 control register PCR5
P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at
P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as
an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be
input to this input pin.
• Prior to executing BCLR instruction
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR5
0
0
1
1
1
1
1
1
PDR5
1
0
0
0
0
0
0
0
Rev. 4.00 Mar. 15, 2006 Page 45 of 556
REJ09B0026-0400
Section 2 CPU
• BCLR instruction executed
BCLR
#0,
@PCR5
The BCLR instruction is executed for PCR5.
• After executing BCLR instruction
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Output
Output
Output
Output
Output
Output
Output
Input
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR5
1
1
1
1
1
1
1
0
PDR5
1
0
0
0
0
0
0
0
• Description on operation
1. When the BCLR instruction is executed, first the CPU reads PCR5. Since PCR5 is a write-only
register, the CPU reads a value of H'FF, even though the PCR5 value is actually H'3F.
2. Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE.
3. Finally, H'FE is written to PCR5 and BCLR instruction execution ends.
As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However, bits 7
and 6 in PCR5 change to 1, so that P57 and P56 change from input pins to output pins. To prevent
this problem, store a copy of the PDR5 data in a work area in memory and manipulate data of the
bit in the work area, then write this data to PDR5.
• Prior to executing BCLR instruction
MOV.B
MOV.B
MOV.B
#3F,
R0L,
R0L,
R0L
@RAM0
@PCR5
The PCR5 value (H'3F) is written to a work area in
memory (RAM0) as well as to PCR5.
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR5
0
0
1
1
1
1
1
1
PDR5
1
0
0
0
0
0
0
0
RAM0
0
0
1
1
1
1
1
1
Rev. 4.00 Mar. 15, 2006 Page 46 of 556
REJ09B0026-0400
Section 2 CPU
• BCLR instruction executed
BCLR
#0,
@RAM0
The BCLR instructions executed for the PCR5 work area
(RAM0).
• After executing BCLR instruction
MOV.B
MOV.B
@RAM0, R0L
R0L, @PCR5
The work area (RAM0) value is written to PCR5.
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR5
0
0
1
1
1
1
1
0
PDR5
1
0
0
0
0
0
0
0
RAM0
0
0
1
1
1
1
1
0
Rev. 4.00 Mar. 15, 2006 Page 47 of 556
REJ09B0026-0400
Section 2 CPU
Rev. 4.00 Mar. 15, 2006 Page 48 of 556
REJ09B0026-0400
Section 3 Exception Handling
Section 3 Exception Handling
Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts.
• Reset
A reset has the highest exception priority. Exception handling starts as soon as the reset is
cleared by the RES pin. The chip is also reset when the watchdog timer overflows, and
exception handling starts. Exception handling is the same as exception handling by the RES
pin.
• Trap Instruction
Exception handling starts when a trap instruction (TRAPA) is executed. The TRAPA
instruction generates a vector address corresponding to a vector number from 0 to 3, as
specified in the instruction code. Exception handling can be executed at all times in the
program execution state, regardless of the setting of the I bit in CCR.
• Interrupts
External interrupts other than NMI and internal interrupts other than address break are masked
by the I bit in CCR, and kept masked while the I bit is set to 1. Exception handling starts when
the current instruction or exception handling ends, if an interrupt request has been issued.
Rev. 4.00 Mar. 15, 2006 Page 49 of 556
REJ09B0026-0400
Section 3 Exception Handling
3.1
Exception Sources and Vector Address
Table 3.1 shows the vector addresses and priority of each exception handling. When more than
one interrupt is requested, handling is performed from the interrupt with the highest priority.
Table 3.1
Exception Sources and Vector Address
Relative Module
Exception Sources
Vector
Number
Vector Address
Priority
RES pin
Watchdog timer
Reset
0
H'0000 to H'0001
High

Reserved for system use
1 to 6
H'0002 to H'000D
External interrupt
pin
NMI
7
H'000E to H'000F
CPU
Trap instruction
(#0)
8
H'0010 to H'0011
(#1)
9
H'0012 to H'0013
(#2)
10
H'0014 to H'0015
(#3)
11
H'0016 to H'0017
Address break
Break conditions satisfied
12
H'0018 to H'0019
CPU
Direct transition by executing the
SLEEP instruction
13
H'001A to H'001B
External interrupt
pin
IRQ0
Low-voltage detection interrupt*1
14
H'001C to H'001D
IRQ1
15
H'001E to H'001F
IRQ2
16
H'0020 to H'0021
IRQ3
17
H'0022 to H'0023
WKP
18
H'0024 to H'0025
Reserved for system use
19
H'0026 to H'0027
20
H'0028 to H'0029

Timer V
Timer V compare match A
Timer V compare match B
Timer V overflow
22
H'002C to H'002D
SCI3
SCI3 receive data full
SCI3 transmit data empty
SCI3 transmit end
SCI3 receive error
23
H'002E to H'002F

Reserved for system use
24
H'0030 to H'0031
A/D converter
A/D conversion end
25
H'0032 to H'0033
Rev. 4.00 Mar. 15, 2006 Page 50 of 556
REJ09B0026-0400
Low
Section 3 Exception Handling
Vector
Number
Vector Address
Priority
Compare match/input capture
A0 to D0
Timer Z overflow
26
H'0034 to H'0035
High
Compare match/input capture
A1 to D1
Timer Z overflow
Timer Z underflow
27
H'0036 to H'0037
Relative Module
Exception Sources
Timer Z
Timer B1
Timer B1 overflow
29
H'003A to H'003B
SCI3_2*2
Receive data full
Transmit data empty
Transmit end
Receive error
32
H'0040 to H'0041
TinyCAN
Error
34
Reset/HALT mode processing
Message reception
Message transmission
Wakeup
H'0044 to H'0045
SSU
Overrun error
Transmit data empty
Transmit end
Receive data full
Conflict error
35
H'0046 to H'0047
Subtimer
Underflow
36
H'0048 to H'0049
Low
Notes: 1. A low-voltage detection interrupt is enabled only in the product with an on-chip poweron reset and low-voltage detection circuit.
2. The H8/36037 Group does not have the SCI3_2.
Rev. 4.00 Mar. 15, 2006 Page 51 of 556
REJ09B0026-0400
Section 3 Exception Handling
3.2
Register Descriptions
Interrupts are controlled by the following registers.
•
•
•
•
•
•
•
Interrupt edge select register 1 (IEGR1)
Interrupt edge select register 2 (IEGR2)
Interrupt enable register 1 (IENR1)
Interrupt enable register 2 (IENR2)
Interrupt flag register 1 (IRR1)
Interrupt flag register 2 (IRR2)
Wakeup interrupt flag register (IWPR)
3.2.1
Interrupt Edge Select Register 1 (IEGR1)
IEGR1 selects the direction of an edge that generates interrupt requests of pins NMI and IRQ3 to
IRQ0.
Bit
Bit Name
Initial
Value
R/W
Description
7
NMIEG
0
R/W
NMI Edge Select
0: Falling edge of NMI pin input is detected
1: Rising edge of NMI pin input is detected
6 to 4

All 1

Reserved
These bits are always read as 1.
3
IEG3
0
R/W
IRQ3 Edge Select
0: Falling edge of IRQ3 pin input is detected
1: Rising edge of IRQ3 pin input is detected
2
IEG2
0
R/W
IRQ2 Edge Select
0: Falling edge of IRQ2 pin input is detected
1: Rising edge of IRQ2 pin input is detected
1
IEG1
0
R/W
IRQ1 Edge Select
0: Falling edge of IRQ1 pin input is detected
1: Rising edge of IRQ1 pin input is detected
0
IEG0
0
R/W
IRQ0 Edge Select
0: Falling edge of IRQ0 pin input is detected
1: Rising edge of IRQ0 pin input is detected
Rev. 4.00 Mar. 15, 2006 Page 52 of 556
REJ09B0026-0400
Section 3 Exception Handling
3.2.2
Interrupt Edge Select Register 2 (IEGR2)
IEGR2 selects the direction of an edge that generates interrupt requests of the pins ADTRG and
WKP5 to WKP0.
Bit
Bit Name
Initial
Value
R/W
Description
7, 6

All 1

Reserved
These bits are always read as 1.
5
WPEG5
0
R/W
WKP5 Edge Select
0: Falling edge of WKP5(ADTRG) pin input is detected
1: Rising edge of WKP5(ADTRG) pin input is detected
4
WPEG4
0
R/W
WKP4 Edge Select
0: Falling edge of WKP4 pin input is detected
1: Rising edge of WKP4 pin input is detected
3
WPEG3
0
R/W
WKP3 Edge Select
0: Falling edge of WKP3 pin input is detected
1: Rising edge of WKP3 pin input is detected
2
WPEG2
0
R/W
WKP2 Edge Select
0: Falling edge of WKP2 pin input is detected
1: Rising edge of WKP2 pin input is detected
1
WPEG1
0
R/W
WKP1Edge Select
0: Falling edge of WKP1 pin input is detected
1: Rising edge of WKP1 pin input is detected
0
WPEG0
0
R/W
WKP0 Edge Select
0: Falling edge of WKP0 pin input is detected
1: Rising edge of WKP0 pin input is detected
Rev. 4.00 Mar. 15, 2006 Page 53 of 556
REJ09B0026-0400
Section 3 Exception Handling
3.2.3
Interrupt Enable Register 1 (IENR1)
IENR1 enables direct transition interrupts and external pin interrupts.
Bit
Bit Name
Initial
Value
R/W
Description
7
IENDT
0
R/W
Direct Transfer Interrupt Enable
When this bit is set to 1, direct transition interrupt
requests are enabled.
6

0

Reserved
This bit is always read as 1.
5
IENWP
0
R/W
Wakeup Interrupt Enable
This bit is an enable bit, which is common to the pins
WKP5 to WKP0. When the bit is set to 1, interrupt
requests are enabled.
4

1

Reserved
This bit is always read as 1.
3
IEN3
0
R/W
IRQ3 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ3
pin are enabled.
2
IEN2
0
R/W
IRQ2 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ2
pin are enabled.
1
IEN1
0
R/W
IRQ1 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ1
pin are enabled.
0
IEN0
0
R/W
IRQ0 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ0
pin are enabled.
When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in
an interrupt flag register, always do so while interrupts are masked (I = 1). If the above clear
operations are performed while I = 0, and as a result a conflict arises between the clear instruction
and an interrupt request, exception handling for the interrupt will be executed after the clear
instruction has been executed.
Rev. 4.00 Mar. 15, 2006 Page 54 of 556
REJ09B0026-0400
Section 3 Exception Handling
3.2.4
Interrupt Enable Register 2 (IENR2)
IENR2 enables, timer B1 overflow interrupts.
Bit
Bit Name
Initial
Value
R/W
Description
7, 6

All 0

Reserved
These bits are always read as 0.
5
IENTB1
0
R/W
Timer B1 Interrupt Enable
When this bit is set to 1, timer B1 overflow interrupt
requests are enabled.
4 to 0

All 1

Reserved
These bits are always read as 1.
When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in
an interrupt flag register, always do so while interrupts are masked (I = 1). If the above clear
operations are performed while I = 0, and as a result a conflict arises between the clear instruction
and an interrupt request, exception handling for the interrupt will be executed after the clear
instruction has been executed.
3.2.5
Interrupt Flag Register 1 (IRR1)
IRR1 is a status flag register for direct transition interrupts and IRQ3 to IRQ0 interrupt requests.
Bit
Bit Name
Initial
Value
R/W
Description
7
IRRDT
0
R/W
Direct Transfer Interrupt Request Flag
[Setting condition]
When a direct transfer is made by executing a SLEEP
instruction while DTON in SYSCR2 is set to 1.
[Clearing condition]
When IRRDT is cleared by writing 0
6

0

Reserved
This bit is always read as 0.
5, 4

All 1

Reserved
These bits are always read as 1.
Rev. 4.00 Mar. 15, 2006 Page 55 of 556
REJ09B0026-0400
Section 3 Exception Handling
Bit
Bit Name
Initial
Value
R/W
Description
3
IRRI3
0
R/W
IRQ3 Interrupt Request Flag
[Setting condition]
When IRQ3 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IRRI3 is cleared by writing 0
2
IRRI2
0
R/W
IRQ2 Interrupt Request Flag
[Setting condition]
When IRQ2 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IRRI2 is cleared by writing 0
1
IRRI1
0
R/W
IRQ1 Interrupt Request Flag
[Setting condition]
When IRQ1 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IRRI1 is cleared by writing 0
0
IRRl0
0
R/W
IRQ0 Interrupt Request Flag
[Setting condition]
When IRQ0 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IRRI0 is cleared by writing 0
Rev. 4.00 Mar. 15, 2006 Page 56 of 556
REJ09B0026-0400
Section 3 Exception Handling
3.2.6
Interrupt Flag Register 2 (IRR2)
IRR2 is a status flag register for timer B1 overflow interrupts.
Bit
Bit Name
Initial
Value
R/W
Description
7, 6

All 0

Reserved
These bits are always read as 0.
5
IRRTB1
0
R/W
Timer B1 Interrupt Request flag
[Setting condition]
When the timer B1 counter value overflows
[Clearing condition]
When IRRTB1 is cleared by writing 0
4 to 0

All 1

Reserved
These bits are always read as 1.
3.2.7
Wakeup Interrupt Flag Register (IWPR)
IWPR is a status flag register for WKP5 to WKP0 interrupt requests.
Bit
Bit Name
Initial
Value
R/W
Description
7, 6

All 1

Reserved
These bits are always read as 1.
5
IWPF5
0
R/W
WKP5 Interrupt Request Flag
[Setting condition]
When WKP5 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IWPF5 is cleared by writing 0.
4
IWPF4
0
R/W
WKP4 Interrupt Request Flag
[Setting condition]
When WKP4 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IWPF4 is cleared by writing 0.
Rev. 4.00 Mar. 15, 2006 Page 57 of 556
REJ09B0026-0400
Section 3 Exception Handling
Bit
Bit Name
Initial
Value
R/W
Description
3
IWPF3
0
R/W
WKP3 Interrupt Request Flag
[Setting condition]
When WKP3 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IWPF3 is cleared by writing 0.
2
IWPF2
0
R/W
WKP2 Interrupt Request Flag
[Setting condition]
When WKP2 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IWPF2 is cleared by writing 0.
1
IWPF1
0
R/W
WKP1 Interrupt Request Flag
[Setting condition]
When WKP1 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IWPF1 is cleared by writing 0.
0
IWPF0
0
R/W
WKP0 Interrupt Request Flag
[Setting condition]
When WKP0 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IWPF0 is cleared by writing 0.
Rev. 4.00 Mar. 15, 2006 Page 58 of 556
REJ09B0026-0400
Section 3 Exception Handling
3.3
Reset Exception Handling
When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of
the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure
that this LSI is reset at power-up, hold the RES pin low until the clock pulse generator output
stabilizes. To reset the chip during operation, hold the RES pin low for at least 10 system clock
cycles. When the RES pin goes high after being held low for the necessary time, this LSI starts
reset exception handling. The reset exception handling sequence is shown in figure 3.1. However,
for the reset exception handling sequence of the product with on-chip power-on reset circuit, refer
to section 19, Power-On Reset and Low-Voltage Detection Circuits (Optional).
The reset exception handling sequence is as follows:
1. Set the I bit in the condition code register (CCR) to 1.
2. The CPU generates a reset exception handling vector address (from H'0000 to H'0001), the
data in that address is sent to the program counter (PC) as the start address, and program
execution starts from that address.
Rev. 4.00 Mar. 15, 2006 Page 59 of 556
REJ09B0026-0400
Section 3 Exception Handling
3.4
Interrupt Exception Handling
3.4.1
External Interrupts
As the external interrupts, there are NMI, IRQ3 to IRQ0, and WKP5 to WKP0 interrupts.
NMI Interrupt: NMI interrupt is requested by input signal edge to pin NMI. This interrupt is
detected by either rising edge sensing or falling edge sensing, depending on the setting of bit
NMIEG in IEGR1.
NMI is the highest-priority interrupt, and can always be accepted without depending on the I bit
value in CCR.
IRQ3 to IRQ0 Interrupts: IRQ3 to IRQ0 interrupts are requested by input signals to pins IRQ3
to IRQ0. These four interrupts are given different vector addresses, and are detected individually
by either rising edge sensing or falling edge sensing, depending on the settings of bits IEG3 to
IEG0 in IEGR1.
When pins IRQ3 to IRQ0 are designated for interrupt input in PMR1 and the designated signal
edge is input, the corresponding bit in IRR1 is set to 1, requesting the CPU of an interrupt. These
interrupts can be masked by setting bits IEN3 to IEN0 in IENR1.
WKP5 to WKP0 Interrupts: WKP5 to WKP0 interrupts are requested by input signals to pins
WKP5 to WKP0. These six interrupts have the same vector addresses, and are detected
individually by either rising edge sensing or falling edge sensing, depending on the settings of bits
WPEG5 to WPEG0 in IEGR2.
When pins WKP5 to WKP0 are designated for interrupt input in PMR5 and the designated signal
edge is input, the corresponding bit in IWPR is set to 1, requesting the CPU of an interrupt. These
interrupts can be masked by setting bit IENWP in IENR1.
Rev. 4.00 Mar. 15, 2006 Page 60 of 556
REJ09B0026-0400
Section 3 Exception Handling
Reset cleared
Initial program
instruction prefetch
Vector fetch Internal
processing
RES
φ
Internal
address bus
(1)
(2)
Internal read
signal
Internal write
signal
Internal data
bus (16 bits)
(2)
(3)
(1) Reset exception handling vector address (H'0000)
(2) Program start address
(3) Initial program instruction
Figure 3.1 Reset Sequence
3.4.2
Internal Interrupts
Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to
enable or disable the interrupt. For direct transfer interrupt request generated by execution of a
SLEEP instruction, this function is included in IRR1, IRR2, IENR1, and IENR2.
When an on-chip peripheral module requests an interrupt, the corresponding interrupt request
status flag is set to 1, requesting the CPU of an interrupt. These interrupts can be masked by
writing 0 to clear the corresponding enable bit.
Rev. 4.00 Mar. 15, 2006 Page 61 of 556
REJ09B0026-0400
Section 3 Exception Handling
3.4.3
Interrupt Handling Sequence
Interrupts are controlled by an interrupt controller.
Interrupt operation is described as follows.
1. If an interrupt occurs while the NMI or interrupt enable bit is set to 1, an interrupt request
signal is sent to the interrupt controller.
2. When multiple interrupt requests are generated, the interrupt controller requests to the CPU for
the interrupt handling with the highest priority at that time according to table 3.1. Other
interrupt requests are held pending.
3. The CPU accepts the NMI and address break without depending on the I bit value. Other
interrupt requests are accepted, if the I bit is cleared to 0 in CCR; if the I bit is set to 1, the
interrupt request is held pending.
4. If the CPU accepts the interrupt after processing of the current instruction is completed,
interrupt exception handling will begin. First, both PC and CCR are pushed onto the stack. The
state of the stack at this time is shown in figure 3.2. The PC value pushed onto the stack is the
address of the first instruction to be executed upon return from interrupt handling.
5. Then, the I bit of CCR is set to 1, masking further interrupts excluding the NMI and address
break. Upon return from interrupt handling, the values of I bit and other bits in CCR will be
restored and returned to the values prior to the start of interrupt exception handling.
6. Next, the CPU generates the vector address corresponding to the accepted interrupt, and
transfers the address to PC as a start address of the interrupt handling-routine. Then a program
starts executing from the address indicated in PC.
Figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip ROM and
the stack area is in the on-chip RAM.
Rev. 4.00 Mar. 15, 2006 Page 62 of 556
REJ09B0026-0400
Section 3 Exception Handling
SP – 4
SP (R7)
CCR
SP – 3
SP + 1
CCR*3
SP – 2
SP + 2
PCH
SP – 1
SP + 3
PCL
SP (R7)
SP + 4
Even address
Stack area
Prior to start of interrupt
exception handling
PC and CCR
saved to stack
After completion of interrupt
exception handling
[Legend]
PCH : Upper 8 bits of program counter (PC)
PCL : Lower 8 bits of program counter (PC)
CCR: Condition code register
SP: Stack pointer
Notes: 1. PC shows the address of the first instruction to be executed upon return from the interrupt
handling routine.
2. Register contents must always be saved and restored by word length, starting from
an even-numbered address.
3. Ignored when returning from the interrupt handling routine.
Figure 3.2 Stack Status after Exception Handling
3.4.4
Interrupt Response Time
Table 3.2 shows the number of wait states after an interrupt request flag is set until the first
instruction of the interrupt handling-routine is executed.
Table 3.2
Interrupt Wait States
Item
States
Total
Waiting time for completion of executing instruction*
1 to 23
15 to 37
Saving of PC and CCR to stack
4
Vector fetch
2
Instruction fetch
4
Internal processing
4
Note:
*
Not including EEPMOV instruction.
Rev. 4.00 Mar. 15, 2006 Page 63 of 556
REJ09B0026-0400
REJ09B0026-0400
Rev. 4.00 Mar. 15, 2006 Page 64 of 556
Figure 3.3 Interrupt Sequence
(2)
(1)
(4)
Instruction
prefetch
(3)
Internal
processing
(5)
(1)
Stack access
(6)
(7)
(9)
Vector fetch
(8)
(1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.)
(2)(4) Instruction code (not executed)
(3) Instruction prefetch address (Instruction is not executed.)
(5) SP – 2
(6) SP – 4
(7) CCR
(8) Vector address
(9) Starting address of interrupt-handling routine (contents of vector)
(10) First instruction of interrupt-handling routine
Internal data bus
(16 bits)
Internal write
signal
Internal read
signal
Internal
address bus
φ
Interrupt
request signal
Interrupt level
decision and wait for
end of instruction
Interrupt is
accepted
(10)
(9)
Prefetch instruction of
Internal
interrupt-handling routine
processing
Section 3 Exception Handling
Section 3 Exception Handling
3.5
Usage Notes
3.5.1
Interrupts after Reset
If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.W #xx: 16, SP).
3.5.2
Notes on Stack Area Use
When word data is accessed, the least significant bit of the address is regarded as 0. Access to the
stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd
address. Use PUSH Rn (MOV.W Rn, @–SP) or POP Rn (MOV.W @SP+, Rn) to save or restore
register values.
3.5.3
Notes on Rewriting Port Mode Registers
When a port mode register is rewritten to switch the functions of external interrupt pins, IRQ3 to
IRQ0, and WKP5 to WKP0, the interrupt request flag may be set to 1.
When switching a pin function, mask the interrupt before setting the bit in the port mode register.
After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the
interrupt request flag from 1 to 0.
Figure 3.4 shows a port mode register setting and interrupt request flag clearing procedure.
CCR I bit ← 1
Interrupts masked. (Another possibility
is to disable the relevant interrupt in
interrupt enable register 1.)
Set port mode register bit
Execute NOP instruction
After setting the port mode register bit,
first execute at least one instruction
(e.g., NOP), then clear the interrupt
request flag to 0.
Clear interrupt request flag to 0
CCR I bit ← 0
Interrupt mask cleared
Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure
Rev. 4.00 Mar. 15, 2006 Page 65 of 556
REJ09B0026-0400
Section 3 Exception Handling
Rev. 4.00 Mar. 15, 2006 Page 66 of 556
REJ09B0026-0400
Section 4 Address Break
Section 4 Address Break
The address break simplifies on-board program debugging. It requests an address break interrupt
when the set break condition is satisfied. The interrupt request is not affected by the I bit in CCR.
Break conditions that can be set include instruction execution at a specific address and a
combination of access and data at a specific address. With the address break function, the
execution start point of a program containing a bug is detected and execution is branched to the
correcting program. Figure 4.1 shows a block diagram of the address break.
Internal address bus
Comparator
BARL
ABRKCR
Interrupt
generation
control circuit
ABRKSR
BDRH
Internal data bus
BARH
BDRL
Comparator
Interrupt
[Legend]
BARH, BARL:
BDRH, BDRL:
ABRKCR:
ABRKSR:
Break address register
Break data register
Address break control register
Address break status register
Figure 4.1 Block Diagram of Address Break
Rev. 4.00 Mar. 15, 2006 Page 67 of 556
REJ09B0026-0400
Section 4 Address Break
4.1
Register Descriptions
The address break has the following registers.
•
•
•
•
Address break control register (ABRKCR)
Address break status register (ABRKSR)
Break address register (BARH, BARL)
Break data register (BDRH, BDRL)
4.1.1
Address Break Control Register (ABRKCR)
ABRKCR sets address break conditions.
Bit
Bit Name
Initial
Value
R/W
Description
7
RTINTE
1
R/W
RTE Interrupt Enable
When this bit is 0, the interrupt immediately after
executing RTE is masked and then one instruction must
be executed. When this bit is 1, the interrupt is not
masked.
6
CSEL1
0
R/W
Condition Select 1 and 0
5
CSEL0
0
R/W
These bits set address break conditions.
00: Instruction execution cycle
01: CPU data read cycle
10: CPU data write cycle
11: CPU data read/write cycle
4
ACMP2
0
R/W
Address Compare Condition Select 2 to 0
3
ACMP1
0
R/W
2
ACMP0
0
R/W
These bits set the comparison condition between the
address set in BAR and the internal address bus.
000: Compares 16-bit addresses
001: Compares upper 12-bit addresses
010: Compares upper 8-bit addresses
011: Compares upper 4-bit addresses
1XX: Reserved (setting prohibited)
Rev. 4.00 Mar. 15, 2006 Page 68 of 556
REJ09B0026-0400
Section 4 Address Break
Bit
Bit Name
Initial
Value
R/W
Description
1
DCMP1
0
R/W
Data Compare Condition Select 1 and 0
0
DCMP0
0
R/W
These bits set the comparison condition between the data
set in BDR and the internal data bus.
00: No data comparison
01: Compares lower 8-bit data between BDRL and data
bus
10: Compares upper 8-bit data between BDRH and data
bus
11: Compares 16-bit data between BDR and data bus
[Legend]
X: Don't care.
When an address break is set in the data read cycle or data write cycle, the data bus used will
depend on the combination of the byte/word access and address. Table 4.1 shows the access and
data bus used. When an I/O register space with an 8-bit data bus width is accessed in word size, a
byte access is generated twice. For details on data widths of each register, see section 21.1,
Register Addresses (Address Order).
Table 4.1
Access and Data Bus Used
Word Access
Byte Access
Even Address Odd Address
Even Address Odd Address
ROM space
Upper 8 bits
Lower 8 bits
Upper 8 bits
Upper 8 bits
RAM space
Upper 8 bits
Lower 8 bits
Upper 8 bits
Upper 8 bits
I/O register with 8-bit data bus Upper 8 bits
width
Upper 8 bits
Upper 8 bits
Upper 8 bits
I/O register with 16-bit data
bus width
Lower 8 bits
—
—
Upper 8 bits
Rev. 4.00 Mar. 15, 2006 Page 69 of 556
REJ09B0026-0400
Section 4 Address Break
4.1.2
Address Break Status Register (ABRKSR)
ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit.
Bit
Bit Name
Initial
Value
R/W
Description
7
ABIF
0
R/W
Address Break Interrupt Flag
[Setting condition]
When the condition set in ABRKCR is satisfied
[Clearing condition]
When 0 is written after ABIF=1 is read
6
ABIE
0
R/W
Address Break Interrupt Enable
When this bit is 1, an address break interrupt request is
enabled.
5 to 0
—
All 1
—
Reserved
These bits are always read as 1.
4.1.3
Break Address Registers (BARH, BARL)
BARH and BARL are 16-bit readable/writable registers that set the address for generating an
address break interrupt. When setting the address break condition to the instruction execution
cycle, set the first byte address of the instruction. The initial value of this register is H'FFFF.
4.1.4
Break Data Registers (BDRH, BDRL)
BDRH and BDRL are 16-bit readable/writable registers that set the data for generating an address
break interrupt. BDRH is compared with the upper 8-bit data bus. BDRL is compared with the
lower 8-bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is
used for even and odd addresses in the data transmission. Therefore, comparison data must be set
in BDRH for byte access. For word access, the data bus used depends on the address. See section
4.1.1, Address Break Control Register (ABRKCR), for details. The initial value of this register is
undefined.
Rev. 4.00 Mar. 15, 2006 Page 70 of 556
REJ09B0026-0400
Section 4 Address Break
4.2
Operation
When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an
interrupt request to the CPU. The ABIF bit in ABRKSR is set to 1 by the combination of the
address set in BAR, the data set in BDR, and the conditions set in ABRKCR. When the interrupt
request is accepted, interrupt exception handling starts after the instruction being executed ends.
The address break interrupt is not masked by the I bit in CCR of the CPU.
Figures 4.2 show the operation examples of the address break interrupt setting.
When the address break is specified in instruction execution cycle
Register setting
• ABRKCR = H'80
• BAR = H'025A
Program
0258
* 025A
025C
0260
0262
:
NOP
NOP
MOV.W @H'025A,R0
NOP
NOP
:
Underline indicates the address
to be stacked.
NOP
MOV
MOV
NOP
instruc- instruc- instruc- instruction
tion
tion 1
tion 2
Internal
prefetch prefetch prefetch prefetch processing
Stack save
φ
Address
bus
0258
025A
025C
025E
SP-2
SP-4
Interrupt
request
Interrupt acceptance
Figure 4.2 Address Break Interrupt Operation Example (1)
Rev. 4.00 Mar. 15, 2006 Page 71 of 556
REJ09B0026-0400
Section 4 Address Break
When the address break is specified in the data read cycle
Register setting
• ABRKCR = H'A0
• BAR = H'025A
Program
0258
025A
* 025C
0260
0262
:
NOP
NOP
MOV.W @H'025A,R0
NOP
Underline indicates the address
NOP
to be stacked.
:
MOV
MOV
NOP
MOV
NOP
Next
instruc- instruc- instruc- instruc- instruc- instrution 1
tion 2
tion
tion
tion
ction
Internal Stack
prefetch prefetch prefetch execution prefetch prefetch processing save
φ
Address
bus
025C
025E
0260
025A
0262
0264
SP-2
Interrupt
request
Interrupt acceptance
Figure 4.2 Address Break Interrupt Operation Example (2)
Rev. 4.00 Mar. 15, 2006 Page 72 of 556
REJ09B0026-0400
Section 5 Clock Pulse Generators
Section 5 Clock Pulse Generators
The clock pulse generator is provided on-chip, including both a system clock pulse generator and
a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator,
a duty correction circuit, and a system clock divider. The subclock pulse generator consists of an
on-chip oscillator, division ratio setting register, and a sub-clock divider.
Figure 5.1 shows a block diagram of the clock pulse generators.
OSC1
OSC2
System
clock
oscillator
φOSC
(fOSC)
Duty
correction
circuit
φOSC
(fOSC)
System
clock
divider
φOSC
φOSC/8
φOSC/16
φOSC/32
φOSC/64
System clock pulse generator
On-chip
oscillator
Ring
oscillator
prescaler
setting register
(ROPCR)
8 bits
φ
Prescaler S
(13 bits)
φ/2
to
φ/8192
φW/2
φw
(fw)
Subclock
divider
φW/4
φW/8
φSUB
Watchdog
timer
Subclock pulse generator
Figure 5.1 Block Diagram of Clock Pulse Generators
The basic clock signals that drive the CPU and on-chip peripheral modules are system clocks (φ)
and subclocks (φSUB). The system clock is divided by the prescaler S to become a clock signal from
φ/8192 to φ/2, which is provided to the on-chip peripheral modules. The output (φW) of the division
ratio setting register (ROPCR) for the on-chip clock pulse generator can be used as one of the
input clocks for the watchdog timer.
Rev. 4.00 Mar. 15, 2006 Page 73 of 556
REJ09B0026-0400
Section 5 Clock Pulse Generators
5.1
System Clock Generator
Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic
resonator, or by providing external clock input. Figure 5.2 shows a block diagram of the system
clock generator.
OSC 2
LPM
OSC 1
LPM: Low-power mode (standby mode, subactive mode, subsleep mode)
Figure 5.2 Block Diagram of System Clock Generator
5.1.1
Connecting Crystal Resonator
Figure 5.3 shows a typical method of connecting a crystal resonator. An AT-cut parallel-resonance
crystal resonator should be used. Figure 5.4 shows the equivalent circuit of a crystal resonator. A
resonator having the characteristics given in table 5.1 should be used.
C1
OSC 1
C2
OSC 2
C1 = C 2 = 10 to 22 pF
Figure 5.3 Typical Connection to Crystal Resonator
LS
RS
CS
OSC 1
OSC 2
C0
Figure 5.4 Equivalent Circuit of Crystal Resonator
Rev. 4.00 Mar. 15, 2006 Page 74 of 556
REJ09B0026-0400
Section 5 Clock Pulse Generators
Table 5.1
Crystal Resonator Parameters
Frequency (MHz)
2
4
8
10
16
20
RS (max)
500 Ω
120 Ω
80 Ω
60 Ω
50 Ω
40 Ω
C0 (max)
7 pF
7 pF
7 pF
7 pF
7 pF
7 pF
5.1.2
Connecting Ceramic Resonator
Figure 5.5 shows a typical method of connecting a ceramic resonator.
C1
OSC1
C2
OSC2
C1 = C2 = 5 to 30 pF
Figure 5.5 Typical Connection to Ceramic Resonator
5.1.3
External Clock Input Method
Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 5.6 shows a typical
connection. The duty cycle of the external clock signal must be 45 to 55%.
OSC1
OSC 2
External clock input
Open
Figure 5.6 Example of External Clock Input
Rev. 4.00 Mar. 15, 2006 Page 75 of 556
REJ09B0026-0400
Section 5 Clock Pulse Generators
5.2
Prescaler
5.2.1
Prescaler S
Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. It is incremented once
per clock period. Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from
the reset state. In standby mode, subactive mode, and subsleep mode, the system clock pulse
generator stops. Prescaler S also stops and is initialized to H'0000. The CPU cannot read or write
prescaler S. The output from prescaler S is shared by the on-chip peripheral modules. The divider
ratio can be set separately for each on-chip peripheral function. In active mode and sleep mode,
the clock input to prescaler S is determined by the division ratio designated by the MA2 to MA0
bits in SYSCR2.
5.3
Usage Notes
5.3.1
Note on Resonators
Resonator characteristics are closely related to board design and should be carefully evaluated by
the user, referring to the examples shown in this section. Resonator circuit constants will differ
depending on the resonator element, stray capacitance in its interconnecting circuit, and other
factors. Suitable constants should be determined in consultation with the resonator element
manufacturer. Design the circuit so that the resonator element never receives voltages exceeding
its maximum rating.
5.3.2
Notes on Board Design
When using a crystal resonator (ceramic resonator), place the resonator and its load capacitors as
close as possible to the OSC1 and OSC2 pins. Other signal lines should be routed away from the
resonator circuit to prevent induction from interfering with correct oscillation (see figure 5.7).
Avoid
Signal A
Signal B
C1
OSC1
C2
OSC2
Figure 5.7 Example of Incorrect Board Design
Rev. 4.00 Mar. 15, 2006 Page 76 of 556
REJ09B0026-0400
Section 6 Power-Down Modes
Section 6 Power-Down Modes
This LSI has six modes of operation after a reset. These include a normal active mode and four
power-down modes, in which power consumption is significantly reduced. Module standby mode
reduces power consumption by selectively halting on-chip module functions.
• Active mode
The CPU and all on-chip peripheral modules are operable on the system clock. The system
clock frequency can be selected from φosc, φosc/8, φosc/16, φosc/32, and φosc/64.
• Subactive mode
The CPU and all on-chip peripheral modules are operable on the subclock. The subclock
frequency can be selected from φw/2, φw/4, and φw/8.
• Sleep mode
The CPU halts. On-chip peripheral modules are operable on the system clock.
• Subsleep mode
The CPU halts. On-chip peripheral modules are operable on the subclock.
• Standby mode
The CPU and all on-chip peripheral modules halt.
• Module standby mode
Independent of the above modes, power consumption can be reduced by halting on-chip
peripheral modules that are not used in module units.
Rev. 4.00 Mar. 15, 2006 Page 77 of 556
REJ09B0026-0400
Section 6 Power-Down Modes
6.1
Register Descriptions
The registers related to power-down modes are listed below.
•
•
•
•
System control register 1 (SYSCR1)
System control register 2 (SYSCR2)
Module standby control register 1 (MSTCR1)
Module standby control register 2 (MSTCR2)
6.1.1
System Control Register 1 (SYSCR1)
SYSCR1 controls the power-down modes, as well as SYSCR2.
Bit
Bit Name
Initial
Value
R/W
Description
7
SSBY
0
R/W
Software Standby
This bit selects the mode to transit after the execution of
the SLEEP instruction.
0: Enters sleep mode or subsleep mode.
1: Enters standby mode.
For details, see table 6.2.
6
STS2
0
R/W
Standby Timer Select 2 to 0
5
STS1
0
R/W
4
STS0
0
R/W
These bits designate the time the CPU and peripheral
modules wait for stable clock operation after exiting from
standby mode, subactive mode, or subsleep mode to
active mode or sleep mode due to an interrupt. The
designation should be made according to the clock
frequency so that the waiting time is at least 6.5 ms. The
relationship between the specified value and the number
of wait states is shown in table 6.1. When an external
clock is to be used, the minimum value (STS2 = STS1 =
STS0 =1) is recommended.
3 to 0

All 0

Reserved
These bits are always read as 0.
Rev. 4.00 Mar. 15, 2006 Page 78 of 556
REJ09B0026-0400
Section 6 Power-Down Modes
Table 6.1
Operating Frequency and Waiting Time
Bit Name
Operating Frequency
STS2 STS1 STS0 Waiting Time
0
0
1
1
0
1
20 MHz 16 MHz
10 MHz 8 MHz 4 MHz 2 MHz 1 MHz 0.5 MHz
0
8,192 states
0.4
0.5
0.8
1.0
2.0
4.1
8.1
16.4
1
16,384 states
0.8
1.0
1.6
2.0
4.1
8.2
16.4
32.8
0
32,768 states
1.6
2.0
3.3
4.1
8.2
16.4
32.8
65.5
1
65,536 states
3.3
4.1
6.6
8.2
16.4
32.8
65.5
131.1
0
131,072 states
6.6
8.2
13.1
16.4
32.8
65.5
131.1 262.1
1
1,024 states
0.05
0.06
0.10
0.13
0.26
0.51
1.02
2.05
0
128 states
0.00
0.00
0.01
0.02
0.03
0.06
0.13
0.26
1
16 states
0.00
0.00
0.00
0.00
0.00
0.01
0.02
0.03
Note: Time unit is ms.
6.1.2
System Control Register 2 (SYSCR2)
SYSCR2 controls the power-down modes, as well as SYSCR1.
Bit
Bit Name
Initial
Value
R/W
Description
7
SMSEL
0
R/W
Sleep Mode Selection
6
LSON
0
R/W
Low Speed on Flag
5
DTON
0
R/W
Direct Transfer on Flag
These bits select the mode to enter after the execution of
a SLEEP instruction, as well as the SSBY bit in SYSCR1.
For details, see table 6.2.
4
MA2
0
R/W
Active Mode Clock Select 2 to 0
3
MA1
0
R/W
2
MA0
0
R/W
These bits select the operating clock frequency in active
and sleep modes. The operating clock frequency
changes to the set frequency after the SLEEP instruction
is executed.
0XX: φOSC
100: φOSC/8
101: φOSC/16
110: φOSC/32
111: φOSC/64
Rev. 4.00 Mar. 15, 2006 Page 79 of 556
REJ09B0026-0400
Section 6 Power-Down Modes
Bit
Bit Name
Initial
Value
R/W
Description
1
SA1
0
R/W
Subactive Mode Clock Select 1 and 0
0
SA0
0
R/W
These bits select the operating clock frequency in
subactive and subsleep modes. The operating clock
frequency changes to the set frequency after the SLEEP
instruction is executed.
00: φW/8
01: φW/4
1X: φW/2
[Legend]
X: Don't care.
6.1.3
Module Standby Control Register 1 (MSTCR1)
MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units.
Bit
Bit Name
Initial
Value
R/W
Description
7, 6

All 0

Reserved
5
MSTS3
0
R/W
SCI3 Module Standby
These bits are always read as 0.
The SCI3 enters standby mode when this bit is set to 1.
4
MSTAD
0
R/W
A/D Converter Module Standby
The A/D converter enters standby mode when this bit is
set to 1.
3
MSTWD
0
R/W
Watchdog Timer Module Standby
The watchdog timer enters standby mode when this bit is
set to 1. When the internal oscillator is selected for the
watchdog timer clock, the watchdog timer operates
regardless of the setting of this bit.
2

0

Reserved
This bit is always read as 0.
1
MSTTV
0
R/W
Timer V Module Standby
The timer V enters standby mode when this bit is set to 1.
0

0

Reserved
This bit is always read as 0.
Rev. 4.00 Mar. 15, 2006 Page 80 of 556
REJ09B0026-0400
Section 6 Power-Down Modes
6.1.4
Module Standby Control Register 2 (MSTCR2)
MSTCR2 allows the on-chip peripheral modules to enter a standby state in module units.
Bit
Bit Name
Initial
Value
R/W
Description
7
MSTS3_2
0
R/W
SCI3_2 Module Standby
The SCI3_2 enters standby mode when this bit is set to
1.
Note: This bit is reserved in the H8/36037 Group. This bit
is always read as 0.
6, 5

All 0

Reserved
These bits are always read as 0.
4
MSTTB1
0
R/W
Timer B1 Module Standby
The timer B1 enters standby mode when this bit is set to
1.
3, 2

All 0

Reserved
These bits are always read as 0.
1
MSTTZ
0
R/W
Timer Z Module Standby
The timer Z enters standby mode when this bit is set to 1.
0

0

Reserved
This bit is always read as 0.
Rev. 4.00 Mar. 15, 2006 Page 81 of 556
REJ09B0026-0400
Section 6 Power-Down Modes
6.2
Mode Transitions and States of LSI
Figure 6.1 shows the possible transitions among these operating modes. A transition is made from
the program execution state to the program halt state by executing a SLEEP instruction. Interrupts
allow for returning from the program halt state to the program execution state. A direct transition
between active mode and subactive mode, which are both program execution states, can be made
without halting the program. The operating frequency can also be changed in the same modes by
making a transition directly from active mode to active mode, and from subactive mode to
subactive mode. RES input enables transitions from a mode to the reset state. Table 6.2 shows the
transition conditions of each mode after the SLEEP instruction is executed and a mode to return
by an interrupt. Table 6.3 shows the internal states of the LSI in each mode.
Reset state
Program halt state
Program execution state
SLEEP
instruction
Direct transition
interrupt
SLEEP
instruction
Sleep mode
Active mode
Standby mode
Program halt state
Interrupt
Interrupt
SLEEP
instruction
Direct
transition
interrupt
Direct
transition
interrupt
Interrupt
SLEEP
instruction
SLEEP
instruction
Interrupt
SLEEP
instruction
Subactive
mode
Subsleep mode
Interrupt
Direct transition
interrupt
Notes: 1. To make a transition to another mode by an interrupt, make sure interrupt handling is after the interrupt
is accepted.
2. Details on the mode transition conditions are given in table 6.2.
Figure 6.1 Mode Transition Diagram
Rev. 4.00 Mar. 15, 2006 Page 82 of 556
REJ09B0026-0400
Section 6 Power-Down Modes
Table 6.2
Transition Mode after SLEEP Instruction Execution and Transition Mode due
to Interrupt
DTON
SSBY
SMSEL
LSON
Transition Mode after
SLEEP Instruction
Execution
0
0
0
0
Sleep mode
1
1
Active mode
Subactive mode
0
Subsleep mode
Active mode
1
1
Transition Mode due to
Interrupt
Subactive mode
1
X
X
Standby mode
Active mode
X
0*
0
Active mode (direct
transition)
—
X
X
1
Subactive mode (direct
transition)
—
[Legend]
X: Don’t care.
Note: * When a state transition is made while SMSEL is 1, the timer V, SCI3, SCI3_2 (only for
the H8/36057 Group), and A/D converter are reset, and all registers are set to their
initial values. To use these functions after entering active mode, reset the registers.
Table 6.3
Internal State in Each Operating Mode
Function
Active Mode
Sleep Mode
Subactive
Mode
Subsleep
Mode
Standby Mode
System clock oscillator
Functioning
Functioning
Halted
Halted
Halted
CPU
operations
Instructions
Functioning
Halted
Functioning
Halted
Halted
Registers
Functioning
Retained
Functioning
Retained
Retained
RAM
Functioning
Retained
Functioning
Retained
Retained
I/O ports
Functioning
Retained
Functioning
Retained
Register contents
are retained, but
output is the highimpedance state.
IRQ3 to IRQ0 Functioning
Functioning
Functioning
Functioning
Functioning
WKP5 to
WKP0
Functioning
Functioning
Functioning
Functioning
External
interrupts
Functioning
Rev. 4.00 Mar. 15, 2006 Page 83 of 556
REJ09B0026-0400
Section 6 Power-Down Modes
Active Mode
Sleep Mode
Subactive
Mode
Subsleep
Mode
Standby Mode
Timer V
Functioning
Functioning
Reset
Reset
Reset
Watchdog
timer
Functioning
Functioning
Retained (functioning if the internal oscillator are
selected as a count clock*)
SCI3, SCI3_2* Functioning
Functioning
Reset
Reset
Reset
TinyCAN
Functioning
Functioning
Retained
Retained
Retained
SSU
Functioning
Functioning
Retained
Retained
Retained
Subtimer
Functioning
Functioning
Functioning
Functioning
Retained
(functioning if
the on-chip
oscillator is
enabled)
Timer B1
Functioning
Functioning
Retained*
Retained
Retained
Timer Z
Functioning
Functioning
Retained (When internal clock φ is selected as a
count clock, the counter counts up with sub
clock*.)
A/D converter
Functioning
Functioning
Reset
Function
Peripheral
functions
2
Note:
6.2.1
*
Reset
Reset
Registers can be read from or written to in subactive mode.
Sleep Mode
In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock
frequency set by the MA2, MA1, and MA0 bits in SYSCR2. CPU register contents are retained.
When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts.
Sleep mode is not cleared if the I bit of the condition code register (CCR) is set to 1 or the
requested interrupt is disabled in the interrupt enable register. After sleep mode is cleared, a
transition is made to active mode when the LSON bit in SYSCR2 is 0, and a transition is made to
subactive mode when the bit is 1.
When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared.
6.2.2
Standby Mode
In standby mode, the clock pulse generator stops, so the CPU and on-chip peripheral modules stop
functioning. However, as long as the rated voltage is supplied, the contents of CPU registers, onchip RAM, and some on-chip peripheral module registers are retained. On-chip RAM contents
will be retained as long as the voltage set by the RAM data retention voltage is provided. The I/O
ports go to the high-impedance state.
Rev. 4.00 Mar. 15, 2006 Page 84 of 556
REJ09B0026-0400
Section 6 Power-Down Modes
Standby mode is cleared by an interrupt. When an interrupt is requested, the system clock pulse
generator starts. After the time set in bits STS2 to STS0 in SYSCR1 has elapsed, and interrupt
exception handling starts. Standby mode is not cleared if the I bit of CCR is set to 1 or the
requested interrupt is disabled in the interrupt enable register.
When the RES pin goes low, the system clock pulse generator starts. Since system clock signals
are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the
RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator
output has stabilized, the CPU starts reset exception handling if the RES pin is driven high.
6.2.3
Subsleep Mode
In subsleep mode, operation of the CPU and on-chip peripheral modules is halted. As long as a
required voltage is applied, the contents of CPU registers, the on-chip RAM, and some registers of
the on-chip peripheral modules are retained. I/O ports keep the same states as before the transition.
Subsleep mode is cleared by an interrupt. When an interrupt is requested, subsleep mode is cleared
and interrupt exception handling starts. Subsleep mode is not cleared if the I bit of CCR is set to 1
or the requested interrupt is disabled in the interrupt enable register. After subsleep mode is
cleared, a transition is made to active mode when the LSON bit in SYSCR2 is 0, and a transition is
made to subactive mode when the bit is 1. After the time set in bits STS2 to STS0 in SYSCR1 has
elapsed, a transition is made to active mode.
When the RES pin goes low, the system clock pulse generator starts. Since system clock signals
are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the
RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator
output has stabilized, the CPU starts reset exception handling if the RES pin is driven high.
6.2.4
Subactive Mode
The operating frequency of subactive mode is selected from φW/2, φW/4, and φW/8 by the SA1 and
SA0 bits in SYSCR2. After the SLEEP instruction is executed, the operating frequency changes to
the frequency which is set before the execution. When the SLEEP instruction is executed in
subactive mode, a transition to sleep mode, subsleep mode, standby mode, active mode, or
subactive mode is made, depending on the combination of SYSCR1 and SYSCR2. When the RES
pin goes low, the system clock pulse generator starts. Since system clock signals are supplied to
the entire chip as soon as the system clock pulse generator starts functioning, the RES pin must be
kept low until the pulse generator output stabilizes. After the pulse generator output has stabilized,
the CPU starts reset exception handling if the RES pin is driven high.
Rev. 4.00 Mar. 15, 2006 Page 85 of 556
REJ09B0026-0400
Section 6 Power-Down Modes
6.3
Operating Frequency in Active Mode
Operation in active mode is clocked at the frequency designated by the MA2, MA1, and MA0 bits
in SYSCR2. The operating frequency changes to the set frequency after SLEEP instruction
execution.
6.4
Direct Transition
The CPU can execute programs in two modes: active and subactive modes. A direct transition is a
transition between these two modes without stopping program execution. A direct transition can
be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1. The direct
transition also enables operating frequency modification in active or subactive mode. After the
mode transition, direct transition interrupt exception handling starts.
If the direct transition interrupt is disabled in interrupt enable register 1, a transition is made
instead to sleep or subsleep mode. Note that if a direct transition is attempted while the I bit in
CCR is set to 1, sleep or subsleep mode will be entered, and the resulting mode cannot be cleared
by means of an interrupt.
6.4.1
Direct Transition from Active Mode to Subactive Mode
The time from the start of SLEEP instruction execution to the end of interrupt exception handling
(the direct transition time) is calculated by equation (1).
Direct transition time = {(number of SLEEP instruction execution states) + (number of internal
processing states)}× (tcyc before transition) + (number of interrupt exception handling states) ×
(tsubcyc after transition) (1)
Example:
Direct transition time = (2 + 1) × tosc + 14 × 8tw = 3tosc + 112tw
(when the CPU operating clock of φosc → φw/8 is selected)
[Legend]
tosc: OSC clock cycle time
tw: Watch clock cycle time
tcyc: System clock (φ) cycle time
tsubcyc: Subclock (φSUB) cycle time
Rev. 4.00 Mar. 15, 2006 Page 86 of 556
REJ09B0026-0400
Section 6 Power-Down Modes
6.4.2
Direct Transition from Subactive Mode to Active Mode
The time from the start of SLEEP instruction execution to the end of interrupt exception handling
(the direct transition time) is calculated by equation (2).
Direct transition time = {(number of SLEEP instruction execution states) + (number of internal
processing states)} × (tsubcyc before transition) + {(waiting time set in bits STS2 to STS0) +
(number of interrupt exception handling states)} × (tcyc after transition)
(2)
Example:
Direct transition time = (2 + 1) × 8tw + (8192 + 14) × tosc = 24tw + 8206tosc
(when the CPU operating clock of φw/8 → φosc and a waiting time of 8192 states are selected)
[Legend]
tosc: OSC clock cycle time
tw: Watch clock cycle time
tcyc: System clock (φ) cycle time
tsubcyc: Subclock (φSUB) cycle time
6.5
Module Standby Function
The module-standby function can be set to any peripheral module. In module standby mode, the
clock supply to modules stops to enter the power-down mode. Module standby mode enables each
on-chip peripheral module to enter the standby state by setting a bit in TCMR, SSCRL, or
MSTCR1 that corresponds to each module to 1 and cancels the standby state by clearing the bit to
0.
Rev. 4.00 Mar. 15, 2006 Page 87 of 556
REJ09B0026-0400
Section 6 Power-Down Modes
Rev. 4.00 Mar. 15, 2006 Page 88 of 556
REJ09B0026-0400
Section 7 ROM
Section 7 ROM
The features of the 56-kbyte or 32-kbyte flash memories built into the flash memory (F-ZTAT)
version are summarized below.
• Programming/erase methods
 The flash memory is programmed 128 bytes at a time. Erase is performed in single-block
units. The flash memory is configured as follows: 1 kbyte × 4 blocks, 28 kbytes × 1 block,
16 kbytes × 1 block, and 8 kbytes × 1 block for the H8/36057F and H8/36037F and 1 kbyte
× 4 blocks and 28 kbytes × 1 block for the H8/36054F and H8/36034F. To erase the entire
flash memory, each block must be erased in turn.
• Reprogramming capability
 The flash memory can be reprogrammed up to 1,000 times.
• On-board programming
 On-board programming/erasing can be done in boot mode, in which the boot program built
into the chip is started to erase or program of the entire flash memory. In normal user
program mode, individual blocks can be erased or programmed.
• Programmer mode
 Flash memory can be programmed/erased in programmer mode using a PROM
programmer, as well as in on-board programming mode.
• Automatic bit rate adjustment
 For data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match
the transfer bit rate of the host.
• Programming/erasing protection
 Sets software protection against flash memory programming/erasing.
• Power-down mode
 Operation of the power supply circuit can be partly halted in subactive mode. As a result,
flash memory can be read with low power consumption.
7.1
Block Configuration
Figure 7.1 shows the block configuration of flash memory. The thick lines indicate erasing units,
the narrow lines indicate programming units, and the values are addresses. The 56-kbyte flash
memory is divided into 1 kbyte × 4 blocks, 28 kbytes × 1 block, 16 kbytes × 1 block, and 8 kbytes
× 1 block. The 32-kbyte flash memory is divided into 1 kbyte × 4 blocks and 28 kbytes × 1 blocks.
Erasing is performed in these units. Programming is performed in 128-byte units starting from an
address with lower eight bits H'00 or H'80.
Rev. 4.00 Mar. 15, 2006 Page 89 of 556
REJ09B0026-0400
Section 7 ROM
Erase unit
H'0000
H'0001
H'0002
H'0080
H'0081
H'0082
H'0380
H'0381
H'0382
H'0400
H'0401
H'0402
H'0480
H'0481
H'0481
H'0780
H'0781
H'0782
H'0800
H'0801
H'0802
H'0880
H'0881
H'0882
H'0B80
H'0B81
H'0B82
H'0C00
H'0C01
H'0C02
H'0C80
H'0C81
H'0C82
H'0F80
H'0F81
H'0F82
H'1000
H'1001
H'1002
H'1080
H'1081
H'1082
Programming unit: 128 bytes
H'007F
H'00FF
1 kbyte
Erase unit
H'03FF
Programming unit: 128 bytes
H'047F
H'04FF
1 kbyte
Erase unit
H'07FF
Programming unit: 128 bytes
H'087F
H'08FF
1 kbyte
Erase unit
H'0BFF
Programming unit: 128 bytes
H'0C7F
H'0CFF
1 kbyte
Erase unit
H'0FFF
Programming unit: 128 bytes
H'107F
H'10FF
28 kbytes
Erase unit
H'7F80
H'7F81
H'7F82
H'8000
H'8001
H'8002
H'8080
H'8081
H'8082
H'BF80
H'BF81
H'BF82
H'C000
H'C001
H'C002
H'C080
H'C081
H'C082
H'C0FF
HDF80
H'DF81
H'DF82
H'DFFF
H'7FFF
Programming unit: 128 bytes
H'807F
H'80FF
16 kbytes
Erase unit
H'BFFF
Programming unit: 128 bytes
H'C07F
8 kbytes
Figure 7.1 Flash Memory Block Configuration
Rev. 4.00 Mar. 15, 2006 Page 90 of 556
REJ09B0026-0400
Section 7 ROM
7.2
Register Descriptions
The flash memory has the following registers.
•
•
•
•
•
Flash memory control register 1 (FLMCR1)
Flash memory control register 2 (FLMCR2)
Erase block register 1 (EBR1)
Flash memory power control register (FLPWCR)
Flash memory enable register (FENR)
7.2.1
Flash Memory Control Register 1 (FLMCR1)
FLMCR1 is a register that makes the flash memory change to program mode, program-verify
mode, erase mode, or erase-verify mode. For details on register setting, refer to section 7.4, Flash
Memory Programming/Erasing.
Bit
Bit Name
Initial
Value
R/W
Description
7
—
0
—
Reserved
This bit is always read as 0.
6
SWE
0
R/W
Software Write Enable
When this bit is set to 1, flash memory
programming/erasing is enabled. When this bit is cleared
to 0, other FLMCR1 register bits and all EBR1 bits cannot
be set.
5
ESU
0
R/W
Erase Setup
When this bit is set to 1, the flash memory changes to the
erase setup state. When it is cleared to 0, the erase setup
state is cancelled. Set this bit to 1 before setting the E bit
to 1 in FLMCR1.
4
PSU
0
R/W
Program Setup
When this bit is set to 1, the flash memory changes to the
program setup state. When it is cleared to 0, the program
setup state is cancelled. Set this bit to 1 before setting the
P bit in FLMCR1.
3
EV
0
R/W
Erase-Verify
When this bit is set to 1, the flash memory changes to
erase-verify mode. When it is cleared to 0, erase-verify
mode is cancelled.
Rev. 4.00 Mar. 15, 2006 Page 91 of 556
REJ09B0026-0400
Section 7 ROM
Bit
Bit Name
Initial
Value
R/W
Description
2
PV
0
R/W
Program-Verify
When this bit is set to 1, the flash memory changes to
program-verify mode. When it is cleared to 0, programverify mode is cancelled.
1
E
0
R/W
Erase
When this bit is set to 1 while SWE = 1 and ESU = 1, the
flash memory changes to erase mode. When it is cleared
to 0, erase mode is cancelled.
0
P
0
R/W
Program
When this bit is set to 1 while SWE = 1 and PSU = 1, the
flash memory changes to program mode. When it is
cleared to 0, program mode is cancelled.
7.2.2
Flash Memory Control Register 2 (FLMCR2)
FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a
read-only register, and should not be written to.
Bit
Bit Name
Initial
Value
R/W
Description
7
FLER
0
R
Flash Memory Error
Indicates that an error has occurred during an operation
on flash memory (programming or erasing). When FLER
is set to 1, flash memory goes to the error-protection
state.
See section 7.5.3, Error Protection, for details.
6 to 0
—
All 0
—
Reserved
These bits are always read as 0.
Rev. 4.00 Mar. 15, 2006 Page 92 of 556
REJ09B0026-0400
Section 7 ROM
7.2.3
Erase Block Register 1 (EBR1)
EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit
in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to
be automatically cleared to 0.
Bit
Bit Name
Initial
Value
R/W
Description
7
—
0
—
Reserved
This bit is always read as 0.
6
EB6
0
R/W
When this bit is set to 1, 8 bytes of H'C000 to H'DFFF will
be erased.
5
EB5
0
R/W
When this bit is set to 1, 16 bytes of H'8000 to H'BFFF
will be erased.
4
EB4
0
R/W
When this bit is set to 1, 28 kbytes of H'1000 to H'7FFF
will be erased.
3
EB3
0
R/W
When this bit is set to 1, 1 kbyte of H'0C00 to H'0FFF will
be erased.
2
EB2
0
R/W
When this bit is set to 1, 1 kbyte of H'0800 to H'0BFF will
be erased.
1
EB1
0
R/W
When this bit is set to 1, 1 kbyte of H'0400 to H'07FF will
be erased.
0
EB0
0
R/W
When this bit is set to 1, 1 kbyte of H'0000 to H'03FF will
be erased.
Rev. 4.00 Mar. 15, 2006 Page 93 of 556
REJ09B0026-0400
Section 7 ROM
7.2.4
Flash Memory Power Control Register (FLPWCR)
FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI
switches to subactive mode. There are two modes: mode in which operation of the power supply
circuit of flash memory is partly halted in power-down mode and flash memory can be read, and
mode in which even if a transition is made to subactive mode, operation of the power supply
circuit of flash memory is retained and flash memory can be read.
Bit
Bit Name
Initial
Value
R/W
Description
7
PDWND
0
R/W
Power-Down Disable
When this bit is 0 and a transition is made to subactive
mode, the flash memory enters the power-down mode.
When this bit is 1, the flash memory remains in the
normal mode even after a transition is made to subactive
mode.
6 to 0
—
All 0
—
Reserved
These bits are always read as 0.
7.2.5
Flash Memory Enable Register (FENR)
Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers,
FLMCR1, FLMCR2, EBR1, and FLPWCR.
Bit
Bit Name
Initial
Value
R/W
Description
7
FLSHE
0
R/W
Flash Memory Control Register Enable
Flash memory control registers can be accessed when
this bit is set to 1. Flash memory control registers cannot
be accessed when this bit is set to 0.
6 to 0
—
All 0
—
Reserved
These bits are always read as 0.
Rev. 4.00 Mar. 15, 2006 Page 94 of 556
REJ09B0026-0400
Section 7 ROM
7.3
On-Board Programming Modes
There are two modes for programming/erasing of the flash memory; boot mode, which enables onboard programming/erasing, and programmer mode, in which programming/erasing is performed
with a PROM programmer. On-board programming/erasing can also be performed in user
program mode. At reset-start in reset mode, this LSI changes to a mode depending on the TEST
pin settings, NMI pin settings, and input level of each port, as shown in table 7.1. The input level
of each pin must be defined four states before the reset ends.
When changing to boot mode, the boot program built into this LSI is initiated. The boot program
transfers the programming control program from the externally-connected host to on-chip RAM
via the SCI3. After erasing the entire flash memory, the programming control program is
executed. This can be used for programming initial values in the on-board state or for a forcible
return when programming/erasing can no longer be done in user program mode. In user program
mode, individual blocks can be erased and programmed by branching to the user program/erase
control program prepared by the user.
Table 7.1
TEST
Setting Programming Modes
NMI
P85
PB0
PB1
PB2
LSI State after Reset End
0
1
X
X
X
X
User Mode
0
0
1
X
X
X
Boot Mode
1
X
X
0
0
0
Programmer Mode
[Legend]
X: Don’t care.
Rev. 4.00 Mar. 15, 2006 Page 95 of 556
REJ09B0026-0400
Section 7 ROM
7.3.1
Boot Mode
Table 7.2 shows the boot mode operations between reset end and branching to the programming
control program.
1. When boot mode is used, the flash memory programming control program must be prepared in
the host beforehand. Prepare a programming control program in accordance with the
description in section 7.4, Flash Memory Programming/Erasing.
2. SCI3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop
bit, and no parity.
3. When the boot program is initiated, the chip measures the low-level period of asynchronous
SCI communication data (H'00) transmitted continuously from the host. The chip then
calculates the bit rate of transmission from the host, and adjusts the SCI3 bit rate to match that
of the host. The reset should end with the RXD pin high. The RXD and TXD pins should be
pulled up on the board if necessary. After the reset is complete, it takes approximately 100
states before the chip is ready to measure the low-level period.
4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the
completion of bit rate adjustment. The host should confirm that this adjustment end indication
(H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could
not be performed normally, initiate boot mode again by a reset. Depending on the host's
transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between
the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit rate
and system clock frequency of this LSI within the ranges listed in table 7.3.
5. In boot mode, a part of the on-chip RAM area is used by the boot program. The area H'F780 to
H'FEEF is the area to which the programming control program is transferred from the host.
The boot program area cannot be used until the execution state in boot mode switches to the
programming control program.
6. Before branching to the programming control program, the chip terminates transfer operations
by the SCI3 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value
remains set in BRR. Therefore, the programming control program can still use it for transfer of
program data or verify data with the host. The TXD pin is high (PCR22 = 1, P22 = 1). The
contents of the CPU general registers are undefined immediately after branching to the
programming control program. These registers must be initialized at the beginning of the
programming control program, as the stack pointer (SP), in particular, is used implicitly in
subroutine calls, etc.
7. Boot mode can be cleared by a reset. End the reset after driving the reset pin low, waiting at
least 20 states, and then setting the NMI pin. Boot mode is also cleared when a WDT overflow
occurs.
8. Do not change the TEST pin and NMI pin input levels in boot mode.
Rev. 4.00 Mar. 15, 2006 Page 96 of 556
REJ09B0026-0400
Section 7 ROM
Boot Mode Operation
Host Operation
Communication Contents
Processing Contents
Transfer of number of bytes of
programming control program
Flash memory erase
Bit rate adjustment
Boot mode initiation
Item
Table 7.2
LSI Operation
Processing Contents
Branches to boot program at reset-start.
Boot program initiation
Continuously transmits data H'00
at specified bit rate.
Transmits data H'55 when data H'00
is received error-free.
H'00, H'00 . . . H'00
H'00
H'55
Boot program
erase error
H'AA reception
Transmits number of bytes (N) of
programming control program to be
transferred as 2-byte data
(low-order byte following high-order
byte)
Transmits 1-byte of programming
control program (repeated for N times)
H'AA reception
H'FF
H'AA
Upper bytes, lower bytes
Echoback
H'XX
Echoback
H'AA
• Measures low-level period of receive data
H'00.
• Calculates bit rate and sets BRR in SCI3.
• Transmits data H'00 to host as adjustment
end indication.
H'55 reception.
Checks flash memory data, erases all flash
memory blocks in case of written data
existing, and transmits data H'AA to host.
(If erase could not be done, transmits data
H'FF to host and aborts operation.)
Echobacks the 2-byte data
received to host.
Echobacks received data to host and also
transfers it to RAM.
(repeated for N times)
Transmits data H'AA to host.
Branches to programming control program
transferred to on-chip RAM and starts
execution.
Rev. 4.00 Mar. 15, 2006 Page 97 of 556
REJ09B0026-0400
Section 7 ROM
Table 7.3
System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is
Possible
Host Bit Rate
System Clock Frequency Range of LSI
19,200 bps
16 to 20 MHz
9,600 bps
8 to 16 MHz
4,800 bps
4 to 16 MHz
2,400 bps
2 to 16 MHz
7.3.2
Programming/Erasing in User Program Mode
On-board programming/erasing of an individual flash memory block can also be performed in user
program mode by branching to a user program/erase control program. The user must set branching
conditions and provide on-board means of supplying programming data. The flash memory must
contain the user program/erase control program or a program that provides the user program/erase
control program from external memory. As the flash memory itself cannot be read during
programming/erasing, transfer the user program/erase control program to on-chip RAM, as in boot
mode. Figure 7.2 shows a sample procedure for programming/erasing in user program mode.
Prepare a user program/erase control program in accordance with the description in section 7.4,
Flash Memory Programming/Erasing.
Rev. 4.00 Mar. 15, 2006 Page 98 of 556
REJ09B0026-0400
Section 7 ROM
Reset-start
No
Program/erase?
Yes
Transfer user program/erase control
program to RAM
Branch to flash memory application
program
Branch to user program/erase control
program in RAM
Execute user program/erase control
program (flash memory rewrite)
Branch to flash memory application
program
Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode
Rev. 4.00 Mar. 15, 2006 Page 99 of 556
REJ09B0026-0400
Section 7 ROM
7.4
Flash Memory Programming/Erasing
A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one
of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify
mode. The programming control program in boot mode and the user program/erase control
program in user program mode use these operating modes in combination to perform
programming/erasing. Flash memory programming and erasing should be performed in
accordance with the descriptions in section 7.4.1, Program/Program-Verify and section 7.4.2,
Erase/Erase-Verify, respectively.
7.4.1
Program/Program-Verify
When writing data or programs to the flash memory, the program/program-verify flowchart shown
in figure 7.3 should be followed. Performing programming operations according to this flowchart
will enable data or programs to be written to the flash memory without subjecting the chip to
voltage stress or sacrificing program data reliability.
1. Programming must be done to an empty address. Do not reprogram an address to which
programming has already been performed.
2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be
performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the
extra addresses.
3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128byte reprogramming data area, and a 128-byte additional-programming data area. Perform
reprogramming data computation according to table 7.4, and additional programming data
computation according to table 7.5.
4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or
additional-programming data area to the flash memory. The program address and 128-byte
data are latched in the flash memory. The lower 8 bits of the start address in the flash memory
destination area must be H'00 or H'80.
5. The time during which the P bit is set to 1 is the programming time. Table 7.6 shows the
allowable programming times.
6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
An overflow cycle of approximately 6.6 ms is allowed.
7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 2 bits
are B'00. Verify data can be read in words or in longwords from the address to which a dummy
write was performed.
Rev. 4.00 Mar. 15, 2006 Page 100 of 556
REJ09B0026-0400
Section 7 ROM
8. The maximum number of repetitions of the program/program-verify sequence of the same bit
is 1,000.
Write pulse application subroutine
START
Apply Write Pulse
Set SWE bit in FLMCR1
WDT enable
Wait 1 µs
Set PSU bit in FLMCR1
Store 128-byte program data in program
data area and reprogram data area
*
Wait 50 µs
n=1
Set P bit in FLMCR1
m=0
Wait (Wait time = programming time)
Write 128-byte data in RAM reprogram
data area consecutively to flash memory
Clear P bit in FLMCR1
Wait 5 µs
Apply Write pulse
Clear PSU bit in FLMCR1
Set PV bit in FLMCR1
Wait 4 µs
Wait 5 µs
Disable WDT
Set block start address as
verify address
End Sub
H'FF dummy write to verify address
n←n+1
Wait 2 µs
*
Read verify data
Increment address
No
Verify data =
write data?
m=1
Yes
n≤6?
No
Yes
Additional-programming data computation
Reprogram data computation
No
128-byte
data verification completed?
Yes
Clear PV bit in FLMCR1
Wait 2 µs
n ≤ 6?
No
Yes
Successively write 128-byte data from additionalprogramming data area in RAM to flash memory
Sub-Routine-Call
Apply Write Pulse
m=0?
Yes
Clear SWE bit in FLMCR1
No
n ≤ 1000 ?
Yes
No
Clear SWE bit in FLMCR1
Wait 100 µs
Wait 100 µs
End of programming
Programming failure
Note: * The RTS instruction must not be used during the following 1. and 2. periods.
1. A period between 128-byte data programming to flash memory and the P bit clearing
2. A period between dummy writing of H'FF to a verify address and verify data reading
Figure 7.3 Program/Program-Verify Flowchart
Rev. 4.00 Mar. 15, 2006 Page 101 of 556
REJ09B0026-0400
Section 7 ROM
Table 7.4
Reprogram Data Computation Table
Program Data
Verify Data
Reprogram Data
Comments
0
0
1
Programming completed
0
1
0
Reprogram bit
1
0
1
—
1
1
1
Remains in erased state
Table 7.5
Additional-Program Data Computation Table
Reprogram Data
Verify Data
Additional-Program
Data
Comments
0
0
0
Additional-program bit
0
1
1
No additional programming
1
0
1
No additional programming
1
1
1
No additional programming
Comments
Table 7.6
Programming Time
n
(Number of Writes)
Programming
Time
In Additional
Programming
1 to 6
30
10
7 to 1,000
200
—
Note: Time shown in µs.
Rev. 4.00 Mar. 15, 2006 Page 102 of 556
REJ09B0026-0400
Section 7 ROM
7.4.2
Erase/Erase-Verify
When erasing flash memory, the erase/erase-verify flowchart shown in figure 7.4 should be
followed.
1. Prewriting (setting erase block data to all 0s) is not necessary.
2. Erasing is performed in block units. Make only a single-bit specification in the erase block
register (EBR1). To erase multiple blocks, each block must be erased in turn.
3. The time during which the E bit is set to 1 is the flash memory erase time.
4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. An
overflow cycle of approximately 19.8 ms is allowed.
5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two
bits are B'00. Verify data can be read in longwords from the address to which a dummy write
was performed.
6. If the read data is not erased successfully, set erase mode again, and repeat the erase/eraseverify sequence as before. The maximum number of repetitions of the erase/erase-verify
sequence is 100.
7.4.3
Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, including the NMI interrupt, are disabled while flash memory is being programmed
or erased, or while the boot program is executing, for the following three reasons:
1. Interrupt during programming/erasing may cause a violation of the programming or erasing
algorithm, with the result that normal operation cannot be assured.
2. If interrupt exception handling starts before the vector address is written or during
programming/erasing, a correct vector cannot be fetched and the CPU malfunctions.
3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be
carried out.
Rev. 4.00 Mar. 15, 2006 Page 103 of 556
REJ09B0026-0400
Section 7 ROM
Erase start
SWE bit ← 1
Wait 1 µs
n←1
Set EBR1
Enable WDT
ESU bit ← 1
Wait 100 µs
E bit ← 1
Wait 10 ms
E bit ← 0
Wait 10 µs
ESU bit ← 0
Wait 10 µs
Disable WDT
EV bit ← 1
Wait 20 µs
Set block start address as verify address
H'FF dummy write to verify address
Wait 2 µs
*
n←n+1
Read verify data
No
Verify data + all 1s ?
Increment address
Yes
No
Last address of block ?
Yes
No
EV bit ← 0
EV bit ← 0
Wait 4 µs
Wait 4 µs
All erase block erased ?
n ≤ 100 ?
Yes
Yes
No
Yes
SWE bit ← 0
SWE bit ← 0
Wait 100 µs
Wait 100 µs
End of erasing
Erase failure
Note: * The RTS instruction must not be used during a period between dummy writing of H'FF to a verify address and verify data reading.
Figure 7.4 Erase/Erase-Verify Flowchart
Rev. 4.00 Mar. 15, 2006 Page 104 of 556
REJ09B0026-0400
Section 7 ROM
7.5
Program/Erase Protection
There are three kinds of flash memory program/erase protection; hardware protection, software
protection, and error protection.
7.5.1
Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted because of a transition to reset, subactive mode, subsleep mode, or standby
mode. Flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2),
and erase block register 1 (EBR1) are initialized. In a reset via the RES pin, the reset state is not
entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of
a reset during operation, hold the RES pin low for the RES pulse width specified in the AC
Characteristics section.
7.5.2
Software Protection
Software protection can be implemented against programming/erasing of all flash memory blocks
by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P or E bit
in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase block
register 1 (EBR1), erase protection can be set for individual blocks. When EBR1 is set to H'00,
erase protection is set for all blocks.
7.5.3
Error Protection
In error protection, an error is detected when CPU runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is forcibly aborted. Aborting the program/erase
operation prevents damage to the flash memory due to overprogramming or overerasing.
When the following errors are detected during programming/erasing of flash memory, the FLER
bit in FLMCR2 is set to 1, and the error protection state is entered.
• When the flash memory of the relevant address area is read during programming/erasing
(including vector read and instruction fetch)
• Immediately after exception handling excluding a reset during programming/erasing
• When a SLEEP instruction is executed during programming/erasing
Rev. 4.00 Mar. 15, 2006 Page 105 of 556
REJ09B0026-0400
Section 7 ROM
The FLMCR1, FLMCR2, and EBR1 settings are retained, however program mode or erase mode
is aborted at the point at which the error occurred. Program mode or erase mode cannot be reentered by re-setting the P or E bit. However, PV and EV bit settings are retained, and a transition
can be made to verify mode. Error protection can be cleared only by a power-on reset.
7.6
Programmer Mode
In programmer mode, a PROM programmer can be used to perform programming/erasing via a
socket adapter, just as a discrete flash memory. Use a PROM programmer that supports the MCU
device type with the on-chip 64-kbyte flash memory (FZTAT64V5).
7.7
Power-Down States for Flash Memory
In user mode, the flash memory will operate in either of the following states:
• Normal operating mode
The flash memory can be read and written to at high speed.
• Power-down operating mode
The power supply circuit of flash memory can be partly halted. As a result, flash memory can
be read with low power consumption.
• Standby mode
All flash memory circuits are halted.
Table 7.7 shows the correspondence between the operating modes of this LSI and the flash
memory. In subactive mode, the flash memory can be set to operate in power-down mode with the
PDWND bit in FLPWCR. When the flash memory returns to its normal operating state from
power-down mode or standby mode, a period to stabilize operation of the power supply circuits
that were stopped is needed. When the flash memory returns to its normal operating state, bits
STS2 to STS0 in SYSCR1 must be set to provide a wait time of at least 20 µs, even when the
external clock is being used.
Rev. 4.00 Mar. 15, 2006 Page 106 of 556
REJ09B0026-0400
Section 7 ROM
Table 7.7
Flash Memory Operating States
Flash Memory Operating State
LSI Operating State
PDWND = 0 (Initial Value)
PDWND = 1
Active mode
Normal operating mode
Normal operating mode
Subactive mode
Power-down mode
Normal operating mode
Sleep mode
Normal operating mode
Normal operating mode
Subsleep mode
Standby mode
Standby mode
Standby mode
Standby mode
Standby mode
Rev. 4.00 Mar. 15, 2006 Page 107 of 556
REJ09B0026-0400
Section 7 ROM
Rev. 4.00 Mar. 15, 2006 Page 108 of 556
REJ09B0026-0400
Section 8 RAM
Section 8 RAM
This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit
data bus, enabling two-state access by the CPU to both byte data and word data.
Product Classification
Flash memory version
Masked ROM version
Note:
*
RAM Size
RAM Address
H8/36057F,
H8/36037F
3 kbytes
H'EC00 to H'EFFF, H'F780 to H'FF7F*
H8/36054F,
H8/36034F
2 kbytes
H'F780 to H'FF7F*
H8/36057,
H8/36037
2 kbytes
H'EC00 to H'EFFF, H'FB80 to H'FF7F
H8/36036
2 kbytes
H'EC00 to H'EFFF, H'FB80 to H'FF7F
H8/36035
2 kbytes
H'EC00 to H'EFFF, H'FB80 to H'FF7F
H8/36054,
H8/36034
2 kbytes
H'EC00 to H'EFFF, H'FB80 to H'FF7F
H8/36033
1 kbyte
H'FB80 to H'FF7F
H8/36032
1 kbyte
H'FB80 to H'FF7F
When the E7 or E8 is used, area H'F780 to H'FB7F must not be accessed.
Rev. 4.00 Mar. 15, 2006 Page 109 of 556
REJ09B0026-0400
Section 8 RAM
Rev. 4.00 Mar. 15, 2006 Page 110 of 556
REJ09B0026-0400
Section 9 I/O Ports
Section 9 I/O Ports
This LSI has forty-five general I/O ports and eight general input-only ports. Port 6 is a large
current port, which can drive 20 mA (@VOL = 1.5 V) when a low level signal is output. Any of
these ports can become an input port immediately after a reset. They can also be used as I/O pins
of the on-chip peripheral modules or external interrupt input pins, and these functions can be
switched depending on the register settings. The registers for selecting these functions can be
divided into two types: those included in I/O ports and those included in each on-chip peripheral
module. General I/O ports are comprised of the port control register for controlling inputs/outputs
and the port data register for storing output data and can select inputs/outputs in bit units.
For functions in each port, see appendix B.1, I/O Port Block Diagrams. For the execution of bitmanipulation instructions to the port control register and port data register, see section 2.8.3, Bit
Manipulation Instruction.
9.1
Port 1
Port 1 is a general I/O port also functioning as IRQ interrupt input pins, a timer B1 input pin, and a
timer V input pin. Figure 9.1 shows its pin configuration.
P17/IRQ3/TRGV
P16/IRQ2
P15/IRQ1/TMIB1
Port 1
P14/IRQ0
P12
P11
P10
Figure 9.1 Port 1 Pin Configuration
Port 1 has the following registers.
•
•
•
•
Port mode register 1 (PMR1)
Port control register 1 (PCR1)
Port data register 1 (PDR1)
Port pull-up control register 1 (PUCR1)
Rev. 4.00 Mar. 15, 2006 Page 111 of 556
REJ09B0026-0400
Section 9 I/O Ports
9.1.1
Port Mode Register 1 (PMR1)
PMR1 switches the functions of pins in port 1 and port 2.
Bit
Bit Name
Initial
Value
R/W
Description
7
IRQ3
0
R/W
This bit selects the function of pin P17/IRQ3/TRGV.
0: General I/O port
1: IRQ3/TRGV input pin
6
IRQ2
0
R/W
This bit selects the function of pin P16/IRQ2.
0: General I/O port
1: IRQ2 input pin
5
IRQ1
0
R/W
This bit selects the function of pin P15/IRQ1/TMIB1.
0: General I/O port
1: IRQ1/TMIB1 input pin
4
IRQ0
0
R/W
This bit selects the function of pin P14/IRQ0.
0: General I/O port
1: IRQ0 input pin
3
TXD2
0
R/W
This bit selects the function of pin P72/TXD_2.
0: General I/O port
1: TXD_2 output pin
Note: This bit is reserved in the H8/36037 Group. This bit
is always read as 0.
2

0

Reserved.
This bit is always read as 0.
1
TXD
0
R/W
This bit selects the function of pin P22/TXD.
0: General I/O port
1: TXD output pin
0

0

Reserved.
This bit is always read as 0.
Rev. 4.00 Mar. 15, 2006 Page 112 of 556
REJ09B0026-0400
Section 9 I/O Ports
9.1.2
Port Control Register 1 (PCR1)
PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1.
Bit
Bit Name
Initial
Value
R/W
Description
7
PCR17
0
W
6
PCR16
0
W
5
PCR15
0
W
When the corresponding pin is designated in PMR1 as a
general I/O pin, setting a PCR1 bit to 1 makes the
corresponding pin an output port, while clearing the bit to
0 makes the pin an input port.
4
PCR14
0
W
Bit 3 is a reserved bit.
3



2
PCR12
0
W
1
PCR11
0
W
0
PCR10
0
W
9.1.3
Port Data Register 1 (PDR1)
PDR1 is a general I/O port data register of port 1.
Bit
Bit Name
Initial
Value
R/W
Description
7
P17
0
R/W
PDR1 stores output data for port 1 pins.
6
P16
0
R/W
5
P15
0
R/W
4
P14
0
R/W
If PDR1 is read while PCR1 bits are set to 1, the value
stored in PDR1 are read. If PDR1 is read while PCR1 bits
are cleared to 0, the pin states are read regardless of the
value stored in PDR1.
3

1

Bit 3 is a reserved bit. This bit is always read as 1.
2
P12
0
R/W
1
P11
0
R/W
0
P10
0
R/W
Rev. 4.00 Mar. 15, 2006 Page 113 of 556
REJ09B0026-0400
Section 9 I/O Ports
9.1.4
Port Pull-Up Control Register 1 (PUCR1)
PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports.
Bit
Bit Name
Initial
Value
R/W
Description
7
PUCR17
0
R/W
Only bits for which PCR1 is cleared are valid.
6
PUCR16
0
R/W
5
PUCR15
0
R/W
4
PUCR14
0
R/W
The pull-up MOS of the corresponding pins enters the onstate when these bits are set to 1, while they enter the
off-state when these bits are cleared to 0.
3

1

2
PUCR12
0
R/W
1
PUCR11
0
R/W
0
PUCR10
0
R/W
9.1.5
Pin Functions
Bit 3 is a reserved bit. This bit is always read as 1.
The correspondence between the register specification and the port functions is shown below.
• P17/IRQ3/TRGV pin
Register
PMR1
PCR1
Bit Name
IRQ3
PCR17
Pin Function
Setting value
0
0
P17 input pin
1
P17 output pin
X
IRQ3 input/TRGV input pin
1
[Legend]
X: Don't care.
Rev. 4.00 Mar. 15, 2006 Page 114 of 556
REJ09B0026-0400
Section 9 I/O Ports
• P16/IRQ2 pin
Register
PMR1
PCR1
Bit Name
IRQ2
PCR16
Pin Function
Setting value
0
0
P16 input pin
1
P16 output pin
X
IRQ2 input pin
1
[Legend]
X: Don't care.
• P15/IRQ1/TMIB1 pin
Register
PMR1
PCR1
Bit Name
IRQ1
PCR15
Pin Function
Setting value
0
0
P15 input pin
1
P15 output pin
X
IRQ1 input/TMIB1 input pin
1
[Legend]
X: Don't care.
• P14/IRQ0 pin
Register
PMR1
PCR1
Bit Name
IRQ0
PCR14
Pin Function
Setting value
0
0
P14 input pin
1
P14 output pin
X
IRQ0 input pin
1
[Legend]
X: Don't care.
• P12 pin
Register
PCR1
Bit Name
PCR12
Pin Function
Setting value
0
P12 input pin
1
P12 output pin
Rev. 4.00 Mar. 15, 2006 Page 115 of 556
REJ09B0026-0400
Section 9 I/O Ports
• P11 pin
Register
PCR1
Bit Name
PCR11
Pin Function
Setting value
0
P11 input pin
1
P11 output pin
• P10 pin
Register
PCR1
Bit Name
PCR10
Pin Function
Setting value
0
P10 input pin
1
P10 output pin
9.2
Port 2
Port 2 is a general I/O port also functioning as SCI3 I/O pins. Each pin of the port 2 is shown in
figure 9.2. The register settings of PMR1and SCI3 have priority for functions of the pins for both
uses.
P24
P23
Port 2
P22/TXD
P21/RXD
P20/SCK3
Figure 9.2 Port 2 Pin Configuration
Port 2 has the following registers.
• Port control register 2 (PCR2)
• Port data register 2 (PDR2)
• Port mode register 3 (PMR3)
Rev. 4.00 Mar. 15, 2006 Page 116 of 556
REJ09B0026-0400
Section 9 I/O Ports
9.2.1
Port Control Register 2 (PCR2)
PCR2 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 2.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 5



Reserved
4
PCR24
0
W
3
PCR23
0
W
2
PCR22
0
W
When each of the port 2 pins P24 to P20 functions as a
general I/O port, setting a PCR2 bit to 1 makes the
corresponding pin an output port, while clearing the bit to
0 makes the pin an input port.
1
PCR21
0
W
0
PCR20
0
W
9.2.2
Port Data Register 2 (PDR2)
PDR2 is a general I/O port data register of port 2.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 5

All 1

Reserved
These bits are always read as 1.
4
P24
0
R/W
PDR2 stores output data for port 2 pins.
3
P23
0
R/W
2
P22
0
R/W
1
P21
0
R/W
If PDR2 is read while PCR2 bits are set to 1, the value
stored in PDR2 is read. If PDR2 is read while PCR2 bits
are cleared to 0, the pin states are read regardless of the
value stored in PDR2.
0
P20
0
R/W
Rev. 4.00 Mar. 15, 2006 Page 117 of 556
REJ09B0026-0400
Section 9 I/O Ports
9.2.3
Port Mode Register 3 (PMR3)
PMR3 selects the CMOS output or NMOS open-drain output for port 2.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 5

All 0

Reserved
These bits are always read as 0.
4
POF24
0
R/W
3
POF23
0
R/W
When the bit is set to 1, the corresponding pin is cut off
by PMOS and it functions as the NMOS open-drain
output. When cleared to 0, the pin functions as the CMOS
output.
2 to 0

All 1

Reserved
These bits are always read as 1.
9.2.4
Pin Functions
The correspondence between the register specification and the port functions is shown below.
• P24 pin
Register
PCR2
Bit Name
PCR24
Pin Function
Setting Value
0
P24 input pin
1
P24 output pin
• P23 pin
Register
PCR2
Bit Name
PCR23
Pin Function
Setting Value
0
P23 input pin
1
P23 output pin
Rev. 4.00 Mar. 15, 2006 Page 118 of 556
REJ09B0026-0400
Section 9 I/O Ports
• P22/TXD pin
Register
PMR1
PCR2
Bit Name
TXD
PCR22
Pin Function
Setting Value
0
0
P22 input pin
1
P22 output pin
X
TXD output pin
1
[Legend]
X: Don't care.
• P21/RXD pin
Register
SCR3
PCR2
Bit Name
RE
PCR21
Pin Function
Setting Value
0
0
P21 input pin
1
P21 output pin
X
RXD input pin
1
[Legend]
X: Don't care.
• P20/SCK3 pin
Register
SCR3
Bit Name
CKE1
Setting Value
0
SMR
PCR2
CKE0
COM
PCR20
Pin Function
0
0
0
P20 input pin
1
P20 output pin
0
0
1
X
SCK3 output pin
0
1
X
X
SCK3 output pin
1
X
X
X
SCK3 input pin
[Legend]
X: Don't care.
Rev. 4.00 Mar. 15, 2006 Page 119 of 556
REJ09B0026-0400
Section 9 I/O Ports
9.3
Port 5
Port 5 is a general I/O port also functioning as an A/D trigger input pin and a wakeup interrupt
input pin. Each pin of the port 5 is shown in figure 9.3. The register setting of the I2C bus interface
register has priority for functions of the pins P57/SCL and P56/SDA. Since the output buffer for
pins P56 and P57 has the NMOS push-pull structure, it differs from an output buffer with the
CMOS structure in the high-level output characteristics (see section 22, Electrical Characteristics).
P57
P56
P55/WKP5/ADTRG
Port 5
P54/WKP4
P53/WKP3
P52/WKP2
P51/WKP1
P50/WKP0
Figure 9.3 Port 5 Pin Configuration
Port 5 has the following registers.
•
•
•
•
Port mode register 5 (PMR5)
Port control register 5 (PCR5)
Port data register 5 (PDR5)
Port pull-up control register 5 (PUCR5)
Rev. 4.00 Mar. 15, 2006 Page 120 of 556
REJ09B0026-0400
Section 9 I/O Ports
9.3.1
Port Mode Register 5 (PMR5)
PMR5 switches the functions of pins in port 5.
Bit
Bit Name
Initial
Value
R/W
Description
7
POF57
0
R/W
6
POF56
0
R/W
When the bit is set to 1, the corresponding pin is cut off
by PMOS and it functions as the NMOS open-drain
output. When cleared to 0, the pin functions as the CMOS
output.
5
WKP5
0
R/W
This bit selects the function of pin P55/WKP5/ADTRG.
0: General I/O port
1: WKP5/ADTRG input pin
4
WKP4
0
R/W
This bit selects the function of pin P54/WKP4.
0: General I/O port
1: WKP4 input pin
3
WKP3
0
R/W
This bit selects the function of pin P53/WKP3.
0: General I/O port
1: WKP3 input pin
2
WKP2
0
R/W
This bit selects the function of pin P52/WKP2.
0: General I/O port
1: WKP2 input pin
1
WKP1
0
R/W
This bit selects the function of pin P51/WKP1.
0: General I/O port
1: WKP1 input pin
0
WKP0
0
R/W
This bit selects the function of pin P50/WKP0.
0: General I/O port
1: WKP0 input pin
Rev. 4.00 Mar. 15, 2006 Page 121 of 556
REJ09B0026-0400
Section 9 I/O Ports
9.3.2
Port Control Register 5 (PCR5)
PCR5 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 5.
Bit
Bit Name
Initial
Value
R/W
Description
7
PCR57
0
W
6
PCR56
0
W
5
PCR55
0
W
When each of the port 5 pins P57 to P50 functions as a
general I/O port, setting a PCR5 bit to 1 makes the
corresponding pin an output port, while clearing the bit to
0 makes the pin an input port.
4
PCR54
0
W
3
PCR53
0
W
2
PCR52
0
W
1
PCR51
0
W
0
PCR50
0
W
9.3.3
Port Data Register 5 (PDR5)
PDR5 is a general I/O port data register of port 5.
Bit
Bit Name
Initial
Value
R/W
Description
7
P57
0
R/W
Stores output data for port 5 pins.
6
P56
0
R/W
5
P55
0
R/W
4
P54
0
R/W
If PDR5 is read while PCR5 bits are set to 1, the value
stored in PDR5 are read. If PDR5 is read while PCR5 bits
are cleared to 0, the pin states are read regardless of the
value stored in PDR5.
3
P53
0
R/W
2
P52
0
R/W
1
P51
0
R/W
0
P50
0
R/W
Rev. 4.00 Mar. 15, 2006 Page 122 of 556
REJ09B0026-0400
Section 9 I/O Ports
9.3.4
Port Pull-Up Control Register 5 (PUCR5)
PUCR5 controls the pull-up MOS in bit units of the pins set as the input ports.
Bit
Bit Name
Initial
Value
R/W
Description
7, 6

All 0

Reserved
These bits are always read as 0.
5
PUCR55
0
R/W
4
PUCR54
0
R/W
3
PUCR53
0
R/W
2
PUCR52
0
R/W
1
PUCR51
0
R/W
0
PUCR50
0
R/W
9.3.5
Pin Functions
Only bits for which PCR5 is cleared are valid. The pull-up
MOS of the corresponding pins enters the on-state when
these bits are set to 1, while they enter the off-state when
these bits are cleared to 0.
The correspondence between the register specification and the port functions is shown below.
• P57 pin
Register
PCR5
Bit Name
PCR57
Pin Function
Setting Value
0
P57 input pin
1
P57 output pin
• P56 pin
Register
PCR5
Bit Name
PCR56
Pin Function
Setting Value
0
P56 input pin
1
P56 output pin
Rev. 4.00 Mar. 15, 2006 Page 123 of 556
REJ09B0026-0400
Section 9 I/O Ports
• P55/WKP5/ADTRG pin
Register
PMR5
PCR5
Bit Name
WKP5
PCR55
Pin Function
Setting Value
0
0
P55 input pin
1
P55 output pin
X
WKP5/ADTRG input pin
1
[Legend]
X: Don't care.
• P54/WKP4 pin
Register
PMR5
PCR5
Bit Name
WKP4
PCR54
Pin Function
Setting Value
0
0
P54 input pin
1
P54 output pin
X
WKP4 input pin
1
[Legend]
X: Don't care.
• P53/WKP3 pin
Register
PMR5
PCR5
Bit Name
WKP3
PCR53
Pin Function
Setting Value
0
0
P53 input pin
1
P53 output pin
X
WKP3 input pin
1
[Legend]
X: Don't care.
Rev. 4.00 Mar. 15, 2006 Page 124 of 556
REJ09B0026-0400
Section 9 I/O Ports
• P52/WKP2 pin
Register
PMR5
PCR5
Bit Name
WKP2
PCR52
Pin Function
Setting Value
0
0
P52 input pin
1
P52 output pin
X
WKP2 input pin
1
[Legend]
X: Don't care.
• P51/WKP1 pin
Register
PMR5
PCR5
Bit Name
WKP1
PCR51
Pin Function
Setting Value
0
0
P51 input pin
1
P51 output pin
X
WKP1 input pin
1
[Legend]
X: Don't care.
• P50/WKP0 pin
Register
PMR5
PCR5
Bit Name
WKP0
PCR50
Pin Function
Setting Value
0
0
P50 input pin
1
P50 output pin
X
WKP0 input pin
1
[Legend]
X: Don't care.
Rev. 4.00 Mar. 15, 2006 Page 125 of 556
REJ09B0026-0400
Section 9 I/O Ports
9.4
Port 6
Port 6 is a general I/O port also functioning as a timer Z I/O pin. Each pin of the port 6 is shown in
figure 9.4. The register setting of the timer Z has priority for functions of the pins for both uses.
P67/FTIOD1
P66/FTIOC1
P65/FTIOB1
P64/FTIOA1
Port 6
P63/FTIOD0
P62/FTIOC0
P61/FTIOB0
P60/FTIOA0
Figure 9.4 Port 6 Pin Configuration
Port 6 has the following registers.
• Port control register 6 (PCR6)
• Port data register 6 (PDR6)
9.4.1
Port Control Register 6 (PCR6)
PCR6 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 6.
Bit
Bit Name
Initial
Value
R/W
Description
7
PCR67
0
W
6
PCR66
0
W
5
PCR65
0
W
When each of the port 6 pins P67 to P60 functions as a
general I/O port, setting a PCR6 bit to 1 makes the
corresponding pin an output port, while clearing the bit to
0 makes the pin an input port.
4
PCR64
0
W
3
PCR63
0
W
2
PCR62
0
W
1
PCR61
0
W
0
PCR60
0
W
Rev. 4.00 Mar. 15, 2006 Page 126 of 556
REJ09B0026-0400
Section 9 I/O Ports
9.4.2
Port Data Register 6 (PDR6)
PDR6 is a general I/O port data register of port 6.
Bit
Bit Name
Initial
Value
R/W
Description
7
P67
0
R/W
Stores output data for port 6 pins.
6
P66
0
R/W
5
P65
0
R/W
4
P64
0
R/W
If PDR6 is read while PCR6 bits are set to 1, the value
stored in PDR6 are read. If PDR6 is read while PCR6 bits
are cleared to 0, the pin states are read regardless of the
value stored in PDR6.
3
P63
0
R/W
2
P62
0
R/W
1
P61
0
R/W
0
P60
0
R/W
9.4.3
Pin Functions
The correspondence between the register specification and the port functions is shown below.
• P67/FTIOD1 pin
Register
TOER
TFCR
TPMR
Bit Name
ED1
CMD1,
CMD0
IOD2 to
PWMD1 IOD0
PCR67
Pin Function
00
0
0
P67 input/FTIOD1 input pin
1
P67 output pin
X
FTIOD1 output pin
Setting Value 1
0
00
TIORC1
000 or
1XX
0
001 or
01X
1
XXX
Other than X
00
XXX
PCR6
[Legend]
X: Don't care.
Rev. 4.00 Mar. 15, 2006 Page 127 of 556
REJ09B0026-0400
Section 9 I/O Ports
• P66/FTIOC1 pin
Register
TOER
TFCR
TPMR
Bit Name
EC1
CMD1,
CMD0
IOC2 to
PWMC1 IOC0
PCR66
Pin Function
00
0
0
P66 input/FTIOC1 input pin
1
P66 output pin
X
FTIOC1 output pin
Setting Value 1
0
00
TIORC1
000 or
1XX
0
001 or
01X
1
XXX
Other than X
00
XXX
TIORA1
PCR6
[Legend]
X: Don't care.
• P65/FTIOB1 pin
Register
TOER
TFCR
TPMR
Bit Name
EB1
CMD1,
CMD0
IOB2 to
PWMB1 IOB0
00
0
Setting Value 1
0
00
0
001 or
01X
1
XXX
Other than X
00
XXX
[Legend]
X: Don't care.
Rev. 4.00 Mar. 15, 2006 Page 128 of 556
REJ09B0026-0400
000 or
1XX
PCR6
PCR65
Pin Function
0
P65 input/FTIOB1 input pin
1
P65 output pin
X
FTIOB1 output pin
Section 9 I/O Ports
• P64/FTIOA1 pin
Register
TOER
TFCR
TIORA1 PCR6
Bit Name
EB1
CMD1,
CMD0
IOA2 to
IOA0
PCR64
Pin Function
XX
000 or
0
P64 input/FTIOA1 input pin
1XX
1
P64 output pin
00
001 or
01X
X
FTIOA1 output pin
TIORC0
PCR6
Setting Value 1
0
[Legend]
X: Don't care.
• P63/FTIOD0 pin
Register
TOER
TFCR
TPMR
Bit Name
ED0
CMD1,
CMD0
IOD2 to
PWMD0 IOD0
PCR63
Pin Function
00
0
0
P63 input/FTIOD0 input pin
1
P63 output pin
X
FTIOD0 output pin
Setting Value 1
0
00
000 or
1XX
0
001 or
01X
1
XXX
Other than X
00
XXX
[Legend]
X: Don't care.
Rev. 4.00 Mar. 15, 2006 Page 129 of 556
REJ09B0026-0400
Section 9 I/O Ports
• P62/FTIOC0 pin
Register
TOER
TFCR
TPMR
Bit Name
EC0
CMD1,
CMD0
IOC2 to
PWMC0 IOC0
PCR62
Pin Function
00
0
0
P62 input/FTIOC0 input pin
1
P62 output pin
X
FTIOC0 output pin
Setting Value 1
0
00
TIORC0
000 or
1XX
0
001 or
01X
1
XXX
Other than X
00
XXX
TIORA0
PCR6
[Legend]
X: Don't care.
• P61/FTIOB0 pin
Register
TOER
TFCR
TPMR
Bit Name
EB0
CMD1,
CMD0
IOB2 to
PWMB0 IOB0
PCR61
Pin Function
00
0
0
P61 input/FTIOB0 input pin
1
P61 output pin
X
FTIOB0 output pin
Setting Value 1
0
00
0
001 or
01X
1
XXX
Other than X
00
XXX
[Legend]
X: Don't care.
Rev. 4.00 Mar. 15, 2006 Page 130 of 556
REJ09B0026-0400
000 or
1XX
PCR6
Section 9 I/O Ports
• P60/FTIOA0 pin
Register
TOER
TFCR
TFCR
TIORA0
PCR6
Bit Name
EA0
CMD1,
CMD0
STCLK
IOA2 to
IOA0
PCR60
Pin Function
XX
X
000 or
1XX
0
P60 input/FTIOA0 input pin
1
P60 output pin
001 or
01X
X
FTIOA0 output pin
Setting Value 1
0
00
0
[Legend]
X: Don't care.
9.5
Port 7
Port 7 is a general I/O port also functioning as a timer V I/O pin and SCI3_2 I/O pin. Each pin of
the port 7 is shown in figure 9.5. The register settings of the timer V and SCI3_2* have priority for
functions of the pins for both uses.
Note: * The H8/36037 Group does not have the SCI3_2.
P76/TMOV
P75/TMCIV
Port 7
P74/TMRIV
P72/TXD_2*
P71/RXD_2*
P70/SCK3_2*
Note: * The H8/36037 Group does not have these pins.
Figure 9.5 Port 7 Pin Configuration
Port 7 has the following registers.
• Port control register 7 (PCR7)
• Port data register 7 (PDR7)
Rev. 4.00 Mar. 15, 2006 Page 131 of 556
REJ09B0026-0400
Section 9 I/O Ports
9.5.1
Port Control Register 7 (PCR7)
PCR7 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 7.
Bit
Bit Name
Initial
Value
R/W
Description
7



6
PCR76
0
W
5
PCR75
0
W
When each of the port 7 pins P76 to P74 and P72 to P70
functions as a general I/O port, setting a PCR7 bit to 1
makes the corresponding pin an output port, while
clearing the bit to 0 makes the pin an input port.
4
PCR74
0
W
Bits 7 and 3 are reserved bits.
3



2
PCR72
0
W
1
PCR71
0
W
0
PCR70
0
W
9.5.2
Port Data Register 7 (PDR7)
PDR7 is a general I/O port data register of port 7.
Bit
Bit Name
Initial
Value
R/W
Description
7

1

Stores output data for port 7 pins.
6
P76
0
R/W
5
P75
0
R/W
4
P74
0
R/W
If PDR7 is read while PCR7 bits are set to 1, the value
stored in PDR7 are read. If PDR7 is read while PCR7 bits
are cleared to 0, the pin states are read regardless of the
value stored in PDR7.
3

1

2
P72
0
R/W
1
P71
0
R/W
0
P70
0
R/W
Rev. 4.00 Mar. 15, 2006 Page 132 of 556
REJ09B0026-0400
Bits 7 and 3 are reserved bits. These bits are always read
as 1.
Section 9 I/O Ports
9.5.3
Pin Functions
The correspondence between the register specification and the port functions is shown below.
• P76/TMOV pin
Register
TCSRV
Bit Name
OS3 to OS0 PCR76
Pin Function
Setting Value
0000
0
P76 input pin
1
P76 output pin
X
TMOV output pin
Other than
the above
values
PCR7
[Legend]
X: Don't care.
• P75/TMCIV pin
Register
PCR7
Bit Name
PCR75
Pin Function
Setting Value
0
P75 input/TMCIV input pin
1
P75 output/TMCIV input pin
• P74/TMRIV pin
Register
PCR7
Bit Name
PCR74
Pin Function
Setting Value
0
P74 input/TMRIV input pin
1
P74 output/TMRIV input pin
Rev. 4.00 Mar. 15, 2006 Page 133 of 556
REJ09B0026-0400
Section 9 I/O Ports
• P72/TXD_2* pin
Register
PMR1*
PCR7
Bit Name
TXD2*
PCR72
Pin Function
Setting Value
0
0
P72 input pin
1
P72 output pin
X
TXD_2 output pin*
1
[Legend]
X: Don't care.
Note: * The H8/36037 Group does not have this pin.
• P71/RXD_2* pin
Register
SCR3_2*
PCR7
Bit Name
RE*
PCR71
Pin Function
Setting Value
0
0
P71 input pin
1
P71 output pin
X
RXD_2 input pin*
1
[Legend]
X: Don't care.
Note: * The H8/36037 Group does not have this pin.
• P70/SCK3_2* pin
Register
SCR3_2*
Bit Name
CKE1* CKE0* COM*
PCR70 Pin Function
Setting Value
0
0
P70 input pin
1
P70 output pin
0
SMR2* PCR7
0
0
0
1
X
SCK3_2 output pin*
0
1
X
X
SCK3_2 output pin*
1
X
X
X
SCK3_2 input pin*
[Legend]
X: Don't care.
Note: * The H8/36037 Group does not have these pins.
Rev. 4.00 Mar. 15, 2006 Page 134 of 556
REJ09B0026-0400
Section 9 I/O Ports
9.6
Port 8
Port 8 is a general I/O port. Each pin of the port 8 is shown in figure 9.6.
P87
Port 8
P86
P85
Figure 9.6 Port 8 Pin Configuration
Port 8 has the following registers.
• Port control register 8 (PCR8)
• Port data register 8 (PDR8)
9.6.1
Port Control Register 8 (PCR8)
PCR8 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 8.
Bit
Bit Name
Initial
Value
R/W
Description
7
PCR87
0
W
6
PCR86
0
W
5
PCR85
0
W
When each of the port 8 pins P87 to P85 functions as a
general I/O port, setting a PCR8 bit to 1 makes the
corresponding pin an output port, while clearing the bit to
0 makes the pin an input port.
4 to 0



Reserved
Rev. 4.00 Mar. 15, 2006 Page 135 of 556
REJ09B0026-0400
Section 9 I/O Ports
9.6.2
Port Data Register 8 (PDR8)
PDR8 is a general I/O port data register of port 8.
Bit
Bit Name
Initial
Value
R/W
Description
7
P87
0
R/W
PDR8 stores output data for port 8 pins.
6
P86
0
R/W
5
P85
0
R/W
If PDR8 is read while PCR8 bits are set to 1, the value
stored in PDR8 is read. If PDR8 is read while PCR8 bits
are cleared to 0, the pin states are read regardless of the
value stored in PDR8.
4 to 0

All 1

Reserved
These bits are always read as 1.
9.6.3
Pin Functions
The correspondence between the register specification and the port functions is shown below.
• P87 pin
Register
PCR8
Bit Name
PCR87
Pin Function
Setting Value
0
P87 input pin
1
P87 output pin
• P86 pin
Register
PCR8
Bit Name
PCR86
Pin Function
Setting Value
0
P86 input pin
1
P86 output pin
• P85 pin
Register
PCR8
Bit Name
PCR85
Pin Function
Setting Value
0
P85 input pin
1
P85 output pin
Rev. 4.00 Mar. 15, 2006 Page 136 of 556
REJ09B0026-0400
Section 9 I/O Ports
9.7
Port 9
Port 9 is a general I/O port also functioning as a TinyCAN I/O pin and an SSU I/O pin. Each pin
of the port 9 is shown in figure 9.7.
P97/SSO
P96/SSI
P95/SSCK
P94/SCS
Port 9
P93
P92/HTXD
P91/HRXD
P90
Figure 9.7 Port 9 Pin Configuration
Port 9 has the following registers.
• Port control register 9 (PCR9)
• Port data register 9 (PDR9)
9.7.1
Port Control Register 9 (PCR9)
PCR9 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 9.
Bit
Bit Name
Initial
Value
R/W
Description
7
PCR97
0
W
6
PCR96
0
W
5
PCR95
0
W
When each of the port 9 pins P97 to P90 functions as a
general I/O port, setting a PCR9 bit to 1 makes the
corresponding pin an output port, while clearing the bit to
0 makes the pin an input port.
4
PCR94
0
W
3
PCR93
0
W
2
PCR92
0
W
1
PCR91
0
W
0
PCR90
0
W
Rev. 4.00 Mar. 15, 2006 Page 137 of 556
REJ09B0026-0400
Section 9 I/O Ports
9.7.2
Port Data Register 9 (PDR9)
PDR9 is a general I/O port data register of port 9.
Bit
Bit Name
Initial
Value
R/W
Description
7
P97
0
R/W
Stores output data for port 9 pins.
6
P96
0
R/W
5
P95
0
R/W
4
P94
0
R/W
If PDR9 is read while PCR9 bits are set to 1, the value
stored in PDR9 are read. If PDR9 is read while PCR9 bits
are cleared to 0, the pin states are read regardless of the
value stored in PDR9.
3
P93
0
R/W
2
P92
0
R/W
1
P91
0
R/W
0
P90
0
R/W
9.7.3
Pin Functions
The correspondence between the register specification and the port functions is shown below.
• P97/HTXD pin
Register
TCMR
PCR9
Bit Name
PMR97
PCR97
Pin Function
Setting Value
0
0
P97 input pin
1
P97 output pin
X
HTXD output pin
1
[Legend]
X: Don't care.
Rev. 4.00 Mar. 15, 2006 Page 138 of 556
REJ09B0026-0400
Section 9 I/O Ports
• P96/HRXD pin
Register
TCMR
PCR9
Bit Name
PMR96
PCR96
Pin Function
Setting Value
0
0
P96 input pin
1
P96 output pin
X
HRXD output pin
1
[Legend]
X: Don't care.
• P95 pin
Register
PCR9
Bit Name
PCR95
Pin Function
Setting Value
0
P95 input pin
1
P95 output pin
• P94 pin
Register
PCR9
Bit Name
PCR94
Pin Function
Setting Value
0
P94 input pin
1
P94 output pin
• P93/SSI pin
Register
PCR9
Bit Name
PCR93
Setting Value 0
Pin Function
P93 input pin
1
P93 output pin
X
SSI input/SSI output pin
[Legend]
X: Don't care.
Note: When this pin is used as the SSI pin, register settings of the SSU are required. For details,
see section 16.4.4, Communication Modes and Pin Functions.
Rev. 4.00 Mar. 15, 2006 Page 139 of 556
REJ09B0026-0400
Section 9 I/O Ports
• P92/SSO pin
Register
PCR9
Bit Name
PCR92
Setting Value 0
Pin Function
P92 input pin
1
P92 output pin
X
SSO input/SSO output pin
[Legend]
X: Don't care.
Note: When this pin is used as the SSO pin, register settings of the SSU are required. For details,
see section 16.4.4, Communication Modes and Pin Functions.
• P91/SSCK pin
Register
SSCRH
PCR9
Bit Name
SCKS
PCR91
Pin Function
Setting Value
0
0
P91 input pin
1
P91 output pin
X
SSCK input/SSCK output pin
1
[Legend]
X: Don't care.
Note: When this pin is used as the SSCK pin, register settings of the SSU are required. For
details, see section 16.4.4, Communication Modes and Pin Functions.
• P90/SCS pin
Register
SSCRL
Bit Name
SSUMS
CSS1
CSS0
PCR90
Pin Function
Setting Value
0
X
X
0
P90 input pin
X
X
1
P90 output pin
0
0
0
P90 input pin
1
P90 output pin
X
SCS input pin
1
SSCRH
0
1
1
X
[Legend]
X: Don't care.
Rev. 4.00 Mar. 15, 2006 Page 140 of 556
REJ09B0026-0400
PCR9
SCS output pin
Section 9 I/O Ports
9.8
Port B
Port B is an input port also functioning as an A/D converter analog input pin. Each pin of the port
B is shown in figure 9.8.
PB7/AN7
PB6/AN6
PB5/AN5
Port B
PB4/AN4
PB3/AN3
PB2/AN2
PB1/AN1
PB0/AN0
Figure 9.8 Port B Pin Configuration
Port B has the following register.
• Port data register B (PDRB)
9.8.1
Port Data Register B (PDRB)
PDRB is a general input-only port data register of port B.
Bit
Bit Name
Initial
Value
R/W
Description
7
PB7

R
6
PB6

R
The input value of each pin is read by reading this
register.
5
PB5

R
4
PB4

R
3
PB3

R
2
PB2

R
1
PB1

R
0
PB0

R
However, if a port B pin is designated as an analog input
channel by ADCSR in A/D converter, 0 is read.
Rev. 4.00 Mar. 15, 2006 Page 141 of 556
REJ09B0026-0400
Section 9 I/O Ports
Rev. 4.00 Mar. 15, 2006 Page 142 of 556
REJ09B0026-0400
Section 10 Timer B1
Section 10 Timer B1
The timer B1 is an 8-bit timer that increments each time a clock pulse is input. This timer has two
operating modes, interval and auto reload. Figure 10.1 shows a block diagram of the timer B1.
10.1
Features
• Selection of seven internal clock sources (φ/8192, φ/2048, φ/512, φ/256, φ/64, φ/16, and φ/4) or
an external clock (can be used to count external events).
• An interrupt is generated when the counter overflows.
φ
PSS
TCB1
TMIB1
Internal data bus
TMB1
TLB1
[Legend]
TMB1 :
TCB1 :
TLB1 :
IRRTB1 :
PSS :
TMIB1 :
Timer mode register B1
Timer counter B1
Timer load register B1
Timer B1 interrupt request flag
Prescaler S
Timer B1 event input
IRRTB1
Figure 10.1 Block Diagram of Timer B1
Rev. 4.00 Mar. 15, 2006 Page 143 of 556
REJ09B0026-0400
Section 10 Timer B1
10.2
Input/Output Pin
Table 10.1 shows the timer B1 pin configuration.
Table 10.1 Pin Configuration
Name
Abbreviation
I/O
Function
Timer B1 event input
TMIB1
Input
Event input to TCB1
Rev. 4.00 Mar. 15, 2006 Page 144 of 556
REJ09B0026-0400
Section 10 Timer B1
10.3
Register Descriptions
The timer B1 has the following registers.
• Timer mode register B1 (TMB1)
• Timer counter B1 (TCB1)
• Timer load register B1 (TLB1)
10.3.1
Timer Mode Register B1 (TMB1)
TMB1 selects the auto-reload function and input clock.
Bit
Bit Name
Initial
Value
R/W
Description
7
TMB17
0
R/W
Auto-reload function select
0: Interval timer function selected
1: Auto-reload function selected
6 to 3

All 1

Reserved
These bits are always read as 1.
2
TMB12
0
R/W
Clock select
1
TMB11
0
R/W
000: Internal clock: φ/8192
0
TMB10
0
R/W
001: Internal clock: φ/2048
010: Internal clock: φ/512
011: Internal clock: φ/256
100: Internal clock: φ/64
101: Internal clock: φ/16
110: Internal clock: φ/4
111: External event (TMIB1): rising or falling edge*
Note: * The edge of the external event signal is selected
by bit IEG1 in the interrupt edge select register 1
(IEGR1). See section 3.2.1, Interrupt Edge
Select Register 1 (IEGR1), for details. Before
setting TMB12 to TMB10 to 1, IRQ1 in the port
mode register 1 (PMR1) should be set to 1.
Rev. 4.00 Mar. 15, 2006 Page 145 of 556
REJ09B0026-0400
Section 10 Timer B1
10.3.2
Timer Counter B1 (TCB1)
TCB1 is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock
source for input to this counter is selected by bits TMB12 to TMB10 in TMB1. TCB1 values can
be read by the CPU at any time. When TCB1 overflows from H'FF to H'00 or to the value set in
TLB1, the IRRTB1 flag in IRR2 is set to 1. TCB1 is allocated to the same address as TLB1. TCB1
is initialized to H'00.
10.3.3
Timer Load Register B1 (TLB1)
TLB1 is an 8-bit write-only register for setting the reload value of TCB1. When a reload value is
set in TLB1, the same value is loaded into TCB1 as well, and TCB1 starts counting up from that
value. When TCB1 overflows during operation in auto-reload mode, the TLB1 value is loaded
into TCB1. Accordingly, overflow periods can be set within the range of 1 to 256 input clocks.
TLB1 is allocated to the same address as TCB1. TLB1 is initialized to H'00.
Rev. 4.00 Mar. 15, 2006 Page 146 of 556
REJ09B0026-0400
Section 10 Timer B1
10.4
Operation
10.4.1
Interval Timer Operation
When bit TMB17 in TMB1 is cleared to 0, timer B1 functions as an 8-bit interval timer. Upon
reset, TCB1 is cleared to H'00 and bit TMB17 is cleared to 0, so up-counting and interval timing
resume immediately. The operating clock of the timer B1 is selected from seven internal clock
signals output by prescaler S, or an external clock input at pin TMB1. The selection is made by
bits TMB12 to TMB10 in TMB1.
After the count value in TMB1 reaches H'FF, the next clock signal input causes timer B1 to
overflow, setting flag IRRTB1 in IRR2 to 1. If IENTB1 in IENR2 is 1, an interrupt is requested to
the CPU.
At overflow, TCB1 returns to H'00 and starts counting up again. During interval timer operation
(TMB17 = 0), when a value is set in TLB1, the same value is set in TCB1.
10.4.2
Auto-Reload Timer Operation
Setting bit TMB17 in TMB1 to 1 causes timer B1 to function as an 8-bit auto-reload timer. When
a reload value is set in TLB1, the same value is loaded into TCB1, becoming the value from which
TCB1 starts its count. After the count value in TCB1 reaches H'FF, the next clock signal input
causes timer B1 to overflow. The TLB1 value is then loaded into TCB1, and the count continues
from that value. The overflow period can be set within a range from 1 to 256 input clocks,
depending on the TLB1 value.
The clock sources and interrupts in auto-reload mode are the same as in interval mode. In autoreload mode (TMB17 = 1), when a new value is set in TLB1, the TLB1 value is also loaded into
TCB1.
10.4.3
Event Counter Operation
Timer B1 can operate as an event counter in which TMIB1 is set to an event input pin. External
event counting is selected by setting bits TMB12 to TMB10 in TMB1 to 1. TCB1 counts up at
rising or falling edge of an external event signal input at pin TMB1.
When timer B1 is used to count external event input, bit IRQ1 in PMR1 should be set to 1 and
IEN1 in IENR1 should be cleared to 0 to disable IRQ1 interrupt requests.
Rev. 4.00 Mar. 15, 2006 Page 147 of 556
REJ09B0026-0400
Section 10 Timer B1
10.5
Timer B1 Operating Modes
Table 10.2 shows the timer B1 operating modes.
Table 10.2 Timer B1 Operating Modes
Operating Mode
Reset
Active
Sleep
Subactive
Subsleep
Standby
TCB1 Interval
Reset
Functions
Functions
Halted
Halted
Halted
Reset
Functions
Functions
Halted
Halted
Halted
Reset
Functions
Retained
Retained
Retained
Retained
Autoreload
TMB1
Rev. 4.00 Mar. 15, 2006 Page 148 of 556
REJ09B0026-0400
Section 11 Timer V
Section 11 Timer V
The timer V is an 8-bit timer based on an 8-bit counter. The timer V counts external events.
Compare-match signals with two registers can also be used to reset the counter, request an
interrupt, or output a pulse signal with an arbitrary duty cycle. Counting can be initiated by a
trigger input at the TRGV pin, enabling pulse output control to be synchronized to the trigger,
with an arbitrary delay from the trigger input. Figure 11.1 shows a block diagram of the timer V.
11.1
Features
• Choice of seven clock signals is available.
Choice of six internal clock sources (φ/128, φ/64, φ/32, φ/16, φ/8, φ/4) or an external clock.
• Counter can be cleared by compare match A or B, or by an external reset signal. If the count
stop function is selected, the counter can be halted when cleared.
• Timer output is controlled by two independent compare match signals, enabling pulse output
with an arbitrary duty cycle, PWM output, and other applications.
• Three interrupt sources: compare match A, compare match B, timer overflow
• Counting can be initiated by trigger input at the TRGV pin. The rising edge, falling edge, or
both edges of the TRGV input can be selected.
Rev. 4.00 Mar. 15, 2006 Page 149 of 556
REJ09B0026-0400
Section 11 Timer V
TCRV1
TCORB
Trigger
control
TRGV
Comparator
TCNTV
Internal data bus
Clock select
TMCIV
Comparator
φ
PSS
TCORA
TMRIV
Clear
control
TCRV0
Interrupt
request
control
TMOV
Output
control
TCSRV
[Legend]
TCORA: Time constant register A
TCORB: Time constant register B
TCNTV: Timer counter V
TCSRV: Timer control/status register V
TCRV0: Timer control register V0
TCRV1: Timer control register V1
PSS: Prescaler S
CMIA: Compare-match interrupt A
CMIB: Compare-match interrupt B
OVI:
Overflow interupt
Figure 11.1 Block Diagram of Timer V
Rev. 4.00 Mar. 15, 2006 Page 150 of 556
REJ09B0026-0400
CMIA
CMIB
OVI
Section 11 Timer V
11.2
Input/Output Pins
Table 11.1 shows the timer V pin configuration.
Table 11.1 Pin Configuration
Name
Abbreviation I/O
Function
Timer V output
TMOV
Output
Timer V waveform output
Timer V clock input
TMCIV
Input
Clock input to TCNTV
Timer V reset input
TMRIV
Input
External input to reset TCNTV
Trigger input
TRGV
Input
Trigger input to initiate counting
11.3
Register Descriptions
The time V has the following registers.
•
•
•
•
•
•
Timer counter V (TCNTV)
Timer constant register A (TCORA)
Timer constant register B (TCORB)
Timer control register V0 (TCRV0)
Timer control/status register V (TCSRV)
Timer control register V1 (TCRV1)
11.3.1
Timer Counter V (TCNTV)
TCNTV is an 8-bit up-counter. The clock source is selected by bits CKS2 to CKS0 in timer
control register V0 (TCRV0). The TCNTV value can be read and written by the CPU at any time.
TCNTV can be cleared by an external reset input signal, or by compare match A or B. The
clearing signal is selected by bits CCLR1 and CCLR0 in TCRV0.
When TCNTV overflows, OVF is set to 1 in timer control/status register V (TCSRV).
TCNTV is initialized to H'00.
Rev. 4.00 Mar. 15, 2006 Page 151 of 556
REJ09B0026-0400
Section 11 Timer V
11.3.2
Time Constant Registers A and B (TCORA, TCORB)
TCORA and TCORB have the same function.
TCORA and TCORB are 8-bit read/write registers.
TCORA and TCNTV are compared at all times. When the TCORA and TCNTV contents match,
CMFA is set to 1 in TCSRV. If CMIEA is also set to 1 in TCRV0, a CPU interrupt is requested.
Note that they must not be compared during the T3 state of a TCORA write cycle.
Timer output from the TMOV pin can be controlled by the identifying signal (compare match A)
and the settings of bits OS3 to OS0 in TCSRV.
TCORA and TCORB are initialized to H'FF.
11.3.3
Timer Control Register V0 (TCRV0)
TCRV0 selects the input clock signals of TCNTV, specifies the clearing conditions of TCNTV,
and controls each interrupt request.
Bit
Bit Name
Initial
Value
R/W
Description
7
CMIEB
0
R/W
Compare Match Interrupt Enable B
When this bit is set to 1, interrupt request from the CMFB
bit in TCSRV is enabled.
6
CMIEA
0
R/W
Compare Match Interrupt Enable A
When this bit is set to 1, interrupt request from the CMFA
bit in TCSRV is enabled.
5
OVIE
0
R/W
Timer Overflow Interrupt Enable
When this bit is set to 1, interrupt request from the OVF
bit in TCSRV is enabled.
4
CCLR1
0
R/W
Counter Clear 1 and 0
3
CCLR0
0
R/W
These bits specify the clearing conditions of TCNTV.
00: Clearing is disabled
01: Cleared by compare match A
10: Cleared by compare match B
11: Cleared on the rising edge of the TMRIV pin. The
operation of TCNTV after clearing depends on TRGE
in TCRV1.
Rev. 4.00 Mar. 15, 2006 Page 152 of 556
REJ09B0026-0400
Section 11 Timer V
Bit
Bit Name
Initial
Value
R/W
Description
2
CKS2
0
R/W
Clock Select 2 to 0
1
CKS1
0
R/W
0
CKS0
0
R/W
These bits select clock signals to input to TCNTV and the
counting condition in combination with ICKS0 in TCRV1.
Refer to table 11.2.
Table 11.2 Clock Signals to Input to TCNTV and Counting Conditions
TCRV0
TCRV1
Bit 2
Bit 1
Bit 0
Bit 0
CKS2
CKS1
CKS0
ICKS0
Description
0
0
0

Clock input prohibited
1
0
Internal clock: counts on φ/4, falling edge
1
Internal clock: counts on φ/8, falling edge
0
Internal clock: counts on φ/16, falling edge
1
Internal clock: counts on φ/32, falling edge
1
0
Internal clock: counts on φ/64, falling edge
1
Internal clock: counts on φ/128, falling edge
0

Clock input prohibited
1

External clock: counts on rising edge
0

External clock: counts on falling edge
1

External clock: counts on rising and falling
edge
1
1
0
1
0
Rev. 4.00 Mar. 15, 2006 Page 153 of 556
REJ09B0026-0400
Section 11 Timer V
11.3.4
Timer Control/Status Register V (TCSRV)
TCSRV indicates the status flag and controls outputs by using a compare match.
Bit
Bit Name
Initial
Value
R/W
Description
7
CMFB
0
R/W
Compare Match Flag B
[Setting condition]
When the TCNTV value matches the TCORB value
[Clearing condition]
After reading CMFB = 1, cleared by writing 0 to CMFB
6
CMFA
0
R/W
Compare Match Flag A
[Setting condition]
When the TCNTV value matches the TCORA value
[Clearing condition]
After reading CMFA = 1, cleared by writing 0 to CMFA
5
OVF
0
R/W
Timer Overflow Flag
[Setting condition]
When TCNTV overflows from H'FF to H'00
[Clearing condition]
After reading OVF = 1, cleared by writing 0 to OVF
4

1

Reserved
This bit is always read as 1.
3
OS3
0
R/W
Output Select 3 and 2
2
OS2
0
R/W
These bits select an output method for the TMOV pin by
the compare match of TCORB and TCNTV.
00: No change
01: 0 output
10: 1 output
11: Output toggles
Rev. 4.00 Mar. 15, 2006 Page 154 of 556
REJ09B0026-0400
Section 11 Timer V
Bit
Bit Name
Initial
Value
R/W
Description
1
OS1
0
R/W
Output Select 1 and 0
0
OS0
0
R/W
These bits select an output method for the TMOV pin by
the compare match of TCORA and TCNTV.
00: No change
01: 0 output
10: 1 output
11: Output toggles
OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level
for compare match A. The two output levels can be controlled independently. After a reset, the
timer output is 0 until the first compare match.
11.3.5
Timer Control Register V1 (TCRV1)
TCRV1 selects the edge at the TRGV pin, enables TRGV input, and selects the clock input to
TCNTV.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 5

All 1

Reserved
These bits are always read as 1.
4
TVEG1
0
R/W
TRGV Input Edge Select
3
TVEG0
0
R/W
These bits select the TRGV input edge.
00: TRGV trigger input is prohibited
01: Rising edge is selected
10: Falling edge is selected
11: Rising and falling edges are both selected
2
TRGE
0
R/W
TCNT starts counting up by the input of the edge which is
selected by TVEG1 and TVEG0.
0: Disables starting counting-up TCNTV by the input of
the TRGV pin and halting counting-up TCNTV when
TCNTV is cleared by a compare match.
1: Enables starting counting-up TCNTV by the input of
the TRGV pin and halting counting-up TCNTV when
TCNTV is cleared by a compare match.
Rev. 4.00 Mar. 15, 2006 Page 155 of 556
REJ09B0026-0400
Section 11 Timer V
Bit
Bit Name
Initial
Value
R/W
Description
1

1

Reserved
This bit is always read as 1.
0
ICKS0
0
R/W
Internal Clock Select 0
This bit selects clock signals to input to TCNTV in
combination with CKS2 to CKS0 in TCRV0.
Refer to table 11.2.
11.4
Operation
11.4.1
Timer V Operation
1. According to table 11.2, six internal/external clock signals output by prescaler S can be
selected as the timer V operating clock signals. When the operating clock signal is selected,
TCNTV starts counting-up. Figure 11.2 shows the count timing with an internal clock signal
selected, and figure 11.3 shows the count timing with both edges of an external clock signal
selected.
2. When TCNTV overflows (changes from H'FF to H'00), the overflow flag (OVF) in TCRV0
will be set. The timing at this time is shown in figure 11.4. An interrupt request is sent to the
CPU when OVIE in TCRV0 is 1.
3. TCNTV is constantly compared with TCORA and TCORB. Compare match flag A or B
(CMFA or CMFB) is set to 1 when TCNTV matches TCORA or TCORB, respectively. The
compare-match signal is generated in the last state in which the values match. Figure 11.5
shows the timing. An interrupt request is generated for the CPU when CMIEA or CMIEB in
TCRV0 is 1.
4. When a compare match A or B is generated, the TMOV responds with the output value
selected by bits OS3 to OS0 in TCSRV. Figure 11.6 shows the timing when the output is
toggled by compare match A.
5. When CCLR1 or CCLR0 in TCRV0 is 01 or 10, TCNTV can be cleared by the corresponding
compare match. Figure 11.7 shows the timing.
6. When CCLR1 or CCLR0 in TCRV0 is 11, TCNTV can be cleared by the rising edge of the
input of TMRIV pin. A TMRIV input pulse-width of at least 1.5 system clocks is necessary.
Figure 11.8 shows the timing.
7. When a counter-clearing source is generated with TRGE in TCRV1 set to 1, the counting-up is
halted as soon as TCNTV is cleared. TCNTV resumes counting-up when the edge selected by
TVEG1 or TVEG0 in TCRV1 is input from the TGRV pin.
Rev. 4.00 Mar. 15, 2006 Page 156 of 556
REJ09B0026-0400
Section 11 Timer V
φ
Internal clock
TCNTV input
clock
TCNTV
N–1
N
N+1
Figure 11.2 Increment Timing with Internal Clock
φ
TMCIV
(External clock
input pin)
TCNTV input
clock
TCNTV
N–1
N
N+1
Figure 11.3 Increment Timing with External Clock
φ
TCNTV
H'FF
H'00
Overflow signal
OVF
Figure 11.4 OVF Set Timing
Rev. 4.00 Mar. 15, 2006 Page 157 of 556
REJ09B0026-0400
Section 11 Timer V
φ
TCNTV
N
TCORA or
TCORB
N
N+1
Compare match
signal
CMFA or
CMFB
Figure 11.5 CMFA and CMFB Set Timing
φ
Compare match
A signal
Timer V output
pin
Figure 11.6 TMOV Output Timing
φ
Compare match
A signal
TCNTV
N
H'00
Figure 11.7 Clear Timing by Compare Match
Rev. 4.00 Mar. 15, 2006 Page 158 of 556
REJ09B0026-0400
Section 11 Timer V
φ
TMRIV (External
counter reset pin)
TCNTV reset
signal
N–1
TCNTV
N
H'00
Figure 11.8 Clear Timing by TMRIV Input
11.5
Timer V Application Examples
11.5.1
Pulse Output with Arbitrary Duty Cycle
Figure 11.9 shows an example of output of pulses with an arbitrary duty cycle.
1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with
TCORA.
2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA
and to 0 at compare match with TCORB.
3. Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source.
4. With these settings, a waveform is output without further software intervention, with a period
determined by TCORA and a pulse width determined by TCORB.
TCNTV value
H'FF
Counter cleared
TCORA
TCORB
H'00
Time
TMOV
Figure 11.9 Pulse Output Example
Rev. 4.00 Mar. 15, 2006 Page 159 of 556
REJ09B0026-0400
Section 11 Timer V
11.5.2
Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input
The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary
delay from the TRGV input, as shown in figure 11.10. To set up this output:
1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with
TCORB.
2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA
and to 0 at compare match with TCORB.
3. Set bits TVEG1 and TVEG0 in TCRV1 and set TRGE to select the falling edge of the TRGV
input.
4. Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source.
5. After these settings, a pulse waveform will be output without further software intervention,
with a delay determined by TCORA from the TRGV input, and a pulse width determined by
(TCORB – TCORA).
TCNTV value
H'FF
Counter cleared
TCORB
TCORA
H'00
Time
TRGV
TMOV
Compare match A
Compare match B
clears TCNTV and
halts count-up
Compare match A
Compare match B
clears TCNTV and
halts count-up
Figure 11.10 Example of Pulse Output Synchronized to TRGV Input
Rev. 4.00 Mar. 15, 2006 Page 160 of 556
REJ09B0026-0400
Section 11 Timer V
11.6
Usage Notes
The following types of contention or operation can occur in timer V operation.
1. Writing to registers is performed in the T3 state of a TCNTV write cycle. If a TCNTV clear
signal is generated in the T3 state of a TCNTV write cycle, as shown in figure 11.11, clearing
takes precedence and the write to the counter is not carried out. If counting-up is generated in
the T3 state of a TCNTV write cycle, writing takes precedence.
2. If a compare match is generated in the T3 state of a TCORA or TCORB write cycle, the write
to TCORA or TCORB takes precedence and the compare match signal is inhibited. Figure
11.12 shows the timing.
3. If compare matches A and B occur simultaneously, any conflict between the output selections
for compare match A and compare match B is resolved by the following priority: toggle output
> output 1 > output 0.
4. Depending on the timing, TCNTV may be incremented by a switch between different internal
clock sources. When TCNTV is internally clocked, an increment pulse is generated from the
falling edge of an internal clock signal that is a divided system clock (φ). Therefore, as shown
in figure 11.3 the switch is from a high clock signal to a low clock signal, the switchover is
seen as a falling edge, causing TCNTV to increment. TCNTV can also be incremented by a
switch between internal and external clocks.
TCNTV write cycle by CPU
T2
T1
T3
φ
Address
TCNTV address
Internal write signal
Counter clear signal
TCNTV
N
H'00
Figure 11.11 Contention between TCNTV Write and Clear
Rev. 4.00 Mar. 15, 2006 Page 161 of 556
REJ09B0026-0400
Section 11 Timer V
TCORA write cycle by CPU
T2
T1
T3
φ
Address
TCORA address
Internal write signal
TCNTV
N
N+1
TCORA
N
M
TCORA write data
Compare match signal
Inhibited
Figure 11.12 Contention between TCORA Write and Compare Match
Clock before
switching
Clock after
switching
Count clock
TCNTV
N
N+1
N+2
Write to CKS1 and CKS0
Figure 11.13 Internal Clock Switching and TCNTV Operation
Rev. 4.00 Mar. 15, 2006 Page 162 of 556
REJ09B0026-0400
Section 12 Timer Z
Section 12 Timer Z
The timer Z has a 16-bit timer with two channels. Figures 12.1, 12.2, and 12.3 show the block
diagrams of entire timer Z, its channel 0, and its channel 1, respectively. For details on the timer Z
functions, refer to table 12.1.
12.1
Features
• Capability to process up to eight inputs/outputs
• Eight general registers (GE): four registers for each channel
 Independently assignable output compare or input capture functions
• Selection of five counter clock sources: four internal clocks (φ, φ/2, φ/4, and φ/8) and an
external clock
• Seven selectable operating modes
 Output compare function
Selection of 0 output, 1 output, or toggle output
 Input capture function
Rising edge, falling edge, or both edges
 Synchronous operation
Timer counters_0 and _1 (TCNT_0 and TCNT_1) can be written simultaneously.
Simultaneous clearing by compare match or input capture is possible.
 PWM mode
Up to six-phase PWM output can be provided with desired duty ratio.
 Reset synchronous PWM mode
Three-phase PWM output for normal and counter phases
 Complementary PWM mode
Three-phase PWM output for non-overlapped normal and counter phases
The A/D conversion start trigger can be set for PWM cycles.
 Buffer operation
The input capture register can be consisted of double buffers.
The output compare register can automatically be modified.
• High-speed access by the internal 16-bit bus
 16-bit TCNT and GR registers can be accessed in high speed by a 16-bit bus interface
• Any initial timer output value can be set
• Output of the timer is disabled by external trigger
Rev. 4.00 Mar. 15, 2006 Page 163 of 556
REJ09B0026-0400
Section 12 Timer Z
• Eleven interrupt sources
 Four compare match/input capture interrupts and an overflow interrupt are available for
each channel. An underflow interrupt can be set for channel 1.
Table 12.1 Timer Z Functions
Item
Channel 0
Channel 1
Count clock
Internal clocks: φ, φ/2, φ/4, φ/8
External clock: FTIOA0 (TCLK)
General registers
(output compare/input
capture registers)
GRA_0, GRB_0, GRC_0, GRD_0 GRA_1, GRB_1, GRC_1, GRD_1
Buffer register
GRC_0, GRD_0
GRC_1, GRD_1
I/O pins
FTIOA0, FTIOB0, FTIOC0,
FTIOD0
FTIOA1, FTIOB1, FTIOC1,
FTIOD1
Counter clearing function
Compare match/input capture of
GRA_0, GRB_0, GRC_0, or
GRD_0
Compare match/input capture of
GRA_1, GRB_1, GRC_1, or
GRD_1
Compare
match output
0 output
Yes
Yes
1 output
Yes
Yes
output
Yes
Yes
Input capture function
Yes
Yes
Synchronous operation
Yes
Yes
PWM mode
Yes
Yes
Reset synchronous PWM
mode
Yes
Yes
Complementary PWM
mode
Yes
Yes
Buffer function
Yes
Yes
Interrupt sources
Compare match/input capture A0
to D0
Overflow
Compare match/input capture A1
to D1
Overflow
Underflow
Rev. 4.00 Mar. 15, 2006 Page 164 of 556
REJ09B0026-0400
Section 12 Timer Z
ITMZ0
FTIOA0
ITMZ1
FTIOB0
FTIOC0
FTIOD0
Control logic
FTIOA1
FTIOB1
FTIOC1
FTIOD1
φ, φ/2,
φ/4, φ/8
ADTRG
Channel 0
timer
Channel 1
timer
TSTR
TMDR
TPMR
TFCR
TOER
TOCR
Module data bus
[Legend]
TSTR :
Timer start register (8 bits)
TMDR : Timer mode register (8 bits)
TPMR : Timer PWM mode register (8 bits)
TFCR :
Timer function control register (8 bits)
TOER :
Timer output master enable register (8 bits)
TOCR : Timer output control register (8 bits)
ADTRG : A/D conversion start trigger output signal
ITMZ0 : Channel 0 interrupt
ITMZ1 : Channel 1 interrupt
Figure 12.1 Timer Z Block Diagram
Rev. 4.00 Mar. 15, 2006 Page 165 of 556
REJ09B0026-0400
Section 12 Timer Z
FTIOA0
FTIOB0
φ, φ/2,
φ/4, φ/8
FTIOC0
Clock select
FTIOD0
Control logic
ITMZ0
Module data bus
[Legend]
TCNT_0 :
GRA_0, GRB_0,
GRC_0, GRD_0 :
TCR_0 :
TIORA_0 :
TIORC_0 :
TSR_0 :
TIER_0 :
POCR_0 :
ITMZ0 :
Timer counter_0 (16 bits)
General registers A_0, B_0, C_0, and D_0 (input capture/output compare registers:
16 bits × 4)
Timer control register_0 (8 bits)
Timer I/O control register A_0 (8 bits)
Timer I/O control register C_0 (8 bits)
Timer status register_0 (8 bits)
Timer interrupt enable register_0 (8 bits)
PWM mode output level control register_0 (8 bits)
Channel 0 interrupt
Figure 12.2 Timer Z (Channel 0) Block Diagram
Rev. 4.00 Mar. 15, 2006 Page 166 of 556
REJ09B0026-0400
POCR_0
TIER_0
TSR_0
TIORC_0
TIORA_0
TCR_0
GRD_0
GRC_0
GRB_0
GRA_0
TCNT_0
Comparator
Section 12 Timer Z
FTIOA1
FTIOB1
φ, φ/2,
φ/4, φ/8
FTIOC1
Clock select
FTIOD1
Control logic
ITMZ1
POCR_1
TIER_1
TSR_1
TIORC_1
TIORA_1
TCR_1
GRD_1
GRC_1
GRB_1
GRA_1
TCNT_1
Comparator
Module data bus
[Legend]
TCNT_1 :
GRA_1, GRB_1,
GRC_1, GRD_1 :
TCR_1 :
TIORA_1 :
TIORC_1 :
TSR_1 :
TIER_1 :
POCR_1 :
ITMZ1 :
Timer counter_1 (16 bits)
General registers A_1, B_1, C_1, and D_1 (input capture/output compare registers:
16 bits × 4)
Timer control register_1 (8 bits)
Timer I/O control register A_1 (8 bits)
Timer I/O control register C_1 (8 bits)
Timer status register_1 (8 bits)
Timer interrupt enable register_1 (8 bits)
PWM mode output level control register_1 (8 bits)
Channel 1 interrupt
Figure 12.3 Timer Z (Channel 1) Block Diagram
Rev. 4.00 Mar. 15, 2006 Page 167 of 556
REJ09B0026-0400
Section 12 Timer Z
12.2
Input/Output Pins
Table 12.2 summarizes the timer Z pins.
Table 12.2 Pin Configuration
Name
Abbreviation I/O
Function
Input capture/output
compare A0
FTIOA0
I/O
GRA_0 output compare output, GRA_0
input capture input, or external clock input
(TCLK)
Input capture/output
compare B0
FTIOB0
I/O
GRB_0 output compare output, GRB_0
input capture input, or PWM output
Input capture/output
compare C0
FTIOC0
I/O
GRC_0 output compare output, GRC_0
input capture input, or PWM synchronous
output (in reset synchronous PWM and
complementary PWM modes)
Input capture/output
compare D0
FTIOD0
I/O
GRD_0 output compare output, GRD_0
input capture input, or PWM output
Input capture/output
compare A1
FTIOA1
I/O
GRA_1 output compare output, GRA_1
input capture input, or PWM output (in
reset synchronous PWM and
complementary PWM modes)
Input capture/output
compare B1
FTIOB1
I/O
GRB_1 output compare output, GRB_1
input capture input, or PWM output
Input capture/output
compare C1
FTIOC1
I/O
GRC_1 output compare output, GRC_1
input capture input, or PWM output
Input capture/output
compare D1
FTIOD1
I/O
GRD_1 output compare output, GRD_1
input capture input, or PWM output
Rev. 4.00 Mar. 15, 2006 Page 168 of 556
REJ09B0026-0400
Section 12 Timer Z
12.3
Register Descriptions
The timer Z has the following registers.
Common
•
•
•
•
•
•
Timer start register (TSTR)
Timer mode register (TMDR)
Timer PWM mode register (TPMR)
Timer function control register (TFCR)
Timer output master enable register (TOER)
Timer output control register (TOCR)
Channel 0
•
•
•
•
•
•
•
•
•
•
•
Timer control register_0 (TCR_0)
Timer I/O control register A_0 (TIORA_0)
Timer I/O control register C_0 (TIORC_0)
Timer status register_0 (TSR_0)
Timer interrupt enable register_0 (TIER_0)
PWM mode output level control register_0 (POCR_0)
Timer counter_0 (TCNT_0)
General register A_0 (GRA_0)
General register B_0 (GRB_0)
General register C_0 (GRC_0)
General register D_0 (GRD_0)
Channel 1
•
•
•
•
•
•
•
•
•
Timer control register_1 (TCR_1)
Timer I/O control register A_1 (TIORA_1)
Timer I/O control register C_1 (TIORC_1)
Timer status register_1 (TSR_1)
Timer interrupt enable register_1 (TIER_1)
PWM mode output level control register_1 (POCR_1)
Timer counter_1 (TCNT_1)
General register A_1 (GRA_1)
General register B_1 (GRB_1)
Rev. 4.00 Mar. 15, 2006 Page 169 of 556
REJ09B0026-0400
Section 12 Timer Z
• General register C_1 (GRC_1)
• General register D_1 (GRD_1)
12.3.1
Timer Start Register (TSTR)
TSTR selects the operation/stop for the TCNT counter.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 2

All 1

Reserved
These bits are always read as 1 and cannot be modified.
1
STR1
0
R/W
Channel 1 Counter Start
0: TCNT_1 halts counting
1: TCNT_1 starts counting
0
STR0
0
R/W
Channel 0 Counter Start
0: TCNT_0 halts counting
1: TCNT_0 starts counting
Rev. 4.00 Mar. 15, 2006 Page 170 of 556
REJ09B0026-0400
Section 12 Timer Z
12.3.2
Timer Mode Register (TMDR)
TMDR selects buffer operation settings and synchronized operation.
Bit
Bit Name
Initial
Value
R/W
Description
7
BFD1
0
R/W
Buffer Operation D1
0: GRD_1 operates normally
1: GRB_1 and GRD_1 are used together for buffer
operation
6
BFC1
0
R/W
Buffer Operation C1
0: GRC_1 operates normally
1: GRA_1 and GRD_1 are used together for buffer
operation
5
BFD0
0
R/W
Buffer Operation D0
0: GRD_0 operates normally
1: GRB_0 and GRD_0 are used together for buffer
operation
4
BFC0
0
R/W
Buffer Operation C0
0: GRC_0 operates normally
1: GRA_0 and GRC_0 are used together for buffer
operation
3 to 1

All 1

Reserved
These bits are always read as 1 and cannot be modified.
0
SYNC
0
R/W
Timer Synchronization
0: TCNT_1 and TCNT_0 operate as a different timer
1: TCNT_1 and TCNT_0 are synchronized
TCNT_1 and TCNT_0 can be pre-set or cleared
synchronously
Rev. 4.00 Mar. 15, 2006 Page 171 of 556
REJ09B0026-0400
Section 12 Timer Z
12.3.3
Timer PWM Mode Register (TPMR)
TPMR sets the pin to enter PWM mode.
Bit
Bit Name
Initial
Value
R/W
Description
7

1

Reserved
This bit is always read as 1 and cannot be modified.
6
PWMD1
0
R/W
PWM Mode D1
0: FTIOD1 operates normally
1: FTIOD1 operates in PWM mode
5
PWMC1
0
R/W
PWM Mode C1
0: FTIOC1 operates normally
1: FTIOC1 operates in PWM mode
4
PWMB1
0
R/W
PWM Mode B1
0: FTIOB1 operates normally
1: FTIOB1 operates in PWM mode
3

1

Reserved
This bit is always read as 1, and cannot be modified.
2
PWMD0
0
R/W
PWM Mode D0
0: FTIOD0 operates normally
1: FTIOD0 operates in PWM mode
1
PWMC0
0
R/W
PWM Mode C0
0: FTIOC0 operates normally
1: FTIOC0 operates in PWM mode
0
PWMB0
0
R/W
PWM Mode B0
0: FTIOB0 operates normally
1: FTIOB0 operates in PWM mode
Rev. 4.00 Mar. 15, 2006 Page 172 of 556
REJ09B0026-0400
Section 12 Timer Z
12.3.4
Timer Function Control Register (TFCR)
TFCR selects the settings and output levels for each operating mode.
Bit
Bit Name
Initial
Value
R/W
Description
7

1

Reserved
This bit is always read as 1.
6
STCLK
0
R/W
External Clock Input Select
0: External clock input is disabled
1: External clock input is enabled
5
ADEG
0
R/W
A/D Trigger Edge Select
A/D module should be set to start an A/D conversion by the
external trigger
0: A/D trigger at the crest in complementary PWM mode
1: A/D trigger at the trough in complementary PWM mode
4
ADTRG
0
R/W
External Trigger Disable
0: A/D trigger for PWM cycles is disabled in complementary
PWM mode
1: A/D trigger for PWM cycles is enabled in complementary
PWM mode
3
OLS1
0
R/W
Output Level Select 1
Selects the counter-phase output levels in reset
synchronous PWM mode or complementary PWM mode.
0: Initial output is high and the active level is low.
1: Initial output is low and the active level is high.
2
OLS0
0
R/W
Output Level Select 0
Selects the normal-phase output levels in reset
synchronous PWM mode or complementary PWM mode.
0: Initial output is high and the active level is low.
1: Initial output is low and the active level is high.
Figure 12.4 shows an example of outputs in reset
synchronous PWM mode and complementary PWM mode
when OLS1 = 0 and OLS0 = 0.
Rev. 4.00 Mar. 15, 2006 Page 173 of 556
REJ09B0026-0400
Section 12 Timer Z
Bit
Bit Name
Initial
Value
R/W
Description
1
CMD1
0
R/W
Combination Mode 1 and 0
0
CMD0
0
R/W
00: Channel 0 and channel 1 operate normally
01: Channel 0 and channel 1 are used together to
operate in reset synchronous PWM mode
10: Channel 0 and channel 1 are used together to
operate in complementary PWM mode (transferred at
the trough)
11: Channel 0 and channel 1 are used together to
operate in complementary PWM mode (transferred at
the crest)
Note: When reset synchronous PWM mode or
complementary PWM mode is selected by these
bits, this setting has the priority to the settings for
PWM mode by each bit in TPMR. Stop TCNT_0
and TCNT_1 before making settings for reset
synchronous PWM mode or complementary PWM
mode.
TCNT_0
TCNT_1
Normal phase
Normal phase
Active level
Active level
Counter phase
Counter phase
Initial
output
Active level
Reset synchronous PWM mode
Initial
output
Active level
Complementary PWM mode
Note: Write H'00 to TOCR to start initial outputs after stopping the counter.
Figure 12.4 Example of Outputs in Reset Synchronous PWM Mode
and Complementary PWM Mode
Rev. 4.00 Mar. 15, 2006 Page 174 of 556
REJ09B0026-0400
Section 12 Timer Z
12.3.5
Timer Output Master Enable Register (TOER)
TOER enables/disables the outputs for channel 0 and channel 1. When WKP4 is selected for
inputs, if a low level signal is input to WKP4, the bits in TOER are set to 1 to disable the output
for timer Z.
Bit
Bit Name
Initial
Value
R/W
Description
7
ED1
1
R/W
Master Enable D1
0: FTIOD1 pin output is enabled according to the TPMR,
TFCR, and TIORC_1 settings
1: FTIOD1 pin output is disabled regardless of the TPMR,
TFCR, and TIORC_1 settings (FTIOD1 pin is operated
as an I/O port).
6
EC1
1
R/W
Master Enable C1
0: FTIOC1 pin output is enabled according to the TPMR,
TFCR, and TIORC_1 settings
1: FTIOC1 pin output is disabled regardless of the TPMR,
TFCR, and TIORC_1 settings (FTIOC1 pin is operated
as an I/O port).
5
EB1
1
R/W
Master Enable B1
0: FTIOB1 pin output is enabled according to the TPMR,
TFCR, and TIORA_1 settings
1: FTIOB1 pin output is disabled regardless of the TPMR,
TFCR, and TIORA_1 settings (FTIOB1 pin is operated
as an I/O port).
4
EA1
1
R/W
Master Enable A1
0: FTIOA1 pin output is enabled according to the TPMR,
TFCR, and TIORA_1 settings
1: FTIOA1 pin output is disabled regardless of the TPMR,
TFCR, and TIORA_1 settings (FTIOA1 pin is operated
as an I/O port).
3
ED0
1
R/W
Master Enable D0
0: FTIOD0 pin output is enabled according to the TPMR,
TFCR, and TIORC_0 settings
1: FTIOD0 pin output is disabled regardless of the TPMR,
TFCR, and TIORC_0 settings (FTIOD0 pin is operated
as an I/O port).
Rev. 4.00 Mar. 15, 2006 Page 175 of 556
REJ09B0026-0400
Section 12 Timer Z
Bit
Bit Name
Initial
Value
R/W
Description
2
EC0
1
R/W
Master Enable C0
0: FTIOC0 pin output is enabled according to the TPMR,
TFCR, and TIORC_0 settings
1: FTIOC0 pin output is disabled regardless of the TPMR,
TFCR, and TIORC_0 settings (FTIOC0 pin is operated
as an I/O port).
1
EB0
1
R/W
Master Enable B0
0: FTIOB0 pin output is enabled according to the TPMR,
TFCR, and TIORA_0 settings
1: FTIOB0 pin output is disabled regardless of the TPMR,
TFCR, and TIORA_0 settings (FTIOB0 pin is operated
as an I/O port).
0
EA0
1
R/W
Master Enable A0
0: FTIOA0 pin output is enabled according to the TPMR,
TFCR, and TIORA_0 settings
1: FTIOA0 pin output is disabled regardless of the TPMR,
TFCR, and TIORA_0 settings (FTIOA0 pin is operated
as an I/O port).
12.3.6
Timer Output Control Register (TOCR)
TOCR selects the initial outputs before the first occurrence of a compare match. Note that bits
OLS1 and OLS0 in TFCR set these initial outputs in reset synchronous PWM mode and
complementary PWM mode.
Bit
Bit Name
Initial
Value
R/W
Description
7
TOD1
0
R/W
Output Level Select D1
0: 0 output at the FTIOD1 pin*
1: 1 output at the FTIOD1 pin*
6
TOC1
0
R/W
Output Level Select C1
0: 0 output at the FTIOC1 pin*
1: 1 output at the FTIOC1 pin*
5
TOB1
0
R/W
Output Level Select B1
0: 0 output at the FTIOB1 pin*
1: 1 output at the FTIOB1 pin*
Rev. 4.00 Mar. 15, 2006 Page 176 of 556
REJ09B0026-0400
Section 12 Timer Z
Bit
Bit Name
Initial
Value
R/W
Description
4
TOA1
0
R/W
Output Level Select A1
0: 0 output at the FTIOA1 pin*
1: 1 output at the FTIOA1 pin*
3
TOD0
0
R/W
Output Level Select D0
0: 0 output at the FTIOD0 pin*
1: 1 output at the FTIOD0 pin*
2
TOC0
0
R/W
Output Level Select C0
0: 0 output at the FTIOC0 pin*
1: 1 output at the FTIOC0 pin*
1
TOB0
0
R/W
Output Level Select B0
0: 0 output at the FTIOB0 pin*
1: 1 output at the FTIOB0 pin*
0
TOA0
0
R/W
Output Level Select A0
0: 0 output at the FTIOA0 pin*
1: 1 output at the FTIOA0 pin*
Note:
12.3.7
*
The change of the setting is immediately reflected in the output value.
Timer Counter (TCNT)
The timer Z has two TCNT counters (TCNT_0 and TCNT_1), one for each channel. The TCNT
counters are 16-bit readable/writable registers that increment/decrement according to input clocks.
Input clocks can be selected by bits TPSC2 to TPSC0 in TCR. TCNT0 and TCNT 1
increment/decrement in complementary PWM mode, while they only increment in other modes.
The TCNT counters are initialized to H'0000 by compare matches with corresponding GRA, GRB,
GRC, or GRD, or input captures to GRA, GRB, GRC, or GRD (counter clearing function). When
the TCNT counters overflow, an OVF flag in TSR for the corresponding channel is set to 1. When
TCNT_1 underflows, an UDF flag in TSR is set to 1. The TCNT counters cannot be accessed in 8bit units; they must always be accessed as a 16-bit unit. TCNT is initialized to H'0000.
Rev. 4.00 Mar. 15, 2006 Page 177 of 556
REJ09B0026-0400
Section 12 Timer Z
12.3.8
General Registers A, B, C, and D (GRA, GRB, GRC, and GRD)
GR are 16-bit registers. Timer Z has eight general registers (GR), four for each channel. The GR
registers are dual function 16-bit readable/writable registers, functioning as either output compare
or input capture registers. Functions can be switched by TIORA and TIORC.
The values in GR and TCNT are constantly compared with each other when the GR registers are
used as output compare registers. When the both values match, the IMFA to IMFD flags in TSR
are set to 1. Compare match outputs can be selected by TIORA and TIORC.
When the GR registers are used as input capture registers, the TCNT value is stored after detecting
external signals. At this point, IMFA to IMFD flags in the corresponding TSR are set to 1.
Detection edges for input capture signals can be selected by TIORA and TIORC.
When PWM mode, complementary PWM mode, or reset synchronous PWM mode is selected, the
values in TIORA and TIORC are ignored. Upon reset, the GR registers are set as output compare
registers (no output) and initialized to H'FFFF. The GR registers cannot be accessed in 8-bit units;
they must always be accessed as a 16-bit unit.
Rev. 4.00 Mar. 15, 2006 Page 178 of 556
REJ09B0026-0400
Section 12 Timer Z
12.3.9
Timer Control Register (TCR)
The TCR registers select a TCNT counter clock, an edge when an external clock is selected, and
counter clearing sources. Timer Z has a total of two TCR registers, one for each channel.
Bit
Bit Name
Initial
Value
R/W
Description
7
CCLR2
0
R/W
Counter Clear 2 to 0
6
CCLR1
0
R/W
000: Disables TCNT clearing
5
CCLR0
0
R/W
001: Clears TCNT by GRA compare match/input
1
capture*
010: Clears TCNT by GRB compare match/input
1
capture*
011: Synchronization clear; Clears TCNT in synchronous
with counter clearing of the other channel’s timer*2
000: Disables TCNT clearing
001: Clears TCNT by GRC compare match/input
1
capture*
010: Clears TCNT by GRD compare match/input
capture*1
011: Synchronization clear; Clears TCNT in synchronous
2
with counter clearing of the other channel’s timer*
4
CKEG1
0
R/W
Clock Edge 1 and 0
3
CKEG0
0
R/W
00: Count at rising edge
01: Count at falling edge
1X: Count at both edges
2
TPSC2
0
R/W
Time Prescaler 2 to 0
1
TPSC1
0
R/W
000: Internal clock: count by φ
0
TPSC0
0
R/W
001: Internal clock: count by φ/2
010: Internal clock: count by φ/4
011: Internal clock: count by φ/8
1XX: External clock: count by FTIOA0 (TCLK) pin input
Notes: 1. When GR functions as an output compare register, TCNT is cleared by compare match.
When GR functions as input capture, TCNT is cleared by input capture.
2. Synchronous operation is set by TMDR.
3. X: Don’t care
Rev. 4.00 Mar. 15, 2006 Page 179 of 556
REJ09B0026-0400
Section 12 Timer Z
12.3.10 Timer I/O Control Register (TIORA and TIORC)
The TIOR registers control the general registers (GR). Timer Z has four TIOR registers
(TIORA_0, TIORA_1, TIORC_0, and TIORC_1), two for each channel. In PWM mode including
complementary PWM mode and reset synchronous PWM mode, the settings of TIOR are invalid.
TIORA: TIORA selects whether GRA or GRB is used as an output compare register or an input
capture register. When an output compare register is selected, the output setting is selected. When
an input capture register is selected, an input edge of an input capture signal is selected. TIORA
also selects the function of FTIOA or FTIOB pin.
Bit
Bit Name
Initial
Value
R/W
Description
7

1

Reserved
This bit is always read as 1.
6
IOB2
0
R/W
I/O Control B2 to B0
5
IOB1
0
R/W
GRB is an output compare register:
4
IOB0
0
R/W
000: Disables pin output by compare match
001: 0 output by GRB compare match
010: 1 output by GRB compare match
011: Toggle output by GRB compare match
GRB is an input capture register:
100: Input capture to GRB at the rising edge
101: Input capture to GRB at the falling edge
11X: Input capture to GRB at both rising and falling edges
3

1

Reserved
This bit is always read as 1.
Rev. 4.00 Mar. 15, 2006 Page 180 of 556
REJ09B0026-0400
Section 12 Timer Z
Bit
Bit Name
Initial
Value
R/W
Description
2
IOA2
0
R/W
I/O Control A2 to A0
1
IOA1
0
R/W
GRA is an output compare register:
0
IOA0
0
R/W
000: Disables pin output by compare match
001: 0 output by GRA compare match
010: 1 output by GRA compare match
011: Toggle output by GRA compare match
GRA is an input capture register:
100: Input capture to GRA at the rising edge
101: Input capture to GRA at the falling edge
11X: Input capture to GRA at both rising and falling edges
[Legend]
X: Don't care
TIORC: TIORC selects whether GRC or GRD is used as an output compare register or an input
capture register. When an output compare register is selected, the output setting is selected. When
an input capture register is selected, an input edge of an input capture signal is selected. TIORC
also selects the function of FTIOC or FTIOD pin.
Bit
Bit Name
Initial
Value
R/W
Description
7

1

Reserved
This bit is always read as 1.
6
IOD2
0
R/W
I/O Control D2 to D0
5
IOD1
0
R/W
GRD is an output compare register:
4
IOD0
0
R/W
000: Disables pin output by compare match
001: 0 output by GRD compare match
010: 1 output by GRD compare match
011: Toggle output by GRD compare match
GRD is an input capture register:
100: Input capture to GRD at the rising edge
101: Input capture to GRD at the falling edge
11X: Input capture to GRD at both rising and falling edges
3

1

Reserved
This bit is always read as 1.
Rev. 4.00 Mar. 15, 2006 Page 181 of 556
REJ09B0026-0400
Section 12 Timer Z
Bit
Bit Name
Initial
value
R/W
Description
2
IOC2
0
R/W
I/O Control C2 to C0
1
IOC1
0
R/W
GRC is an output compare register:
0
IOC0
0
R/W
000: Disables pin output by compare match
001: 0 output by GRC compare match
010: 1 output by GRC compare match
011: Toggle Output by GRC compare match
GRC is an input capture register:
100: Input capture to GRC at the rising edge
101: Input capture to GRC at the falling edge
11X: Input capture to GRC at both rising and falling edges
[Legend]
X: Don't care
12.3.11 Timer Status Register (TSR)
TSR indicates generation of an overflow/underflow of TCNT and a compare match/input capture
of GRA, GRB, GRC, and GRD. These flags are interrupt sources. If an interrupt is enabled by a
corresponding bit in TIER, TSR requests an interrupt for the CPU. Timer Z has two TSR registers,
one for each channel.
Bit
Bit Name
Initial
Value
R/W
Description
7, 6

All 1

Reserved
These bits are always read as 1.
5
UDF*
0
R/W
Underflow Flag
[Setting condition]
•
When TCNT_1 underflows
[Clearing condition]
•
4
OVF
0
R/W
When 0 is written to UDF after reading UDF = 1
Overflow Flag
[Setting condition]
•
When the TCNT value underflows
[Clearing condition]
•
Rev. 4.00 Mar. 15, 2006 Page 182 of 556
REJ09B0026-0400
When 0 is written to OVF after reading OVF = 1
Section 12 Timer Z
Bit
Bit Name
Initial
Value
R/W
Description
3
IMFD
0
R/W
Input Capture/Compare Match Flag D
[Setting conditions]
•
When TCNT = GRD and GRD is functioning as output
compare register
•
When TCNT value is transferred to GRD by input
capture signal and GRD is functioning as input
capture register
[Clearing condition]
•
2
IMFC
0
R/W
When 0 is written to IMFD after reading IMFD = 1
Input Capture/Compare Match Flag C
[Setting conditions]
•
When TCNT = GRC and GRC is functioning as output
compare register
•
When TCNT value is transferred to GRC by input
capture signal and GRC is functioning as input
capture register
[Clearing condition]
•
1
IMFB
0
R/W
When 0 is written to IMFC after reading IMFC = 1
Input Capture/Compare Match Flag B
[Setting conditions]
•
When TCNT = GRB and GRB is functioning as output
compare register
•
When TCNT value is transferred to GRB by input
capture signal and GRB is functioning as input
capture register
[Clearing condition]
•
When 0 is written to IMFB after reading IMFB = 1
Rev. 4.00 Mar. 15, 2006 Page 183 of 556
REJ09B0026-0400
Section 12 Timer Z
Bit
Bit Name
Initial
Value
R/W
Description
0
IMFA
0
R/W
Input Capture/Compare Match Flag A
[Setting conditions]
•
When TCNT = GRA and GRA is functioning as output
compare register
•
When TCNT value is transferred to GRA by input
capture signal and GRA is functioning as input
capture register
[Clearing condition]
•
When 0 is written to IMFA after reading IMFA = 1
Note: Bit 5 is not the UDF flag in TSR_0. It is a reserved bit. It is always read as 1.
12.3.12 Timer Interrupt Enable Register (TIER)
TIER enables or disables interrupt requests for overflow or GR compare match/input capture.
Timer Z has two TIER registers, one for each channel.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 5

All 1

Reserved
These bits are always read as 1.
4
OVIE
0
R/W
Overflow Interrupt Enable
0: Interrupt requests (OVI) by OVF or UDF flag are
disabled
1: Interrupt requests (OVI) by OVF or UDF flag are
enabled
3
IMIED
0
R/W
Input Capture/Compare Match Interrupt Enable D
0: Interrupt requests (IMID) by IMFD flag are disabled
1: Interrupt requests (IMID) by IMFD flag are enabled
2
IMIEC
0
R/W
Input Capture/Compare Match Interrupt Enable C
0: Interrupt requests (IMIC) by IMFC flag are disabled
1: Interrupt requests (IMIC) by IMFC flag are enabled
1
IMIEB
0
R/W
Input Capture/Compare Match Interrupt Enable B
0: Interrupt requests (IMIB) by IMFB flag are disabled
1: Interrupt requests (IMIB) by IMFB flag are enabled
Rev. 4.00 Mar. 15, 2006 Page 184 of 556
REJ09B0026-0400
Section 12 Timer Z
Bit
Bit Name
Initial
Value
R/W
Description
0
IMIEA
0
R/W
Input Capture/Compare Match Interrupt Enable A
0: Interrupt requests (IMIA) by IMFA flag are disabled
1: Interrupt requests (IMIA) by IMFA flag are enabled
12.3.13 PWM Mode Output Level Control Register (POCR)
POCR control the active level in PWM mode. Timer Z has two POCR registers, one for each
channel.
Bit
Bit Name
Initial
value
R/W
Description
7 to 3

All 1

Reserved
2
POLD
0
R/W
These bits are always read as 1.
PWM Mode Output Level Control D
0: The output level of FTIOD is low-active
1: The output level of FTIOD is high-active
1
POLC
0
R/W
PWM Mode Output Level Control C
0: The output level of FTIOC is low-active
1: The output level of FTIOC is high-active
0
POLB
0
R/W
PWM Mode Output Level Control B
0: The output level of FTIOB is low-active
1: The output level of FTIOB is high-active
Rev. 4.00 Mar. 15, 2006 Page 185 of 556
REJ09B0026-0400
Section 12 Timer Z
12.3.14 Interface with CPU
16-Bit Register: TCNT and GR are 16-bit registers. Reading/writing in a 16-bit unit is enabled
but disabled in an 8-bit unit since the data bus with the CPU is 16-bit width. These registers must
always be accessed in a 16-bit unit. Figure 12.5 shows an example of accessing the 16-bit
registers.
Internal data bus
H
C
P
L
Module data bus
Bus interface
U
TCNTH
TCNTL
Figure 12.5 Accessing Operation of 16-Bit Register (between CPU and TCNT (16 Bits))
8-Bit Register: Registers other than TCNT and GR are 8-bit registers that are connected internally
with the CPU in an 8-bit width. Figure 12.6 shows an example of accessing the 8-bit registers.
Internal data bus
H
C
P
L
Module data bus
Bus interface
U
TSTR
Figure 12.6 Accessing Operation of 8-Bit Register (between CPU and TSTR (8 Bits))
Rev. 4.00 Mar. 15, 2006 Page 186 of 556
REJ09B0026-0400
Section 12 Timer Z
12.4
Operation
12.4.1
Counter Operation
When one of bits STR0 and STR1 in TSTR is set to 1, the TCNT counter for the corresponding
channel begins counting. TCNT can operate as a free-running counter, periodic counter, for
example. Figure 12.7 shows an example of the counter operation setting procedure.
Operation selection
Select counter clock
[1]
Periodic counter
Free-running counter
Select counter clearing source
[2]
Select output compare register
[3]
Set period
Start count operation
[4]
[5]
[1] Select the counter
clock with bits
TPSC2 to TPSC0 in
TCR. When an external
clock is selected, select
the external clock edge
with bits CKEG1
and CKEG0 in TCR.
[2] For periodic counter
operation, select the
TCNT clearing
source with bits
CCLR2 to CCLR0 in
TCR.
[3] Designate the general
register selected in [2]
as an output compare
register by means of
TIOR.
[4] Set the periodic counter
cycle in the general
register selected
in [2].
[5] Set the STR bit in TSTR
to 1 to start the counter
operation.
Figure 12.7 Example of Counter Operation Setting Procedure
Rev. 4.00 Mar. 15, 2006 Page 187 of 556
REJ09B0026-0400
Section 12 Timer Z
Free-Running Count Operation and Periodic Count Operation: Immediately after a reset, the
TCNT counters for channels 0 and 1 are all designated as free-running counters. When the
relevant bit in TSTR is set to 1, the corresponding TCNT counter starts an increment operation as
a free-running counter. When TCNT overflows, the OVF flag in TSR is set to 1. If the value of the
OVIE bit in the corresponding TIER is 1 at this point, timer Z requests an interrupt. After
overflow, TCNT starts an increment operation again from H'0000.
Figure 12.8 illustrates free-running counter operation.
TCNT value
H'FFFF
H'0000
Time
STR0,
STR1
OVF
Figure 12.8 Free-Running Counter Operation
When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant
channel performs periodic count operation. The GR registers for setting the period are designated
as output compare registers, and counter clearing by compare match is selected by means of bits
CCLR1 and CCLR0 in TCR. After the settings have been made, TCNT starts an increment
operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count
value matches the value in GR, the IMFA, IMFB, IMFC, or IMFD flag in TSR is set to 1 and
TCNT is cleared to H'0000.
If the value of the corresponding IMIEA, IMIEB, IMIEC, or IMIED bit in TIER is 1 at this point,
the timer Z requests an interrupt. After a compare match, TCNT starts an increment operation
again from H'0000.
Rev. 4.00 Mar. 15, 2006 Page 188 of 556
REJ09B0026-0400
Section 12 Timer Z
Figure 12.9 illustrates periodic counter operation.
TCNT value
Counter cleared by GR compare match
GR value
H'0000
Time
STR
IMF
Figure 12.9 Periodic Counter Operation
TCNT Count Timing:
• Internal clock operation
A system clock (φ) or three types of clocks (φ/2, φ/4, or φ/8) that divides the system clock can
be selected by bits TPSC2 to TPSC0 in TCR.
Figure 12.10 illustrates this timing.
φ
Internal clock
TCNT input
TCNT
N-1
N
N+1
Figure 12.10 Count Timing at Internal Clock Operation
Rev. 4.00 Mar. 15, 2006 Page 189 of 556
REJ09B0026-0400
Section 12 Timer Z
• External clock operation
An external clock input pin (TCLK) can be selected by bits TPSC2 to TPSC0 in TCR, and a
detection edge can be selected by bits CKEG1 and CKEG0. To detect an external clock, the
rising edge, falling edge, or both edges can be selected. The pulse width of the external clock
needs two or more system clocks. Note that an external clock does not operate correctly with
the lower pulse width.
Figure 12.11 illustrates the detection timing of the rising and falling edges.
φ
External clock input pin
TCNT input
TCNT
N-1
N
N+1
Figure 12.11 Count Timing at External Clock Operation (Both Edges Detected)
Rev. 4.00 Mar. 15, 2006 Page 190 of 556
REJ09B0026-0400
Section 12 Timer Z
12.4.2
Waveform Output by Compare Match
Timer Z can perform 0, 1, or toggle output from the corresponding FTIOA, FTIOB, FTIOC, or
FTIOD output pin using compare match A, B, C, or D.
Figure 12.12 shows an example of the setting procedure for waveform output by compare match.
Output selection
Select waveform output mode
[1]
Set output timing
[2]
Enable waveform output
[3]
Start count operation
[4]
[1] Select 0 output, 1 output, or toggle
output as a compare much output, by
means of TIOR. The initial values set in
TOCR are output unit the first compare
match occurs.
[2] Set the timing for compare match
generation in GRA/GRB/GRC/GRD.
[3] Enable or disable the timer output by
TOER.
[4] Set the STR bit in TSTR to 1 to start the
TCNT count operation.
<Waveform output>
Figure 12.12 Example of Setting Procedure for Waveform Output by Compare Match
Rev. 4.00 Mar. 15, 2006 Page 191 of 556
REJ09B0026-0400
Section 12 Timer Z
Examples of Waveform Output Operation: Figure 12.13 shows an example of 0 output/1
output.
In this example, TCNT has been designated as a free-running counter, and settings have been
made such that 0 is output by compare match A, and 1 is output by compare match B. When the
set level and the pin level coincide, the pin level does not change.
TCNT value
H'FFFF
Time
H'0000
FTIOB
No change
FTIOA
No change
No change
No change
Figure 12.13 Example of 0 Output/1 Output Operation
Rev. 4.00 Mar. 15, 2006 Page 192 of 556
REJ09B0026-0400
Section 12 Timer Z
Figure 12.14 shows an example of toggle output.
In this example, TCNT has been designated as a periodic counter (with counter clearing on
compare match B), and settings have been made such that the output is toggled by both compare
match A and compare match B.
TCNT value
GRB
GRA
Time
H'0000
Toggle output
FTIOB
FTIOA
Toggle output
Figure 12.14 Example of Toggle Output Operation
Rev. 4.00 Mar. 15, 2006 Page 193 of 556
REJ09B0026-0400
Section 12 Timer Z
Output Compare Timing: The compare match signal is generated in the last state in which
TCNT and GR match (when TCNT changes from the matching value to the next value). When the
compare match signal is generated, the output value selected in TIOR is output at the compare
match output pin (FTIOA, FTIOB, FTIOC, or FTIOD). When TCNT matches GR, the compare
match signal is generated only after the next TCNT input clock pulse is input.
Figure 12.15 shows an example of the output compare timing.
φ
TCNT input
TCNT
N
GR
N
N+1
Compare match
signal
FTIOA to FTIOD
Figure 12.15 Output Compare Timing
Rev. 4.00 Mar. 15, 2006 Page 194 of 556
REJ09B0026-0400
Section 12 Timer Z
12.4.3
Input Capture Function
The TCNT value can be transferred to GR on detection of the input edge of the input
capture/output compare pin (FTIOA, FTIOB, FTIOC, or FTIOD). Rising edge, falling edge, or
both edges can be selected as the detected edge. When the input capture function is used, the pulse
width or period can be measured.
Figure 12.16 shows an example of the input capture operation setting procedure.
Input selection
Select input edge of
input capture
[1]
Start counter operation
[2]
[1] Designate GR as an input capture
register by means of TIOR, and select
rising edge, falling edge, or both edges
as the input edge of the input capture
signal.
[2] Set the STR bit in TSTR to 1 to start the
TCNT counter operation.
<Input capture operation>
Figure 12.16 Example of Input Capture Operation Setting Procedure
Rev. 4.00 Mar. 15, 2006 Page 195 of 556
REJ09B0026-0400
Section 12 Timer Z
Example of Input Capture Operation: Figure 12.17 shows an example of input capture
operation.
In this example, both rising and falling edges have been selected as the FTIOA pin input capture
input edge, the falling edge has been selected as the FTIOB pin input capture input edge, and
counter clearing by GRB input capture has been designated for TCNT.
Counter cleared by FTIOB input (falling edge)
TCNT value
H'0180
H'0160
H'0005
H'0000
Time
FTIOB
FTIOA
GRA
H'0005
GRB
H'0160
H'0180
Figure 12.17 Example of Input Capture Operation
Rev. 4.00 Mar. 15, 2006 Page 196 of 556
REJ09B0026-0400
Section 12 Timer Z
Input Capture Signal Timing: Input capture on the rising edge, falling edge, or both edges can
be selected through settings in TIOR. Figure 12.18 shows the timing when the rising edge is
selected. The pulse width of the input capture signal must be at least two system clock (φ) cycles.
φ
Input capture input
Input capture signal
TCNT
N
GR
N
Figure 12.18 Input Capture Signal Timing
Rev. 4.00 Mar. 15, 2006 Page 197 of 556
REJ09B0026-0400
Section 12 Timer Z
12.4.4
Synchronous Operation
In synchronous operation, the values in a number of TCNT counters can be rewritten
simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared
simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous
operation enables GR to be increased with respect to a single time base.
Figure 12.19 shows an example of the synchronous operation setting procedure.
Synchronous operation
selection
Set synchronous
operation
[1]
Synchronous presetting
Set TCNT
Synchronous clearing
[2]
Clearing
source generation
channel?
No
Yes
<Synchronous presetting>
Select counter
clearing source
[3]
Select counter
clearing source
[4]
Start counter operation
[5]
Start counter operation
[5]
<Counter clearing>
<Synchronous clearing>
[1] Set the SYNC bits in TMDR to 1.
[2] When a value is written to either of the TCNT counters, the same value is simultaneously written to the
other TCNT counter.
[3] Set bits CCLR1 and CCLR0 in TCR to specify counter clearing by compare match/input capture.
[4] Set bits CCLR1 and CCLR0 in TCR to designate synchronous clearing for the counter clearing source.
[5] Set the STR bit in TSTR to 1 to start the count operation.
Figure 12.19 Example of Synchronous Operation Setting Procedure
Rev. 4.00 Mar. 15, 2006 Page 198 of 556
REJ09B0026-0400
Section 12 Timer Z
Figure 12.20 shows an example of synchronous operation. In this example, synchronous operation
has been selected, FTIOB0 and FTIOB1 have been designated for PWM mode, GRA_0 compare
match has been set as the channel 0 counter clearing source, and synchronous clearing has been set
for the channel 1 counter clearing source. In addition, the same input clock has been set as the
counter input clock for channel 0 and channel 1. Two-phase PWM waveforms are output from
pins FTIOB0 and FTIOB1. At this time, synchronous presetting and synchronous operation by
GRA_0 compare match are performed by TCNT counters.
For details on PWM mode, see section 12.4.5, PWM Mode.
TCNT values
Synchronous clearing by GRA_0 compare match
GRA_0
GRA_1
GRB_0
GRB_1
H'0000
Time
FTIOB0
FTIOB1
Figure 12.20 Example of Synchronous Operation
Rev. 4.00 Mar. 15, 2006 Page 199 of 556
REJ09B0026-0400
Section 12 Timer Z
12.4.5
PWM Mode
In PWM mode, PWM waveforms are output from the FTIOB, FTIOC, and FTIOD output pins
with GRA as a cycle register and GRB, GRC, and GRD as duty registers. The initial output level
of the corresponding pin depends on the setting values of TOCR and POCR. Table 12.3 shows an
example of the initial output level of the FTIOB0 pin.
The output level is determined by the POLB to POLD bits corresponding to POCR. When POLB
is 0, the FTIOB output pin is set to 0 by compare match B and set to 1 by compare match A. When
POLB is 1, the FTIOB output pin is set to 1 by compare match B and cleared to 0 by compare
match A. In PWM mode, maximum 6-phase PWM outputs are possible.
Figure 12.21 shows an example of the PWM mode setting procedure.
Table 12.3 Initial Output Level of FTIOB0 Pin
TOB0
POLB
Initial Output Level
0
0
1
0
1
0
1
0
0
1
1
1
Rev. 4.00 Mar. 15, 2006 Page 200 of 556
REJ09B0026-0400
Section 12 Timer Z
PWM mode
Select counter clock
[1]
Select counter clearing source
[2]
Set PWM mode
[3]
Set initial output level
[4]
Select output level
[5]
Set GR
[6]
Enable waveform output
[7]
Start counter operation
[8]
[1] Select the counter clock with bits TPSC2
to TOSC0 in TCR. When an external
clock is selected, select the external
clock edge with bits CKEG1 and CKEG0
in TCR.
[2] Use bits CCLR1 and CCLR0 in TCR to
select the counter clearing source.
[3] Select the PWM mode with bits PWMB0
to PWMD0 and PWMB1 to PWMD1 in
TPMR.
[4] Set the initial output value with bits
TOB0 to TOD0 and TOB1 to TOD1 in
TOCR.
[5] Set the output level with bits POLB to
POLD in POCR.
[6] Set the cycle in GRA, and set the duty in
the other GR.
[7] Enable or disable the timer output by
TOER.
[8] Set the STR bit in TSTR to 1 and start
the counter operation.
<PWM mode>
Figure 12.21 Example of PWM Mode Setting Procedure
Rev. 4.00 Mar. 15, 2006 Page 201 of 556
REJ09B0026-0400
Section 12 Timer Z
Figure 12.22 shows an example of operation in PWM mode. The output signals go to 1 and TCNT
is reset at compare match A, and the output signals go to 0 at compare match B, C, and D (TOB,
TOC, and TOD = 0, POLB, POLC, and POLD = 0).
Counter cleared by GRA compare match
TCNT value
GRA
GRB
GRC
GRD
H'0000
Time
FTIOB
FTIOC
FTIOD
Figure 12.22 Example of PWM Mode Operation (1)
Rev. 4.00 Mar. 15, 2006 Page 202 of 556
REJ09B0026-0400
Section 12 Timer Z
Figure 12.23 shows another example of operation in PWM mode. The output signals go to 0 and
TCNT is reset at compare match A, and the output signals go to 1 at compare match B, C, and D
(TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 1).
Counter cleared by GRA compare match
TCNT value
GRA
GRB
GRC
GRD
H'0000
Time
FTIOB
FTIOC
FTIOD
Figure 12.23 Example of PWM Mode Operation (2)
Figures 12.24 (when TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 0) and 12.25 (when
TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 1) show examples of the output of PWM
waveforms with duty cycles of 0% and 100% in PWM mode.
Rev. 4.00 Mar. 15, 2006 Page 203 of 556
REJ09B0026-0400
Section 12 Timer Z
TCNT value
GRB rewritten
GRA
GRB
rewritten
GRB
Time
H'0000
0% duty
FTIOB
TCNT value
GRB rewritten
When cycle register and duty register compare matches
occur simultaneously, duty register compare match has
priority.
GRA
GRB rewritten
GRB
rewritten
GRB
H'0000
Time
FTIOB
100% duty
When cycle register and duty register compare matches
occur simultaneously, duty register compare match has
priority.
TCNT value
GRB rewritten
GRB rewritten
GRA
GRB rewritten
GRB
H'0000
Time
FTIOB
100% duty
0% duty
Figure 12.24 Example of PWM Mode Operation (3)
Rev. 4.00 Mar. 15, 2006 Page 204 of 556
REJ09B0026-0400
Section 12 Timer Z
TCNT value
GRB rewritten
GRA
GRB
rewritten
GRB
H'0000
Time
FTIOB
0% duty
TCNT value
GRB rewritten
When cycle register and duty register compare matches
occur simultaneously, duty register compare match has
priority.
GRA
GRB rewritten
GRB
rewritten
GRB
Time
H'0000
100% duty
FTIOB
When cycle register and duty register compare matches
occur simultaneously, duty register compare match has
priority.
TCNT value
GRB rewritten
GRB rewritten
GRA
GRB rewritten
GRB
Time
H'0000
FTIOB
100% duty
0% duty
Figure 12.25 Example of PWM Mode Operation (4)
Rev. 4.00 Mar. 15, 2006 Page 205 of 556
REJ09B0026-0400
Section 12 Timer Z
12.4.6
Reset Synchronous PWM Mode
Three normal- and counter-phase PWM waveforms are output by combining channels 0 and 1 that
one of changing points of waveforms will be common.
In reset synchronous PWM mode, the FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1 pins become
PWM-output pins automatically. TCNT_0 performs an increment operation. Tables 12.4 and 12.5
show the PWM-output pins used and the register settings, respectively.
Figure 12.26 shows the example of reset synchronous PWM mode setting procedure.
Table 12.4 Output Pins in Reset Synchronous PWM Mode
Channel
Pin Name
I/O
Pin Function
0
FTIOC0
Output
Toggle output in synchronous with PWM cycle
0
FTIOB0
Output
PWM output 1
0
FTIOD0
Output
PWM output 1 (counter-phase waveform of PWM output 1)
1
FTIOA1
Output
PWM output 2
1
FTIOC1
Output
PWM output 2 (counter-phase waveform of PWM output 2)
1
FTIOB1
Output
PWM output 3
1
FTIOD1
Output
PWM output 3 (counter-phase waveform of PWM output 3)
Table 12.5 Register Settings in Reset Synchronous PWM Mode
Register
Description
TCNT_0
Initial setting of H'0000
TCNT_1
Not used (independently operates)
GRA_0
Sets counter cycle of TCNT_0
GRB_0
Set a changing point of the PWM waveform output from pins FTIOB0 and
FTIOD0.
GRA_1
Set a changing point of the PWM waveform output from pins FTIOA1 and
FTIOC1.
GRB_1
Set a changing point of the PWM waveform output from pins FTIOB1 and
FTIOD1.
Rev. 4.00 Mar. 15, 2006 Page 206 of 556
REJ09B0026-0400
Section 12 Timer Z
Reset synchronous PWM mode
Stop counter operation
[1]
Select counter clock
[2]
Select counter clearing source
[3]
Set reset synchronous PWM mode
[4]
Initialize the output pin
[5]
Set TCNT
[6]
Set GR
[7]
Enable waveform output
[8]
Start counter operation
[9]
[1] Clear bit STR0 in TSTR to 0 and stop the
counter operation of TCNT_0. Set reset
synchronous PWM mode after TCNT_0
stops.
[2] Select the counter clock with bits TPSC2
to TOSC0 in TCR. When an external
clock is selected, select the external clock
edge with bits CKEG1 and CKEG0 in
TCR.
[3] Use bits CCLR1 and CCLR0 in TCR to
select counter clearing source GRA_0.
[4] Select the reset synchronous PWM mode
with bits CMD1 and CMD0 in TFCR.
FTIOB0 to FTIOD0 and FTIOA1 to
FTIOD1 become PWM output pins
automatically.
[5] Set H'00 to TOCR.
[6] Set TCNT_0 as H'0000. TCNT1 does not
need to be set.
[7] GRA_0 is a cycle register. Set a cycle for
GRA_0. Set the changing point timing of
the PWM output waveform for GRB_0,
GRA_1, and GRB_1.
[8] Enable or disable the timer output by
TOER.
[9] Set the STR bit in TSTR to 1 and start the
counter operation.
<Reset synchronous PWM mode>
Figure 12.26 Example of Reset Synchronous PWM Mode Setting Procedure
Rev. 4.00 Mar. 15, 2006 Page 207 of 556
REJ09B0026-0400
Section 12 Timer Z
Figures 12.27 and 12.28 show examples of operation in reset synchronous PWM mode.
Counter cleared by GRA compare match
TCNT value
GRA_0
GRB_0
GRA_1
GRB_1
H'0000
Time
FTIOB0
FTIOD0
FTIOA1
FTIOC1
FTIOB1
FTIOD1
FTIOC0
Figure 12.27 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 1)
Rev. 4.00 Mar. 15, 2006 Page 208 of 556
REJ09B0026-0400
Section 12 Timer Z
Counter cleared by GRA compare match
TCNT value
GRA_0
GRB_0
GRA_1
GRB_1
H'0000
Time
FTIOB0
FTIOD0
FTIOA1
FTIOC1
FTIOB1
FTIOD1
FTIOC0
Figure 12.28 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 0)
In reset synchronous PWM mode, TCNT_0 and TCNT_1 perform increment and independent
operations, respectively. However, GRA_1 and GRB_1 are separated from TCNT_1. When a
compare match occurs between TCNT_0 and GRA_0, a counter is cleared and an increment
operation is restarted from H'0000.
The PWM pin outputs 0 or 1 whenever a compare match between GRB_0, GRA_1, GRB_1 and
TCNT_0 or counter clearing occur.
For details on operations when reset synchronous PWM mode and buffer operation are
simultaneously set, refer to section 12.4.8, Buffer Operation.
Rev. 4.00 Mar. 15, 2006 Page 209 of 556
REJ09B0026-0400
Section 12 Timer Z
12.4.7
Complementary PWM Mode
Three PWM waveforms for non-overlapped normal and counter phases are output by combining
channels 0 and 1.
In complementary PWM mode, the FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1 pins become
PWM-output pins automatically. TCNT_0 and TCNT_1 perform an increment or decrement
operation. Tables 12.6 and 12.7 show the output pins and register settings in complementary PWM
mode, respectively.
Figure 12.29 shows the example of complementary PWM mode setting procedure.
Table 12.6 Output Pins in Complementary PWM Mode
Channel
Pin Name
I/O
Pin Function
0
FTIOC0
Output
Toggle output in synchronous with PWM cycle
0
FTIOB0
Output
PWM output 1
0
FTIOD0
Output
PWM output 1 (counter-phase waveform non-overlapped
with PWM output 1)
1
FTIOA1
Output
PWM output 2
1
FTIOC1
Output
PWM output 2 (counter-phase waveform non-overlapped
with PWM output 2)
1
FTIOB1
Output
PWM output 3
1
FTIOD1
Output
PWM output 3 (counter-phase waveform non-overlapped
with PWM output 3)
Rev. 4.00 Mar. 15, 2006 Page 210 of 556
REJ09B0026-0400
Section 12 Timer Z
Table 12.7 Register Settings in Complementary PWM Mode
Register
Description
TCNT_0
Initial setting of non-overlapped periods (non-overlapped periods are differences
with TCNT_1)
TCNT_1
Initial setting of H'0000
GRA_0
Sets (upper limit value – 1) of TCNT_0
GRB_0
Set a changing point of the PWM waveform output from pins FTIOB0 and
FTIOD0.
GRA_1
Set a changing point of the PWM waveform output from pins FTIOA1 and
FTIOC1.
GRB_1
Set a changing point of the PWM waveform output from pins FTIOB1 and
FTIOD1.
Rev. 4.00 Mar. 15, 2006 Page 211 of 556
REJ09B0026-0400
Section 12 Timer Z
Complementary PWM mode
Stop counter operation
[1]
Initialize output pin
[2]
Select counter clock
[3]
Set complementary
PWM mode
[4]
Initialize output pin
[5]
Set TCNT
[6]
Set GR
[7]
Enable waveform output
[8]
Start counter operation
[9]
[1] Clear bits STR0 and STR1 in TSTR to 0,
and stop the counter operation of
TCNT_0. Stop TCNT_0 and TCNT_1 and
set complementary PWM mode.
[2] Write H'00 to TOCR.
[3] Use bits TPSC2 to TPSC0 in TCR to
select the same counter clock for channels
0 and 1. When an external clock is
selected, select the edge of the external
clock by bits CKEG1 and CKEG0 in TCR.
Do not use bits CCLR1 and CCLR0 in
TCR to clear the counter.
[4] Use bits CMD1 and CMD0 in TFCR to set
complementary PWM mode. FTIOB0 to
FTIOD0 and FTIOA1 to FTIOD1
automatically become PWM output pins.
[5] Set H'00 to TOCR.
[6] TCNT_1 must be H'0000. Set a nonoverlapped period to TCNT_0.
[7] GRA_0 is a cycle register. Set the cycle to
GRA_0. Set the timing to change the
PWM output waveform to GRB_0, GRA_1,
and GRB_1. Note that the timing must be
set within the range of compare match
carried out for TCNT_0 and TCNT_1.
For GR settings, see Setting GR Value in
Complementary PWM Mode in section
12.4.7, Complementary PWM Mode.
[8] Use TOER to enable or disable the timer
output.
[9] Set the STR0 and STR1 bits in TSTR to 1
to start the count operation.
<Complementary PWM mode>
Note: To re-enter complementary PWM mode, first, enter a mode other than the complementary
PWM mode. After that, repeat the setting procedures from step [1].
For settings of waveform outputs with a duty cycle of 0% and 100%, see Examples of
Complementary PWM Mode Operation and Setting GR Value in Complementary PWM
Mode in section 12.4.7, Complementary PWM Mode.
Figure 12.29 Example of Complementary PWM Mode Setting Procedure
Rev. 4.00 Mar. 15, 2006 Page 212 of 556
REJ09B0026-0400
Section 12 Timer Z
Canceling Procedure of Complementary PWM Mode: Figure 12.30 shows the complementary
PWM mode canceling procedure.
Complementary PWM mode
Stop counter operation
[1]
Cancel complementary
PWM mode
[2]
[1] Clear bit CMD1 in TFCR to 0, and set
channels 0 and 1 to normal operation.
[2] After setting channels 0 and 1 to normal
operation, clear bits STR0 and STR1 in
TSTR to 0 and stop TCNT0 and TCNT1.
<Normal operation>
Figure 12.30 Canceling Procedure of Complementary PWM Mode
Rev. 4.00 Mar. 15, 2006 Page 213 of 556
REJ09B0026-0400
Section 12 Timer Z
Examples of Complementary PWM Mode Operation: Figure 12.31 shows an example of
complementary PWM mode operation. In complementary PWM mode, TCNT_0 and TCNT_1
perform an increment or decrement operation. When TCNT_0 and GRA_0 are compared and their
contents match, the counter is decremented, and when TCNT_1 underflows, the counter is
incremented. In GRA_0, GRA_1, and GRB_1, compare match is carried out in the order of
TCNT_0 → TCNT_1 → TCNT_1 → TCNT_0 and PWM waveform is output, during one cycle of
an up/down counter. In this mode, the initial setting will be TCNT_0 > TCNT_1.
TCNT_0 and GRA_0 are compared and their contents match
TCNT values
GRA_0
GRB_0
GRA_1
GRB_1
H'0000
Time
FTIOB0
FTIOD0
FTIOA1
FTIOC1
FTIOB1
FTIOD1
FTIOC0
Figure 12.31 Example of Complementary PWM Mode Operation (1)
Rev. 4.00 Mar. 15, 2006 Page 214 of 556
REJ09B0026-0400
Section 12 Timer Z
Figure 12.32 (1) and (2) show examples of PWM waveform output with 0% duty and 100% duty
in complementary PWM mode (for one phase).
•
TPSC2 = TPSC1 = TPSC0 = 0
Set GRB_0 to H'0000 or a value equal to or more than GRA_0, and the waveform with a duty
cycle of 0% and 100% can be output. When buffer operation is used together, the duty cycles
can easily be changed, including the above settings, during operation. For details on buffer
operation, see section 12.4.8, Buffer Operation.
• Other than TPSC2 = TPSC1 = TPSC0 = 0
Set GRB_0 to satisfy the following expression: GRA_0 + 1 < GRB_0 < H'FFFF, and the
waveform with a duty cycle of 0% and 100% can be output. For details on 0%- and 100%-duty
cycle waveform output, see Setting GR Value in Complementary PWM Mode: C, Outputting a
waveform with a duty cycle of 0% and 100% in section 12.4.7, Complementary PWM Mode.
Rev. 4.00 Mar. 15, 2006 Page 215 of 556
REJ09B0026-0400
Section 12 Timer Z
TCNT values
GRA0
GRB0
H'0000
Time
FTIOB0
FTIOD0
0% duty
(a) When duty is 0%
TCNT values
GRA0
GRB0
H'0000
Time
FTIOB0
FTIOD0
100% duty
(b) When duty is 100%
Figure 12.32 (1) Example of Complementary PWM Mode Operation
(TPSC2 = TPSC1 = TPSC0 = 0) (2)
Rev. 4.00 Mar. 15, 2006 Page 216 of 556
REJ09B0026-0400
Section 12 Timer Z
TCNT values
GRA0
GRB0
H'0000
Time
FTIOB0
FTIOD0
0% duty
(a) When duty is 0%
TCNT values
GRA0
GRB0
H'0000
Time
FTIOB0
FTIOD0
100% duty
(b) When duty is 100%
Figure 12.32 (2) Example of Complementary PWM Mode Operation
(Other than TPSC2 = TPSC1 = TPSC0) (3)
Rev. 4.00 Mar. 15, 2006 Page 217 of 556
REJ09B0026-0400
Section 12 Timer Z
In complementary PWM mode, when the counter switches from up-counter to down-counter or
vice versa, TCNT_0 and TCNT_1 overshoots or undershoots, respectively. In this case, the
conditions to set the IMFA flag in channel 0 and the UDF flag in channel 1 differ from usual
settings. Also, the transfer conditions in buffer operation differ from usual settings. Such timings
are shown in figures 12.33 and 12.34.
TCNT
N-1
N
N
N+1
N-1
N
GRA_0
IMFA
Set to 1
Flag is not set
Buffer transfer signal
GR
Transferred
to buffer
Not transferred
to buffer
Figure 12.33 Timing of Overshooting
TCNT
H'0001
H'0000
H'FFFF
H'0000
Flag is not set
UDF
Set to 1
Buffer transfer signal
GR
Transferred
to buffer
Not transferred
to buffer
Figure 12.34 Timing of Undershooting
Rev. 4.00 Mar. 15, 2006 Page 218 of 556
REJ09B0026-0400
H'0001
Section 12 Timer Z
When the counter is incremented or decremented, the IMFA flag of channel 0 is set to 1, and when
the register is underflowed, the UDF flag of channel 0 is set to 1. After buffer operation has been
designated for BR, BR is transferred to GR when the counter is incremented by compare match
A0 or when TCNT_1 is underflowed.
If the φ or φ/2 clock is selected by TPSC2 to TPSC0 bits, the OVF flag is not set to 1 at the timing
that the counter value changes from H'FFFF to H'0000. If the φ/4 or φ/8 clock is selected by
TPSC2 to TPSC0 bits, the OVF flag is set to 1.
Setting GR Value in Complementary PWM Mode: To set GR or modify GR during operation
in complementary PWM mode, refer to the following notes.
1. Initial value
 When other than TPSC2 = TPSC1 = TPSC0 = 0, the GRA_0 value must be equal to
H'FFFC or less. When TPSC2 = TPSC1 = TPSC0 = 0, the GRA_0 value can be set to
H'FFFF or less.
 H'0000 to T – 1 (T: Initial value of TCNT0) must not be set for the initial value.
 GRA_0 – (T – 1) or more must not be set for the initial value.
 When using buffer operation, the same values must be set in the buffer registers and
corresponding general registers.
2. Modifying the setting value
 Writing to GR directly must be performed while the TCNT_1 and TCNT_0 values should
satisfy the following expression: H'0000 ≤ TCNT_1 < previous GR value, and previous GR
value < TCNT_0 ≤ GRA_0. Otherwise, a waveform is not output correctly. For details on
outputting a waveform with a duty cycle of 0% and 100%, see 3., Outputting a waveform
with a duty cycle of 0% and 100%.
 Do not write the following values to GR directly. When writing the values, a waveform is
not output correctly.
H'0000 ≤ GR ≤ T – 1 and GRA_0 – (T – 1) ≤ GR < GRA_0 when TPSC2 = TPSC1 =
TPSC0 = 0
H'0000 < GR ≤ T – 1 and GRA_0 – ( T – 1) ≤ GR < GRA_0 + 1 when TPSC2 = TPSC1 =
TPSC0 = 0
 Do not change settings of GRA_0 during operation.
3. Outputting a waveform with a duty cycle of 0% and 100%
A. When buffer operation is not used and TPSC2 = TPSC1 = TPSC0 = 0.
• Write H'0000 or a value equal to or more than the GRA_0 value to GR directly at the
timing shown below.
• To output a 0%-duty cycle waveform, write a value equal to or more than the GRA_0
value while H'0000 ≤ TCNT_1 < previous GR value.
Rev. 4.00 Mar. 15, 2006 Page 219 of 556
REJ09B0026-0400
Section 12 Timer Z
• To output a 100%-duty cycle waveform, write H'0000 while previous GR value <
TCNT_0 ≤ GRA_0.
• To change duty cycles while a waveform with a duty cycle of 0% or 100% is being
output, make sure the following procedure.
• To change duty cycles while a 0%-duty cycle waveform is being output, write to GR
while H'0000 ≤TCNT_1 < previous GR value.
• To change duty cycles while a 100%-duty cycle waveform is being output, write to GR
while previous GR value< TCNT_0 ≤ GRA_0.
Note that changing from a 0%-duty cycle waveform to a 100%-duty cycle waveform
B. When buffer operation is used and TPSC2 = TPSC1 = TPSC0 = 0.
Write H'0000 or a value equal to or more than the GRA_0 value to the buffer register.
• To output a 0%-duty cycle waveform, write a value equal to or more than the
GRA_0value to the buffer register.
• To output a 100%-duty cycle waveform, write H'0000 to the buffer register.
For details on buffer operation, see section 12.4.8, Buffer Operation.
C. When buffer operation is not used and other than TPSC2 = TPSC1 = TPSC0 = 0.
Write a value which satisfies GRA_0 + 1 < GR < H'FFFF to GR directly at the timing
shown below.
• To output a 0%-duty cycle waveform, write the value while H'0000 is TCNT_1 <
previous GR value
• To output a 100%-duty cycle waveform, write the value while previous GR value <
TCNT_0 ≤ GRA_0.
To change duty cycles while a waveform with a duty cycle of 0% and 100% is being output,
the following procedure must be followed.
• To change duty cycles while a 0%-duty cycle waveform is being output, write to GR
while H'0000 ≤ TCNT_1 < previous GR value.
• To change duty cycles while a 100%-duty cycle waveform is being output, write to GR
while previous GR value< TCNT_0 ≤ GRA_0.
Note that changing from a 0%-duty cycle waveform to a 100%-duty cycle waveform
and vice versa is not possible.
D. Buffer operation is used and other than TPSC2 = TPSC1 = TPSC0 = 0
Write a value which satisfies GRA_0 + 1 < GR < H'FFFF to the buffer register. A
waveform with a duty cycle of 0% can be output. However, a waveform with a duty cycle
of 100% cannot be output using the buffer operation. Also, the buffer operation cannot be
used to change duty cycles while a waveform with a duty cycle of 100% is being output.
For details on buffer operation, see section 12.4.8, Buffer Operation.
Rev. 4.00 Mar. 15, 2006 Page 220 of 556
REJ09B0026-0400
Section 12 Timer Z
12.4.8
Buffer Operation
Buffer operation differs depending on whether GR has been designated for an input capture
register or an output compare register, or in reset synchronous PWM mode or complementary
PWM mode.
Table 12.8 shows the register combinations used in buffer operation.
Table 12.8 Register Combinations in Buffer Operation
General Register
Buffer Register
GRA
GRC
GRB
GRD
When GR is Output Compare Register: When a compare match occurs, the value in the buffer
register of the corresponding channel is transferred to the general register.
This operation is illustrated in figure 12.35.
Compare match signal
Buffer register
General
register
Comparator
TCNT
Figure 12.35 Compare Match Buffer Operation
When GR is Input Capture Register: When an input capture occurs, the value in TCNT is
transferred to the general register and the value previously stored in the general register is
transferred to the buffer register.
This operation is illustrated in figure 12.36.
Input capture
signal
Buffer register
General
register
TCNT
Figure 12.36 Input Capture Buffer Operation
Rev. 4.00 Mar. 15, 2006 Page 221 of 556
REJ09B0026-0400
Section 12 Timer Z
Complementary PWM Mode: When the counter switches from counting up to counting down or
vice versa, the value of the buffer register is transferred to the general register. Here, the value of
the buffer register is transferred to the general register in the following timing:
1. When TCNT_0 and GRA_0 are compared and their contents match
2. When TCNT_1 underflows
Reset Synchronous PWM Mode: The value of the buffer register is transferred from compare
match A0 to the general register.
Example of Buffer Operation Setting Procedure: Figure 12.37 shows an example of the buffer
operation setting procedure.
Buffer operation
Select GR function
[1]
Set buffer operation
[2]
Start count operation
[3]
[1] Designate GR as an input capture register
or output compare register by means of
TIOR.
[2] Designate GR for buffer operation with bits
BFD1, BFC1, BFD0, or BFC0 in TMDR.
[3] Set the STR bit in TSTR to 1 to start the
count operation of TCNT.
<Buffer operation>
Figure 12.37 Example of Buffer Operation Setting Procedure
Rev. 4.00 Mar. 15, 2006 Page 222 of 556
REJ09B0026-0400
Section 12 Timer Z
Examples of Buffer Operation: Figure 12.38 shows an operation example in which GRA has
been designated as an output compare register, and buffer operation has been designated for GRA
and GRC.
This is an example of TCNT operating as a periodic counter cleared by compare match B.
Pins FTIOA and FTIOB are set for toggle output by compare match A and B.
As buffer operation has been set, when compare match A occurs, the FTIOA pin performs toggle
outputs and the value in buffer register is simultaneously transferred to the general register. This
operation is repeated each time that compare match A occurs.
The timing to transfer data is shown in figure 12.39.
Counter is cleared by GBR compare match
TCNT value
GRB
H'0250
H'0200
H'0100
Time
H'0000
GRC
H'0200
H'0100
GRA
H'0250
H'0200
H'0200
H'0200
H'0100
FTIOB
FTIOA
Compare match A
Figure 12.38 Example of Buffer Operation (1)
(Buffer Operation for Output Compare Register)
Rev. 4.00 Mar. 15, 2006 Page 223 of 556
REJ09B0026-0400
Section 12 Timer Z
φ
n
TCNT
n+1
Compare match
signal
Buffer transfer
signal
N
GRC
n
GRA
N
Figure 12.39 Example of Compare Match Timing for Buffer Operation
Figure 12.40 shows an operation example in which GRA has been designated as an input capture
register, and buffer operation has been designated for GRA and GRC.
Counter clearing by input capture B has been set for TCNT, and falling edges have been selected
as the FIOCB pin input capture input edge. And both rising and falling edges have been selected
as the FIOCA pin input capture input edge.
As buffer operation has been set, when the TCNT value is stored in GRA upon the occurrence of
input capture A, the value previously stored in GRA is simultaneously transferred to GRC. The
transfer timing is shown in figure 12.41.
Rev. 4.00 Mar. 15, 2006 Page 224 of 556
REJ09B0026-0400
Section 12 Timer Z
Counter is cleared by the input capture B
TCNT value
H'0180
H'0160
H'0005
H'0000
Time
FTIOB
FTIOA
GRA
H'0005
GRC
H'0160
H'0005
GRB
H'0160
H'0180
Input capture A
Figure 12.40 Example of Buffer Operation (2)
(Buffer Operation for Input Capture Register)
Rev. 4.00 Mar. 15, 2006 Page 225 of 556
REJ09B0026-0400
Section 12 Timer Z
φ
FTIO pin
Input capture
signal
TCNT
n
n+1
N
GRA
M
n
n
N
GRC
m
M
M
n
Figure 12.41 Input Capture Timing of Buffer Operation
Rev. 4.00 Mar. 15, 2006 Page 226 of 556
REJ09B0026-0400
N+1
Section 12 Timer Z
Figures 12.42 and 12.43 show the operation examples when buffer operation has been designated
for GRB_0 and GRD_0 in complementary PWM mode. These are examples when a PWM
waveform of 0% duty is created by using the buffer operation and performing GRD_0 ≥ GRA_0.
Data is transferred from GRD_0 to GRB_0 according to the settings of CMD_0 and CMD_1 when
TCNT_0 and GRA_0 are compared and their contents match or when TCNT_1 underflows.
However, when GRD_0 ≥ GRA_0, data is transferred from GRD_0 to GRB_0 when TCNT_1
underflows regardless of the setting of CMD_0 and CMD_1. When GRD_0 = H'0000, data is
transferred from GRD_0 to GRB_0 when TCNT_0 and GRA_0 are compared and their contents
match regardless of the settings of CMD_0 and CMD_1.
TCNT values
GRB_0 (When restored, data will be transferred
to the saved location regardless of the
CMD1 and CMD0 values)
TCNT_0
GRA_0
TCNT_1
H'0999
H'0000
Time
GRD_0
H'0999
GRB_0
H'0999
H'1FFF
H'0999
H'1FFF
H'0999
H'0999
FTIOB0
FTIOD0
Figure 12.42 Buffer Operation (3)
(Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1)
Rev. 4.00 Mar. 15, 2006 Page 227 of 556
REJ09B0026-0400
Section 12 Timer Z
GRB_0 (When restored, data will be transferred
to the saved location regardless of the
CMD1 and CMD0 values)
TCNT values
TCNT_0
GRA_0
TCNT_1
H'0999
H'0000
Time
GRB_0
GRD_0
H'0999
GRB_0
H'0999
H'0000
H'0999
H'0000
H'0999
FTIOC0
FTIOD0
Figure 12.43 Buffer Operation (4)
(Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1)
Rev. 4.00 Mar. 15, 2006 Page 228 of 556
REJ09B0026-0400
Section 12 Timer Z
12.4.9
Timer Z Output Timing
The outputs of channels 0 and 1 can be disabled or inverted by the settings of TOER and TOCR
and the external level.
Output Disable/Enable Timing of Timer Z by TOER: Setting the master enable bit in TOER to
1 disables the output of timer Z. By setting the PCR and PDR of the corresponding I/O port
beforehand, any value can be output. Figure 12.44 shows the timing to enable or disable the output
of timer Z by TOER.
T1
T2
φ
Address bus
TOER address
TOER
Timer Z
output pin
I/O port
Timer output
Timer Z output
I/O port
Figure 12.44 Example of Output Disable Timing of Timer Z by Writing to TOER
Rev. 4.00 Mar. 15, 2006 Page 229 of 556
REJ09B0026-0400
Section 12 Timer Z
Output Disable Timing of Timer Z by External Trigger: When P54/WKP4 is set as a WKP4
input pin, and low level is input to WKP4, the master enable bit in TOER is set to 1 and the output
of timer Z will be disabled.
φ
WKP4
TOER
Timer Z
output pin
H'FF
N
Timer Z output
I/O port
Timer Z output
I/O port
Figure 12.45 Example of Output Disable Timing of Timer Z by External Trigger
Output Inverse Timing by TFCR: The output level can be inverted by inverting the OLS1 and
OLS0 bits in TFCR in reset synchronous PWM mode or complementary PWM mode. Figure
12.46 shows the timing.
T1
T2
φ
Address bus
TOER address
TFCR
Timer Z
output pin
Inverted
Figure 12.46 Example of Output Inverse Timing of Timer Z by Writing to TFCR
Rev. 4.00 Mar. 15, 2006 Page 230 of 556
REJ09B0026-0400
Section 12 Timer Z
Output Inverse Timing by POCR: The output level can be inverted by inverting the POLD,
POLC, and POLB bits in POCR in PWM mode. Figure 12.47 shows the timing.
T1
T2
φ
Address bus
POCR address
TFCR
Timer Z
output pin
Inverted
Figure 12.47 Example of Output Inverse Timing of Timer Z by Writing to POCR
Rev. 4.00 Mar. 15, 2006 Page 231 of 556
REJ09B0026-0400
Section 12 Timer Z
12.5
Interrupts
There are three kinds of timer Z interrupt sources; input capture/compare match, overflow, and
underflow. An interrupt is requested when the corresponding interrupt request flag is set to 1 while
the corresponding interrupt enable bit is set to 1.
12.5.1
Status Flag Set Timing
IMF Flag Set Timing: The IMF flag is set to 1 by the compare match signal that is generated
when the GR matches with the TCNT. The compare match signal is generated at the last state of
matching (timing to update the counter value when the GR and TCNT match). Therefore, when
the TCNT and GR matches, the compare match signal will not be generated until the TCNT input
clock is generated. Figure 12.48 shows the timing to set the IMF flag.
φ
TCNT input clock
TCNT
N
N+1
N
GR
Compare match
signal
IMF
ITMZ
Figure 12.48 IMF Flag Set Timing when Compare Match Occurs
Rev. 4.00 Mar. 15, 2006 Page 232 of 556
REJ09B0026-0400
Section 12 Timer Z
IMF Flag Set Timing at Input Capture: When an input capture signal is generated, the IMF flag
is set to 1 and the value of TCNT is simultaneously transferred to corresponding GR. Figure 12.49
shows the timing.
φ
Input capture
signal
IMF
TCNT
N
GR
N
ITMZ
Figure 12.49 IMF Flag Set Timing at Input Capture
Overflow Flag (OVF) Set Timing: The overflow flag is set to 1 when the TCNT overflows.
Figure 12.50 shows the timing.
φ
TCNT
H'FFFF
H'0000
Overflow
signal
OVF
ITMZ
Figure 12.50 OVF Flag Set Timing
Rev. 4.00 Mar. 15, 2006 Page 233 of 556
REJ09B0026-0400
Section 12 Timer Z
12.5.2
Status Flag Clearing Timing
The status flag can be cleared by writing 0 after reading 1 from the CPU. Figure 12.51 shows the
timing in this case.
φ
Address
TSR address
WTSR
(internal write signal)
IMF, OVF
ITMZ
Figure 12.51 Status Flag Clearing Timing
Rev. 4.00 Mar. 15, 2006 Page 234 of 556
REJ09B0026-0400
Section 12 Timer Z
12.6
Usage Notes
Contention between TCNT Write and Clear Operations: If a counter clear signal is generated
in the T2 state of a TCNT write cycle, TCNT clearing has priority and the TCNT write is not
performed. Figure 12.52 shows the timing in this case.
TCNT write cycle
T1
T2
φ
TCNT address
WTCNT
(internal write signal)
Counter clear signal
TCNT
N
H'0000
Clearing has priority.
Figure 12.52 Contention between TCNT Write and Clear Operations
Rev. 4.00 Mar. 15, 2006 Page 235 of 556
REJ09B0026-0400
Section 12 Timer Z
Contention between TCNT Write and Increment Operations: If incrementation is done in the
T2 state of a TCNT write cycle, TCNT writing has priority. Figure 12.53 shows the timing in this
case.
TCNT write cycle
T1
T2
φ
TCNT address
WTCNT
(internal write signal)
TCNT input clock
TCNT
M
N
TCNT write data
Figure 12.53 Contention between TCNT Write and Increment Operations
Rev. 4.00 Mar. 15, 2006 Page 236 of 556
REJ09B0026-0400
Section 12 Timer Z
Contention between GR Write and Compare Match: If a compare match occurs in the T2 state
of a GR write cycle, GR write has priority and the compare match signal is disabled. Figure 12.54
shows the timing in this case.
GR write cycle
T1
T2
φ
GR address
WGR
(internal write signal)
TCNT
N
GR
N
N+1
M
GR write data
Compare match
signal
Disabled
Figure 12.54 Contention between GR Write and Compare Match
Rev. 4.00 Mar. 15, 2006 Page 237 of 556
REJ09B0026-0400
Section 12 Timer Z
Contention between TCNT Write and Overflow/Underflow: If overflow/underflow occurs in
the T2 state of a TCNT write cycle, TCNT write has priority without an increment operation. At
this time, the OVF flag is set to 1. Figure 12.55 shows the timing in this case.
TCNT write cycle
T1
T2
φ
TCNT address
WTCNT
(internal write signal)
TCNT input clock
Overflow signal
TCNT
H'FFFF
M
TCNT write data
OVF
Figure 12.55 Contention between TCNT Write and Overflow
Rev. 4.00 Mar. 15, 2006 Page 238 of 556
REJ09B0026-0400
Section 12 Timer Z
Contention between GR Read and Input Capture: If an input capture signal is generated in the
T1 state of a GR read cycle, the data that is read will be transferred before input capture transfer.
Figure 12.56 shows the timing in this case.
GR read cycle
T1
T2
φ
GR address
Internal read
signal
Input capture
signal
GR
Internal data
bus
X
M
X
Figure 12.56 Contention between GR Read and Input Capture
Rev. 4.00 Mar. 15, 2006 Page 239 of 556
REJ09B0026-0400
Section 12 Timer Z
Contention between Count Clearing and Increment Operations by Input Capture: If an input
capture and increment signals are simultaneously generated, count clearing by the input capture
operation has priority without an increment operation. The TCNT contents before clearing counter
are transferred to GR. Figure 12.57 shows the timing in this case.
φ
Input capture signal
Counter clear signal
TCNT input clock
TCNT
N
GR
H'0000
N
Clearing has priority.
Figure 12.57 Contention between Count Clearing and Increment Operations
by Input Capture
Rev. 4.00 Mar. 15, 2006 Page 240 of 556
REJ09B0026-0400
Section 12 Timer Z
Contention between GR Write and Input Capture: If an input capture signal is generated in the
T2 state of a GR write cycle, the input capture operation has priority and the write to GR is not
performed. Figure 12.58 shows the timing in this case.
GR write cycle
T1
T2
φ
Address bus
GR address
WGR
(internal write signal)
Input capture
signal
TCNT
GR
N
M
GR write data
Figure 12.58 Contention between GR Write and Input Capture
Notes on Setting Reset Synchronous PWM Mode/Complementary PWM Mode: When bits
CMD1 and CMD0 in TFCR are set, note the following:
1. Write bits CMD1 and CMD0 while TCNT_1 and TCNT_0 are halted.
2. Changing the settings of reset synchronous PWM mode to complementary PWM mode or vice
versa is disabled. Set reset synchronous PWM mode or complementary PWM mode after the
normal operation (bits CMD1 and CMD0 are cleared to 0) has been set.
Rev. 4.00 Mar. 15, 2006 Page 241 of 556
REJ09B0026-0400
Section 12 Timer Z
Note on Clearing TSR Flag: When a specific flag in TSR is cleared, a combination of the BCLR
or MOV instructions is used to read 1 from the flag and then write 0 to the flag. However, if
another bit is set during this processing, the bit may also be cleared simultaneously. To avoid this,
the following processing that does not use the BCLR instruction must be executed. Note that this
note is only applied to the F-ZTAT version. This problem has already been solved in the mask
ROM version.
Example: When clearing bit 4 (OVF) in TSR
MOV.B @TSR,R0L
MOV.B #B'11101111, R0L
Only the bit to be cleared is 0 and
the other bits are all set to 1.
MOV.B R0L,@TSR
Note on Writing to the TOA0 to TOD0 Bits and the TOA1 to TOD1 Bits in TOCR:
The TOA0 to TOD0 bits and the TOA1 to TOD1 bits in TOCR decide the value of the FTIO pin,
which is output until the first compare match occurs. Once a compare match occurs and this
compare match changes the values of FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 output, the
values of the FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 pin output and the values read from the
TOA0 to TOD0 and TOA1 to TOD1 bits may differ. Moreover, when the writing to TOCR and
the generation of the compare match A0 to D0 and A1 to D1 occur at the same timing, the writing
to TOCR has the priority. Thus, output change due to the compare match is not reflected to the
FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 pins. Therefore, when bit manipulation instruction is
used to write to TOCR, the values of the FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 pin output
may result in an unexpected result. When TOCR is to be written to while compare match is
operating, stop the counter once before accessing to TOCR, read the port 6 state to reflect the
values of FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 output, to TOA0 to TOD0 and TOA1 to
TOD1, and then restart the counter. Figure 12.59 shows an example when the compare match and
the bit manipulation instruction to TOCR occur at the same timing.
Rev. 4.00 Mar. 15, 2006 Page 242 of 556
REJ09B0026-0400
Section 12 Timer Z
TOCR has been set to H'06. Compare match B0 and compare match C0 are used. The FTIOB0 pin is in the 1 output state,
and is set to the toggle output or the 0 output by compare match B0.
When BCLR#2, @TOCR is executed to clear the TOC0 bit (the FTIOC0 signal is low) and compare match B0 occurs
at the same timing as shown below, the H'02 writing to TOCR has priority and compare match B0 does not drive the FTIOB0 signal low;
the FTIOB0 signal remains high.
7
6
5
4
3
2
1
0
TOD1
0
TOC1
0
TOB1
0
TOA1
0
TOD0
0
TOC0
1
TOB0
1
TOA0
0
Bit
TOCR
Set value
BCLR#2, @TOCR
(1) TOCR read operation: Read H'06
(2) Modify operation: Modify H'06 to H'02
(3) Write operation to TOCR: Write H'02
φ
TOCR
write signal
Compare match
signal B0
FTIOB0 pin
Expected output
Remains high because the 1 writing to TOB has priority
Figure 12.59 When Compare Match and Bit Manipulation Instruction to TOCR Occur at
the Same Timing
Rev. 4.00 Mar. 15, 2006 Page 243 of 556
REJ09B0026-0400
Section 12 Timer Z
Rev. 4.00 Mar. 15, 2006 Page 244 of 556
REJ09B0026-0400
Section 13 Watchdog Timer
Section 13 Watchdog Timer
The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a
system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow.
The block diagram of the watchdog timer is shown in figure 13.1.
φ
CLK
TCSRWD
PSS
TCWD
From subtimer
[Legend]
TCSRWD:
TCWD:
PSS:
TMWD:
φw(fw)
Timer control/status register WD
Timer counter WD
Prescaler S
Timer mode register WD
Internal data bus
Internal
oscillator
TMWD
Internal reset
signal
Figure 13.1 Block Diagram of Watchdog Timer
13.1
Features
• Selectable from nine counter input clocks.
Eight internal clock sources (φ/64, φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096, and φ/8192)
or the internal oscillator (WDT and SBT) can be selected as the timer-counter clock. When the
internal oscillator is selected, it can operate as the watchdog timer in any operating mode.
• Reset signal generated on counter overflow
An overflow period of 1 to 256 times the selected clock can be set.
[Legend]
WDT: Watchdog timer
SBT: Subtimer
Rev. 4.00 Mar. 15, 2006 Page 245 of 556
REJ09B0026-0400
Section 13 Watchdog Timer
13.2
Register Descriptions
The watchdog timer has the following registers.
• Timer control/status register WD (TCSRWD)
• Timer counter WD (TCWD)
• Timer mode register WD (TMWD)
13.2.1
Timer Control/Status Register WD (TCSRWD)
TCSRWD performs the TCSRWD and TCWD write control. TCSRWD also controls the
watchdog timer operation and indicates the operating state. TCSRWD must be rewritten by using
the MOV instruction. The bit manipulation instruction cannot be used to change the setting value.
Bit
Bit Name
Initial
Value
R/W
Description
7
B6WI
1
R/W
Bit 6 Write Inhibit
The TCWE bit can be written only when the write value of
the B6WI bit is 0.
This bit is always read as 1.
6
TCWE
0
R/W
Timer Counter WD Write Enable
TCWD can be written when the TCWE bit is set to 1.
When writing data to this bit, the value for bit 7 must be 0.
5
B4WI
1
R/W
Bit 4 Write Inhibit
The TCSRWE bit can be written only when the write
value of the B4WI bit is 0. This bit is always read as 1.
4
TCSRWE
0
R/W
Timer Control/Status Register WD Write Enable
The WDON and WRST bits can be written when the
TCSRWE bit is set to 1.
When writing data to this bit, the value for bit 5 must be 0.
3
B2WI
1
R/W
Bit 2 Write Inhibit
This bit can be written to the WDON bit only when the
write value of the B2WI bit is 0.
This bit is always read as 1.
Rev. 4.00 Mar. 15, 2006 Page 246 of 556
REJ09B0026-0400
Section 13 Watchdog Timer
Bit
Bit Name
Initial
Value
R/W
Description
2
WDON
0
R/W
Watchdog Timer On
TCWD starts counting up when WDON is set to 1 and
halts when WDON is cleared to 0.
[Setting condition]
When 1 is written to the WDON bit while writing 0 to the
B2WI bit when the TCSRWE bit=1
[Clearing conditions]
1
B0WI
1
R/W
•
Reset by RES pin
•
When 0 is written to the WDON bit while writing 0 to
the B2WI when the TCSRWE bit = 1
Bit 0 Write Inhibit
This bit can be written to the WRST bit only when the
write value of the B0WI bit is 0. This bit is always read as
1.
0
WRST
0
R/W
Watchdog Timer Reset
[Setting condition]
When TCWD overflows and an internal reset signal is
generated
[Clearing conditions]
•
Reset by RES pin
•
When 0 is written to the WRST bit while writing 0 to
the B0WI bit when the TCSRWE bit=1
Rev. 4.00 Mar. 15, 2006 Page 247 of 556
REJ09B0026-0400
Section 13 Watchdog Timer
13.2.2
Timer Counter WD (TCWD)
TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the
internal reset signal is generated and the WRST bit in TCSRWD is set to 1. TCWD is initialized to
H'00.
13.2.3
Timer Mode Register WD (TMWD)
TMWD selects the input clock.
Bit
Bit Name
Initial
Value
R/W
7
CKS7
1
R/W
Description
Clock Select 7
Selects the subtimer internal oscillator.
CKS7 CKS3
0
6 to 4

All 1

1
: SBT internal oscillator
X
0
: WDT internal oscillator
1
1
: WDT internal oscillator
Reserved
These bits are always read as 1.
3
CKS3
1
R/W
Clock Select 3 to 0
2
CKS2
1
R/W
Select the clock to be input to TCWD.
1
CKS1
1
R/W
1000: Internal clock: counts on φ/64
0
CKS0
1
R/W
1001: Internal clock: counts on φ/128
1010: Internal clock: counts on φ/256
1011: Internal clock: counts on φ/512
1100: Internal clock: counts on φ/1024
1101: Internal clock: counts on φ/2048
1110: Internal clock: counts on φ/4096
1111: Internal clock: counts on φ/8192
0XXX: WDT internal oscillator
For the internal oscillator overflow periods, see section
22, Electrical Characteristics.
[Legend]
X: Don't care.
Rev. 4.00 Mar. 15, 2006 Page 248 of 556
REJ09B0026-0400
Section 13 Watchdog Timer
13.3
Operation
The watchdog timer is provided with an 8-bit counter. If 1 is written to WDON while writing 0 to
B2WI when the TCSRWE bit in TCSRWD is set to 1, TCWD begins counting up. (To operate the
watchdog timer, two write accesses to TCSRWD are required.) When a clock pulse is input after
the TCWD count value has reached H'FF, the watchdog timer overflows and an internal reset
signal is generated. The internal reset signal is output for a period of 256 φosc clock cycles. TCWD
is a writable counter, and when a value is set in TCWD, the count-up starts from that value. An
overflow period in the range of 1 to 256 input clock cycles can therefore be set, according to the
TCWD set value.
Figure 13.2 shows an example of watchdog timer operation.
Example:
With 30-ms overflow period when φ = 4 MHz
4 × 106
8192
× 30 × 10–3 = 14.6
Therefore, 256 – 15 = 241 (H'F1) is set in TCW.
TCWD overflow
H'FF
H'F1
TCWD
count value
H'00
Start
H'F1 written
to TCWD
H'F1 written to TCWD
Reset generated
Internal reset
signal
256 φosc clock cycles
Figure 13.2 Watchdog Timer Operation Example
Rev. 4.00 Mar. 15, 2006 Page 249 of 556
REJ09B0026-0400
Section 13 Watchdog Timer
Rev. 4.00 Mar. 15, 2006 Page 250 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
Section 14 Serial Communication Interface 3 (SCI3)
This LSI includes a serial communication interface 3 (SCI3), which has two independent
channels*1. The SCI3 can handle both asynchronous and clocked synchronous serial
communication. In asynchronous mode, serial data communication can be carried out using
standard asynchronous communication chips such as a Universal Asynchronous
Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA). A
function is also provided for serial communication between processors (multiprocessor
communication function).
Table 14.1 shows the SCI3 channel configuration and figure 14.1 shows a block diagram of the
SCI3. Since pin functions are identical for each of the two channels (SCI3 and SCI3_2*2), separate
explanations are not given in this section.
Notes: 1. Only one channel is available in the H8/36037 Group.
2. The H8/36037 Group does not have the SCI3_2.
14.1
Features
• Choice of asynchronous or clocked synchronous serial communication mode
• Full-duplex communication capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously.
Double-buffering is used in both the transmitter and the receiver, enabling continuous
transmission and continuous reception of serial data.
• On-chip baud rate generator allows any bit rate to be selected
• External clock or on-chip baud rate generator can be selected as a transfer clock source.
• Six interrupt sources
Transmit-end, transmit-data-empty, receive-data-full, overrun error, framing error, and parity
error.
Asynchronous mode
•
•
•
•
Data length: 7 or 8 bits
Stop bit length: 1 or 2 bits
Parity: Even, odd, or none
Receive error detection: Parity, overrun, and framing errors
Rev. 4.00 Mar. 15, 2006 Page 251 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
• Break detection: Break can be detected by reading the RXD pin level directly in the case of a
framing error
Clocked synchronous mode
• Data length: 8 bits
• Receive error detection: Overrun errors
Table 14.1 Channel Configuration
Channel
Channel 1*
Channel 2*
1
2
Abbreviation
Pin
Register
Register Address
SCI3
SCK3
RXD
TXD
SMR
H'FFA8
BRR
H'FFA9
SCI3_2
SCK3_2
RXD_2
TXD_2
SCR3
H'FFAA
TDR
H'FFAB
SSR
H'FFAC
RDR
H'FFAD
RSR

TSR

SMR_2
H'F740
BRR_2
H'F741
SCR3_2
H'F742
TDR_2
H'F743
SSR_2
H'F744
RDR_2
H'F745
RSR_2

TSR_2

Notes: 1. Channel 1 is used in on-board programming mode by boot mode.
2. The H8/36037 Group does not have the channel 2.
Rev. 4.00 Mar. 15, 2006 Page 252 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
SCK3
External
clock
Internal clock (φ/64, φ/16, φ/4, φ)
Baud rate generator
BRC
BRR
Clock
Transmit/receive
control circuit
Internal data bus
SMR
SCR3
SSR
TXD
TSR
TDR
RXD
RSR
RDR
Interrupt request
(TEI, TXI, RXI, ERI)
[Legend]
Receive shift register
RSR:
Receive data register
RDR:
Transmit shift register
TSR:
Transmit data register
TDR:
Serial mode register
SMR:
SCR3: Serial control register 3
Serial status register
SSR:
Bit rate register
BRR:
Bit rate counter
BRC:
Figure 14.1 Block Diagram of SCI3
Rev. 4.00 Mar. 15, 2006 Page 253 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
14.2
Input/Output Pins
Table 14.2 shows the SCI3 pin configuration.
Table 14.2 Pin Configuration
Pin Name
Abbreviation
I/O
Function
SCI3 clock
SCK3
I/O
SCI3 clock input/output
SCI3 receive data input
RXD
Input
SCI3 receive data input
SCI3 transmit data output
TXD
Output
SCI3 transmit data output
14.3
Register Descriptions
The SCI3 has the following registers for each channel.
•
•
•
•
•
•
•
•
Receive shift register (RSR)
Receive data register (RDR)
Transmit shift register (TSR)
Transmit data register (TDR)
Serial mode register (SMR)
Serial control register 3 (SCR3)
Serial status register (SSR)
Bit rate register (BRR)
Rev. 4.00 Mar. 15, 2006 Page 254 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
14.3.1
Receive Shift Register (RSR)
RSR is a shift register that is used to receive serial data input from the RXD pin and convert it into
parallel data. When one frame of data has been received, it is transferred to RDR automatically.
RSR cannot be directly accessed by the CPU.
14.3.2
Receive Data Register (RDR)
RDR is an 8-bit register that stores received data. When the SCI3 has received one frame of serial
data, it transfers the received serial data from RSR to RDR, where it is stored. After this, RSR is
receive-enabled. As RSR and RDR function as a double buffer in this way, continuous receive
operations are possible. After confirming that the RDRF bit in SSR is set to 1, read RDR only
once. RDR cannot be written to by the CPU. RDR is initialized to H'00.
14.3.3
Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI3 first
transfers transmit data from TDR to TSR automatically, then sends the data that starts from the
LSB to the TXD pin. TSR cannot be directly accessed by the CPU.
14.3.4
Transmit Data Register (TDR)
TDR is an 8-bit register that stores data for transmission. When the SCI3 detects that TSR is
empty, it transfers the transmit data written in TDR to TSR and starts transmission. The doublebuffered structure of TDR and TSR enables continuous serial transmission. If the next transmit
data has already been written to TDR during transmission of one-frame data, the SCI3 transfers
the written data to TSR to continue transmission. To achieve reliable serial transmission, write
transmit data to TDR only once after confirming that the TDRE bit in SSR is set to 1. TDR is
initialized to H'FF.
Rev. 4.00 Mar. 15, 2006 Page 255 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
14.3.5
Serial Mode Register (SMR)
SMR is used to set the SCI3’s serial transfer format and select the baud rate generator clock
source.
Bit
Bit Name
Initial
Value
R/W
Description
7
COM
0
R/W
Communication Mode
0: Asynchronous mode
1: Clocked synchronous mode
6
CHR
0
R/W
Character Length (enabled only in asynchronous mode)
0: Selects 8 bits as the data length.
1: Selects 7 bits as the data length.
5
PE
0
R/W
Parity Enable (enabled only in asynchronous mode)
When this bit is set to 1, the parity bit is added to transmit
data before transmission, and the parity bit is checked in
reception.
4
PM
0
R/W
Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
3
STOP
0
R/W
Stop Bit Length (enabled only in asynchronous mode)
Selects the stop bit length in transmission.
0: 1 stop bit
1: 2 stop bits
For reception, only the first stop bit is checked, regardless
of the value in the bit. If the second stop bit is 0, it is
treated as the start bit of the next transmit character.
2
MP
0
R/W
Multiprocessor Mode
When this bit is set to 1, the multiprocessor
communication function is enabled. The PE bit and PM
bit settings are invalid in multiprocessor mode. In clocked
synchronous mode, clear this bit to 0.
Rev. 4.00 Mar. 15, 2006 Page 256 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
Bit
Bit Name
Initial
Value
R/W
Description
1
CKS1
0
R/W
Clock Select 0 and 1
0
CKS0
0
R/W
These bits select the clock source for the baud rate
generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/14 clock (n = 2)
11: φ/64 clock (n = 3)
For the relationship between the bit rate register setting
and the baud rate, see section 14.3.8, Bit Rate Register
(BRR). n is the decimal representation of the value of n in
BRR (see section 14.3.8, Bit Rate Register (BRR)).
14.3.6
Serial Control Register 3 (SCR3)
SCR3 is a register that enables or disables SCI3 transfer operations and interrupt requests, and is
also used to select the transfer clock source. For details on interrupt requests, refer to section 14.7,
Interrupts.
Bit
Bit Name
Initial
Value
R/W
Description
7
TIE
0
R/W
Transmit Interrupt Enable
When this bit is set to 1, the TXI interrupt request is
enabled.
6
RIE
0
R/W
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests
are enabled.
5
TE
0
R/W
Transmit Enable
4
RE
0
R/W
Receive Enable
When this bit s set to 1, transmission is enabled.
When this bit is set to 1, reception is enabled.
Rev. 4.00 Mar. 15, 2006 Page 257 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
Bit
Bit Name
Initial
Value
R/W
Description
3
MPIE
0
R/W
Multiprocessor Interrupt Enable (enabled only when the
MP bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and OER status flags in SSR is disabled.
On receiving data in which the multiprocessor bit is 1, this
bit is automatically cleared and normal reception is
resumed. For details, refer to section 14.6, Multiprocessor
Communication Function.
2
TEIE
0
R/W
Transmit End Interrupt Enable
When this bit is set to 1, TEI interrupt request is enabled.
1
CKE1
0
R/W
Clock Enable 0 and 1
0
CKE0
0
R/W
Selects the clock source.
•
Asynchronous mode
00: On-chip baud rate generator
01: On-chip baud rate generator
Outputs a clock of the same frequency as the bit rate
from the SCK3 pin.
10: External clock
Inputs a clock with a frequency 14 times the bit rate
from the SCK3 pin.
11:Reserved
•
Clocked synchronous mode
00: On-chip clock (SCK3 pin functions as clock output)
01: Reserved
10: External clock (SCK3 pin functions as clock input)
11: Reserved
Rev. 4.00 Mar. 15, 2006 Page 258 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
14.3.7
Serial Status Register (SSR)
SSR is a register containing status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot
be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared.
Bit
Bit Name
Initial
Value
R/W
Description
7
TDRE
1
R/W
Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
•
When the TE bit in SCR3 is 0
•
When data is transferred from TDR to TSR
[Clearing conditions]
6
RDRF
0
R/W
•
When 0 is written to TDRE after reading TDRE = 1
•
When the transmit data is written to TDR
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
•
When serial reception ends normally and receive data
is transferred from RSR to RDR
[Clearing conditions]
5
OER
0
R/W
•
When 0 is written to RDRF after reading RDRF = 1
•
When data is read from RDR
Overrun Error
[Setting condition]
•
When an overrun error occurs in reception
[Clearing condition]
•
4
FER
0
R/W
When 0 is written to OER after reading OER = 1
Framing Error
[Setting condition]
•
When a framing error occurs in reception
[Clearing condition]
•
When 0 is written to FER after reading FER = 1
Rev. 4.00 Mar. 15, 2006 Page 259 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
Bit
Bit Name
Initial
Value
R/W
Description
3
PER
0
R/W
Parity Error
[Setting condition]
•
When a parity error is detected during reception
[Clearing condition]
•
2
TEND
1
R
When 0 is written to PER after reading PER = 1
Transmit End
[Setting conditions]
•
When the TE bit in SCR3 is 0
•
When TDRE = 1 at transmission of the last bit of a 1frame serial transmit character
[Clearing conditions]
1
MPBR
0
R
•
When 0 is written to TDRE after reading TDRE = 1
•
When the transmit data is written to TDR
Multiprocessor Bit Receive
MPBR stores the multiprocessor bit in the receive
character data. When the RE bit in SCR3 is cleared to 0,
its state is retained.
0
MPBT
0
R/W
Multiprocessor Bit Transfer
MPBT stores the multiprocessor bit to be added to the
transmit character data.
Rev. 4.00 Mar. 15, 2006 Page 260 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
14.3.8
Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 14.3
shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of
SMR in asynchronous mode. Table 14.4 shows the maximum bit rate for each frequency in
asynchronous mode. The values shown in both tables 14.3 and 14.4 are values in active (highspeed) mode. Table 14.5 shows the relationship between the N setting in BRR and the n setting in
bits CKS1 and CKS0 of SMR in clocked synchronous mode. The values shown in table 14.5 are
values in active (high-speed) mode. The N setting in BRR and error for other operating
frequencies and bit rates can be obtained by the following formulas:
[Asynchronous Mode]
N=
φ
× 106 – 1
64 × 22n–1 × B
φ × 106

2n–1 – 1 × 100
(N
+
1)
×
B
×
64
×
2



Error (%) = 
[Clocked Synchronous Mode]
N=
φ
× 106 – 1
8 × 22n–1 × B
[Legend]
B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n: CSK1 and CSK0 settings in SMR (0 ≤ n ≤ 3)
Rev. 4.00 Mar. 15, 2006 Page 261 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
Table 14.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
Operating Frequency φ (MHz)
2
2.097152
2.4576
3
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
1
141
0.03
1
148
–0.04
1
174
–0.26
1
212
0.03
150
1
103
0.14
1
108
0.21
1
127
0.00
1
155
0.14
300
0
207
0.14
0
217
0.21
0
255
0.00
1
77
0.14
600
0
103
0.14
0
108
0.21
0
127
0.00
0
155
0.14
1200
0
51
0.14
0
54
–0.70
0
63
0.00
0
77
0.14
2400
0
25
0.14
0
26
1.14
0
31
0.00
0
38
0.14
4800
0
12
0.14
0
13
–2.48
0
15
0.00
0
19
–2.34
9600
0
6
–6.99
0
6
–2.48
0
7
0.00
0
9
–2.34
19200
0
2
8.51
0
2
13.78
0
3
0.00
0
4
–2.34
31250
0
1
0.00
0
1
4.86
0
1
22.88
0
2
0.00
38400
0
1
–18.62
0
1
–14.67
0
1
0.00
—
—
—
Rev. 4.00 Mar. 15, 2006 Page 262 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
Operating Frequency φ (MHz)
3.6864
4
4.9152
5
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
64
0.70
2
70
0.03
2
86
0.31
2
88
–0.25
150
1
191
0.00
1
207
0.14
1
255
0.00
2
64
0.14
300
1
95
0.00
1
103
0.14
1
127
0.00
1
129
0.14
600
0
191
0.00
0
207
0.14
0
255
0.00
1
64
0.14
1200
0
95
0.00
0
103
0.14
0
127
0.00
0
129
0.14
2400
0
47
0.00
0
51
0.14
0
63
0.00
0
64
0.14
4800
0
23
0.00
0
25
0.14
0
31
0.00
0
32
–1.36
9600
0
11
0.00
0
12
0.14
0
15
0.00
0
15
1.73
19200
0
5
0.00
0
6
–6.99
0
7
0.00
0
7
1.73
31250
—
—
—
0
3
0.00
0
4
–1.70
0
4
0.00
38400
0
2
0.00
0
2
8.51
0
3
0.00
0
3
1.73
[Legend]
: A setting is available but error occurs.
Rev. 4.00 Mar. 15, 2006 Page 263 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
Table 14.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
Operating Frequency φ (MHz)
6
6.144
7.3728
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
106
–0.44
2
108
0.08
2
130
–0.07
150
2
77
0.14
2
79
0.00
2
95
0.00
300
1
155
0.14
1
159
0.00
1
191
0.00
600
1
77
0.14
1
79
0.00
1
95
0.00
1200
0
155
0.14
0
159
0.00
0
191
0.00
2400
0
77
0.14
0
79
0.00
0
95
0.00
4800
0
38
0.14
0
39
0.00
0
47
0.00
9600
0
19
–2.34
0
19
0.00
0
23
0.00
19200
0
9
–2.34
0
9
0.00
0
11
0.00
31250
0
5
0.00
0
5
2.40
0
6
5.33
38400
0
4
–2.34
0
4
0.00
0
5
0.00
Rev. 4.00 Mar. 15, 2006 Page 264 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
Operating Frequency φ (MHz)
8
9.8304
10
12
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
141
0.03
2
174
–0.26
2
177
–0.25
2
212
0.03
150
2
103
0.14
2
127
0.00
2
129
0.14
2
155
0.14
300
1
207
0.14
1
255
0.00
2
64
0.14
2
77
0.14
600
1
103
0.14
1
127
0.00
1
129
0.14
1
155
0.14
1200
0
207
0.14
0
255
0.00
1
64
0.14
1
77
0.14
2400
0
103
0.14
0
127
0.00
0
129
0.14
0
155
0.14
4800
0
51
0.14
0
63
0.00
0
64
0.14
0
77
0.14
9600
0
25
0.14
0
31
0.00
0
32
–1.36
0
38
0.14
19200
0
12
0.14
0
15
0.00
0
15
1.73
0
19
–2.34
31250
0
7
0.00
0
9
–1.70
0
9
0.00
0
11
0.00
38400
0
6
-6.99
0
7
0.00
0
7
1.73
0
9
–2.34
[Legend]
: A setting is available but error occurs.
Rev. 4.00 Mar. 15, 2006 Page 265 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
Table 14.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3)
Operating Frequency φ (MHz)
12.888
14
14.7456
14
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
217
0.08
2
248
–0.17
3
64
0.70
3
70
0.03
150
2
159
0.00
2
181
0.14
2
191
0.00
2
207
0.14
300
2
79
0.00
2
90
0.14
2
95
0.00
2
103
0.14
600
1
159
0.00
1
181
0.14
1
191
0.00
1
207
0.14
1200
1
79
0.00
1
90
0.14
1
95
0.00
1
103
0.14
2400
0
159
0.00
0
181
0.14
0
191
0.00
0
207
0.14
4800
0
79
0.00
0
90
0.14
0
95
0.00
0
103
0.14
9600
0
39
0.00
0
45
–0.93
0
47
0.00
0
51
0.14
19200
0
19
0.00
0
22
–0.93
0
23
0.00
0
25
0.14
31250
0
11
2.40
0
13
0.00
0
14
–1.70
0
15
0.00
38400
0
9
0.00
—
—
—
0
11
0.00
0
12
0.14
Rev. 4.00 Mar. 15, 2006 Page 266 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
Operating Frequency φ (MHz)
18
20
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
110
3
79
–0.12
3
88
–0.25
150
2
233
0.14
3
64
0.14
300
2
114
0.14
2
129
0.14
600
1
233
0.14
2
64
0.14
1200
1
114
0.14
1
129
0.14
2400
0
233
0.14
1
64
0.14
4800
0
114
0.14
0
129
0.14
9600
0
58
–0.96
0
64
0.14
19200
0
28
1.02
0
32
–1.36
31250
0
17
0.00
0
19
0.00
38400
0
14
–2.34
0
15
1.73
[Legend]
—: A setting is available but error occurs.
Table 14.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
φ (MHz)
Maximum Bit
Rate (bit/s)
n
N
φ (MHz)
Maximum Bit
Rate (bit/s)
n
N
2
62500
0
0
8
250000
0
0
2.097152
65536
0
0
9.8304
307200
0
0
2.4576
76800
0
0
10
312500
0
0
3
93750
0
0
12
375000
0
0
3.6864
115200
0
0
12.288
384000
0
0
4
125000
0
0
14
437500
0
0
4.9152
153600
0
0
14.7456
460800
0
0
5
156250
0
0
14
500000
0
0
6
187500
0
0
17.2032
537600
0
0
6.144
192000
0
0
18
562500
0
0
7.3728
230400
0
0
20
625000
0
0
Rev. 4.00 Mar. 15, 2006 Page 267 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
Table 14.5 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode)
(1)
Operating Frequency φ (MHz)
2
4
8
10
Bit Rate
(bit/s)
n
N
n
N
n
N
n
N
110
3
70
—
—
—
—
—
—
250
2
124
2
249
3
124
—
—
16
n
N
3
249
500
1
249
2
124
2
249
—
—
3
124
1k
1
124
1
249
2
124
—
—
2
249
2.5k
0
199
1
99
1
199
1
249
2
99
5k
0
99
0
199
1
99
1
124
1
199
10k
0
49
0
99
0
199
0
249
1
99
25k
0
19
0
39
0
79
0
99
0
159
50k
0
9
0
19
0
39
0
49
0
79
100k
0
4
0
9
0
19
0
24
0
39
250k
0
1
0
3
0
7
0
9
0
15
500k
0
0*
0
1
0
3
0
4
0
7
0
0*
0
1
—
—
0
3
0
0*
—
—
0
1
0
0*
—
—
0
0*
1M
2M
2.5M
4M
[Legend]
Blank: No setting is available.
—:
A setting is available but error occurs.
*:
Continuous transfer is not possible.
Rev. 4.00 Mar. 15, 2006 Page 268 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
Table 14.5 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode)
(2)
Operating Frequency φ (MHz)
18
20
Bit Rate
(bit/s)
n
N
n
N
110
—
—
—
—
250
—
—
—
—
500
3
140
3
155
1k
3
69
3
77
2.5k
2
112
2
124
5k
1
224
1
249
10k
1
112
1
124
25k
0
179
0
199
50k
0
89
0
99
100k
0
44
0
49
250k
0
17
0
19
500k
0
8
0
9
1M
0
4
0
4
2M
—
—
—
—
2.5M
—
—
0
1
4M
—
—
—
—
[Legend]
Blank: No setting is available.
—:
A setting is available but error occurs.
*:
Continuous transfer is not possible.
Rev. 4.00 Mar. 15, 2006 Page 269 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
14.4
Operation in Asynchronous Mode
Figure 14.2 shows the general format for asynchronous serial communication. One character (or
frame) consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or
low level), and finally stop bits (high level). Inside the SCI3, the transmitter and receiver are
independent units, enabling full-duplex. Both the transmitter and the receiver also have a doublebuffered structure, so data can be read or written during transmission or reception, enabling
continuous data transfer.
LSB
MSB
Serial Start
data
bit
Transmit/receive data
7 or 8 bits
1 bit
1
Parity
bit
Stop bit
Mark state
1 or
2 bits
1 bit,
or none
One unit of transfer data (character or frame)
Figure 14.2 Data Format in Asynchronous Communication
14.4.1
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK3 pin can be selected as the SCI3’s serial clock, according to the setting of the COM bit in
SMR and the CKE0 and CKE1 bits in SCR3. When an external clock is input at the SCK3 pin, the
clock frequency should be 14 times the bit rate used.
When the SCI3 is operated on an internal clock, the clock can be output from the SCK3 pin. The
frequency of the clock output in this case is equal to the bit rate, and the phase is such that the
rising edge of the clock is in the middle of the transmit data, as shown in figure 14.3.
Clock
Serial data
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 character (frame)
Figure 14.3 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits)
Rev. 4.00 Mar. 15, 2006 Page 270 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
14.4.2
SCI3 Initialization
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR3 to 0,
then initialize the SCI3 as described below. When the operating mode, or transfer format, is
changed for example, the TE and RE bits must be cleared to 0 before making the change using the
following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing
the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and OER flags, or the
contents of RDR. When the external clock is used in asynchronous mode, the clock must be
supplied even during initialization.
[1]
Start initialization
When the clock output is selected in
asynchronous mode, clock is output
immediately after CKE1 and CKE0
settings are made. When the clock
output is selected at reception in clocked
synchronous mode, clock is output
immediately after CKE1, CKE0, and RE
are set to 1.
Clear TE and RE bits in SCR3 to 0
[1]
Set CKE1 and CKE0 bits in SCR3
Set data transfer format in SMR
[2]
Set value in BRR
[3]
Wait
[2]
Set the data transfer format in SMR.
[3]
Write a value corresponding to the bit
rate to BRR. Not necessary if an
external clock is used.
[4]
Wait at least one bit interval, then set the
TE bit or RE bit in SCR3 to 1. RE
settings enable the RXD pin to be used.
For transmission, set the TXD bit in
PMR1 to 1 to enable the TXD output pin
to be used. Also set the RIE, TIE, TEIE,
and MPIE bits, depending on whether
interrupts are required. In asynchronous
mode, the bits are marked at
transmission and idled at reception to
wait for the start bit.
No
1-bit interval elapsed?
Yes
Set TE and RE bits in
SCR3 to 1, and set RIE, TIE, TEIE,
and MPIE bits. For transmit (TE=1),
also set the TxD bit in PMR1.
<Initialization completion>
[4]
Set the clock selection in SCR3.
Be sure to clear bits RIE, TIE, TEIE, and
MPIE, and bits TE and RE, to 0.
Figure 14.4 Sample SCI3 Initialization Flowchart
Rev. 4.00 Mar. 15, 2006 Page 271 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
14.4.3
Data Transmission
Figure 14.5 shows an example of operation for transmission in asynchronous mode. In
transmission, the SCI3 operates as described below.
1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that
data has been written to TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI3 sets the TDRE flag to 1 and starts
transmission. If the TIE bit is set to 1 at this time, a TXI interrupt request is generated.
Continuous transmission is possible because the TXI interrupt routine writes next transmit data
to TDR before transmission of the current transmit data has been completed.
3. The SCI3 checks the TDRE flag at the timing for sending the stop bit.
4. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then
serial transmission of the next frame is started.
5. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark
state” is entered, in which 1 is output. If the TEIE bit in SCR3 is set to 1 at this time, a TEI
interrupt request is generated.
6. Figure 14.6 shows a sample flowchart for transmission in asynchronous mode.
Start
bit
Serial
data
1
0
Transmit
data
D0
D1
D7
1 frame
Parity Stop Start
bit
bit bit
0/1
1
0
Transmit
data
D0
D1
D7
Parity Stop
bit
bit
0/1
Mark
state
1
1
1 frame
TDRE
TEND
TXI interrupt
LSI
operation request
generated
User
processing
TDRE flag
cleared to 0
TXI interrupt request generated
TEI interrupt request
generated
Data written
to TDR
Figure 14.5 Example of SCI3 Transmission in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)
Rev. 4.00 Mar. 15, 2006 Page 272 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
Start transmission
[1]
Read TDRE flag in SSR
No
TDRE = 1
Yes
Write transmit data to TDR
[2]
Yes
All data transmitted?
[1] Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. When data is
written to TDR, the TDRE flag is
automaticaly cleared to 0.
[2] To continue serial transmission,
read 1 from the TDRE flag to
confirm that writing is possible,
then write data to TDR. When data
is written to TDR, the TDRE flag is
automaticaly cleared to 0.
[3] To output a break in serial
transmission, after setting PCR to 1
and PDR to 0, clear TxD in PMR1
to 0, then clear the TE bit in SCR3
to 0.
No
Read TEND flag in SSR
No
TEND = 1
Yes
[3]
No
Break output?
Yes
Clear PDR to 0 and
set PCR to 1
Clear TE bit in SCR3 to 0
<End>
Figure 14.6 Sample Serial Transmission Data Flowchart (Asynchronous Mode)
Rev. 4.00 Mar. 15, 2006 Page 273 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
14.4.4
Serial Data Reception
Figure 14.7 shows an example of operation for reception in asynchronous mode. In serial
reception, the SCI3 operates as described below.
1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs
internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this time, an
ERI interrupt request is generated. Receive data is not transferred to RDR.
3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated.
4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive
data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt
request is generated.
5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is
generated. Continuous reception is possible because the RXI interrupt routine reads the receive
data transferred to RDR before reception of the next receive data has been completed.
Start
bit
Serial
data
1
0
Receive
data
D0
D1
D7
Parity Stop Start
bit
bit bit
0/1
1
0
1 frame
Receive
data
D0
D1
Parity Stop
bit
bit
D7
0/1
0
Mark state
(idle state)
1
1 frame
RDRF
FER
LSI
operation
RXI request
RDRF
cleared to 0
0 stop bit
detected
RDR data read
User
processing
Figure 14.7 Example of SCI3 Reception in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)
Rev. 4.00 Mar. 15, 2006 Page 274 of 556
REJ09B0026-0400
ERI request in
response to
framing error
Framing error
processing
Section 14 Serial Communication Interface 3 (SCI3)
Table 14.6 shows the states of the SSR status flags and receive data handling when a receive error
is detected. If a receive error is detected, the RDRF flag retains its state before receiving data.
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.8 shows a sample flow chart
for serial data reception.
Table 14.6 SSR Status Flags and Receive Data Handling
SSR Status Flag
RDRF*
OER
FER
PER
Receive Data
Receive Error Type
1
1
0
0
Lost
Overrun error
0
0
1
0
Transferred to RDR
Framing error
0
0
0
1
Transferred to RDR
Parity error
1
1
1
0
Lost
Overrun error + framing error
1
1
0
1
Lost
Overrun error + parity error
0
0
1
1
Transferred to RDR
Framing error + parity error
1
1
1
1
Lost
Overrun error + framing error +
parity error
Note:
*
The RDRF flag retains the state it had before data reception.
Rev. 4.00 Mar. 15, 2006 Page 275 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
Start reception
Read OER, PER, and
FER flags in SSR
[1]
Yes
OER+PER+FER = 1
[4]
No
Error processing
(Continued on next page)
Read RDRF flag in SSR
[2]
No
RDRF = 1
Yes
Read receive data in RDR
[1] Read the OER, PER, and FER flags in
SSR to identify the error. If a receive
error occurs, performs the appropriate
error processing.
[2] Read SSR and check that RDRF = 1,
then read the receive data in RDR.
The RDRF flag is cleared automatically.
[3] To continue serial reception, before the
stop bit for the current frame is
received, read the RDRF flag and read
RDR.
The RDRF flag is cleared automatically.
[4] If a receive error occurs, read the OER,
PER, and FER flags in SSR to identify
the error. After performing the
appropriate error processing, ensure
that the OER, PER, and FER flags are
all cleared to 0. Reception cannot be
resumed if any of these flags are set to
1. In the case of a framing error, a
break can be detected by reading the
value of the input port corresponding to
the RxD pin.
Yes
All data received?
[3]
No
(A)
Clear RE bit in SCR3 to 0
<End>
Figure 14.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (1)
Rev. 4.00 Mar. 15, 2006 Page 276 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
[4]
Error processing
No
OER = 1
Yes
Overrun error processing
No
FER = 1
Yes
Yes
Break?
No
Framing error processing
No
PER = 1
Yes
Parity error processing
(A)
Clear OER, PER, and
FER flags in SSR to 0
<End>
Figure 14.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (2)
Rev. 4.00 Mar. 15, 2006 Page 277 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
14.5
Operation in Clocked Synchronous Mode
Figure 14.9 shows the general format for clocked synchronous communication. In clocked
synchronous mode, data is transmitted or received synchronous with clock pulses. A single
character in the transmit data consists of the 8-bit data starting from the LSB. In clocked
synchronous serial communication, data on the transmission line is output from one falling edge of
the synchronization clock to the next. In clocked synchronous mode, the SCI3 receives data in
synchronous with the rising edge of the synchronization clock. After 8-bit data is output, the
transmission line holds the MSB state. In clocked synchronous mode, no parity or multiprocessor
bit is added. Inside the SCI3, the transmitter and receiver are independent units, enabling fullduplex communication through the use of a common clock. Both the transmitter and the receiver
also have a double-buffered structure, so data can be read or written during transmission or
reception, enabling continuous data transfer.
8-bit
One unit of transfer data (character or frame)
*
*
Synchronization
clock
LSB
Bit 0
Serial data
MSB
Bit 1
Don’t care
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Don’t care
Note: * High except in continuous transfer
Figure 14.9 Data Format in Clocked Synchronous Communication
14.5.1
Clock
Either an internal clock generated by the on-chip baud rate generator or an external
synchronization clock input at the SCK3 pin can be selected, according to the setting of the COM
bit in SMR and CKE0 and CKE1 bits in SCR3. When the SCI3 is operated on an internal clock,
the synchronization clock is output from the SCK3 pin. Eight synchronization clock pulses are
output in the transfer of one character, and when no transfer is performed the clock is fixed high.
14.5.2
SCI3 Initialization
Before transmitting and receiving data, the SCI3 should be initialized as described in a sample
flowchart in figure 14.4.
Rev. 4.00 Mar. 15, 2006 Page 278 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
14.5.3
Serial Data Transmission
Figure 14.10 shows an example of SCI3 operation for transmission in clocked synchronous mode.
In serial transmission, the SCI3 operates as described below.
1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI3 recognizes that data
has been written to TDR, and transfers the data from TDR to TSR.
2. The SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR3 is set to 1 at
this time, a transmit data empty interrupt (TXI) is generated.
3. 8-bit data is sent from the TXD pin synchronized with the output clock when output clock
mode has been specified, and synchronized with the input clock when use of an external clock
has been specified. Serial data is transmitted sequentially from the LSB (bit 0), from the TXD
pin.
4. The SCI3 checks the TDRE flag at the timing for sending the MSB (bit 7).
5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
of the next frame is started.
6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains the
output state of the last bit. If the TEIE bit in SCR3 is set to 1 at this time, a TEI interrupt
request is generated.
7. The SCK3 pin is fixed high at the end of transmission.
Figure 14.11 shows a sample flow chart for serial data transmission. Even if the TDRE flag is
cleared to 0, transmission will not start while a receive error flag (OER, FER, or PER) is set to 1.
Make sure that the receive error flags are cleared to 0 before starting transmission.
Serial
clock
Serial
data
Bit 0
Bit 1
1 frame
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
1 frame
TDRE
TEND
TXI interrupt
LSI
operation request
generated
TDRE flag
cleared
to 0
User
processing
Data written
to TDR
TXI interrupt request generated
TEI interrupt request
generated
Figure 14.10 Example of SCI3 Transmission in Clocked Synchronous Mode
Rev. 4.00 Mar. 15, 2006 Page 279 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
Start transmission
[1]
[1]
Read TDRE flag in SSR
No
TDRE = 1
Yes
[2]
Read SSR and check that the TDRE flag is
set to 1, then write transmit data to TDR.
When data is written to TDR, the TDRE flag
is automatically cleared to 0 and clocks are
output to start the data transmission.
To continue serial transmission, be sure to
read 1 from the TDRE flag to confirm that
writing is possible, then write data to TDR.
When data is written to TDR, the TDRE flag
is automatically cleared to 0.
Write transmit data to TDR
[2]
All data transmitted?
Yes
No
Read TEND flag in SSR
No
TEND = 1
Yes
Clear TE bit in SCR3 to 0
<End>
Figure 14.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode)
Rev. 4.00 Mar. 15, 2006 Page 280 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
14.5.4
Serial Data Reception (Clocked Synchronous Mode)
Figure 14.12 shows an example of SCI3 operation for reception in clocked synchronous mode. In
serial reception, the SCI3 operates as described below.
1. The SCI3 performs internal initialization synchronous with a synchronization clock input or
output, starts receiving data.
2. The SCI3 stores the receive data in RSR.
3. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
in SSR is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this
time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the
RDRF flag remains to be set to 1.
4. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is
generated.
Serial
clock
Serial
data
Bit 7
Bit 0
Bit 7
1 frame
Bit 0
Bit 1
Bit 6
Bit 7
1 frame
RDRF
OER
LSI
operation
User
processing
RXI interrupt
request
generated
RDRF flag
cleared
to 0
RDR data read
RXI interrupt request generated
RDR data has
not been read
(RDRF = 1)
ERI interrupt request
generated by
overrun error
Overrun error
processing
Figure 14.12 Example of SCI3 Reception in Clocked Synchronous Mode
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.13 shows a sample flow
chart for serial data reception.
Rev. 4.00 Mar. 15, 2006 Page 281 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
Start reception
[1]
[1]
Read OER flag in SSR
[2]
Yes
OER = 1
[4]
No
Error processing
[3]
(Continued below)
Read RDRF flag in SSR
[2]
[4]
No
RDRF = 1
Yes
Read the OER flag in SSR to determine if
there is an error. If an overrun error has
occurred, execute overrun error processing.
Read SSR and check that the RDRF flag is
set to 1, then read the receive data in RDR.
When data is read from RDR, the RDRF
flag is automatically cleared to 0.
To continue serial reception, before the
MSB (bit 7) of the current frame is received,
reading the RDRF flag and reading RDR
should be finished. When data is read from
RDR, the RDRF flag is automatically
cleared to 0.
If an overrun error occurs, read the OER
flag in SSR, and after performing the
appropriate error processing, clear the OER
flag to 0. Reception cannot be resumed if
the OER flag is set to 1.
Read receive data in RDR
Yes
All data received?
[3]
No
Clear RE bit in SCR3 to 0
<End>
[4]
Error processing
Overrun error processing
Clear OER flag in SSR to 0
<End>
Figure 14.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)
Rev. 4.00 Mar. 15, 2006 Page 282 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
14.5.5
Simultaneous Serial Data Transmission and Reception
Figure 14.14 shows a sample flowchart for simultaneous serial transmit and receive operations.
The following procedure should be used for simultaneous serial data transmit and receive
operations. To switch from transmit mode to simultaneous transmit and receive mode, after
checking that the SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear
TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive
mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished
reception, clear RE to 0. Then after checking that the RDRF and receive error flags (OER, FER,
and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction.
Rev. 4.00 Mar. 15, 2006 Page 283 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
Start transmission/reception
Read TDRE flag in SSR
[1]
[1]
No
TDRE = 1
Yes
Write transmit data to TDR
Read OER flag in SSR
OER = 1
No
Read RDRF flag in SSR
Yes
[4]
Error processing
[2]
No
RDRF = 1
Yes
Read receive data in RDR
Read SSR and check that the TDRE
flag is set to 1, then write transmit
data to TDR.
When data is written to TDR, the
TDRE flag is automatically cleared to
0.
[2] Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR.
When data is read from RDR, the
RDRF flag is automatically cleared to
0.
[3] To continue serial transmission/
reception, before the MSB (bit 7) of
the current frame is received, finish
reading the RDRF flag, reading RDR.
Also, before the MSB (bit 7) of the
current frame is transmitted, read 1
from the TDRE flag to confirm that
writing is possible. Then write data to
TDR.
When data is written to TDR, the
TDRE flag is automatically cleared to
0. When data is read from RDR, the
RDRF flag is automatically cleared to
0.
[4] If an overrun error occurs, read the
OER flag in SSR, and after
performing the appropriate error
processing, clear the OER flag to 0.
Transmission/reception cannot be
resumed if the OER flag is set to 1.
For overrun error processing, see
figure 14.13.
Yes
All data received?
[3]
No
Clear TE and RE bits in SCR to 0
<End>
Figure 14.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
(Clocked Synchronous Mode)
Rev. 4.00 Mar. 15, 2006 Page 284 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
14.6
Multiprocessor Communication Function
Use of the multiprocessor communication function enables data transfer between a number of
processors sharing communication lines by asynchronous serial communication using the
multiprocessor format, in which a multiprocessor bit is added to the transfer data. When
multiprocessor communication is performed, each receiving station is addressed by a unique ID
code. The serial communication cycle consists of two component cycles; an ID transmission cycle
that specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to
differentiate between the ID transmission cycle and the data transmission cycle. If the
multiprocessor bit is 1, the cycle is an ID transmission cycle; if the multiprocessor bit is 0, the
cycle is a data transmission cycle. Figure 14.15 shows an example of inter-processor
communication using the multiprocessor format. The transmitting station first sends the ID code
of the receiving station with which it wants to perform serial communication as data with a 1
multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added.
When data with a 1 multiprocessor bit is received, the receiving station compares that data with its
own ID. The station whose ID matches then receives the data sent next. Stations whose IDs do not
match continue to skip data until data with a 1 multiprocessor bit is again received.
The SCI3 uses the MPIE bit in SCR3 to implement this function. When the MPIE bit is set to 1,
transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags,
RDRF, FER, and OER, to 1, are inhibited until data with a 1 multiprocessor bit is received. On
reception of a receive character with a 1 multiprocessor bit, the MPBR bit in SSR is set to 1 and
the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR3 is
set to 1 at this time, an RXI interrupt is generated.
When the multiprocessor format is selected, the parity bit setting is rendered invalid. All other bit
settings are the same as those in normal asynchronous mode. The clock used for multiprocessor
communication is the same as that in normal asynchronous mode.
Rev. 4.00 Mar. 15, 2006 Page 285 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
Transmitting
station
Serial transmission line
Receiving
station A
Receiving
station B
Receiving
station C
Receiving
station D
(ID = 01)
(ID = 02)
(ID = 03)
(ID = 04)
Serial
data
H'01
H'AA
(MPB = 1)
(MPB = 0)
ID transmission cycle = Data transmission cycle =
receiving station
Data transmission to
specification
receiving station specified by ID
[Legend]
MPB: Multiprocessor bit
Figure 14.15 Example of Inter-Processor Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A)
14.6.1
Multiprocessor Serial Data Transmission
Figure 14.14 shows a sample flowchart for multiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission
cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI3 operations are the same
as those in asynchronous mode.
Rev. 4.00 Mar. 15, 2006 Page 286 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
Start transmission
[1]
[1]
Read TDRE flag in SSR
No
TDRE = 1
[2]
Yes
Set MPBT bit in SSR
[3]
Write transmit data to TDR
Yes
[2]
Read SSR and check that the TDRE
flag is set to 1, set the MPBT bit in
SSR to 0 or 1, then write transmit
data to TDR. When data is written to
TDR, the TDRE flag is automatically
cleared to 0.
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR. When data is
written to TDR, the TDRE flag is
automatically cleared to 0.
To output a break in serial
transmission, set the port PCR to 1,
clear PDR to 0, then clear the TE bit
in SCR3 to 0.
All data transmitted?
No
Read TEND flag in SSR
No
TEND = 1
Yes
No
[3]
Break output?
Yes
Clear PDR to 0 and set PCR to 1
Clear TE bit in SCR3 to 0
<End>
Figure 14.16 Sample Multiprocessor Serial Transmission Flowchart
14.6.2
Multiprocessor Serial Data Reception
Figure 14.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in
SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data
with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is
Rev. 4.00 Mar. 15, 2006 Page 287 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
generated at this time. All other SCI3 operations are the same as those in asynchronous mode.
Figure 14.18 shows an example of SCI3 operation for multiprocessor format reception.
Start reception
[1]
[2]
Set MPIE bit in SCR3 to 1
[1]
Read OER and FER flags in SSR
[2]
[3]
Yes
FER+OER = 1
No
Read RDRF flag in SSR
[3]
[4]
No
RDRF = 1
[5]
Yes
Read receive data in RDR
No
This station’s ID?
Yes
Read OER and FER flags in SSR
Set the MPIE bit in SCR3 to 1.
Read OER and FER in SSR to check for
errors. Receive error processing is performed
in cases where a receive error occurs.
Read SSR and check that the RDRF flag is
set to 1, then read the receive data in RDR
and compare it with this station’s ID.
If the data is not this station’s ID, set the MPIE
bit to 1 again.
When data is read from RDR, the RDRF flag
is automatically cleared to 0.
Read SSR and check that the RDRF flag is
set to 1, then read the data in RDR.
If a receive error occurs, read the OER and
FER flags in SSR to identify the error. After
performing the appropriate error processing,
ensure that the OER and FER flags are all
cleared to 0.
Reception cannot be resumed if either of
these flags is set to 1.
In the case of a framing error, a break can be
detected by reading the RxD pin value.
Yes
FER+OER = 1
No
[4]
Read RDRF flag in SSR
No
RDRF = 1
[5]
Error processing
Yes
Read receive data in RDR
(Continued on
next page)
Yes
All data received?
No
[A]
Clear RE bit in SCR3 to 0
<End>
Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (1)
Rev. 4.00 Mar. 15, 2006 Page 288 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
[5]
Error processing
No
OER = 1
Yes
Overrun error processing
No
FER = 1
Yes
Yes
Break?
No
[A]
Framing error processing
Clear OER, and
FER flags in SSR to 0
<End>
Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (2)
Rev. 4.00 Mar. 15, 2006 Page 289 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
Start
bit
Serial
data
1
0
Receive
data (ID1)
D0
D1
D7
MPB
1
Stop Start
bit bit
1
0
Receive data
(Data1)
D0
1 frame
D1
D7
MPB
Stop
bit
Mark state
(idle state)
0
1
1
1 frame
MPIE
RDRF
RDR
value
ID1
LSI
operation
RDRF flag
cleared
to 0
RXI interrupt
request
MPIE cleared
to 0
User
processing
RXI interrupt request
is not generated, and
RDR retains its state
RDR data read
When data is not
this station's ID,
MPIE is set to 1
again
(a) When data does not match this receiver's ID
Start
bit
Serial
data
1
0
Receive
data (ID2)
D0
D1
D7
MPB
1
Stop Start
bit bit
1
0
Receive data
(Data2)
D0
1 frame
D1
D7
MPB
Stop
bit
Mark state
(idle state)
0
1
1
1 frame
MPIE
RDRF
RDR
value
ID1
LSI
operation
User
processing
ID2
RXI interrupt
request
MPIE cleared
to 0
RDRF flag
cleared
to 0
RDR data read
Data2
RXI interrupt
request
When data is
this station's
ID, reception
is continued
RDRF flag
cleared
to 0
RDR data read
MPIE set to 1
again
(b) When data matches this receiver's ID
Figure 14.18 Example of SCI3 Reception Using Multiprocessor Format
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
Rev. 4.00 Mar. 15, 2006 Page 290 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
14.7
Interrupts
The SCI3 creates the following six interrupt requests: transmission end, transmit data empty,
receive data full, and receive errors (overrun error, framing error, and parity error). Table 14.7
shows the interrupt sources.
Table 14.7 SCI3 Interrupt Requests
Interrupt Requests
Abbreviation
Interrupt Sources
Receive Data Full
RXI
Setting RDRF in SSR
Transmit Data Empty
TXI
Setting TDRE in SSR
Transmission End
TEI
Setting TEND in SSR
Receive Error
ERI
Setting OER, FER, and PER in SSR
The initial value of the TDRE flag in SSR is 1. Thus, when the TIE bit in SCR3 is set to 1 before
transferring the transmit data to TDR, a TXI interrupt request is generated even if the transmit data
is not ready. The initial value of the TEND flag in SSR is 1. Thus, when the TEIE bit in SCR3 is
set to 1 before transferring the transmit data to TDR, a TEI interrupt request is generated even if
the transmit data has not been sent. It is possible to make use of the most of these interrupt
requests efficiently by transferring the transmit data to TDR in the interrupt routine. To prevent
the generation of these interrupt requests (TXI and TEI), set the enable bits (TIE and TEIE) that
correspond to these interrupt requests to 1, after transferring the transmit data to TDR.
Rev. 4.00 Mar. 15, 2006 Page 291 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
14.8
Usage Notes
14.8.1
Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RXD pin value
directly. In a break, the input from the RXD pin becomes all 0s, setting the FER flag, and possibly
the PER flag. Note that as the SCI3 continues the receive operation after receiving a break, even if
the FER flag is cleared to 0, it will be set to 1 again.
14.8.2
Mark State and Break Sending
When TE is 0, the TXD pin is used as an I/O port whose direction (input or output) and level are
determined by PCR and PDR. This can be used to set the TXD pin to mark state (high level) or
send a break during serial data transmission. To maintain the communication line at mark state
until TE is set to 1, set both PCR and PDR to 1. As TE is cleared to 0 at this point, the TXD pin
becomes an I/O port, and 1 is output from the TXD pin. To send a break during serial
transmission, first set PCR to 1 and clear PDR to 0, and then clear TE to 0. When TE is cleared to
0, the transmitter is initialized regardless of the current transmission state, the TXD pin becomes
an I/O port, and 0 is output from the TXD pin.
14.8.3
Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Transmission cannot be started when a receive error flag (OER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared
to 0.
Rev. 4.00 Mar. 15, 2006 Page 292 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
14.8.4
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 14 times the
transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock,
and performs internal synchronization. Receive data is latched internally at the rising edge of the
8th pulse of the basic clock as shown in figure 14.19. Thus, the reception margin in asynchronous
mode is given by formula (1) below.


1
D – 0.5
M = (0.5 –
)–
– (L – 0.5) F × 100(%)
2N
N


... Formula (1)
[Legend]
N: Ratio of bit rate to clock (N = 14)
D: Clock duty (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in
formula (1), the reception margin can be given by the formula.
M = {0.5 – 1/(2 × 14)} × 100 [%] = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed for in
system design.
16 clocks
8 clocks
0
7
15 0
7
15 0
Internal basic
clock
Receive data
(RxD)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 14.19 Receive Data Sampling Timing in Asynchronous Mode
Rev. 4.00 Mar. 15, 2006 Page 293 of 556
REJ09B0026-0400
Section 14 Serial Communication Interface 3 (SCI3)
Rev. 4.00 Mar. 15, 2006 Page 294 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
Section 15 Controller Area Network for Tiny (TinyCAN)
The TinyCAN is a module for controlling a controller area network (CAN) for realtime
communication in vehicular and industrial equipment systems, etc and conforms to the Bosch
2.0B active. For details on CAN specifications, refer to Bosch CAN Specification Version 2.0
1991, Robert Bosch GmbH.
15.1
Features
• CAN version: Conforms to Bosch 2.0B active
Communication systems: NRZ (Non-Return to Zero) system (with bit-stuffing function)
Broadcast communication system
Transmission path: Bidirectional 2-wire serial communication
Communication speed: Max. 1 Mbps
Data length: 0 to 8 bytes
• Data buffers
Four (one receive-only buffer and three buffers settable for transmission/reception)
• Data transmission
Mailbox (buffer) number order (high-to-low)
• Data reception
Message identifier match
Reception with message identifier masked
Supports four buffers for the filter mask
• CPU interrupt sources
Various error interrupts
Reset/Halt mode processing interrupt
Message reception interrupt
Message transmission interrupt
• TinyCAN operating modes
Software reset
Normal status (error-active, error-passive)
Bus off state
Configuration mode
Halt mode
Module standby mode
Rev. 4.00 Mar. 15, 2006 Page 295 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
• Other features
Standby mode can be cleared by falling edge detection of the HRXD pin.
The block diagram of the TinyCAN is shown in figure 15.1.
Mailboxes
MCn0, MCn4
to MCn7
(n = 0 to 3)
MDn0 to
MDn7
(n = 0 to 3)
HTXD
Temporary
buffer
HRXD
LAFMn
(n = 0 to 3)
MCR
REC
MBCR
TEC
TXPR
RXPR
GSR
TXCR
RFPR
TCR
TXACK
UMSR
TCIRR0/1
ABACK
MBIMR
TCIMR0/1
BCR0/1
Internal data bus
CDLC
TCMR
Port control
Interrupt generator
Interrupt request
[Legend]
MCR:
GSR:
TCR:
TCIRR0/1:
TCIMR0/1:
MBCR:
TXPR:
TXCR:
TXACK:
ABACK:
RXPR:
RFPR:
Master control register
General status register
Test control register
TinyCAN interrupt register 0/1
TinyCAN interrupt mask register 0/1
Mailbox configuration register
Transmit pending register
Transmit pending cancel register
Transmit acknowledge register
Abort acknowlege register
Data frame receive complete register
Remote request register
UMSR:
MBIMR:
BCR0/1:
TEC:
REC:
LAFMn:
MCn0, MCn4 to
MCn7:
MDn0 to MDn7:
TCMR:
CDLC:
Unread message status register
Mailbox interrupt mask register
Bit configuration register 0/1
Transmit error counter
Receive error counter
Local acceptance filter mask (n = 0 to 3)
Message control (n = 0 to 3)
Message data (n = 0 to 3)
TinyCAN module control register
CAN data link controller
The CDLC conforms to the Bosch CAN Ver. 2.0B active
standard, and performs transmission and reception
of messages, CRC checking, bus arbitration, etc.
Figure 15.1 TinyCAN Block Diagram
Rev. 4.00 Mar. 15, 2006 Page 296 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
15.2
Input/Output Pins
Table 15.1 shows the TinyCAN pin configuration.
TinyCAN pins must be configured in configuration mode (while the RSTRQ bit in MCR and the
RESET bit in GSR are both set to 1). A bus driver is necessary for the interface between the
TinyCAN pins and the CAN bus. A Renesas Technology HA13721 compatible model is
recommended.
Table 15.1 Pin Configuration
Name
Abbreviation
I/O
Function
TinyCAN transmit data pin
HTXD
Output
CAN bus transmission pin
TinyCAN receive data pin
HRXD
Input
CAN bus reception pin
15.3
Register Descriptions
The TinyCAN has the following registers.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Test control register (TCR)
Master control register (MCR)
TinyCAN module control register (TCMR)
General status register (GSR)
Bit configuration registers 0, 1 (BCR0, BCR1)
Mailbox configuration register (MBCR)
Transmit pending register (TXPR)
Transmit pending cancel register (TXCR)
Transmit acknowledge register (TXACK)
Abort acknowledge register (ABACK)
Data frame receive complete register (RXPR)
Remote request register (RFPR)
Unread message status register (UMSR)
TinyCAN interrupt registers 0, 1 (TCIRR0, TCIRR1)
Mailbox interrupt mask register (MBIMR)
TinyCAN interrupt mask registers 0, 1 (TCIMR0, TCIMR1)
Transmit error counter (TEC)
Receive error counter (REC)
Rev. 4.00 Mar. 15, 2006 Page 297 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
• Message control (MCn0, MCn4 to MCn7 [n = 0 to 3])
• Local acceptance filter mask (LAFMHn1, LAFMHn0, LAFMLn1, and LAFMLn0 [n = 0 to 3])
• Message data (MDn0 to MDn7 [n = 0 to 3])
15.3.1
Test Control Register (TCR)
TCR controls the CDLC test mode.
TCR must be configured in the initial state or in halt mode. For details, see section 15.7, Test
Mode Settings.
Bit
Bit Name
Initial
Value
R/W
Description
7
TSTMD
0
R/W
Test Mode
Enables or disables the test mode.
0: TinyCAN in normal mode
1: TinyCAN in test mode
6
WREC
0
R/W
CAN Error Counters Write Enable
Enables or disables write to TEC and REC.
0: TEC and REC can only be read
1: The same value can be written to CAN Error Counter
(TEC and REC) simultaneously (enabled only in test
mode)
5
FERPS
0
R/W
Force to Error Passive Mode
Enables to force to the error-passive state.
0: CAN Error Counter is determined by TEC/REC
1: TinyCAN behaves as the error-passive state
regardless of the TEC/REC value (enabled only in test
mode)
4
ATACK
0
R/W
Auto-Acknowledge
Enables generation of an auto-acknowledge bit in order
to execute the self-test.
0: Does not to generate its auto-acknowledge bit
1: Generates its auto-acknowledge bit (enabled only in
test mode)
Rev. 4.00 Mar. 15, 2006 Page 298 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
Bit
Bit Name
Initial
Value
R/W
Description
3
DEC
0
R/W
Error Count Disable Bit
Enables or disables the TEC and REC to be functional.
0: TEC and REC function according to CAN specification
1: TEC and REC is disabled to function (count value is
retained, enabled only in test mode)
2
DRXIN
0
R/W
HRXD Pin Input Enable
Enables or disables the HRXD pin to be supplied into the
CDLC.
0: Input from the CAN bus to the HRXD pin is enabled
1: Input from the CAN bus to the HRXD pin is disabled
(enabled only in test mode)
1
DTXOT
0
R/W
•
When INTLE = 0, the HRXD pin always holds
recessive data.
•
When INTLE = 1, data is input from the internal HTXD
to the HRXD pin.
HTXD Pin Output Enable
Enables or disables the HTXD pin to output the CAN bus.
0: Output from the HTXD pin to the CAN bus is enabled
1: Output from the HTXD pin to the CAN bus is disabled
(enabled only in test mode)
0
INTLE
0
R/W
•
When INTLE = 0, the HTXD pin always outputs
recessive data to the CAN bus.
•
When INTLE = 1, the internal HTXD outputs data to
the internal HRXD.
Internal Loop Enable
Enables or disables connection between the internal
HTXD and internal HRXD.
0: Internal HRXD is supplied from the HRXD pin
1: Internal HRXD is supplied from the internal HTXD
(enabled only in test mode)
Rev. 4.00 Mar. 15, 2006 Page 299 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
15.3.2
Master Control Register (MCR)
MCR controls a transition request to halt mode and a software reset request.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 2
—
All 0
R/W
Reserved
These bits are always read as 0.
1
HLTRQ
0
R/W
Halt Request
Halts communication between the TinyCAN and CAN
bus. Communication with the CAN bus can be resumed
by clearing this bit to 0 and then receiving 11 recessive
bits.
0: TinyCAN in normal mode
1: Halt mode is requested
0
RSTRQ
1
R/W
Reset Request
Controls a software reset of the TinyCAN. After a reset
has been requested and the initial state is entered, both
the RESET bit in GSR and the RHI bit in TCIRR0 are set
to 1. When this bit is cleared to 0, communication with the
CAN bus is resumed. After powering on, this bit and the
RESET bit are always set to 1.
0: TinyCAN in normal mode
1: Software reset of TinyCAN is requested
Rev. 4.00 Mar. 15, 2006 Page 300 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
15.3.3
TinyCAN Module Control Register (TCMR)
TCMR controls the configuration of module standby mode for the TinyCAN and selection of the
P97/HTXD and P96/HRXD pins.
Bit
Bit Name
Initial
Value
R/W
Description
7
MSTTC
0
R/W
TinyCAN Module Standby Control Bit
Controls the configuration of module standby mode for
the TinyCAN. When this bit is set to 1, the TinyCAN
makes a transition to module standby mode. At this time,
the values of the TinyCAN registers are preserved.
0: TinyCAN in normal mode
1: Module standby mode
6 to 2
—
All 0
—
Reserved
These bits are always read as 0.
1
PMR97
0
R/W
Port Mode Register 97
Selects a function of the P97/HTXD pin.
0: P97
1: HTXD
0
PMR96
0
R/W
Port Mode Register 96
Selects a function of the P96/HRXD pin.
0: P96
1: HRXD
Rev. 4.00 Mar. 15, 2006 Page 301 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
15.3.4
General Status Register (GSR)
GSR indicates the status of the CAN bus. Each bit in GSR is set or cleared to notify the CPU of
the TinyCAN status.
Bit
Bit Name
Initial
Value
R/W
Description
7, 6
—
All 0
—
Reserved
5
ERPS
0
R
These bits are always read as 0.
Error Passive Status Flag
Indicates whether the CDLC is in the error-passive state.
This flag is always set to 1 when the CDLC is in the errorpassive state or bus off state.
[Setting condition]
When TEC ≥ 128 or REC ≥ 128
[Clearing condition]
When the error-active state is entered
4
HALT
0
R
Halt Status Flag
Indicates whether the TinyCAN is in halt mode.
[Setting condition]
When the CAN bus receives an intermission frame or the
bus is idle with the HLTRQ bit in MCR set to 1
[Clearing condition]
When the HLTRQ bit is cleared to 0 and halt mode is
exited
3
RESET
1
R
Reset Status Flag
Indicates whether the TinyCAN is in reset mode.
[Setting condition]
When the TinyCAN is in the reset state
[Clearing condition]
When communication with the CAN bus is enabled after
the reset procedure completes
Rev. 4.00 Mar. 15, 2006 Page 302 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
Bit
Bit Name
Initial
Value
R/W
Description
2
TCMPL
1
R
Message Transmission Complete Flag
Indicates whether the TinyCAN has finished message
transmission.
[Setting condition]
When the TinyCAN has finished message transmission
[Clearing condition]
While a message is being transmitted (period from SOF
(start of frame) to the third bit of the intermission space)
1
ECWRG
0
R
Error Counter Warning Flag
Indicates an error warning.
[Setting condition]
When 96 ≤ TEC ≤ 256 or 96 ≤ REC ≤ 256
[Clearing condition]
When TEC< 96, REC < 96, or TEC ≥ 256
0
BOFF
0
R
Bus Off Flag
Indicates the bus off state.
[Setting condition]
When TEC ≥ 256 (bus off state)
[Clearing condition]
When the TinyCAN recovers from the bus off state
Rev. 4.00 Mar. 15, 2006 Page 303 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
15.3.5
Bit Configuration Registers 0, 1 (BCR0, BCR1)
BCR configures the CAN bit timing parameters and baud rate prescaler for the CDLC.
• BCR0
Bit
Bit Name
Initial
Value
R/W
Description
7
SJW1
0
R/W
Re-Synchronization Jump Width
6
SJW0
0
R/W
These bits set the maximum value of synchronization
width.
00: 1 time quantum
01: 2 time quanta
10: 3 time quanta
11: 4 time quanta
5
BRP5
0
R/W
Baud Rate Prescaler
4
BRP4
0
R/W
These bits set the clock used for time quanta.
3
BRP3
0
R/W
000000: Setting prohibited
2
BRP2
0
R/W
000001: 2 system clocks
1
BRP1
0
R/W
0
BRP0
0
R/W
111111: 64 system clocks
:
:
(BRP + 1) system clocks
• BCR1
Bit
Bit Name
Initial
Value
R/W
Description
7

0

Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 4.00 Mar. 15, 2006 Page 304 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
Bit
Bit Name
Initial
Value
R/W
Description
6
TSG22
0
R/W
Time Segment 2
5
TSG21
0
R/W
4
TSG20
0
R/W
This segment is used for correcting the error of 1 bit time.
The TSG2 width can be set within a range of 2 to 8 time
quanta.
000: Setting prohibited
001: PHSEG2 = 2 time quanta
010: PHSEG2 = 3 time quanta
011: PHSEG2 = 4 time quanta
100: PHSEG2 = 5 time quanta
101: PHSEG2 = 6 time quanta
110: PHSEG2 = 7 time quanta
111: PHSEG2 = 8 time quanta
3
TSG13
0
R/W
Time Segment 1
2
TSG12
0
R/W
1
TSG11
0
R/W
0
TSG10
0
R/W
This segment is used for absorbing the delay of the
output buffer, CAN bus, and input buffer. The TSG1 width
can be set within a range of 1 to 16 time quanta. TSG1
comprises PRSEG and PHSEG1 according to the CAN
specifications.
0000: Setting prohibited
0001: Setting prohibited
0010: Setting prohibited
0011: PRSEG + PHSEG1 = 4 time quanta
:
1111: PRSEG + PHSEG1 = 16 time quanta
Rev. 4.00 Mar. 15, 2006 Page 305 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
15.3.6
Mailbox Configuration Register (MBCR)
MBCR configures each Mailbox as either reception or transmission, except for the receive-only
Mailbox. Changing the corresponding bits for the receive-only Mailbox is ignored.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4
—
All 0
—
Reserved
3
MB3
0
R/W
2
MB2
0
R/W
These bits are configured for the corresponding
Mailboxes.
1
MB1
0
R/W
0: Corresponding Mailbox is configured as transmission
These bits are always read as 0.
1: Corresponding Mailbox is configured as reception
0
—
1
—
Reserved
This bit is always read as 1. This bit is relevant to the
receive-only Mailbox, and its value cannot be changed.
Rev. 4.00 Mar. 15, 2006 Page 306 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
15.3.7
Transmit Pending Register (TXPR)
TXPR sets transmit pending (CAN bus arbitration wait) for the transmit message that is stored in a
Mailbox. Setting the corresponding bit in TXPR to 1 enables a message to be transmitted. Writing
0 to the bit in TXPR is ignored.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4
—
All 0
—
Reserved
These bits are always read as 0.
3
MB3
0
R/W
[Setting condition]
2
MB2
0
R/W
1
MB1
0
R/W
When the corresponding MBCR bit for a mailbox is 0, the
corresponding bit in TXPR is set to 1
(n = 3 to 1)
[Clearing conditions]
•
When message transmission has completed
successfully (TXACKn set)
•
When transmission cancellation for an untransmitted
message has finished (ABACKn set)
•
When a transmission cancellation request has
occurred during message transmission, and an error
occurs or arbitration is lost on the CAN bus (ABACKn
set)
•
When a transmit error or arbitration loss occurred with
the corresponding DART bit for a message being
transmitted set to 1
If the message is not transmitted successfully, the MBn
bit is not cleared to 0. If any of these MB bits in TXPR are
cleared to 0, the EMPI bit in TCIRR1 is set to 1. The
TinyCAN automatically attempts retransmission as long
as the DART bit in the message control of the
corresponding Mailbox is not set to 1 or the
corresponding bit in TXCR is not set to 1.
Note:
0
—
0
—
When the MBn bit in MBCR is set to 1, the
TinyCAN does not transmit a message even if
the MBn bit in TXPR is set to 1. To clear the
MBn bit in TXPR to 0, set the MBn bit in TXCR
to 1 beforehand.
Reserved
This bit is always read as 0. This bit is relevant to the
receive-only Mailbox, and its value cannot be changed.
Rev. 4.00 Mar. 15, 2006 Page 307 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
15.3.8
Transmit Pending Cancel Register (TXCR)
TXCR cancels transmission of transmit pending messages in Mailboxes. By setting the TXCR bit
correspondent to TXPR, TXPR is cleared to 0. If the transmission has been canceled successfully,
the corresponding bits in both TXPR and TXCR are cleared to 0 and then the corresponding bit in
ABACK is set. Writing 0 to the bit in TXCR is ignored.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4
—
All 0
—
Reserved
3
MB3
0
R/W
[Setting condition]
2
MB2
0
R/W
The corresponding bit of a mailbox is set to 1
1
MB1
0
R/W
[Clearing condition]
These bits are always read as 0.
When the corresponding bit in TXPR is cleared (the
transmit message is canceled successfully)
Note: Writing 1 to these bits is enabled only when the
TXPR bit corresponding to Mailbox is set to 1.
0
—
0
—
Reserved
This bit is always read as 0. This bit is relevant to the
receive-only Mailbox, and its value cannot be changed.
15.3.9
Transmit Acknowledge Register (TXACK)
TXACK is a status flag that indicates the successful transmit completion of Mailbox transmit
messages.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4
—
All 0
—
Reserved
3
MB3
0
R/(W)* [Setting condition]
2
MB2
0
1
MB1
0
R/(W)* When transmission of the message in the corresponding
R/(W)* Mailbox has completed successfully
These bits are always read as 0.
[Clearing condition]
When 1 is written to these bits
Rev. 4.00 Mar. 15, 2006 Page 308 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
Bit
Bit Name
Initial
Value
R/W
0
—
0
—
Description
Reserved
This bit is always read as 0. This bit is relevant to the
receive-only Mailbox, and its value cannot be changed.
Note:
*
Only 1 can be written to clear the flag.
15.3.10 Abort Acknowledge Register (ABACK)
ABACK is a status flag that indicates successful cancellation of Mailbox transmit messages. If the
transmit request cancellation is completed, the bit in ABACK corresponding to the transmit
message is set to 1.
Bit
Bit Name
Initial
Value
R/W
7 to 4
—
All 0
—
Description
Reserved
These bits are always read as 0.
3
MB3
0
R/(W)* [Setting condition]
2
MB2
0
1
MB1
0
R/(W)* When cancellation of the transmit message in the
R/(W)* corresponding Mailbox has completed
[Clearing condition]
When 1 is written to these bits
0
—
0
—
Reserved
This bit is always read as 0. This bit is relevant to the
receive-only Mailbox, and its value cannot be changed.
Note:
*
Only 1 can be written to clear the flag.
Rev. 4.00 Mar. 15, 2006 Page 309 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
15.3.11 Data Frame Receive Complete Register (RXPR)
RXPR is a status flag that indicates the successful reception of data frame messages in the
corresponding Mailboxes. When the received data frame is successfully stored in the receive
Mailbox, the corresponding RXPR bit is set to 1. When a remote frame is received, the bit is not
set to 1.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4
—
All 0
—
Reserved
These bits are always read as 0.
3
MB3
0
R/(W)* [Setting condition]
2
MB2
0
1
MB1
0
R/(W)* When the corresponding Mailbox has completed
R/(W)* reception of a data frame
0
MB0
0
Note:
*
R/(W)* [Clearing condition]
When 1 is written to these bits
Only 1 can be written to clear the flag.
15.3.12 Remote Request Register (RFPR)
RFPR is a status flag that indicates successful reception of remote frames in the corresponding
Mailboxes. When a data frame is received, the corresponding RFPR bit is not set to 1.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4
—
All 0
—
Reserved
These bits are always read as 0.
3
MB3
0
R/(W)* [Setting condition]
2
MB2
0
1
MB1
0
R/(W)* When the corresponding Mailbox has completed
R/(W)* reception of a remote frame
0
MB0
0
Note:
*
R/(W)* [Clearing condition]
When 1 is written to these bits
Only 1 can be written to clear the flag.
Rev. 4.00 Mar. 15, 2006 Page 310 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
15.3.13 Unread Message Status Register (UMSR)
UMSR is a status flag that indicates that an unread message in each Mailbox has been overwritten
by a new receive message or a new receive message has been discarded.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4
—
All 0
—
Reserved
3
MB3
0
2
MB2
0
R/(W)* Status flags indicating that a new receive message has
R/(W)* overwritten/overrun an unread message.
1
MB1
0
0
MB0
0
These bits are always read as 0.
R/(W)* [Setting condition]
R/(W)* When a new message is received before the
corresponding bit in RXPR or RFPR is cleared to 0
[Clearing condition]
When 1 is written to these bits
Note:
*
Only 1 can be written to clear the flag.
Rev. 4.00 Mar. 15, 2006 Page 311 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
15.3.14 TinyCAN Interrupt Registers 0, 1 (TCIRR0, TCIRR1)
TCIRR is a status flag for each interrupt source.
• TCIRR0
Bit
Bit Name
Initial
Value
R/W
7
OVLI
0
R/(W)* Overload Frame Transmit Interrupt Flag
Description
Status flag indicating that the TinyCAN has transmitted
an overload frame.
[Setting condition]
When an overload frame is transmitted
[Clearing condition]
When 1 is written to this bit
6
BOFI
0
R/(W)* Bus Off Interrupt Flag
Status flag indicating the bus off state caused by the TEC
or recovery from the bus off state to the error-active state.
[Setting condition]
When TEC ≥ 256 or when 11 bits are received for 128
times in the bus off state
[Clearing condition]
When 1 is written to this bit
5
EPI
0
R/(W)* Error Passive Interrupt Flag
Status flag indicating the error-passive state caused by
REC or TEC.
[Setting condition]
When TEC ≥ 128 or REC ≥ 128
[Clearing condition]
When 1 is written to this bit
4
ROWI
0
R/(W)* Receive Overload Warning Interrupt Flag
Status flag indicating the error warning state caused by
REC.
[Setting condition]
When REC ≥ 96
[Clearing condition]
When 1 is written to this bit
Rev. 4.00 Mar. 15, 2006 Page 312 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
Bit
Bit Name
Initial
Value
R/W
3
TOWI
0
R/(W)* Transmit Overload Warning Interrupt Flag
Description
Status flag indicating the error warning state caused by
TEC.
[Setting condition]
When TEC ≥ 96
[Clearing condition]
When 1 is written to this bit
2
RFRI
0
R
Remote Frame Request Interrupt Flag
Status flag indicating that a remote frame has been
received in a Mailbox.
[Setting condition]
When remote frame reception is completed, and the
corresponding MBIMR bit is 0
[Clearing condition]
When all bits in RFPR are cleared to 0
1
DFRI
0
R
Data Frame Receive Message Interrupt Flag
Status flag indicating that a data frame has been received
in a Mailbox.
[Setting condition]
When message reception is completed, and the
corresponding MBIMR bit is 0
[Clearing condition]
When all bits in RXPR are cleared to 0
0
RHI
1
R/(W)* Reset/Halt Interrupt Flag
Status flag indicating that the TinyCAN has been reset or
has entered halt mode.
[Setting condition]
When each processing has finished after a software reset
request (RSTRQ = 1) or a halt mode request (HLTRQ =
1)
[Clearing condition]
When 1 is written to this bit
Note:
*
Only 1 can be written to clear the flag.
Rev. 4.00 Mar. 15, 2006 Page 313 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
• TCIRR1
Bit
Bit Name
Initial
Value
R/W
Description
7 to 5
—
All 0
—
Reserved
4
WUPI
0
R/(W)* Wakeup Interrupt Flag
These bits are always read as 0.
Status flag indicating detection of a dominant bit on the
CAN bus while the LSI is in standby mode. This flag can
be set to 1 only in standby mode.
[Setting condition]
When the falling edge of HRXD is detected in standby
mode
[Clearing condition]
When 1 is written to this bit
3, 2
—
All 0
—
Reserved
These bits are always read as 0.
1
OVRI
0
R
Unread Message Interrupt Flag
Status flag indicating that a new message has been
received regardless of existence of an unread message.
The NMC bit in MCn0 (n = 0 to 3) will determine how to
handle the newly received message: NMC = 1 selects
overwrite and NMC = 0 selects overrun (ignore).
[Setting condition]
When a new message is received with the MBIMR
corresponding to the receive message cleared to 0 and
the corresponding bit in RXPR or RFPR set to 1
[Clearing condition]
When all bits in UMSR are cleared to 0
0
EMPI
0
R
Mailbox Empty Interrupt Flag
Status flag indicating that the next transmit message can
be written to the Mailbox.
[Setting condition]
When TXPR is cleared to 0 by completion of transmission
or completion of transmission cancellation
[Clearing condition]
When TXACK and ABACK is cleared to 0
Note:
*
Only 1 can be written to clear the flag.
Rev. 4.00 Mar. 15, 2006 Page 314 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
15.3.15 Mailbox Interrupt Mask Register (MBIMR)
MBIMR controls enabling or disabling of individual Mailbox interrupt requests. Setting and
clearing each status flag has nothing to do with the configuration of bits in MBIMR.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4
—
All 1
—
Reserved
3
MB3
1
R/W
2
MB2
1
R/W
1
MB1
1
R/W
0
MB0
1
R/W
These bits are always read as 1.
These flags enable or disable individual Mailbox interrupt
requests.
The interrupt source in a transmit Mailbox is clearing of
the corresponding bit in TXPR caused by transmission
end or transmission cancellation. The interrupt source in
a receive Mailbox is setting of the corresponding bit in
RXPR or RFPR caused by reception end.
0: An interrupt request in the corresponding Mailbox is
enabled
1: An interrupt request in the corresponding Mailbox is
disabled
15.3.16 TinyCAN Interrupt Mask Registers 0, 1 (TCIMR0, TCIMR1)
TCIMR controls enabling or disabling of TCIRR interrupt requests. When the corresponding bit is
set to 1, the interrupt request is masked. This register corresponds to TCIRR.
• TCIMR0
Bit
Bit Name
Initial
Value
R/W
Description
7
OVLIM
1
R/W
Overload Frame Transmit Interrupt Mask
Enables or disables an interrupt request for overload
frame transmission.
0: The interrupt request for the overload frame
transmission is enabled
1: The interrupt request for the overload frame
transmission is disabled
Rev. 4.00 Mar. 15, 2006 Page 315 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
Bit
Bit Name
Initial
Value
R/W
Description
6
BOFIM
1
R/W
Bus Off Interrupt Mask
Enables or disables a bus-off interrupt request.
0: The bus-off interrupt request is enabled
1: The bus-off interrupt request is disabled
5
EPIM
1
R/W
Error Passive Interrupt Mask
Enables or disables an error passive interrupt request.
0: The error passive interrupt request is enabled
1: The error passive interrupt request is disabled
4
ROWIM
1
R/W
Receive Overload Warning Interrupt Mask
Enables or disables an interrupt request for a receive
overload warning.
0: The interrupt request for the receive overload warning
is enabled
1: The interrupt request for the receive overload warning
is disabled
3
TOWIM
1
R/W
Transmit Overload Warning Interrupt Mask
Enables or disables an interrupt request for a transmit
overload warning.
0: The interrupt request for the transmit overload warning
is enabled
1: The interrupt request for the transmit overload warning
is disabled
2
RFRIM
1
R/W
Remote Frame Request Interrupt Mask
Enables or disables an interrupt request for a remote
frame request.
0: The interrupt request for the remote frame request is
enabled
1: The interrupt request for the remote frame request is
disabled
1
DFRIM
1
R/W
Data Frame Receive Message Interrupt Mask
Enables or disables an interrupt request for a data frame
receive message.
0: The interrupt request for the data frame receive
message is enabled
1: The interrupt request for the data frame receive
message is disabled
Rev. 4.00 Mar. 15, 2006 Page 316 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
Bit
Bit Name
Initial
Value
R/W
Description
0
RHIM
1
R/W
Reset/Halt Interrupt Mask
Enables or disables a reset/halt interrupt request.
0: The reset/halt interrupt request is enabled
1: The reset/halt interrupt request is disabled
• TCIMR1
Bit
Bit Name
Initial
Value
R/W
7 to 5
—
All 1
—
Description
Reserved
These bits are always read as 1.
4
WUPIM
1
R/W
Wakeup Interrupt Mask
Enables or disables a wakeup interrupt request.
0: The wakeup interrupt request is enabled
1: The wakeup interrupt request is disabled
3, 2
—
All 1
—
Reserved
These bits are always read as 1.
1
OVRIM
1
R/W
Unread Message Interrupt Mask
Enables or disables an interrupt request for an unread
message.
0: The interrupt request for the unread message is
enabled
1: The interrupt request for the unread message is
disabled
0
EMPIM
1
R/W
Mailbox Empty Interrupt Mask
Enables or disables an interrupt request for mailbox
empty.
0: The interrupt request for mailbox empty is enabled
1: The interrupt request for mailbox empty is disabled
Rev. 4.00 Mar. 15, 2006 Page 317 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
15.3.17 Transmit Error Counter (TEC)
TEC counts the number of transmit message errors on the CAN bus.
Bit
Bit Name
Initial
Value
R/W
Description
7
TEC7
0
R/W*
6
TEC6
0
R/W*
5
TEC5
0
R/W*
4
TEC4
0
R/W*
3
TEC3
0
R/W*
TEC functions as a counter indicating the number of
transmit message errors on the CAN bus. The count
value is stipulated in the CAN protocol. In normal
operation, TEC can only be read, but can only be
modified by the CDLC. TEC is cleared to 0 by a reset
request (MCR.RSTRQ = 1) or on entering the bus off
state.
2
TEC2
0
R/W*
1
TEC1
0
R/W*
0
TEC0
0
R/W*
Note:
*
TEC can be written to in test mode (TCR.TSTMD = 1 and
TCR.WREC = 1). The same value can be written to both
TEC and REC. TEC should be written to in halt mode. In
other modes, a CAN bus communication error may occur
depending on the TEC value. Note that TEC can be
written to only in test mode.
TEC can be written to only in test mode (TCR.TSTMD = 1 and TCR.WREC = 1). The
same value should be written to TEC and REC.
15.3.18 Receive Error Counter (REC)
REC counts the number of receive message errors on the CAN bus.
Bit
Bit Name
Initial
Value
R/W
Description
7
REC7
0
R/W*
6
REC6
0
R/W*
5
REC5
0
R/W*
4
REC4
0
R/W*
3
REC3
0
R/W*
REC functions as a counter indicating the number of
receive message errors on the CAN bus. The count value
is stipulated in the CAN protocol. In normal operation,
REC can only be read, but can only be modified by the
CDLC. REC is cleared to 0 by a reset request
(MCR.RSTRQ = 1) or on entering the bus off state.
2
REC2
0
R/W*
1
REC1
0
R/W*
0
REC0
0
R/W*
Note:
*
REC can be written to in test mode (TCR.TSTMD = 1 and
TCR.WREC = 1). The same value can be written to both
TEC and REC. REC should be written to in halt mode. In
other modes, a CAN bus communication error may occur
depending on the REC value. Note that REC can be
written to only in test mode.
REC can be written to only in test mode (TCR.TSTMD = 1 and TCR.WREC = 1). The
same value should be written to TEC and REC.
Rev. 4.00 Mar. 15, 2006 Page 318 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
15.4
Message Data and Control
Each Mailbox has a storage area for control information and transmitted or received.
15.4.1
Message Control (MCn0, MCn4 to MCn7 [n = 0 to 3])
The message control configures the arbitration field and control field of the data frames and
remote frames. The bit names in MCn0 and MCn4 to MCn7 correspond to the bit names of each
frame. Since the MCn0 and MCn4 to MCn7 (n = 0 to 3) are in RAM, the initial values are
undefined after power-on. Be sure to initialize these bits by writing 0 or 1.
Control field
Arbitration field
Standard
format
SOF
ID28
ID27
•••
ID18
RTR
IDE
R0
Data field or CRC field
DLC
(Standard ID)
Control field
Arbitration field
Extended
format
SOF
ID28
ID27 • • •
(Standard ID)
ID18
SSR
IDE
Data field or CRC field
ID17
ID16
•••
(Extended ID)
ID0
RTR
R1
R0
DLC
(R0 and R1 bits are reserved)
Figure 15.2 Standard Format and Extended Format
Rev. 4.00 Mar. 15, 2006 Page 319 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
Register
Name
MCn[0]
(n = 0 to 3)
Bit
Bit Name
R/W
Description
7
DART
R/W
Automatic Retransmission Disable
When this bit is set to 1,the message disables to be
retransmitted in the event of an error on CAN bus or
an arbitration lost on CAN bus.
0: Automatic retransmission is carried out
1: Automatic retransmission is prohibited
6
NMC
R/W
New Message Control
When a Mailbox with an unread message receives a
new message, this bit selects whether to overrun or
overwrite the unread message with the new message.
0: The new receive message is ignored and the
unread message is saved, and the corresponding
UMSR bit is set to 1 (overrun)
1: The unread message is lost by being overwritten
with the new receive message, and the
corresponding UMSR bit is set to 1 (overwrite)
5, 4
—
—
Reserved
These bits are always read as 0.
3 to 0
DLC3 to
DLC0
R/W
Data Length Code
These bits set the transmit data length of data frames
and data length requested by remote frames. These
bits are stipulated in Bosch 2.0B active.
0000: 0 bytes
0001: 1 byte
0010: 2 bytes
0011: 3 bytes
0100: 4 bytes
0101: 5 bytes
0110: 6 bytes
0111: 7 bytes
1xxx: 8 bytes
MCn[4]
(n = 0 to 3)
7 to 5
ID20 to
ID18
R/W
Rev. 4.00 Mar. 15, 2006 Page 320 of 556
REJ09B0026-0400
These bits set bits 2 to 0 in the standard identifier of
data frames and remote frames.
Section 15 Controller Area Network for Tiny (TinyCAN)
Register
Name
MCn[4]
(n = 0 to 3)
Bit
Bit Name
R/W
Description
4
RTR
R/W
Remote Transmission Request
Distinguishes between data frame and remote frame.
0: Data frame
1: Remote frame
3
IDE
R/W
Identifier Extension
Distinguishes between standard format and extended
format.
0: Standard format
1: Extended format
2
—
—
Reserved
This bit is always read as 0.
1, 0
ID17, ID16
R/W
These bits set bits 17 and 16 of the extended
identifier and are stipulated in Bosch 2.0B active.
MCn[5]
(n = 0 to 3)
7 to 0
ID28 to
ID21
R/W
These bits set bits 10 to 3 of the standard identifier
and are stipulated in Bosch 2.0B active.
MCn[6]
(n = 0 to 3)
7 to 0
ID7 to ID0
R/W
These bits set bits 7 to 0 of the extended identifier
and are stipulated in Bosch 2.0B active.
MCn[7]
(n = 0 to 3)
7 to 0
ID15 to ID8 R/W
These bits set bits 15 to 8 of the extended identifier
and are stipulated in Bosch 2.0B active.
Rev. 4.00 Mar. 15, 2006 Page 321 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
15.4.2
Local Acceptance Filter Mask (LAFMHn1, LAFMHn0, LAFMLn1, LAFMLn0
[n = 0 to 3])
LAFM consists of four registers for one Mailbox. LAFM filters mask of bit-unit comparison
between the message identifier of RXn (n = 0 to 3) stored in the receive Mailbox and the receive
message identifier. Since LAFM is in RAM, initial values are undefined after power-on. Be sure
to initialize each bit by writing 0 or 1.
Register
Name
LAFMLn1
(n = 0 to 3)
Bit
Bit Name
R/W
Description
7 to 0
LAFMLn7 to
LAFMLn0
R/W
Filter mask for bits 7 to 0 of the extended identifier.
0: Receive message is stored in RXn because the
RXn message identifier bits match the receive
message identifier bits
1: Receive message is stored in RXn regardless of
whether the RXn message identifier bits match
the receive message identifier bits
LAFMLn0
(n = 0 to 3)
7 to 0
LAFMLn15 to
LAFMLn8
R/W
Filter mask for bits 15 to 8 of the extended
identifier.
0: Receive message is stored in RXn because the
RXn message identifier bits match the receive
message identifier bits
1: Receive message is stored in RXn regardless of
whether the RXn message identifier bits match
the receive message identifier bits
LAFMHn1
(n = 0 to 3)
7 to 5
LAFMHn7 to
LAFMHn5
R/W
Filter mask for bits 2 to 0 of the standard identifier.
0: Receive message is stored in RXn because the
RXn message identifier bits match the receive
message identifier bits
1: Receive message is stored in RXn regardless of
whether the RXn message identifier bits match
the receive message identifier bits
Rev. 4.00 Mar. 15, 2006 Page 322 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
Register
Name
LAFMHn1
(n = 0 to 3)
Bit
Bit Name
R/W
Description
4 to 2
—
—
Reserved
These bits are always read as 0.
1, 0
LAFMHn1,
LAFMHn0
R/W
Filter mask for bits 17 and 16 of the extended
identifier.
0: Receive message is stored in RXn because the
RXn message identifier bits match the receive
message identifier bits
1: Receive message is stored in RXn regardless of
whether the RXn message identifier bits match
the receive message identifier bits
LAFMHn0
(n = 0 to 3)
7 to 0
LAFMHn15 to R/W
LAFMHn8
Filter mask for bits 10 to 3 of the standard
identifier.
0: Receive message is stored in RXn because the
RXn message identifier bits match the receive
message identifier bits
1: Receive message is stored in RXn regardless of
whether the RXn message identifier bits match
the receive message identifier bits
15.4.3
Message Data (MDn0 to MDn7 [n = 0 to 3])
The message data is configured as eight 8-bit registers for a single Mailbox. The transmit and
receive data are stored from byte 0 in the low-to-high order. The TinyCAN has four sets of
message data. The bit order on the CAN bus is from 1 to 8 bytes. Since MDn0 to MDn7 (n = 0 to
3) are in RAM, initial values are undefined after power-on. Be sure to initialize these bits by
writing 0 or 1.
Mailbox 0
MD0[0]
MD0[1]
MD0[2]
MD0[3]
MD0[4]
MD0[5]
MD0[6]
MD0[7]
Mailbox 1
MD1[0]
MD1[1]
MD1[2]
MD1[3]
MD1[4]
MD1[5]
MD1[6]
MD1[7]
Mailbox 2
MD2[0]
MD2[1]
MD2[2]
MD2[3]
MD2[4]
MD2[5]
MD2[6]
MD2[7]
Mailbox 3
MD3[0]
MD3[1]
MD3[2]
MD3[3]
MD3[4]
MD3[5]
MD3[6]
MD3[7]
Figure 15.3 Message Data Configuration
Rev. 4.00 Mar. 15, 2006 Page 323 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
15.5
Operation
15.5.1
TinyCAN Initial Settings
Figure 15.4 shows a flowchart for reset clearing of the TinyCAN. After a reset is cleared, all
registers are initialized.
Configuration mode
23 clocks
Reset *1
RESET in
Clear RSTRQ in MCR to 0
Clear RHI in TCIRR0 to 0
Clear necessary bit in
TCIMR to 0
Set Mailboxes
(ID, DLC,
RTR, IDE, MBCR, DART,
LAFM, MDn0 to MDn7
[n = 0 to 3])
GSR*3
= 0?
No
Yes
Normal operation
11 recessive
bits received
continuously?
No
Yes
Reception*4
Transmission*5
Set PMR97 and PMR96 in
TCMR*2
Set BCR0 and BCR1*2
Notes: 1. The TinyCAN is reset at any time when the RSTRQ bit in MCR is set to 1.
2. The PMR97 and PMR96 bits in TCMR should be set after Mailboxes and LAFM have been
initialized. Then BCR1 and BVR0 should be set.
The TinyCAN starts communication with the CAN bus after BCR1 and BVR0 have been set.
3. The RESET bit in GSR is a status flag that indicates CAN bus communication is possible
after reset procedure. This bit is cleared to 0 when 23 clock cycles are elapsed after BCR0 and
BCR1 have been set.
4. The TinyCAN receives messages when MBCR and TXPR are not set.
5. When MBCR and TXPR are set, the TinyCAN starts message transmission
and carries out CAN bus arbitration. If an arbitration loss occurs, receive
operation starts.
Figure 15.4 Reset Clearing Flowchart
Rev. 4.00 Mar. 15, 2006 Page 324 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
15.5.2
Bit Timing
The bit rate and bit timing are set by the bit configuration register (BCR). The CAN controllers
connected to the CAN bus should be set so that all of them have the same baud rate and same bit
width. One bit time consists of total settable Time Quantum (TQ).
1 bit time (8 to 25 time quanta)
Sampling point
SYNC_SEG
PRSEG
PHSEG1
PHSEG2
Time segment 1 (TSG1)
Time segment 2
(TSG2)
4 to 16 time quanta
2 to 8 time quanta
1 time quantum
Figure 15.5 CAN Bit Configuration
The SYNC_SEG is a segment for establishing the synchronization of nodes on the CAN bus.
Normal bit edge changes in this segment. The PRSEG is a segment for adjusting the physical
delay between networks. The PHSEG1 is a buffer segment for adjusting positive phase drift. This
segment is extended when re-synchronization is established. The PHSEG2 is a buffer segment for
adjusting negative phase drift. This segment is shortened when re-synchronization is established.
The range of settable values in BCR (TSG1, TSG2, BRP, and SJW) is shown in table 15.2.
Table 15.2 Settable Values in BCR
Name
Abbreviation
TSG1*
1
Time segment 2
TSG2*
1
Baud rate prescaler
BRP
Time segment 1
Re-Synchronization Jump width
SJW*
2
Min. Value
Max. Value
3
15
1*
4
7
1
63
0
3
3*
Notes: 1. The time quanta values for the TSEG1 and TSEG2 are as follows: TSG value + 1
2. In the CAN specifications, the Re-Synchronization Jump Width is stipulated as
4 ≥ SJW ≥ 1. The value of SJW is given by adding 1 to the setting value of the bits
SJW0 to SJW1 in BCR.
3. The minimum value of TSG1 is stipulated in the CAN specifications:
TSG1 > TSG2
4. The minimum value of TSG2 is stipulated in the CAN specifications:
TSG2 ≥ SJW
Rev. 4.00 Mar. 15, 2006 Page 325 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
Time Quantum (TQ) is an integer multiple of the number of system clocks, and is determined by
the baud rate prescaler (BRP) as follows. φ means the system clock frequency.
TQ = (BRP + 1)/φ
The following formula is used to calculate the 1-bit time and bit rate.
1-bit time = TQ × {1 + (1 + TSG1) + (1 + TSG2)}
Bit rate = 1/Bit time
= φ/{(BRP + 1) × {1 + (1 + TSG1) + (1 + TSG2)}}
Values that can be set for TSG1 and TSG2 in BCR1 are listed in table 15.3.
Table 15.3 Settable Values for TSG1 and TSG2 in BCR1
TSG2
TSG1
[Legend]
001
010
011
100
101
110
111
0011
No
0100
Yes
Yes
No
No
No
No
No
Yes
Yes
No
No
No
No
0101
Yes
Yes
Yes
Yes
No
No
No
0110
Yes
Yes
Yes
Yes
Yes
No
No
0111
Yes
Yes
Yes
Yes
Yes
Yes
No
1000
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1001
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1010
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1011
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1100
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1101
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1110
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1111
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes: Setting is possible
No: Setting is prohibited
[Example]
To have a baud rate of 1 Mbps with φ = 16 MHz, BRP = 1, and (1 + TSG1) + (1 + TSG2) = 7. In
this case, the settings are BCR1 = H′23 and BCR0 = H'01.
Rev. 4.00 Mar. 15, 2006 Page 326 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
15.5.3
Message Transmission
Message Transmission Request: Figure 15.6 shows a transmission flowchart.
TinyCAN in normal mode
(MBn in MBCR = 0)
Update data in Mailbox n
(n = 1 to 3)
Write 1 to MBn in TXPR
Internal arbitration determination
Transmission pending?
Yes
MBn in TXCR = 1?
No
No
Yes
Transmission start
Error detected or
CAN bus arbitration lost?
Yes
DART = 1?
or
MBn in TXCR = 1?
No
Yes
No
Transmission completed
• Clear MBn in TXPR to 0
• Set MBn in TXACK to 1
• Mailbox empty interrupt (EMPI)
occurred (when EMPIM = 0)
Transmission canceled
• Clear MBn in TXPR to 0
• Clear MBn in TXCR to 0 (when MBn in TXCR = 1)
• Set MBn in ABACK to 1
• Mailbox empty interrupt (EMPI) occurred
(when EMPIM = 0)
Read TCIRR
EMPI in TCIRR1 = 1?
No
Other interrupt processing
No
Read 1 from MBn in ABACK
Yes
MBn in TXACK = 1?
Yes
Clear MBn in TXACK to 0
Clear MBn in ABACK to 0
Clear EMPI in TCIRR1 to 0
Clear EMPI in TCIRR1 to 0
Read 0 from MBn in TXACK
Read 0 from MBn in ABACK
Transmit processing for
Mailbox n completed
Note: Processing in a shaded box requires setting by software.
Figure 15.6 Transmission Request Flowchart
Rev. 4.00 Mar. 15, 2006 Page 327 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
Internal Arbitration at Transmission: The TinyCAN transmits untransmitted messages in the
priority order from Mailbox 3 to Mailbox 1. The internal arbitration function selects the Mailbox
with the highest priority among all transmission request messages. Internal arbitration is based on
the three sources given below.
• TXPR/TXCR is set
• Arbitration lost during message transmission
• CAN bus error
TXPR/TXCR Setting: Figure 15.7 shows the timing of the TinyCAN internal arbitration caused
by the TXPR/TXCR setting. Transmit procedure and operation are as follows.
1. Write data of a transmit message to MCn0, MCn4 to MCn7, and MDn0 to MDn7 [n = 1 to 3]
before clearing the MBn bit in MBCR corresponding to the Mailbox of the transmit message to
0 (initial setting).
2. Set the corresponding MBn bit in TXPR to 1 (start condition issuance). Then, the start
condition is generated.
3. The internal arbitration for message 1 is determined and the transmit message is transferred to
the temporary buffer. After that, even if a transmit request cancellation is issued to the message
being transmitted by the DART or MBn bit in TXCR, message 1 is transmitted continuously
unless the TinyCAN detects an arbitration loss or error on the CAN bus.
4. After the seventh bit of the EOF has been transmitted (normal message transmission end), the
MBn bits in TXPR and TXCR which are corresponding Mailbox are cleared to 0 and the MBn
bit in TXACK and the EMPI bit in TCIRR1 are set to 1. At this time, the MBn bit in ABACK
is always 0. Then, message transmission is completed.
5. When there is a transmit request other than for message 1, the transmit message is transferred
to the temporary buffer and transmitted to the CAN bus after the arbitration for message 2 has
been determined. When there is no transmit request other than for message 1, the TinyCAN
performs reception.
Rev. 4.00 Mar. 15, 2006 Page 328 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
Message 1
HRXD
Bus idle
HTXD
Bus idle
SOF
Arbitration
Control
Data
Message 2
CRC
ACK
EOF
Intermission
Message 1
SOF
Arbitration
Control
Data
SOF
Message 2
CRC
ACK
EOF
Intermission
MBn in TXPR
[4] Clear MBn in TXPR and MBn in TXCR
MBn in TXCR
MBn in TXACK
[4] Set MBn in TXACK and EMPI in TCIRR1
EMPI in TCIRR1
MBn in ABACK
Transmission for message 1 cannot be cancelled by TXCR
Internal arbitration for message 2 can be configurable
(Transmission settings can be changed by TXPR/TXCR)
[2] Set TXPR
[3] Set MBn bit in TXCR immediately after internal arbitration
for message 1 has been determined
Transmission for message 2
cannot be cancelled by TXCR
Internal arbitration for message 3
can be configurable
[5] Internal arbitration for message 2
is determined
Figure 15.7 Internal Arbitration at Transmission Caused by TXCR/TXPR Setting
Arbitration Lost during Message Transmission: If an arbitration loss on the CAN bus occurs,
the TinyCAN halts transmission, and starts message reception. If the DART bit for the
transmission-requested message is cleared to 0, on the completion of reception, the transmissionrequested message is retransmitted. However, if the DART bit is set to 1, it is not transmitted in
frame 2. Figures 15.8 to 15.10 show the timings of the arbitration loss on the CAN bus. Procedure
and operation are as follows.
1. Write data of a transmit message to MCn0, MCn4 to MCn7, and MDn0 to MDn7 [n = 1 to 3]
before clearing the MBn bit in MBCR corresponding to the Mailbox of the transmit message to
0 (initial setting).
2. Set the corresponding MBn bit in TXPR to 1 (start condition issuance). Then, the start
condition is generated.
3. The internal arbitration for message 1 is determined and the transmit message is transferred to
the temporary buffer. After that, even if a transmit request cancellation is issued to the message
being transmitted by the DART or MBn bit in TXCR, message 1 is transmitted continuously
unless the TinyCAN detects an arbitration loss or error on the CAN bus.
Rev. 4.00 Mar. 15, 2006 Page 329 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
4. If an arbitration loss occurs in the arbitration field, the TinyCAN starts reception. When the
DART or MBn bit in TXCR is set to 1, a transmit request for message 1 is canceled. At this
time, the MBn bits in TXPR and TXCR are cleared to 0 and the MBn bit in ABACK and the
EMPI bit in TCIRR1 are set to 1. The MBn bit in TXACK is always 0.
5. When there is a transmit request after reception has completed (for details, see section 15.5.4,
Message Reception), the arbitration for message 2 is determined and it is transmitted to the
CAN bus. When there is no transmit request, the TinyCAN starts reception.
Message 1
Message 2
Bus idle
HRXD
SOF
Arbitration
Control
Data
CRC
ACK
EOF
Intermission
[4] Arbitration loss
Bus idle
HTXD
SOF
Arbitration
ACK bit
SOF
Message 2
Intermission
SOF
MBn in TXPR
MBn in TXCR
DART
MBn in ABACK
EMPI in TCIRR1
Transmission for message 1
cannot be cancelled by TXCR
Message 1 reception
Internal arbitration for message 2 can be configurable
(Transmission settings can be changed by TXPR/TXCR)
[2] Set TXPR
[3] Internal arbitration for message 1
is determined
Transmission for message 2
cannot be cancelled by TXCR
Internal arbitration for message 3
can be configurable
[5] Internal arbitration for message 2
is determined after normal reception
has completed
Figure 15.8 Internal Arbitration at Reception Caused by CAN Bus Arbitration Loss
(MBn in TXCR = 0 and DART = 0)
Rev. 4.00 Mar. 15, 2006 Page 330 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
Message 1
Message 2
Bus idle
HRXD
SOF
Arbitration
Control
Data
CRC
ACK
EOF
Intermission
[4] Arbitration loss
Bus idle
HTXD
SOF
Arbitration
SOF
Message 2
ACK bit
MBn in TXPR
[4] Clear MBn in TXPR and MBn in TXCR for message 1
MBn in TXCR
DART
MBn in ABACK
[4] Set MBn in ABACK and EMPI in TCIRR1 for message 1
EMPI in TCIRR1
MBn in TXACK
Transmission for message 1
cannot be cancelled by TXCR
Message 1 reception
Internal arbitration for message 2 can be configurable
(Transmission settings can be changed by TXPR/TXCR)
[2] Set TXPR
[3] Set MBn in TXCR after internal arbitration
for message 1 has been determined
Transmission for message 2
cannot be cancelled by TXCR
Internal arbitration for message 3
can be configurable
[5] Internal arbitration for message 2
is determined after normal reception
has completed
If other Mailbox has a transmit
request, transmission is started at this
timing
Figure 15.9 Internal Arbitration at Reception Caused by CAN Bus Arbitration Loss
(MBn in TXCR = 1)
Rev. 4.00 Mar. 15, 2006 Page 331 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
Message 1
HRXD
Bus idle
SOF
Arbitration
Control
Data
Message 2
CRC
ACK
EOF
Intermission
SOF
[4] Arbitration loss
HTXD
Bus idle
SOF
Arbitration
ACK Bit
TXPR.MBn
[4] Clear MBn bit in TXPR for message 1
TXCR.MBn
[5] Overwrite DART bit for message 2
DART
ABACK.MBn
[4] Set MBn in ABACK and EMPI in TCIRR1 for message 1
TCIRR.EMPI
TXACK.MBn
Transmission for message 1
cannot be cancelled by TXCR
Message 1 reception
Internal arbitration for message 2 can be configurable
(Transmission settings can be changed by TXPR/TXCR)
[2] Set TXPR
[3] Load DART bit when message 1
is transferred to temporary buffer
Transmission for message 2
cannot be cancelled by TXCR
Internal arbitration for message 3
can be configurable
[5] Internal arbitration for message 2
is determined after normal reception
has completed
If other Mailbox has a transmit
request, transmission is started at this
timing
Figure 15.10 Internal Arbitration at Reception Caused by CAN Bus Arbitration Loss
(DART = 1)
CAN Bus Error: Figures 15.11 to 15.13 show timings for internal arbitration caused by an error
on the CAN bus. Procedure and operation are as follows.
1. Write data of a transmit message to MCn0, MCn4 to MCn7, and MDn0 to MDn7 [n = 1 to 3]
before clearing the MBn bit in MBCR corresponding to the Mailbox of the transmit message to
0 (initial setting).
2. Set the MBn bit in TXPR to 1 (start condition issuance). Then, the start condition is generated.
3. The internal arbitration for message 1 is determined and the transmit message is transferred to
the temporary buffer. After that, even if a transmit request cancellation is issued to the message
being transmitted by the DART or MBn bit in TXCR, message 1 is transmitted continuously
unless the TinyCAN detects an arbitration loss or error on the CAN bus.
Rev. 4.00 Mar. 15, 2006 Page 332 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
4. If an arbitrary controller detects an error in a bit of the transmit message, the controller
transmits an error frame. At this time, when the DART or MBn bit in TXCR of the TinyCAN
is set to 1, a transmit request for message 1 is canceled. At the same time, the MBn bits in
TXPR and TXCR are cleared to 0 and the MBn bit in ABACK and the EMPI bit in TCIRR1
are set to 1. The MBn bit in TXACK is always 0.
5. When there is a transmit request at intermission after the error frame, the arbitration for
message 2 is determined and it is transmitted to the CAN bus. When there is no transmit
request, the TinyCAN starts reception.
[4] Error frame detection
Message 1
Bus idle
HRXD
SOF
.....
Message 1
Bus idle
HTXD
SOF
.....
Message 2
Error flag
Error flag
delimiter
Intermission
[4] Error frame detection
Error flag
Error flag
delimiter
SOF
Message 2
Intermission
SOF
MBn in TXPR
MBn in TXCR
DART
MBn in ABACK
EMPI in TCIRR1
MBn in TXACK
Transmission for message 1
cannot be cancelled by TXCR
Internal arbitration for message 2 can be configurable
(Transmission settings can be changed by TXPR/TXCR)
[2] Set MBn
in TXPR
[3] Internal arbitration for message 1 is determined
Transmission for message 2
cannot be cancelled by TXCR
Internal arbitration for message 3
can be configurable
[5] Internal arbitration for message 2 is determined
after error frame has ended
Figure 15.11 Internal Arbitration at Error Detection (MBn in TXCR = 0 and DART = 0)
Rev. 4.00 Mar. 15, 2006 Page 333 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
[4] Error frame detection
Message 1
Bus idle
HRXD
SOF
.....
Message 1
Bus idle
HTXD
SOF
.....
Message 2
Error flag
Error flag
delimiter
Intermission
[4] Error frame detection
Error flag
SOF
Message 2
Error flag
delimiter
MBn in TXPR
[4] Clear MBn in TXPR and MBn in TXCR
MBn in TXCR
DART
MBn in ABACK
[4] Set MBn in ABACK and EMPI in TCIRR1
EMPI in TCIRR1
MBn in TXACK
Transmission for message 1
cannot be cancelled by TXCR
Internal arbitration for message 2 can be configurable
(Transmission settings can be changed by TXPR/TXCR)
[2] Set MBn
in TXPR
[3] Set MBn in TXCR after internal arbitration
for message 1 has been determined
Transmission for message 2
cannot be cancelled by TXCR
Internal arbitration for message 3
can be configurable
[5] Internal arbitration for message 2 is determined
after error frame has ended
If other Mailbox has a transmit request,
transmission is started at this timing
Figure 15.12 Internal Arbitration at Error Detection (MBn in TXCR = 1)
Rev. 4.00 Mar. 15, 2006 Page 334 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
Message 1
Bus idle
HRXD
SOF
.....
Message 1
HTXD
Bus idle
SOF
.....
[4] Error frame detection
Error Flag
Error Flag
Delimiter
Message 2
Intermission
[4] Error frame detection
Error Flag
SOF
Message 2
Error Flag
Delimiter
[4] Clear MBn in TXPR
TXPR.MBn
TXCR.MBn
[5] Overwrite DART when other Mailbox has
transmit request
DART
ABACK.MBn
[4] Set MBn in ABACK and EMPI in TCIRR1
TCIRR.EMPI
TXACK.MBn
Transmission for message 1
cannot be cancelled by TXCR
Internal arbitration for message 2 can be configurable
(Transmission settings can be changed by TXPR/TXCR)
[2] Set MBn [3] Load DART when message 1
in TXPR is transferred to temporary buffer
Transmission for message 2
cannot be cancelled by TXCR
Internal arbitration for message 3
can be configurable
[5] Internal arbitration for message 2 is determined
after error frame has ended
If other Mailbox has a transmit request,
transmission is started at this timing
Figure 15.13 Internal Arbitration at Error Detection (DART = 1)
Rev. 4.00 Mar. 15, 2006 Page 335 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
15.5.4
Message Reception
Figure 15.14 shows a message reception flowchart. Figure 15.15 shows the set timing for TXPR
and TXCR during reception. A transmit request can be canceled by TXCR at any time during
reception.
*1
Frame received
EOF received
Read TCIRR
n = 3 (n: Mailbox number)
OVRI in TCIRR1
set to 1?
No
Yes
Read MBn in UMSR = 1
n=n−1
Receive frame ID
and Mailboxn ID + LAFM
match?
No
Clear MBn in UMSR to 0
n = 0?
No
Yes
DFRI in TCIRR0
set to 1?
Yes
TinyCAN is in idle state
No
RFRI in TCIRR0
set to 1?
Yes
Yes
MBn in RXPR or MBn in
RFPR set to 1?
No
Read MBn in RXPR = 1
Read MBn in RFPR = 1
Read Mailboxn
Read Mailboxn
MBn in UMSR
cleared to 0?
MBn in UMSR
cleared to 0?
Other interrupt
processing
No
Yes
No
NMC = 1?
No
Yes
Yes
Unread message
overwrite
Unread message
overrun
Message reception
 Discard unread message
 Overwrite with receive
message
 Set MBn in UMSR to 1
 Set OVRI in TCIRR1 to 1
(when MBn in MBIMR
= 1)
 Interrupt occurred (when
OVRIM in TCIRR1 = 0)
Overwrite with unread
message
Discard receive message
Set MBn in UMSR to 1
Set OVRI in TCIRR1 to 1
(when MBn in MBIMR
= 1)
Interrupt occurred (when
OVRIM in TCIRR1 = 0)
Write receive message
Set MBn in RXPR or
MBn in RFPR to 1
Set DFRI in TCIRR0 or
RFRI in TCIRR0 to 1
(when MBn in MBIMR
= 1)
Interrupt occurred (when
DFRIM in TCIMR0 or
RFRIM in TCIMR0 = 0)
*1
*1
*1
Clear MBn in RXPR to 0
Clear MBn in RFPR to 0
Read MBn in RXPR = 0
Read MBn in RFPR = 0
TinyCAN data
frame receive
operation end
TinyCAN remote
frame receive
operation end
Note: Processing in a shaded box requires setting by software.
Figure 15.14 Message Reception Flowchart
Rev. 4.00 Mar. 15, 2006 Page 336 of 556
REJ09B0026-0400
No
Yes
Section 15 Controller Area Network for Tiny (TinyCAN)
Receive procedure and operation are as follows.
1. Write data of a receive message to MCn0, MCn4 to MCn7, and MDn0 to MDn7 [n = 0 to 3]
before setting MBCR corresponding to the Mailbox of the receive message to 1 (initial
setting).
2. On detecting EOF of a data frame or remote frame, the TinyCAN compares the receive
message identifier with the identifier set in the receive Mailbox. After LAFM has been read
and then the identifier set in Mailbox 3 (receive mailbox) has been read, the read data is
compared with the receive message identifier. When a mismatch occurs even if the identifier
mask is set, the same comparison procedure is repeated for all other Mailboxes; starting from
Mailbox 2 (receive mailbox) and ending with Mailbox 0. If a mismatch occurs in Mailbox 0,
the TinyCAN clears the temporary buffer and enters the idle state.
3. When the identifier has been compared at the seventh bit of the EOF or the higher bit, the
message is written to the receive Mailbox whose identifier matches that of the receive
message. The identifier, which is masked by LAFM, may be overwritten. If there is more than
one Mailbox whose ID and LAFM matches with those of the receive message, the Mailbox
with the highest number is always to receive the relevant message. Note that Mailboxes with
lower numbers cannot receive that message.
4. After the message has been written to the receive Mailbox, the DFRI bit in TCIRR0 and the
MBn bit in RXPR are set to 1 when the receive message is a data frame, the RFRI bit in
TCIRR0 and the MBn bit in RFPR are set to 1 when the receive message is a remote frame,
and the OVRI bit in TCIRR1 and the MBn bit in UMSR are set to 1 when an overrun or
overwrite occurs.
5. When the MBn bit in RXPR or the MBn bit in RFPR is set to 1, the temporary buffer is
cleared. When the TinyCAN transmits message 2, the internal arbitration is determined, and
the transmit message is transferred to the temporary buffer and output to HTXD after the
temporary buffer has been cleared.
Rev. 4.00 Mar. 15, 2006 Page 337 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
Message 1
HRXD
Bus idle
HTXD
Bus idle
SOF
Arbitration
Control
Data
Message 2
CRC
ACK
EOF
Intermission
SOF
Message 2
ACK bit
Intermission
SOF
[4] Clear MBn in TXCR
to 0 even if set to 1 at
frame reception
MBn in TXPR
MBn in TXCR
[4] Set MBn in RXPR and
DFRI in TCIRR0 to 1 at
data frame reception
MBn in RXPR
DFRI in TCIRR0
[4] Set MBn in RFPR and
RFRI in TCIRR0 to 1 at
remote frame reception
MBn in RFPR
RFRI in TCIRR0
[2] Identifier of message
1 is compared with that
of Mailbox
Message 2 transmission
Message 1 reception
[3] Write receive message
Internal arbitration for message 2 can be set
Transmission for message 2
cannot be canceled by TX
[5] Internal arbitration for message 2
is determined after normal reception
has completed
Figure 15.15 Set Timing for Message Reception
Rev. 4.00 Mar. 15, 2006 Page 338 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
Case 1: Overwrite (NMC = 1, 1st: Data Frame, 2nd: Remote Frame)
Data frame reception
Remote frame reception
MBn in RXPR
DFRI in TCIRR0
MBn in RFPR
RFRI in TCIRR0
MBn in UMSR
OVRI in TCIRR1
RTR in MCn4
CPU access
Other module
TinyCAN
Case 2: Overwrite (NMC = 1, 1st: Remote Frame, 2nd: Data Frame)
Remote frame reception
Data frame reception
MBn in RXPR
DFRI in TCIRR0
MBn in RFPR
RFRI in TCIRR0
MBn in UMSR
OVRI in TCIRR1
RTR in MCn4
CPU access
Other module
TinyCAN
Case 3: Overrun (NMC = 0, 1st: Data Frame, 2nd: Remote Frame)
Data frame reception
Remote frame reception
MBn in RXPR
DFRI in TCIRR0
MBn in RFPR
RFRI in TCIRR0
MBn in UMSR
OVRI in TCIRR1
RTR in MCn4
CPU access
Other module
TinyCAN
Case 4: Overrun (NMC = 0, 1st: Remote Frame, 2nd: Data Frame)
Remote frame reception
Data frame reception
MBn in RXPR
DFRI in TCIRR0
MBn in RFPR
RFRI in TCIRR0
MBn in UMSR
OVRI in TCIRR1
RTR in MCn4
CPU access
Other module
TinyCAN
Figure 15.16 RXPR/RFPR Set/Clear Timing when Overrun/Overwrite Occurs
Rev. 4.00 Mar. 15, 2006 Page 339 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
15.5.5
Reconfiguring Mailbox
A Mailbox can be reconfigured using the following procedure:
Changing CAN-ID and MBCR of Transmit Mailbox: Make sure that the bit corresponding to
the Mailbox in TXPR is not set to 1. The identifier of the transmit Mailbox and corresponding
MBCR bit can be changed at any time. If both of them need to be changed, change the identifier
first, clear RXPR and RFPR to 0, and then change MBCR.
Changing CAN-ID, MBCR, and LAFM of Receive Mailbox:
<Method 1: Halt mode (see figure 15.17)>
1. Set the HLTRQ bit in MCR bit to 1.
2. Determine whether the TinyCAN is during transmission or reception, or in the bus off state
and wait for recovery from transmission, reception, or bus off state.
3. The TinyCAN enters halt mode at the first bit in the intermission frame of the message and
sets the RHI bit in TCIRR0 and the HALT bit in GSR to 1. Note that the TinyCAN cannot
transmit or receive a message in halt mode.
4. Confirm that the RHI bit in TCIRR0 and the HALT bit in GSR are both set to 1 before
changing settings of the identifier, LAFM, and the MBn bit in MBCR of the Mailbox.
5. When the HLTRQ bit in MCR is cleared to 0, the TinyCAN returns to normal operation after
11 recessive bits have been continuously received.
<Method 2: Other than halt mode (see figure 15.17)>
1. Set the MBn bit in MBIMR for the corresponding Mailbox to 1 to disable interrupts. (n = 0 to
3)
2. Determine whether the MBn bits in RXPR and RFPR are cleared to 0 to confirm that there are
no receive messages.
3. Change the settings of the identifier, LAFM, and the MBn bit in MBCR in the Mailbox.
4. Determine whether the MBn bits in RXPR and RFPR are cleared to 0 to confirm that no
message is received during reconfiguration. The function of MBIMR is not to prevent RXPR,
RFPR, or the OVRI bit in TCIRR1 from being set.
5. At this time, when the MBn bit in RXPR or RFPR is set to 1, clear the relevant bit to 0. Delete
the receive message because it cannot be determined whether the message was addressed to the
new Mailbox ID or the old Mailbox ID.
6. Then clear the MBn bit in MBIMR for the corresponding Mailbox to 0. The TinyCAN returns
to normal operation.
Rev. 4.00 Mar. 15, 2006 Page 340 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
Method 1: Halt mode
Method 2: Other than halt mode
TinyCAN is in normal mode
TinyCAN is in normal mode
Set HLTRQ in MCR to 1
(halt mode)
TinyCAN is during
transmission, reception,
or in bus off state?
No
Set corresponding MBn in
MBIMR to 1
Yes
Read corresponding
RXPR (RFPR) = 0
No
Write 1 to MBn in RXPR
(MBn in RFPR)
Yes
Interrupt occurred
(RHI in TCIRR0 = 1)
Change ID and MBCR
of Mailbox
Read RHI in TCIRR0 = 1
Read HALT in GSR = 1
Read corresponding
RXPR (RFPR)
0
1
TinyCAN is in halt mode
Write 1 to corresponding MBn
in RXPR (MBn in RFPR) and
delete receive message
Change ID, MBCR, and LAFM
of Mailbox
Clear corresponding MBn in
MBIMR to 0
Clear HLTRQ in MCR to 0
TinyCAN is in normal mode
TinyCAN is in normal mode
and ready for action
Note: Processing in a shaded box requires setting by software.
Figure 15.17 Flowchart for Changing ID, MBCR, and LAFM of Receive Mailbox
Rev. 4.00 Mar. 15, 2006 Page 341 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
15.5.6
TinyCAN Standby Transition
To make this LSI enter or clear standby mode when the TinyCAN is used or to make the
TinyCAN enter or clear module standby mode, follow the procedure below.
Transition from Normal Operation to Standby Mode or Module Standby Mode: This LSI can
make a transition from normal mode to standby mode with the following procedure.
1.
2.
3.
4.
Set the halt mode request bit (HLTRQ bit in MCR) to 1.
Wait until the reset/halt interrupt flag (RHI bit in TCIRR0) is set to 1.
Clear all interrupt request flags (in TCIRR1 and TCIRR0) to 0.
Make this LSI enter standby mode or module standby mode. In module standby mode, set the
MSTTC bit in TCMR to 1. Then the TinyCAN enters module standby mode.
Making the CAN bus enter the bus idle state using this procedure will reduce power consumption
of this LSI. The TinyCAN registers retain their settings in standby mode.
Transition from Standby Mode to Normal Operation: This LSI can make a transition from
standby mode to normal mode with the following procedure.
1. When data on the CAN bus changes from recessive to dominant, a falling edge is detected at
the HRXD pin.
2. This causes the WUPI bit in TCIRR1 to be set to 1, and generates an interrupt request.
3. After an interrupt request is issued, the TinyCAN registers resume operation with the settings
before entering standby mode. Change the settings at this timing if necessary.
4. To re-enable communication with the CAN bus, clear both the WUPI bit in TCIRR1 and the
HLTRQ bit in MCR to 0. After 11 recessive bits are consecutively received, communication
will resume.
Note however that the first frame to be received cannot be received normally.
Transition from Module Standby Mode to Normal Operation: The TinyCAN can make a
transition from module standby mode to normal mode with the following procedure.
1. When the MSTTC bit in TCMR is cleared to 0, the TinyCAN registers resume operation with
the settings before entering module standby mode. Change the settings at this timing if
necessary.
2. To re-enable communication with the CAN bus, clear both the HLTRQ bit in MCR to 0. After
11 recessive bits are consecutively received, communication will resume.
Rev. 4.00 Mar. 15, 2006 Page 342 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
Normal operation → LSI standby mode
or
Normal operation → module standby mode
TinyCAN is in normal mode
LSI standby mode → normal operation
Module standby mode → normal operation
TinyCAN is in module
standby mode
LSI standby mode
Write 1 to HLTRQ in MCR
(halt mode)
Clear MSTTC in TCMR to 0
Falling edge detected
on CAN bus?
TinyCAN is during
transmission, reception,
or in bus off state?
No
Interrupt occurred
(RHI in TCIRR0 = 1)
No
Yes
Write 0 to HLTRQ in MCR
Yes
Interrupt occurred
(WUPI in TCIRR1 = 1)
11 recessive bits received
continuously?
Clear WUPI bit in TCIRR1 to 0
No
Yes
Read RHI in TCIRR0 = 1
Write 0 to HLTRQ in MCR
TinyCAN is in normal mode
and ready for action
Read HALT in GSR = 1
TinyCAN is in halt mode
11 recessive bits
received continuously?
No
Yes
Clear all bits in TCIRR1
and TCIRR0
TinyCAN is in normal mode
and ready for action
Specify transition to standby
mode or set TCMSC in TCMR
LSI standby mode or
TinyCAN module standby
mode
Note: Processing in a shaded box requires setting by software.
Figure 15.18 Flowchart for Transition between Active Mode and Standby Mode or
Module Standby Mode
Rev. 4.00 Mar. 15, 2006 Page 343 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
15.6
Interrupt Requests
The TinyCAN has the following interrupt requests. These interrupts can be masked except for a
reset processing interrupt caused by powering on. To mask them, the Mailbox interrupt mask
register (MBIMR) and interrupt mask register (IMR) are used. Since these interrupt requests are
allocated to the common vector addresses, their sources need to be identified by flags.
Table 15.4 Interrupt Requests
Interrupt Request
Abbreviation
Interrupt Condition
Wakeup
WUPI
When falling edge of HRXD is detected in LSI
standby mode
Unread message
OVRI
When new message is received while MBIMR
corresponding to receive message is 0 and
RXPR or RFPR is 1
Mailbox empty
EMPI
When TXPR is cleared to 0 by completion of
transmission or completion of transmission
cancellation
Overload frame transmission
OVLI
When overload frame is transmitted
Bus off
BOFI
When TEC ≥ 256 or 11 bits are received 128
times in bus off state
Error passive
EPI
When TEC ≥ 128 or REC ≥ 128
Receive overload warning
ROWI
When REC ≥ 96
Transmit overload warning
TOWI
When TEC ≥ 96
Remote frame request
RFRI
When remote frame is received and
corresponding MBIMR is 0
Receive message
DFRI
When message reception is completed and
corresponding MBIMR is 0
Reset/Halt
RHI
When processing is completed after software
reset request (RSTRQ) or halt mode request
(HLTRQ) is issued
When TEC or REC becomes 128 after incrementing or decrementing, note that the error passive
(EPI) flag issues an interrupt request. When REC or TEC becomes 96 after incrementing or
decrementing, note that the receive overload warning (ROWI) flag or transmit overload warning
(TOWI) flag issues an interrupt request, respectively.
Rev. 4.00 Mar. 15, 2006 Page 344 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
15.7
Test Mode Settings
The TinyCAN has various test modes. TCR is used to select each test modes. In the initial
configuration, the TinyCAN performs a normal operation. Table 15.5 lists examples of setting the
test mode.
Table 15.5 Test Mode Settings
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TSTMD
WREC
FERPS
ATACK
DEC
DRXIN
DTXOT
INTLE
Description
0
0
0
0
0
0
0
0
Normal mode
(Initial value)
1
0
0
0
1
0
1
0
Receive-only
mode
1
0
0
1

0
0
0
External self-test
mode
1
0
0
1

1
1
1
Internal self-test
mode
1
1
0





Counter write
error-passive
1
0
1





Force to errorpassive
Normal Mode: The TinyCAN operates in normal mode.
Receive-Only Mode: This mode is used for running tests required by the ISO-11898 standard,
such as baud rate detection. Counting by the error counter is disabled and the TEC and REC value
is not incremented. To prevent the TinyCAN from generating an error frame, transmission of the
HTXD output is disabled.
External Self-Test Mode: The TinyCAN generates its own acknowledge bit. The HRXD and
HTXD pins must be connected to the CAN bus.
Internal Self-Test Mode: The TinyCAN generates its own acknowledge bit. Since the internal Tx
is loop back to the internal Rx, the HRXD and HTXD pins need not be connected to the CAN bus
or another external device.
Rev. 4.00 Mar. 15, 2006 Page 345 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
Counter Write Error Passive: The TinyCAN can be forced to make a transition to the errorpassive state by writing a value of 127 or higher to the error counter. To write a value to the error
counter, set the HLTRQ bit to 1. A value written to TEC is automatically also written to REC; the
same value is to be written to TEC and REC. Note that the TinyCAN need to be in halt mode to
write a value to TEC and REC. The TinyCAN should communicate in normal mode (TSTMD bit
= 0), since written values of TEC and REC are retained unless the TinyCAN is reset or detects an
error.
Force to Error Passive: The TinyCAN can be forced to make a transition to the error-passive
state by setting the FERPS bit to 1.
15.8
CAN Bus Interface
A bus transceiver IC and a pull-up resistor are necessary to connect this LSI to a CAN bus. A
Renesas Technology HA13721 transceiver IC is recommended. If any other product is used,
confirm that it is compatible with the HA13721. Figure 15.19 shows a sample connection diagram.
Vcc
120 W
This LSI
HA13721
HTXD
TXD
Mode
CAN bus
GND CANH
Vcc
HRXD
RXD
CANL
NC
NC
120 W
Note: NC: Non connection
Figure 15.19 High-Speed CAN Bus Interface Using HA13721
Rev. 4.00 Mar. 15, 2006 Page 346 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
15.9
Usage Notes
1. Since Mailboxes (MCn0, MCn4 to MCn7, and MDn0 to MDn7 (n = 0 to 3)) and LAFM are
configured of RAM, initial values are undefined after powering on. Initialize (write 0 or 1) all
Mailboxes and LAFM.
2. Set BCR1, BCR0, and the PMR97 and PMR96 bits in TMCR after initializing Mailboxes and
LAFM. Otherwise, the TinyCAN starts reception and the receive message ID may be
compared with an undefined value of RAM.
3. To change Mailbox settings from transmission to reception, confirm that TXPR is 0.
4. To change Mailbox settings from reception to transmission, confirm that both RXPR and
RFPR are 0 after transition to halt mode.
5. If MCn0, MCn4 to MCn7, and MDn0 to MDn7 (n = 0 to 3) are written to by the CPU between
the seventh EOF bit and intermission space at message reception, note that data of the receive
message may be overwritten.
6. If MCn0, MCn4 to MCn7, and MDn0 to MDn7 (n = 0 to 3) are written to by the CPU between
intermission spaces during a transmit request, note that the transmit message may be updated.
7. RXPR and RFPR are exclusively set or cleared during overwrite.
8. A wakeup operation is enabled only in LSI standby mode. Note that it is disabled in module
standby mode.
9. To enter module standby mode, make a transition to halt mode beforehand. Otherwise, when
clearing module standby mode, communication with the CAN bus resumes with the setting
before making a transition and an error occurs.
10. When an error is detected during reception, the TinyCAN clears data in the temporary buffer.
Rev. 4.00 Mar. 15, 2006 Page 347 of 556
REJ09B0026-0400
Section 15 Controller Area Network for Tiny (TinyCAN)
Rev. 4.00 Mar. 15, 2006 Page 348 of 556
REJ09B0026-0400
Section 16 Synchronous Serial Communication Unit (SSU)
Section 16 Synchronous Serial Communication Unit (SSU)
The synchronous serial communication unit (SSU) can handle clocked synchronous serial data
communication.
Figure 16.1 shows a block diagram of the SSU.
16.1
Features
• Can be operated in clocked synchronous communication mode or four-line bus communication
mode (including bidirectional communication mode)
• Can be operated as a master or a slave device
• Choice of seven internal clocks (φ/256, φ/128, φ/64, φ/32, φ/16, φ/8, φ/4) and an external clock
as a clock source
• Clock polarity and phase of SSCK can be selected
• Choice of data transfer direction (MSB-first or LSB-first)
• Receive error detection: overrun error
• Multimaster error detection: conflict error
• Five interrupt sources: transmit-end, transmit-data-empty, receive-data-full, overrun error, and
conflict error
16.2
Continuous transmission and reception of serial data are enabled
since both transmitter and Input/Output Pins
Table 16.1 shows the pin configuration of the SSU.
Table 16.1 Pin Configuration
Pin Name
Abbreviation
I/O
Function
SSU clock
SSCK
I/O
SSU clock input/output
SSU data input/output
SSI
I/O
SSU data input/output
SSU data input/output
SSO
I/O
SSU data input/output
SSU chip select input/output
SCS
I/O
SSU chip select input/output
Rev. 4.00 Mar. 15, 2006 Page 349 of 556
REJ09B0026-0400
Section 16 Synchronous Serial Communication Unit (SSU)
16.3
Register Descriptions
The SSU has the following registers.
•
•
•
•
•
•
•
•
SS control register H (SSCRH)
SS control register L (SSCRL)
SS mode register (SSMR)
SS enable register (SSER)
SS status register (SSSR)
SS receive data register (SSRDR)
SS transmit data register (SSTDR)
SS shift register (SSTRSR)
Internal clock
Multiplexer
SSCK
SSMR
SSCRL
Transmission/
reception
control circuit
SSCRH
SSER
SSSR
SSTDR
SSO
SSI
Selector
SSTRSR
SSRDR
Interrupt request
(TXI, TEI, RXI, OEI, CEI)
[Legend]
SSCRL:
SSCRH:
SSER:
SSSR:
SSTDR:
SSTRSR:
SSRDR:
SS control register L
SS control register H
SS enable register
SS status register
SS transmit data register
SS shift register
SS receive data register
Figure 16.1 Block Diagram of SSU
Rev. 4.00 Mar. 15, 2006 Page 350 of 556
REJ09B0026-0400
Internal data bus
SCS
Section 16 Synchronous Serial Communication Unit (SSU)
16.3.1
SS Control Register H (SSCRH)
SSCRH is a register that selects a master or a slave device, enables bidirectional mode, selects
open-drain output of the serial data output pin, selects an output value of the serial data output pin,
selects the SSCK pin, and selects the SCS pin.
Bit
Bit Name
Initial
Value
R/W
Description
7
MSS
0
R/W
Master/Slave Device Select
Selects whether this module is used as a master device
or a slave device. When this module is used as a master
device, transfer clock is output from the SSCK pin. When
the CE bit in SSSR is set, this bit is automatically cleared.
0: Operates as a slave device
1: Operates as a master device
6
BIDE
0
R/W
Bidirectional Mode Enable
Selects whether the serial data input pin and the output
pin are both used or only one pin is used. For details,
refer to section 16.4.3, Relationship between Data
Input/Output Pin and Shift Register. When the SSUMS bit
in SSCRL is 0, this setting is invalid.
0: Normal mode. Communication is performed by using
two pins.
1: Bidirectional mode. Communication is performed by
using only one pin.
5
SOOS
0
R/W
Serial Data Open-Drain Output Select
Selects whether the serial data output pin is CMOS
output or NMOS open-drain output. The serial data output
pin is changed according to the register setting value. For
details, refer to section 16.4.3, Relationship between
Data Input/Output Pin and Shift Register.
0: CMOS output
1: NMOS open-drain output
Rev. 4.00 Mar. 15, 2006 Page 351 of 556
REJ09B0026-0400
Section 16 Synchronous Serial Communication Unit (SSU)
Bit
Bit Name
Initial
Value
R/W
Description
4
SOL
0
R/W
Serial Data Output Level Setting
Although the value in the last bit of transmit data is
retained in the serial data output after the end of
transmission, the output level of serial data can be
changed by manipulating this bit before or after
transmission. When the output level is changed, the
SOLP bit should be cleared to 0 and the MOV instruction
should be used. If this bit is written during data transfer,
erroneous operation may occur. Therefore this bit must
not be manipulated during transmission.
0: Shows serial data output level to low in reading.
Changes serial data output level to low in writing
1: Shows serial data output level to high in reading.
Changes serial data output level to high in writing
3
SOLP
1
R/W
SOL Write Protect
When output level of serial data is changed, the MOV
instruction is used to set the SOL bit to 1 and clear this bit
to 0 or to clear the SOL bit and this bit to 0.
0: In writing, output level can be changed according to the
value of the SOL bit.
1: In reading, this bit is always read as 1. In writing, it
cannot be modified output level.
2
SCKS
0
R/W
SSCK Pin Select
Selects whether the SSCK pin functions as a port or a
serial clock pin.
0: Functions as a port
1: Functions as a serial clock pin
1
CSS1
0
R/W
SCS Pin Select
0
CSS0
0
R/W
Selects whether the SCS pin functions as a port, an SCS
input, or SCS output. When the SSUMS bit in SSCRL is
0, the SCS pin functions as a port regardless of the
setting of this bit.
00: Functions as a port
01: Functions as an SCS input
1X: Functions as an SCS output (however, functions as
an SCS input before starting transfer)
[Legend]
X: Don't care.
Rev. 4.00 Mar. 15, 2006 Page 352 of 556
REJ09B0026-0400
Section 16 Synchronous Serial Communication Unit (SSU)
16.3.2
SS Control Register L (SSCRL)
SSCRL is a register that controls module standby, mode, and software reset and selects open-drain
output of the SSCK and SCS pins.
Bit
Bit Name
Initial
Value
R/W
Description
7
MSTSSU
0
R/W
SSU Module Standby
When this bit is 1, the SSU enters the module standby
state. In the module standby state, the SSU internal
registers other than SSCRL cannot be written to.
6
SSUMS
0
R/W
SSU Mode Select
Selects which combination of the serial data input pin and
serial data output pin is used.
For details, refer to section 16.4.3, Relationship between
Data Input/Output Pin and Shift Register.
0: Clocked synchronous communication mode
Data input: SSI pin, Data output: SSO pin
1: Four-line bus communication mode
When MSS = 1 and BIDE = 0 in SSCRH:
Data input: SSI pin, Data output: SSO pin
When MSS = 0 and BIDE = 0 in SSCRH:
Data input: SSO pin, Data output: SSI pin
When BIDE = 1 in SSCRH:
Data input and output: SSO pin
5
SRES
0
R/W
Software reset
When this bit is set to 1, the SSU internal sequencer is
forcibly reset. Then this bit is automatically cleared. The
register value in the SSU is retained.
4
SCKOS
0
R/W
SSCK Pin Open-Drain Output Select
Selects whether the SSCK pin functions as CMOS output
or NMOS open-drain output.
0: CMOS output
1: NMOS open-drain output
Rev. 4.00 Mar. 15, 2006 Page 353 of 556
REJ09B0026-0400
Section 16 Synchronous Serial Communication Unit (SSU)
Bit
Bit Name
Initial
Value
R/W
Description
3
CSOS
0
R/W
SCS Pin Open-Drain Output Select
Selects whether the SCS pin functions as CMOS output
or NMOS open-drain output.
0: CMOS output
1: NMOS open-drain output
2 to 0

All 0

Reserved
These bits are always read as 0.
16.3.3
SS Mode Register (SSMR)
SSMR is a register that selects MSB-first or LSB-first, clock polarity, clock phase, and transfer
clock rate.
Bit
Bit Name
Initial
Value
R/W
Description
7
MLS
0
R/W
MSB-First/LSB-First Select
Selects whether data transfer is performed in MSB-first or
LSB-first.
6
CPOS
0
R/W
•
0: LSB-first
•
1: MSB-first
Clock Polarity Select
Selects the clock polarity of SSCK.
0: Idle state = high
1: Idle state = low
5
CPHS
0
R/W
Clock Phase Select
Selects the clock phase of SSCK.
0: Data change at first edge
1: Data latch at first edge
4, 3

All 0

Reserved
These bits are always read as 0.
Rev. 4.00 Mar. 15, 2006 Page 354 of 556
REJ09B0026-0400
Section 16 Synchronous Serial Communication Unit (SSU)
Bit
Bit Name
Initial
Value
R/W
Description
2
CKS2
0
R/W
Transfer clock rate select
1
CKS1
0
R/W
0
CKS0
0
R/W
Sets transfer clock rate (prescaler division ratio) when the
internal clock is selected.
000: φ/256
001: φ/128
010: φ/64
011: φ/32
100: φ/16
101: φ/8
110: φ/4
111: Reserved
16.3.4
SS Enable Register (SSER)
SSER is a register that sets transmit enable, receive enable, and interrupt enable.
Bit
Bit Name
Initial
Value
R/W
Description
7
TE
0
R/W
Transmit enable
When this bit is 1, transmit operation is enabled.
6
RE
0
R/W
Receive enable
When this bit is 1, receive operation is enabled.
5
RSSTP
0
R/W
Receive single stop
When this bit is 1, receive operation is completed after
receiving one byte.
4
—
0
—
Reserved
This bit is always read as 0.
3
TEIE
0
R/W
Transmit End Interrupt Enable
When this bit is set to 1, a TEI interrupt request is
enabled.
2
TIE
0
R/W
Transmit Interrupt Enable
When this bit is set to 1, a TXI interrupt request is
enabled.
Rev. 4.00 Mar. 15, 2006 Page 355 of 556
REJ09B0026-0400
Section 16 Synchronous Serial Communication Unit (SSU)
Bit
Bit Name
Initial
Value
R/W
Description
1
RIE
0
R/W
Receive Interrupt Enable
When this bit is set to 1, an RXI and an OEI interrupt
requests are enabled.
0
CEIE
0
R/W
Conflict Error Interrupt Enable
When this bit is set to 1, a CEI interrupt request is
enabled.
16.3.5
SS Status Register (SSSR)
SSSR is a register that sets interrupt flags.
Bit
Bit Name
Initial
Value
R/W
Description
7
—
0
—
Reserved
This bit is always read as 0.
6
ORER
0
R/W
Overrun Error Flag
Indicates that the RDRF bit is abnormally terminated in
reception because an overrun error has occurred.
SSRDR retains received data before the overrun error
occurs and the received data after the overrun error
occurs is lost. When this bit is set to 1, subsequent serial
reception cannot be continued. When the MSS bit in
SSCRH is 1, this is also applied to serial transmission.
[Setting condition]
•
When the next serial reception is completed while
RDRF = 1
[Clearing condition]
•
5, 4

All 0

When 0 is written to this bit after reading 1
Reserved
These bits are always read as 0.
Rev. 4.00 Mar. 15, 2006 Page 356 of 556
REJ09B0026-0400
Section 16 Synchronous Serial Communication Unit (SSU)
Bit
Bit Name
Initial
Value
R/W
Description
3
TEND
0
R/W
Transmit End
[Setting condition]
•
When the last bit of data is transmitted, the TDRE bit
is 1
[Clearing conditions]
2
TDRE
1
R/W
•
When 0 is written to this bit after reading 1
•
When data is written in SSTDR
Transmit Data Empty
[Setting conditions]
•
When the TE bit in SSER is 0
•
When data transfer is performed from SSTDR to
SSTRSR and data can be written in SSTDR
[Clearing conditions]
1
RDRF
0
R/W
•
When 0 is written to this bit after reading 1
•
When data is written in SSTDR
Receive Data Register Full
[Setting condition]
•
When serial reception is completed normally and
receive data is transferred from SSTRSR to SSRDR
[Clearing conditions]
0
CE
0
R/W
•
When 0 is written to this bit after reading 1
•
When data is read from SSRDR
Conflict Error Flag
[Setting conditions]
•
When serial communication is started while SSUMS =
1 and MSS =1, the SCS pin input is low
•
When the SCS pin level changes from low to high
during transfer while SSUMS = 1 and MSS = 0
[Clearing condition]
•
When 0 is written to this bit after reading 1
Rev. 4.00 Mar. 15, 2006 Page 357 of 556
REJ09B0026-0400
Section 16 Synchronous Serial Communication Unit (SSU)
16.3.6
SS Receive Data Register (SSRDR)
SSRDR is an 8-bit register that stores received serial data. When the SSU has received one byte of
serial data, it transfers the received serial data from SSTRSR and the data is stored. After this,
SSTRSR is receive-enabled. As SSTRSR and SSRDR function as a double buffer in this way,
continuous receive operations are possible. SSRDR is a read-only register and cannot be written to
by the CPU. SSRDR is initialized to H'00.
16.3.7
SS Transmit Data Register (SSTDR)
SSTDR is an 8-bit register that stores serial data for transmission. SSTDR can be read or written
to by the CPU at all times. When the SSU detects that SSTRSR is empty, it transfers the transmit
data written in SSTDR to SSTRSR and starts serial transmission. If the next transmit data has
already been written to SSTDR during serial transmission, continuous serial transmission is
possible. SSTDR is initialized to H′00.
16.3.8
SS Shift Register (SSTRSR)
SSTRSR is a shift register that transmits and receives serial data. When transmit data is transferred
from SSTDR to SSTRSR, bit 0 in SSTDR is transferred to bit 0 in SSTRSR while the MLS bit in
SSMR is 0 (LSB-first transfer) and bit 7 in SSTDR is transferred to bit 0 in SSTRSR while the
MLS bit in SSMR is 1 (MSB-first transfer). SSTRSR cannot be directly accessed by the CPU.
Rev. 4.00 Mar. 15, 2006 Page 358 of 556
REJ09B0026-0400
Section 16 Synchronous Serial Communication Unit (SSU)
16.4
Operation
16.4.1
Transfer Clock
Transfer clock can be selected from seven internal clocks and an external clock. When this module
is used, the SSCK pin must be selected as a serial clock by setting the SCKS bit in SSCRH to 1.
When the MSS bit in SSCRH is 1, an internal clock is selected and the SSCK pin is in the output
state. If transfer is started, the SSCK pin outputs clocks of the transfer rate set in the CKS2 to
CKS0 bits in SSMR. When the MSS bit is 0, an external clock is selected and the SSCK pin is in
the input state.
16.4.2
Relationship between Clock Polarity and Phase, and Data
Relationship between clock polarity and phase, and transfer data changes according to a
combination of the SSUMS bit in SSCRL and the CPOS and CPHS bits in SSMR. Figure 16.2
shows the relationship.
MSB-first transfer or LSB first transfer can be selected by the setting of the MLS bit in SSMR.
When the MLS bit is 0, transfer is started from LSB to MSB. When the MLS bit is 1, transfer is
started from MSB to LSB.
Rev. 4.00 Mar. 15, 2006 Page 359 of 556
REJ09B0026-0400
Section 16 Synchronous Serial Communication Unit (SSU)
(1) When CPHS = 0, CPOS =0, and SSUMS = 0:
SSCK
Bit 0
SSO, SSI
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
(2) When CPHS = 0 and SSUMS = 1:
SSCK
(CPOS = 0)
SSCK
(CPOS = 1)
SSO, SSI
Bit 0
SCS
(3) When CPHS = 1 and SSUMS = 1:
SSCK
(CPOS = 0)
SSCK
(CPOS = 1)
SSO, SSI
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
SCS
Figure 16.2 Relationship between Clock Polarity and Phase, and Data
Rev. 4.00 Mar. 15, 2006 Page 360 of 556
REJ09B0026-0400
Section 16 Synchronous Serial Communication Unit (SSU)
16.4.3
Relationship between Data Input/Output Pin and Shift Register
Relationship of connection between the data input/output pin and SSTRSR changes according to a
combination of the MSS bit in SSCRH and the SSUMS bit in SSCRL. It also changes by the
BIDE bit in SSCRH. Figure 16.3 shows the relationship.
(1) When SSUMS = 0:
Shift register
(SSTRSR)
(2) When SSUMS = 1, BIDE = 0, and MSS = 1:
SSO
Shift register
(SSTRSR)
SSO
SSI
(3) When SSUMS = 1, BIDE = 0, and MSS = 0:
Shift register
(SSTRSR)
SSI
(4) When SSUMS = 1 and BIDE = 1:
SSO
Shift register
(SSTRSR)
SSO
SSI
SSI
Figure 16.3 Relationship between Data Input/Output Pin and Shift Register
Rev. 4.00 Mar. 15, 2006 Page 361 of 556
REJ09B0026-0400
Section 16 Synchronous Serial Communication Unit (SSU)
16.4.4
Communication Modes and Pin Functions
The SSU switches functions of the input/output pin in each communication mode according to the
settings of the MSS bit in SSCRH and the RE and TE bits in SSER. Figure 16.2 shows the
relationship between communication modes and the input/output pins.
Table 16.2 Relationship between Communication Modes and Input/Output Pins
Communication
Mode
Clocked
Synchronous
Communication
Mode
Register State
SSUMS
BIDE
MSS
0
*
0
1
Four-Line Bus
Communication
Mode
1
0
0
1
Four-Line Bus
(Bidirectional)
Communication
Mode
1
1
[Legend]
: Can be used as a general I/O port.
Rev. 4.00 Mar. 15, 2006 Page 362 of 556
REJ09B0026-0400
0
1
TE
Pin State
RE
SSI
SSO
SSCK
0
1
In

In
1
0

Out
In
1
In
Out
In
0
1
In

Out
1
0

Out
Out
1
In
Out
Out
0
1

In
In
1
0
Out

In
1
Out
In
In
0
1
In

Out
1
0

Out
Out
1
In
Out
Out
0
1

In
In
1
0

Out
In
0
1

In
Out
1
0

Out
Out
Section 16 Synchronous Serial Communication Unit (SSU)
16.4.5
Operation in Clocked Synchronous Communication Mode
Initialization in Clocked Synchronous Communication Mode: Figure 16.4 shows the
initialization in clocked synchronous communication mode. Before transmitting and receiving
data, the TE and RE bits in SSER should be cleared to 0, then the SSU should be initialized.
Note: When the operating mode, or transfer format, is changed for example, the TE and RE bits
must be cleared to 0 before making the change using the following procedure. When the
TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not
change the contents of the RDRF and ORER flags, or the contents of SSRDR.
Start
Clear TE and RE bits in SSER to 0
Clear SSUMS bit in SSCRL to 0
Set SCKS bit in SSCRH to 1
and set MSS and SOOS bits
Clear CPOS and CPHS bits to 0 and set
MLS and CKS2 to CKS0 bits in SSMR
Clear ORER bit in SSSR to 0
Set the TE and RE bits in SSER to 1
and set RIE, TIE, TEIE, and RSSTP
bits according to transmission/
reception/transmission and reception
End
Figure 16.4 Initialization in Clocked Synchronous Communication Mode
Rev. 4.00 Mar. 15, 2006 Page 363 of 556
REJ09B0026-0400
Section 16 Synchronous Serial Communication Unit (SSU)
Serial Data Transmission: Figure 16.5 shows an example of the SSU operation for transmission.
In serial transmission, the SSU operates as described below.
When the SSU is set as a master device, it outputs a synchronous clock and data. When the SSU is
set as a slave device, it outputs data in synchronized with the input clock.
When the SSU writes transmit data in SSTDR after setting the TE bit to 1, the TDRE flag is
automatically cleared to 0 and data is transferred from SSTDR to SSTRSR. Then the SSU sets the
TDRE flag to 1 and starts transmission. If the TIE bit in SSER is set to 1 at this time, a TXI is
generated.
When the TDRE flag is 0 and one frame of data has transferred, data is transferred from SSTDR to
SSTRSR and serial transmission of the next frame is started. If the eighth bit is transmitted while
the TDRE flag is 1, the TEND bit in SSSR is set to 1 and the state is retained. If the TEIE bit in
SSER is set to 1 at this time, a TEI is generated. After transmission is ended, the SSCK pin is
fixed high.
While the ORER bit in SSSR is set to 1, transmission cannot be performed. Therefore confirm that
the ORER bit is cleared to 0 before transmission.
Figure 16.6 shows a sample flowchart for serial data transmission.
SSCK
SSO
Bit 0
Bit 1
Bit 7
One frame
Bit 0
Bit 1
Bit 7
One frame
TDRE
TEND
LSI Operation
User
processing
TXI generated
Write data
in SSTDR
TXI generated
Write data
in SSTDR
Figure 16.5 Example of Operation in Data Transmission
Rev. 4.00 Mar. 15, 2006 Page 364 of 556
REJ09B0026-0400
TEI generated
Section 16 Synchronous Serial Communication Unit (SSU)
Start
Initialization
[1]
Read TDRE bit in SSSR
No
TDRE = 1?
[1] After reading SSSR and confirming
that the TDRE bit is 1, write transmit
data in SSTDR. Then the TDRE bit is
automatically cleared to 0.
Yes
Write transmit data
in SSTDR
[2]
Data transmission
continued?
Yes
[2] Determine whether data transmission
is continued.
No
[3]
Read TEND bit in SSSR
No
TEND = 1?
[3] Read 1 from the TEND bit in SSSR
to confirm that data transmission is
completed. After the TEND bit is set to 1,
clear the TEND bit and TE bit in SSER
to 0 and transmit mode is ended.
Yes
Clear TEND bit and
TE bit in SSER to 0
End
Figure 16.6 Sample Serial Transmission Flowchart
Rev. 4.00 Mar. 15, 2006 Page 365 of 556
REJ09B0026-0400
Section 16 Synchronous Serial Communication Unit (SSU)
Serial Data Reception: Figure 16.7 shows an example of the SSU operation for reception. In
serial reception, the SSU operates as described below.
When the SSU is set as a master device, it outputs a synchronous clock and inputs data. When the
SSU is set as a slave device, it inputs data in synchronized with the input clock. When the SSU is
set as a master device, it outputs a receive clock and starts reception by performing dummy read
on SSRDR.
After eight bits of data is received, the RDRF bit in SSSR is set to 1 and received data is stored in
SSRDR. If the RIE bit in SSER is set to 1 at this time, a RXI is generated. If SSRDR is read, the
RDRF bit is automatically cleared to 0.
When the SSU is set as a master device and reception is ended, received data is read after setting
the RSSTP bit in SSER to 1. Then the SSU outputs eight bits of clocks and operation is stopped.
After that, the RE and RSSTP bits are cleared to 0 and the last received data is read. Note that if
SSRDR is read while the RE bit is set to 1, received clock is output again.
When the eighth clock rises while the RDRF bit is 1, the ORER bit in SSSR is set. Then an
overrun error (OEI) is generated and operation is stopped. When the ORER bit in SSSR is set to 1,
reception cannot be performed. Therefore confirm that the ORER bit is cleared to 0 before
reception.
Figure 16.8 shows a sample flowchart for serial data reception.
SSCK
SSO
Bit 0
Bit 7
One frame
Bit 0
Bit 7
Bit 0
Bit 7
One frame
RDRF
RSSTP
LSI operation
User
processing
RXI generated
Dummy read
on SSRDR
RXI generated
Read data in SSRDR
Set RSSTP to 1
RXI generated
Read data
in SSRDR
Figure 16.7 Example of Operation in Data Reception (MSS = 1)
Rev. 4.00 Mar. 15, 2006 Page 366 of 556
REJ09B0026-0400
Section 16 Synchronous Serial Communication Unit (SSU)
Start
Initialization
[1]
Dummy read on SSRDR
[2]
Last reception?
[1] After setting each register in the SSU,
dummy read on SSRDR is performed
and reception is started.
Yes
[2] Determine whether the last one byte of
data is received. When the last one byte
of data is received, set to stop reception
after the data is received.
No
Read ORER
[3]
ORER = 1?
Yes
[3][6] When a receive error occurs, clear the
ORER flag to 0 after the ORER flag in
SSSR is read and an appropriate error
processing is performed. When the ORER
flag is set to 1, transmission/reception
cannot be started again.
No
Read RDRF
[4]
No
[4] Confirm that the RDRF bit is 1. If the RDRF
bit is 1, receive data in SSRDR is read. If the
SSRDR bit is read, the RDRF bit is automatically
cleared.
RDRF = 1?
Yes
Read receive data
in SSRDR
[5]
[5] Before the last one byte of data is received,
set the RSSTP bit to 1 and reception is stopped
after the data is received.
Set RSSTP to 1
Read ORER
Yes
[6]
ORER = 1?
No
Read RDRF
No
[7] Confirm that the RDRF bit is 1. To end
reception, clear the RE and RSSTP bits to
0 and then read the last receive data. If the
SSRDR bit is read before clearing the RE bit,
reception is started again.
RDRF = 1?
[7]
Yes
RE = 0, RSSTP = 0
Overrun error
processing
Read receive data
in SSRDR
End
Figure 16.8 Sample Serial Reception Flowchart (MSS = 1)
Rev. 4.00 Mar. 15, 2006 Page 367 of 556
REJ09B0026-0400
Section 16 Synchronous Serial Communication Unit (SSU)
Serial Data Transmission and Reception: Data transmission and reception is a combined
operation of data transmission and reception which are described before. Transmission and
reception is started by writing data in SSTDR. When the eighth clock rises or the ORER bit is set
to 1 while the TDRE bit is set to 1, transmission and reception is stopped.
To switch from transmit mode (TE = 1) or receive mode (RE = 1) to transmit and receive mode
(TE = RE = 1), the TE and RE bits should be cleared to 0. After confirming that the TEND,
RDRF, and ORER bits are cleared to 0, set the TE and RE bits to 1.
Figure 16.9 shows a sample flowchart for serial transmit and receive operations.
Rev. 4.00 Mar. 15, 2006 Page 368 of 556
REJ09B0026-0400
Section 16 Synchronous Serial Communication Unit (SSU)
Start
Initialization
[1]
Read TDRE in SSSR
No
TDRE = 1?
[1] After reading SSSR and confirming that
the TDRE bit is 1, write transmit data in
SSTDR. Then the TDRE bit is automatically
cleared to 0.
Yes
Write transmit data
in SSTDR
[2]
No
[2] Confirm that the RDRF bit is 1. If the RDRF
bit is 1, receive data in SSRDR is read. If the
SSRDR bit is read, the RDRF bit is automatically
cleared.
Read RDRF in SSSR
RDRF = 1?
Yes
Read receive data
in SSRDR
[3]
Data transmission
continued?
Yes
[3] Determine whether data transmission is continued.
No
[4]
No
Read TEND in SSSR
[4] Data transfer completion can be confirmed
to see if TEND in SSSR becomes 1.
TEND = 1?
Yes
[5]
Clear TEND to 0 and
clear TE and RE in
SSER to 0
[5] To end transmit and receive mode, clear the
TEND bit to 0 and clear the TE and RE bits in
SSER to 0.
End
Figure 16.9 Sample Flowchart for Serial Transmit and Receive Operations
Rev. 4.00 Mar. 15, 2006 Page 369 of 556
REJ09B0026-0400
Section 16 Synchronous Serial Communication Unit (SSU)
16.4.6
Operation in Four-Line Bus Communication Mode
Four-line bus communication mode is a mode which communicates with the four-line bus; a clock
line, a data input line, a data output line, and a chip select line. This mode includes bidirectional
mode in which the data input line and the data output line function as a single pin. The data input
line and the data output line are changed according to the settings of the MSS and BIDE bits in
SSCRH. For details, refer to section 16.4.3, Relationship between Data Input/Output Pin and Shift
Register. In this mode, relationship between clock polarity and phase, and data can be set by the
CPOS and CPHS bits in SSMR. For details, refer to section 16.4.2, Relationship between Clock
Polarity and Phase, and Data.
When the SSU is set as a master device, the chip select line controls output. When the SSU is set
as a slave device, the chip select line controls input. When the SSU is set as a master device, the
chip select line controls output of the SCS pin or controls output of a general port by setting the
CSS1 bit in SSCRH to 1. When the SSU is set as a slave device, the chip select line sets the SCS
pin as an input pin by setting the CSS1 and CSS0 bits in SSCRH to 01.
In four-line bus communication mode, the MLS bit in SSMR is set to 1 and transfer is performed
in MSB-first order.
Rev. 4.00 Mar. 15, 2006 Page 370 of 556
REJ09B0026-0400
Section 16 Synchronous Serial Communication Unit (SSU)
16.4.7
Initialization in Four-Line Bus Communication Mode
Figure 16.10 shows the initialization in four-line bus communication mode. Before transmitting
and receiving data, the TE and RE bits in SSER should be cleared to 0, then the SSU should be
initialized.
Note: When the operating mode, or transfer format, is changed for example, the TE and RE bits
must be cleared to 0 before making the change using the following procedure. When the
TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not
change the contents of the RDRF and ORER flags, or the contents of SSRDR.
Start
Clear TE and RE in SSER to 0
Set SSUMS in SSCRL to 1
[1]
Set MLS in SSMR to 1 and
set CPOS, CPHS, and
CKS2 to CKS0
[2]
Set SCKS in SSCRH to 1 and
set BIDE, MSS, SOOS, CSS1,
and CSS0
[1] The MLS bit is set to 1 for MSB-first transfer.
The clock polarity and phase are set in the
CPOS and CPHS bits.
[2] In bidirectional mode, the BIDE bit is set
to 1 and input/output of the SCS pin is set
by the CSS1 and CSS0 bits.
Clear ORER in SSSR to 0
Set TE and RE in SSER to 1 and
set RIE, TIE, TEIE, and RSSTP
according to transmission/reception/
transmission and reception
End
Figure 16.10 Initialization in Four-Line Bus Communication Mode
Rev. 4.00 Mar. 15, 2006 Page 371 of 556
REJ09B0026-0400
Section 16 Synchronous Serial Communication Unit (SSU)
16.4.8
Serial Data Transmission
Figure 16.11 shows an example of the SSU operation for transmission. In serial transmission, the
SSU operates as described below.
When the SSU is set as a master device, it outputs a synchronous clock and data. When the SSU is
set as a slave device, the SCS pin is in the low-input state and the SSU outputs data in
synchronized with the input clock.
When the SSU writes transmit data in SSTDR after setting the TE bit to 1, the TDRE flag is
automatically cleared to 0 and data is transferred from SSTDR to SSTRSR. Then the SSU sets the
TDRE flag to 1 and starts transmission. If the TIE bit in SSER is set to 1 at this time, a TXI is
generated.
When the TDRE flag is 0 and one frame of data has transferred, data is transferred from SSTDR to
SSTRSR and serial transmission of the next frame is started. If the eighth bit is transmitted while
the TDRE flag is 1, the TEND bit in SSSR is set to 1 and the state is retained. If the TEIE bit in
SSER is set to 1 at this time, a TEI is generated. After transmission is ended, the SSCK pin is
fixed high and the SCS pin goes high. When continuous transmission is performed with the SCS
pin low, the next data should be written to SSTDR before transmitting the eighth bit of the frame.
While the ORER bit in SSSR is set to 1, transmission cannot be performed. Therefore confirm that
the ORER bit is cleared to 0 before transmission.
The difference between this mode and clocked synchronous communication mode is as follows:
when the SSU is set as a master device, the SSO pin is in the Hi-Z state if the SCS pin is in the HiZ state and when the SSU is set as a slave device, the SSI pin is in the Hi-Z state if the SCS pin is
in the high-input state. The sample flowchart for serial data transmission is the same as that in
clocked synchronous communication mode.
Rev. 4.00 Mar. 15, 2006 Page 372 of 556
REJ09B0026-0400
Section 16 Synchronous Serial Communication Unit (SSU)
(1) When CPOS = 0 and CPHS = 0:
SCS
(output)
(Hi-Z)
SSCK
SSO
Bit 7
Bit 6
Bit 0
Bit 7
One frame
Bit 6
Bit 0
One frame
TDRE
TEND
LSI operation
User
processing
TXI generated
Write data
in SSTDR
TXI generated
TEI generated
Write data
in SSTDR
(2) When CPOS = 0 and CPHS = 1:
SCS
(output)
(Hi-Z)
SSCK
Bit 7
SSO
Bit 6
Bit 0
Bit 7
One frame
Bit 6
Bit 0
One frame
TDRE
TEND
LSI operation
User
processing
TXI generated
Write data
in SSTDR
TXI generated
TEI generated
Write data
in SSTDR
Figure 16.11 Example of Operation in Data Transmission (MSS = 1)
Rev. 4.00 Mar. 15, 2006 Page 373 of 556
REJ09B0026-0400
Section 16 Synchronous Serial Communication Unit (SSU)
16.4.9
Serial Data Reception
Figure 16.12 shows an example of the SSU operation for reception. In serial reception, the SSU
operates as described below.
When the SSU is set as a master device, it outputs a synchronous clock and inputs data. When the
SSU is set as a slave device, the SCS pin is in the low-input state and inputs data in synchronized
with the input clock. When the SSU is set as a master device, it outputs a receive clock and starts
reception by performing dummy read on SSRDR.
After eight bits of data is received, the RDRF bit in SSSR is set to 1 and received data is stored in
SSRDR. If the RIE bit in SSER is set to 1 at this time, an RXI is generated. If SSRDR is read, the
RDRF bit is automatically cleared to 0.
When the SSU is set as a master device and reception is ended, received data is read after setting
the RSSTP bit in SSER to 1. Then the SSU outputs eight bits of clocks and operation is stopped.
After that, the RE and RSSTP bits are cleared to 0 and the last received data is read. Note that if
SSRDR is read while the RE bit is set to 1, received clock is output again.
When the eighth clock rises while the RDRF bit is 1, the ORER bit in SSSR is set. Then an
overrun error (OEI) is generated and operation is stopped. When the ORER bit in SSSR is set to 1,
reception cannot be performed. Therefore confirm that the ORER bit is cleared to 0 before
reception.
The set timings of the RDRF and ORER flags differ according to the CPHS setting. These timings
are shown in figure 16.2. When the CPHS bit is set to 1, the flag is set during the frame. Therefore
care should be taken at the end of reception.
The sample flowchart for serial data reception is the same as that in clocked synchronous
communication mode.
Rev. 4.00 Mar. 15, 2006 Page 374 of 556
REJ09B0026-0400
Section 16 Synchronous Serial Communication Unit (SSU)
(1) When CPOS = 0 and CPHS = 0:
SCS
(output)
(Hi-Z)
SSCK
SSI
Bit 7
Bit 0
Bit 7
One frame
Bit 0
Bit 7
Bit 0
One frame
RDRF
RSSTP
RXI generated
LSI operation
User
processing
Dummy read on SSRDR
RXI generated
Read data in SSRDR
Set RSSTP to 1
RXI generated
Read data in SSRDR
(2) When CPOS = 0 and CPHS = 1:
SCS
(output)
(Hi-Z)
SSCK
SSI
Bit 7
Bit 0
One frame
Bit 7
Bit 0
Bit 7
Bit 0
One frame
RDRF
RSSTP
LSI operation
User
processing
RXI generated
Dummy read on SSRDR
RXI generated
Read data in SSRDR
Set RSSTP to 1
RXI generated
Read data in SSRDR
Figure 16.12 Example of Operation in Data Reception (MSS = 1)
Rev. 4.00 Mar. 15, 2006 Page 375 of 556
REJ09B0026-0400
Section 16 Synchronous Serial Communication Unit (SSU)
16.4.10 SCS Pin Control and Arbitration
When the SSUMS bit in SSCRL is set to 1 and the CSS1 bit in SSCRH is set to 1, the MSS bit in
SSCRH is set to 1 and then the arbitration of the SCS pin is checked before starting serial transfer.
If the SSU detects that the synchronized internal SCS pin goes low in this period, the CE bit in
SSSR is set and the MSS bit is cleared.
Note: When a conflict error is set, subsequent transmit operation is not possible. Therefore the
CE bit must be cleared to 0 before starting transmission.
When the multimaster error is used, the CSOS bit in SSCRL should be set to 1.
SCS input
Internal SCS
(synchronized)
MSS
Transfer start
Write data
in SSTDR
CE
SCS output
Maximum time of SCS internal synchronization
Arbitration detection
period
Figure 16.13 Arbitration Check Timing
Rev. 4.00 Mar. 15, 2006 Page 376 of 556
REJ09B0026-0400
Section 16 Synchronous Serial Communication Unit (SSU)
16.4.11 Interrupt Requests
The SSU has five interrupt requests: transmit data empty, transmit end, receive data full, overrun
error, and conflict error. Since these interrupt requests are assigned to the common vector address,
interrupt sources must be determined by flags. Table 16.3 lists the interrupt requests.
Table 16.3 Interrupt Requests
Interrupt Request
Abbreviation
Interrupt Condition
Transmit data empty
TXI
(TIE = 1), (TDRE = 1)
Transmit end
TEI
(TEIE = 1), (TEND = 1)
Receive data full
RXI
(RIE = 1), (RDRF = 1)
Overrun error
OEI
(RIE = 1), (ORER = 1)
Conflict error
CEI
(CEIE = 1), (CE = 1)
When an interrupt condition shown in table 16.3 is 1 and the I bit in CCR is 0, the CPU executes
the interrupt exception handling. Each interrupt source must be cleared during the exception
handling. Note that the TDRE and TEND bits are automatically cleared by writing transmit data in
SSTDR and the RDRF bit is automatically cleared by reading SSRDR. When transmit data is
written in SSTDR, the TDRE bit is set again at the same time. Then if the TDRE bit is cleared,
additional one byte of data may be transmitted.
Rev. 4.00 Mar. 15, 2006 Page 377 of 556
REJ09B0026-0400
Section 16 Synchronous Serial Communication Unit (SSU)
16.5
Usage Note
When the output level of serial data is changed according to the values of the SOL and SOLP bit,
follow the procedures shown in figure 16.14.
Start
Clear the SOLP bit in SSCRH to 0.
Write the new value noted above
to the SOL bit.
Set the SOLP bit in SSCRH to 1.
Write the new value noted above
to the SOL bit.
End
Figure 16.14 Procedures when Changing Output Level of Serial Data
Rev. 4.00 Mar. 15, 2006 Page 378 of 556
REJ09B0026-0400
Section 17 Subsystem Timer (Subtimer)
Section 17 Subsystem Timer (Subtimer)
The subtimer is a timer for controlling subsystem which has an on-chip oscillator for supplying
system clocks in subactive and subsleep modes and an on-chip 8-bit down counter. Since the
subtimer has a prescaler that can set the division ratio by software, it can supply a clock with any
frequency. This LSI has an on-chip single-channel subtimer.
17.1
Features
• On-chip oscillator
Oscillation frequency: 64 kHz to 850 kHz
Temperature characteristic: Source clock ± 10% (typ.)
• Counter: two
8-bit readable/writable down counter
8-bit counter for measuring oscillation frequency of the on-chip oscillator
• CPU interrupt source
Underflow (interrupt interval: 731 µsec to 67.4 msec)
• Subtimer clock supply operating modes:
Subactive mode
Subsleep mode
• On-chip oscillator
The on-chip oscillator supplies three kinds of clocks:
Subactive or subsleep mode (φw)
Subtimer down counter (input clock)
Watchdog timer (input clock)
• Subtimer prescaler (SBTPS)
The subtimer prescaler is a divider which controls input clocks to the counter which measures
oscillation cycle of the on-chip oscillator and the down counter for the subtimer.
Rev. 4.00 Mar. 15, 2006 Page 379 of 556
REJ09B0026-0400
Section 17 Subsystem Timer (Subtimer)
Figure 17.1 shows a block diagram of the subtimer. For details on the signal to the watchdog
timer, refer to section 13, Watchdog Timer.
To system clock
On-chip
oscillator
PSCIN
1/2
SBTPS
1/128
SBTDCNT
ROPCR
Internal data bus
To watchdog timer
SBTCTL
[Legend]
PSCIN:
SBTPS:
ROPCR:
SBTDCNT:
SBTCTL:
Interrupt request signal
Output clock of on-chip oscillator
Subtimer prescaler
Ring oscillator prescaler setting register
Subtimer counter
Subtimer control register
Figure 17.1 Block Diagram of Subtimer
Rev. 4.00 Mar. 15, 2006 Page 380 of 556
REJ09B0026-0400
Section 17 Subsystem Timer (Subtimer)
17.2
Register Descriptions
The subtimer has the following registers.
• Subtimer control register (SBTCTL)
• Subtimer counter (SBTDCNT)
• Ring oscillator prescaler setting register (ROPCR)
17.2.1
Subtimer Control Register (SBTCTL)
SBTCTL controls oscillation of the on-chip oscillator, subclock output, and counter operation and
indicates the operating state. SBTCTL is initialized to H'60.
Bit
Bit Name
Initial
Value
R/W
Description
7
PCEF
0
R/W
Division Count End Flag
[Setting condition]
When counting starts at the first falling edge and SBTPS
halts at the third falling edge after the on-chip oscillator
starts oscillation.
[Clearing condition]
When 0 is written to this bit after reading 1
6, 5

All 1

Reserved
These bits are always read as 1.
4
START
0
R/W
Count Down Start
Starts or halts the SBTDCNT operation.
0: SBTDCNT halts counting down.
1: SBTDCNT starts counting down.
3
OSCEB
0
R/W
On-Chip Oscillator Oscillation Enable
Enables or disables the oscillation of the on-chip
oscillator.
0: Oscillation of on-chip oscillator is disabled.
1: Oscillation of on-chip oscillator is enabled.
Rev. 4.00 Mar. 15, 2006 Page 381 of 556
REJ09B0026-0400
Section 17 Subsystem Timer (Subtimer)
Bit
Bit Name
Initial
Value
R/W
Description
2
SYSCKS
0
R/W
Subclock Supply Enable
Enables or disables clock supply to the entire chip when
the on-chip oscillator for the subtimer is used.
0: Clock supply is disabled.
1: Clock supply is enabled.
1
SBTIB
0
R/W
Subtimer Interrupt Request Enable
When this bit is set to 1, an interrupt request caused by
the SBTUF flag is enabled.
0
SBTUF
0
R/W
Underflow Interrupt Flag
[Setting condition]
When the SBTDCNT value underflows
[Clearing condition]
When 0 is written to this bit after reading 1
17.2.2
Subtimer Counter (SBTDCNT)
SBTDCNT is an 8-bit readable/writable down counter. When SBTDCNT underflows, an interrupt
request is issued and the SBTUF flag in SBTCTL is set to 1. SBTDCNT is initialized to H'FF.
17.2.3
Ring Oscillator Prescaler Setting Register (ROPCR)
ROPCR is an 8-bit readable/writable register. When the OSCEB bit in SBTCTL is set to 1,
SBTPS counts two system clock cycles from the first falling edge of the on-chip oscillator to the
third falling edge and then transfers the count value to ROPCR. After that, ROPCR configures the
division ratio of subclock. ROPCR is initialized to H'FF.
Rev. 4.00 Mar. 15, 2006 Page 382 of 556
REJ09B0026-0400
Section 17 Subsystem Timer (Subtimer)
17.3
Operation
17.3.1
SBTPS Division Ratio Setting
The oscillation frequency of the on-chip oscillator ranges from 64 kHz to 850 kHz. To make a
subclock with expected frequency by dividing the oscillation frequency, ROPCR must be
configured by using following (1) to (6) formulas. The SBTPS division ratio is set as follows.
1. When the OSCEB bit in SBTCTL is set to 1, SBTPS counts two system clock cycles from the
first falling edge of PSCIN to the third falling edge.
2. SBTPS halts counting at the third falling edge of PSCIN, the PCEF flag in SBTCTL is set to 1,
and then the SBTPS value is transferred to ROPCR.
3. By using this count value, the division ratio of the on-chip oscillator is determined and the
value is set in ROPCR.
4. SBTPS starts supplying clocks and SBTDCNT starts counting down by clearing the PCEF flag
in SBTCTL to 0.
t
System clock (φ)
2TRO
PSCIN
PCEF flag
ROPCR H'FF
n
m
Subclock (φw)
OSCEB is set
ROPCR is set
SBTPS counting halts
PCEF is set
Count value is transferred
to ROPCR
PCEF is cleared
Supplying subclocks starts
SBTDCNT counting starts
Figure 17.2 Timing for On-Chip Oscillator
Rev. 4.00 Mar. 15, 2006 Page 383 of 556
REJ09B0026-0400
Section 17 Subsystem Timer (Subtimer)
2TRO = t × n
Formula (1)
The division ratio of the on-chip oscillator to make the subclock be the setting cycle can be
obtained by the following formula.
k=
TSUB
=
TRO
2
t×n
× TSUB =
2 × TSUB
t×n
Formula (2)
In the subtimer, relationship between the setting values in ROPCR and the division ratio is as
follows.
k = 2 (m + 2) (Note that m ≥ 0)
Formula (3)
Then the setting value m in ROPCR can be obtained by assigning the value k obtained by formula
(2) to formula (3).
m=
TSUB
t×n
− 2 (Note that m ≥ 0)
Formula (4)
The cycle to be actually used as the subclock is as follows.
TCAL = 2 (m + 2) × TRO
Formula (5)
Therefore, the rounding error between the expected value and the setting value of the subclock
cycle can be obtained by the following formula.
σ=
TSUB − TCAL
K×t×n
× 100 (%) = 1−
TSUB
2 × TSUB
× 100 (%)
Formula (6)
[Legend]
t:
System clock cycle
n: SBTPS count value (for two cycles)
TRO: On-chip oscillator cycle (calculated value)
TCAL: Subclock cycle (calculated value)
TSUB: Subclock setting cycle (expected value)
k:
Division ratio for oscillation cycle of on-chip oscillator and subclock setting cycle
m: ROPCR setting value
Rev. 4.00 Mar. 15, 2006 Page 384 of 556
REJ09B0026-0400
Section 17 Subsystem Timer (Subtimer)
• Subclock error
In addition to the above rounding error, the subtimer may have a count error caused by time
lag between the system clock and the on-chip oscillator. The example is shown below.
Table 17.1 Example of Subclock Error
Condition: System clock = 10 MHz, on-chip oscillator = 400 kHz, and subclock = 12 kHz
Min.
Expected Value
Max.
Count Value n
49
50
51
Division ratio k
34
33
33
Rounding error of
division ratio σ

+1.0 %

Rounding error of
division ratio σ + count
error
−2.0 %

+1.0 %
After deciding the division ratio according to formulas (1) to (3), the division ratio is
configured in ROPCR. After ROPCR divides clocks of the on-chip oscillator, clocks for the
subtimer counter, input clocks to the system, and input clocks to the watchdog timer are
generated.
Start configuration of division ratio
Set OSCEB bit in SBTCTL to 1
PCEF flag in SBTCTL = 1?
No
Yes
Calculate division ratio
Write calculated division ratio in ROPCR
Clear PCEF flag in SBTCTL to 0
Configuration of division ratio completed
Figure 17.3 SBTPS Setting Flowchart
Rev. 4.00 Mar. 15, 2006 Page 385 of 556
REJ09B0026-0400
Section 17 Subsystem Timer (Subtimer)
The duty cycle of the divided system clock differs according to the ROPCR setting value m.
When m is an even number, the duty cycle is 50 %. When m is an odd number, the duty cycle
is determined according to the following formula:
m+3
× 100 (%)
2m + 4
When m is an odd number, the larger is the setting value m, the closer is the duty cycle to 50
%.
Rev. 4.00 Mar. 15, 2006 Page 386 of 556
REJ09B0026-0400
Section 17 Subsystem Timer (Subtimer)
17.4
Count Operation
The subtimer has an 8-bit readable/writable down counter, SBTDCNT. When any value ranging
from H′00 to H′FF is written to SBTDCNT and the START bit in SBTCTL is set to 1, the
subtimer starts counting down from the configured value in SBTDCNT. When an underflow
occurs at H'00, the subtimer requests an interrupt to the CPU. At the end of the exception
handling, the subtimer starts counting down again from the configured value written in
SBTDCNT. If another value is written in SBTDCNT, the subtimer starts counting down from the
rewritten value. Therefore, the underflow cycle can be set in the range from 1 to 256 input clocks
according to the configured value in SBTDCNT. Figure 17.4 shows an example of the subtimer
operation and figure 17.5 shows the flowchart.
Clocks are supplied to the entire chip by setting the SYSCKS bit in SBTCTL to 1. When the
SYSCKS bit is cleared to 0, clock supply to the entire chip is disabled and only the subtimer
operates.
(Example) When φ is 32 kHz and the underflow cycle is 100 ms:
32 × 103
× 100 × 10-3 = 25
128
Therefore, set 25 (H′19) in SBTDCNT.
Rev. 4.00 Mar. 15, 2006 Page 387 of 556
REJ09B0026-0400
Section 17 Subsystem Timer (Subtimer)
SBTDCNT
count value
H'FF
H'19
H'00
A
B
C
D
E
F
Interrupt request signal
A
B
C
D
E
F
G
: Write H'19 in SBTDCNT
: Set START to 1 to start counting
: Underflow occurs and request an interrupt
: Underflow occurs again and request an interrupt
: Clear START to 0 to stop counting
: Set START to 1 to restart counting
: Reset generated
Figure 17.4 Example of Subtimer Operation
Rev. 4.00 Mar. 15, 2006 Page 388 of 556
REJ09B0026-0400
G
Time
Section 17 Subsystem Timer (Subtimer)
Start count operation setting
Write configured value in SBTDCNT
Set START bit in SBTCTL to 1
No
SBTUF in SBTCTL = 1?
Yes
Clear SBTUF to 0
Yes
Count continued?
No
Clear START bit in SBTCTL to 0
Clear OSCEB bit in SBTCTL to 0
End count operation
Figure 17.5 Count Operation Flowchart
Rev. 4.00 Mar. 15, 2006 Page 389 of 556
REJ09B0026-0400
Section 17 Subsystem Timer (Subtimer)
17.5
Usage Notes
17.5.1
Clock Supply to Watchdog Timer
When the on-chip oscillator for the subtimer is used to supply clocks to the watchdog timer, the
setting is necessary not only for the subtimer but also for the watchdog timer. For details, refer to
section 13, Watchdog Timer.
17.5.2
Writing to ROPCR
ROPCR must be written to in active mode with the PCEF bit in SBTCTL set to 1. Otherwise, the
subtimer may operate incorrectly.
Rev. 4.00 Mar. 15, 2006 Page 390 of 556
REJ09B0026-0400
Section 18 A/D Converter
Section 18 A/D Converter
This LSI includes a successive approximation type 10-bit A/D converter that allows up to eight
analog input channels to be selected. The block diagram of the A/D converter is shown in figure
18.1.
18.1
•
•
•
•
•
•
•
•
Features
10-bit resolution
Eight input channels
Conversion time: at least 3.5 µs per channel (at 20-MHz operation)
Two operating modes
 Single mode: Single-channel A/D conversion
 Scan mode: Continuous A/D conversion on 1 to 4 channels
Four data registers
 Conversion results are held in a data register for each channel
Sample-and-hold function
Two conversion start methods
 Software
 External trigger signal
Interrupt request
 An A/D conversion end interrupt request (ADI) can be generated
Rev. 4.00 Mar. 15, 2006 Page 391 of 556
REJ09B0026-0400
Section 18 A/D Converter
Module data bus
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Analog multiplexer
10-bit D/A
Bus interface
Successive approximations
register
AVCC
Internal data bus
A
D
D
R
A
A
D
D
R
B
A
D
D
R
C
A
D
D
R
D
A
D
C
S
R
A
D
C
R
+
φ/4
Control circuit
Comparator
Sample-andhold circuit
ADTRG
[Legend]
ADCR : A/D control register
ADCSR : A/D control/status register
ADDRA : A/D data register A
ADDRB : A/D data register B
ADDRC : A/D data register C
ADDRD : A/D data register D
Figure 18.1 Block Diagram of A/D Converter
Rev. 4.00 Mar. 15, 2006 Page 392 of 556
REJ09B0026-0400
φ/8
ADI
interrupt
Section 18 A/D Converter
18.2
Input/Output Pins
Table 18.1 summarizes the input pins used by the A/D converter. The 8 analog input pins are
divided into two groups; analog input pins 0 to 3 (AN0 to AN3) comprising group 0, analog input
pins 4 to 7 (AN4 to AN7) comprising group 1. The AVcc pin is the power supply pin for the
analog block in the A/D converter.
Table 18.1 Pin Configuration
Pin Name
Abbreviation
I/O
Function
Analog power supply pin
AVCC
Input
Analog block power supply
Analog input pin 0
AN0
Input
Group 0 analog input
Analog input pin 1
AN1
Input
Analog input pin 2
AN2
Input
Analog input pin 3
AN3
Input
Analog input pin 4
AN4
Input
Analog input pin 5
AN5
Input
Analog input pin 6
AN6
Input
Analog input pin 7
AN7
Input
A/D external trigger input pin ADTRG
Input
Group 1 analog input
External trigger input for starting
A/D conversion
Rev. 4.00 Mar. 15, 2006 Page 393 of 556
REJ09B0026-0400
Section 18 A/D Converter
18.3
Register Descriptions
The A/D converter has the following registers.
•
•
•
•
•
•
A/D data register A (ADDRA)
A/D data register B (ADDRB)
A/D data register C (ADDRC)
A/D data register D (ADDRD)
A/D control/status register (ADCSR)
A/D control register (ADCR)
18.3.1
A/D Data Registers A to D (ADDRA to ADDRD)
There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of
A/D conversion. The ADDR registers, which store a conversion result for each analog input
channel, are shown in table 18.2.
The converted 10-bit data is stored in bits 15 to 6. The lower 6 bits are always read as 0.
The data bus width between the CPU and the A/D converter is 8 bits. The upper byte can be read
directly from the CPU, however the lower byte should be read via a temporary register. The
temporary register contents are transferred from the ADDR when the upper byte data is read.
Therefore, byte access to ADDR should be done by reading the upper byte first then the lower
one. Word access is also possible. ADDR is initialized to H'0000.
Table 18.2 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel
Group 0
Group 1
A/D Data Register to be Stored Results of A/D Conversion
AN0
AN4
ADDRA
AN1
AN5
ADDRB
AN2
AN6
ADDRC
AN3
AN7
ADDRD
Rev. 4.00 Mar. 15, 2006 Page 394 of 556
REJ09B0026-0400
Section 18 A/D Converter
18.3.2
A/D Control/Status Register (ADCSR)
ADCSR consists of the control bits and conversion end status bits of the A/D converter.
Bit
Bit Name
Initial
Value
R/W
Description
7
ADF
0
R/W
A/D End Flag
[Setting conditions]
•
When A/D conversion ends in single mode
•
When A/D conversion ends once on all the channels
selected in scan mode
[Clearing condition]
•
6
ADIE
0
R/W
When 0 is written after reading ADF = 1
A/D Interrupt Enable
A/D conversion end interrupt request (ADI) is enabled by
ADF when this bit is set to 1
5
ADST
0
R/W
A/D Start
Setting this bit to 1 starts A/D conversion. In single mode,
this bit is cleared to 0 automatically when conversion on
the specified channel is complete. In scan mode,
conversion continues sequentially on the specified
channels until this bit is cleared to 0 by software, a reset,
or a transition to standby mode.
4
SCAN
0
R/W
Scan Mode
Selects single mode or scan mode as the A/D conversion
operating mode.
0: Single mode
1: Scan mode
3
CKS
0
R/W
Clock Select
Selects the A/D conversions time.
0: Conversion time = 134 states (max.)
1: Conversion time = 70 states (max.)
Clear the ADST bit to 0 before switching the conversion
time.
Rev. 4.00 Mar. 15, 2006 Page 395 of 556
REJ09B0026-0400
Section 18 A/D Converter
Bit
Bit Name
Initial
Value
R/W
Description
2
CH2
0
R/W
Channel Select 2 to 0
1
CH1
0
R/W
Select analog input channels.
0
CH0
0
R/W
When SCAN = 0
When SCAN = 1
000: AN0
000: AN0
001: AN1
001: AN0 and AN1
010: AN2
010: AN0 to AN2
011: AN3
011: AN0 to AN3
100: AN4
100: AN4
101: AN5
101: AN4 and AN5
110: AN6
110: AN4 to AN6
111: AN7
111: AN4 to AN7
18.3.3
A/D Control Register (ADCR)
ADCR enables A/D conversion started by an external trigger signal.
Bit
Bit Name
Initial
Value
R/W
Description
7
TRGE
0
R/W
Trigger Enable
A/D conversion is started at the falling edge and the rising
edge of the external trigger signal (ADTRG) when this bit
is set to 1.
The selection between the falling edge and rising edge of
the external trigger pin (ADTRG) conforms to the WPEG5
bit in the interrupt edge select register 2 (IEGR2)
6 to 1
—
All 1
—
Reserved
These bits are always read as 1.
0
—
0
R/W
Reserved
Although this bit is readable/writable, do not set this bit to
1.
Rev. 4.00 Mar. 15, 2006 Page 396 of 556
REJ09B0026-0400
Section 18 A/D Converter
18.4
Operation
The A/D converter operates by successive approximation with 10-bit resolution. It has two
operating modes; single mode and scan mode. When changing the operating mode or analog input
channel, in order to prevent incorrect operation, first clear the bit ADST in ADCSR to 0. The
ADST bit can be set at the same time as the operating mode or analog input channel is changed.
18.4.1
Single Mode
In single mode, A/D conversion is performed once for the analog input of the specified single
channel as follows:
1. A/D conversion is started when the ADST bit in ADCSR is set to 1, according to software or
external trigger input.
2. When A/D conversion is completed, the result is transferred to the corresponding A/D data
register of the channel.
3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at
this time, an ADI interrupt request is generated.
4. The ADST bit remains set to 1 during A/D conversion. When A/D conversion ends, the ADST
bit is automatically cleared to 0 and the A/D converter enters the wait state.
18.4.2
Scan Mode
In scan mode, A/D conversion is performed sequentially for the analog input of the specified
channels (four channels maximum) as follows:
1. When the ADST bit in ADCSR is set to 1 by software or external trigger input, A/D
conversion starts on the first channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1).
2. When A/D conversion for each channel is completed, the result is sequentially transferred to
the A/D data register corresponding to each channel.
3. When conversion of all the selected channels is completed, the ADF flag in ADCSR is set to 1.
If the ADIE bit is set to 1 at this time, an ADI interrupt requested is generated. A/D conversion
starts again on the first channel in the group.
4. The ADST bit is not automatically cleared to 0. Steps [2] and [3] are repeated as long as the
ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops.
Rev. 4.00 Mar. 15, 2006 Page 397 of 556
REJ09B0026-0400
Section 18 A/D Converter
18.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (tD) has passed after the ADST bit is set to 1, then
starts conversion. Figure 18.2 shows the A/D conversion timing. Table 18.3 shows the A/D
conversion time.
As indicated in figure 18.2, the A/D conversion time includes tD and the input sampling time. The
length of tD varies depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 18.3.
In scan mode, the values given in table 18.3 apply to the first conversion time. In the second and
subsequent conversions, the conversion time is 128 states (fixed) when CKS = 0 and 66 states
(fixed) when CKS = 1.
(1)
φ
Address
(2)
Write signal
Input sampling
timing
ADF
tD
tSPL
tCONV
[Legend]
ADCSR write cycle
(1):
ADCSR address
(2):
A/D conversion start delay time
tD:
tSPL: Input sampling time
tCONV: A/D conversion time
Figure 18.2 A/D Conversion Timing
Rev. 4.00 Mar. 15, 2006 Page 398 of 556
REJ09B0026-0400
Section 18 A/D Converter
Table 18.3 A/D Conversion Time (Single Mode)
CKS = 0
Item
Symbol
Min.
A/D conversion start delay time
tD
Input sampling time
tSPL
A/D conversion time
tCONV
CKS = 1
Typ.
Max.
Min.
Typ.
Max.
6
—
9
—
31
—
4
—
5
—
15
—
131
—
134
69
—
70
Note: All values represent the number of states.
18.4.4
External Trigger Input Timing
A/D conversion can also be started by an external trigger input. When the TRGE bit in ADCR is
set to 1, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG input
pin sets the ADST bit in ADCSR to 1, starting A/D conversion. Other operations, in both single
and scan modes, are the same as when the bit ADST has been set to 1 by software. Figure 18.3
shows the timing.
φ
ADTRG
Internal trigger signal
ADST
A/D conversion
Figure 18.3 External Trigger Input Timing
Rev. 4.00 Mar. 15, 2006 Page 399 of 556
REJ09B0026-0400
Section 18 A/D Converter
18.5
A/D Conversion Accuracy Definitions
This LSI's A/D conversion accuracy definitions are given below.
• Resolution
The number of A/D converter digital output codes
• Quantization error
The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 18.4).
• Offset error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from the minimum voltage value 0000000000 to 0000000001
(see figure 18.5).
• Full-scale error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from 1111111110 to 1111111111 (see figure 18.5).
• Nonlinearity error
The deviation from the ideal A/D conversion characteristic as the voltage changes from zero to
full scale. This does not include the offset error, full-scale error, or quantization error.
• Absolute accuracy
The deviation between the digital value and the analog input value. Includes offset error, fullscale error, quantization error, and nonlinearity error.
Rev. 4.00 Mar. 15, 2006 Page 400 of 556
REJ09B0026-0400
Section 18 A/D Converter
Digital output
Ideal A/D conversion
characteristic
111
110
101
100
011
010
Quantization error
001
000
1
8
2
8
3
8
4
8
5
8
6
8
7 FS
8
Analog
input voltage
Figure 18.4 A/D Conversion Accuracy Definitions (1)
Full-scale error
Digital output
Ideal A/D conversion
characteristic
Nonlinearity
error
Actual A/D conversion
characteristic
Offset error
FS
Analog
input voltage
Figure 18.5 A/D Conversion Accuracy Definitions (2)
Rev. 4.00 Mar. 15, 2006 Page 401 of 556
REJ09B0026-0400
Section 18 A/D Converter
18.6
Usage Notes
18.6.1
Permissible Signal Source Impedance
This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal
for which the signal source impedance is 5 kΩ or less. This specification is provided to enable the
A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time;
if the sensor output impedance exceeds 5 kΩ, charging may be insufficient and it may not be
possible to guarantee A/D conversion accuracy. However, for A/D conversion in single mode with
a large capacitance provided externally, the input load will essentially comprise only the internal
input resistance of 10 kΩ, and the signal source impedance is ignored. However, as a low-pass
filter effect is obtained in this case, it may not be possible to follow an analog signal with a large
differential coefficient (e.g., 5 mV/µs or greater) (see figure 18.6). When converting a high-speed
analog signal or converting in scan mode, a low-impedance buffer should be inserted.
18.6.2
Influences on Absolute Accuracy
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely
affect absolute accuracy. Be sure to make the connection to an electrically stable GND.
Care is also required to ensure that filter circuits do not interfere with digital signals or act as
antennas on the mounting board.
This LSI
Sensor output
impedance
up to 5 kΩ
A/D converter
equivalent circuit
10 kΩ
Sensor input
Low-pass
filter
C to 0.1 µF
Cin =
15 pF
Figure 18.6 Analog Input Circuit Example
Rev. 4.00 Mar. 15, 2006 Page 402 of 556
REJ09B0026-0400
20 pF
Section 19 Power-On Reset and Low-Voltage Detection Circuits (Optional)
Section 19 Power-On Reset and Low-Voltage Detection
Circuits (Optional)
This LSI can include a power-on reset circuit and low-voltage detection circuit as optional circuits.
The low-voltage detection circuit consists of two circuits: LVDI (interrupt by low voltage detect)
and LVDR (reset by low voltage detect) circuits.
This circuit is used to prevent abnormal operation (runaway execution) from occurring due to the
power supply voltage fall and to recreate the state before the power supply voltage fall when the
power supply voltage rises again.
Even if the power supply voltage falls, the unstable state when the power supply voltage falls
below the guaranteed operating voltage can be removed by entering standby mode when
exceeding the guaranteed operating voltage and during normal operation. Thus, system stability
can be improved. If the power supply voltage falls more, the reset state is automatically entered. If
the power supply voltage rises again, the reset state is held for a specified period, then active mode
is automatically entered.
Figure 19.1 is a block diagram of the power-on reset circuit and the low-voltage detection circuit.
Rev. 4.00 Mar. 15, 2006 Page 403 of 556
REJ09B0026-0400
Section 19 Power-On Reset and Low-Voltage Detection Circuits (Optional)
19.1
Features
• Power-on reset circuit
Uses an external capacitor to generate an internal reset signal when power is first supplied.
• Low-voltage detection circuit
LVDR: Monitors the power-supply voltage, and generates an internal reset signal when the
voltage falls below a specified value.
LVDI: Monitors the power-supply voltage, and generates an interrupt when the voltage falls
below or rises above respective specified values.
Two pairs of detection levels for reset generation voltage are available: when only the LVDR
circuit is used, or when the LVDI and LVDR circuits are both used.
φ
CK
R
OVF
PSS
R
RES
Internal reset
signal
Q
Noise canceler
S
CRES
Power-on reset circuit
Noise canceler
Vcc
Internal data bus
LVDCR
Vreset
Ladder
resistor
+
−
Vint
LVDRES
+
−
LVDINT
Reference
voltage
generator
Interrupt
control
circuit
LVDSR
Interrupt
request
Low-voltage detection circuit
[Legend]
PSS:
LVDCR:
LVDSR:
LVDRES:
LVDINT:
Vreset:
Vint:
Prescaler S
Low-voltage-detection control register
Low-voltage-detection status register
Low-voltage-detection reset signal
Low-voltage-detection interrupt signal
Reset detection voltage
Power-supply fall/rise detection voltage
Figure 19.1 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit
Rev. 4.00 Mar. 15, 2006 Page 404 of 556
REJ09B0026-0400
Section 19 Power-On Reset and Low-Voltage Detection Circuits (Optional)
19.2
Register Descriptions
The low-voltage detection circuit has the following registers.
• Low-voltage-detection control register (LVDCR)
• Low-voltage-detection status register (LVDSR)
19.2.1
Low-Voltage-Detection Control Register (LVDCR)
LVDCR is used to enable or disable the low-voltage detection circuit, set the detection levels for
the LVDR function, enable or disable the LVDR function, and enable or disable generation of an
interrupt when the power-supply voltage rises above or falls below the respective levels.
Table 19.1 shows the relationship between the LVDCR settings and select functions. LVDCR
should be set according to table 19.1.
Bit
Bit Name
Initial
Value
R/W
Description
7
LVDE
0*
R/W
LVD Enable
0: The low-voltage detection circuit is not used (In
standby mode)
1: The low-voltage detection circuit is used
6 to 4

All 1

Reserved
These bits are always read as 1 and cannot be modified.
3
LVDSEL
0*
R/W
LVDR Detection Level Select
0: Reset detection voltage is 2.3 V (typ.)
1: Reset detection voltage is 3.6 V (typ.)
When the falling or rising voltage detection interrupt is
used, reset detection voltage of 2.3 V (typ.) should be
used. When only a reset detection interrupt is used, reset
detection voltage of 3.6 V (typ.) should be used.
2
LVDRE
0*
R/W
LVDR Enable
0: Disables the LVDR function
1: Enables the LVDR function
1
LVDDE
0
R/W
Voltage-Fall-Interrupt Enable
0: Interrupt on the power-supply voltage falling below the
selected detection level disabled
1: Interrupt on the power-supply voltage falling below the
selected detection level enabled
Rev. 4.00 Mar. 15, 2006 Page 405 of 556
REJ09B0026-0400
Section 19 Power-On Reset and Low-Voltage Detection Circuits (Optional)
Bit
Bit Name
Initial
Value
R/W
Description
0
LVDUE
0
R/W
Voltage-Rise-Interrupt Enable
0: Interrupt on the power-supply voltage rising above the
selected detection level disabled
1: Interrupt on the power-supply voltage rising above the
selected detection level enabled
Note:
Not initialized by LVDR but initialized by a power-on reset or WDT reset.
*
Table 19.1 LVDCR Settings and Select Functions
LVDCR Settings
Select Functions
Low-VoltageDetection
Falling
Interrupt
Low-VoltageDetection
Rising
Interrupt
LVDE
LVDSEL
LVDRE
LVDDE
LVDUE
Power-On
Reset
LVDR
0
*
*
*
*
O



1
1
1
0
0
O
O


1
0
0
1
0
O

O

1
0
0
1
1
O

O
O
1
0
1
1
1
O
O
O
O
Note:
*
means invalid.
Rev. 4.00 Mar. 15, 2006 Page 406 of 556
REJ09B0026-0400
Section 19 Power-On Reset and Low-Voltage Detection Circuits (Optional)
19.2.2
Low-Voltage-Detection Status Register (LVDSR)
LVDSR indicates whether the power-supply voltage falls below or rises above the respective
specified values.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 2

All 1

Reserved
1
LVDDF
0*
R/W
LVD Power-Supply Voltage Fall Flag
These bits are always read as 1 and cannot be modified.
[Setting condition]
When the power-supply voltage falls below Vint (D) (typ.
= 3.7 V)
[Clearing condition]
Writing 0 to this bit after reading it as 1
0
LVDUF
0*
R/W
LVD Power-Supply Voltage Rise Flag
[Setting condition]
When the power supply voltage falls below Vint (D) while
the LVDUE bit in LVDCR is set to 1, then rises above Vint
(U) (typ. = 4.0 V) before falling below Vreset1 (typ. = 2.3
V)
[Clearing condition]
Writing 0 to this bit after reading it as 1
Note:
*
Initialized by LVDR.
Rev. 4.00 Mar. 15, 2006 Page 407 of 556
REJ09B0026-0400
Section 19 Power-On Reset and Low-Voltage Detection Circuits (Optional)
19.3
Operation
19.3.1
Power-On Reset Circuit
Figure 19.2 shows the timing of the operation of the power-on reset circuit. As the power-supply
voltage rises, the capacitor which is externally connected to the RES pin is gradually charged via
the on-chip pull-up resistor (typ. 150 kΩ). Since the state of the RES pin is transmitted within the
chip, the prescaler S and the entire chip are in their reset states. When the level on the RES pin
reaches the specified value, the prescaler S is released from its reset state and it starts counting.
The OVF signal is generated to release the internal reset signal after the prescaler S has counted
131,072 clock (φ) cycles. The noise canceler of approximately 500 ns is incorporated to prevent
the incorrect operation of the chip by noise on the RES pin.
To achieve stable operation of this LSI, the power supply needs to rise to its full level and settles
within the specified time. The maximum time required for the power supply to rise and settle after
power has been supplied (tPWON) is determined by the oscillation frequency (fOSC) and capacitance
which is connected to RES pin (CRES). If tPWON means the time required to reach 90 % of power
supply voltage, the power supply circuit should be designed to satisfy the following formula.
tPWON (ms) ≤ 90 × CRES (µF) + 162/fOSC (MHz)
(tPWON ≤ 3000 ms, CRES ≥ 0.22 µF, and fOSC = 10 in 2-MHz to 10-MHz operation)
Note that the power supply voltage (Vcc) must fall below Vpor = 100 mV and rise after charge on
the RES pin is removed. To remove charge on the RES pin, it is recommended that the diode
should be placed near Vcc. If the power supply voltage (Vcc) rises from the point above Vpor, a
power-on reset may not occur.
Rev. 4.00 Mar. 15, 2006 Page 408 of 556
REJ09B0026-0400
Section 19 Power-On Reset and Low-Voltage Detection Circuits (Optional)
tPWON
Vcc
Vpor
Vss
RES
Vss
PSS-reset
signal
OVF
Internal reset
signal
131,072 cycles
PSS counter starts
Reset released
Figure 19.2 Operational Timing of Power-On Reset Circuit
19.3.2
Low-Voltage Detection Circuit
LVDR (Reset by Low Voltage Detect) Circuit:
Figure 19.3 shows the timing of the LVDR function. The LVDR enters the module-standby state
after a power-on reset is canceled. To operate the LVDR, set the LVDE bit in LVDCR to 1, wait
for 50 µs (tLVDON) until the reference voltage and the low-voltage-detection power supply have
stabilized by a software timer, etc., then set the LVDRE bit in LVDCR to 1. After that, the output
settings of ports must be made. To cancel the low-voltage detection circuit, first the LVDRE bit
should be cleared to 0 and then the LVDE bit should be cleared to 0. The LVDE and LVDRE bits
must not be cleared to 0 simultaneously because incorrect operation may occur.
When the power-supply voltage falls below the Vreset voltage (typ. = 2.3 V or 3.6 V), the LVDR
clears the LVDRES signal to 0, and resets the prescaler S. The low-voltage detection reset state
remains in place until a power-on reset is generated. When the power-supply voltage rises above
the Vreset voltage again, the prescaler S starts counting. It counts 131,072 clock (φ) cycles, and
then releases the internal reset signal. In this case, the LVDE, LVDSEL, and LVDRE bits in
LVDCR are not initialized.
Note that if the power supply voltage (Vcc) falls below VLVDRmin = 1.0 V and then rises from that
point, the low-voltage detection reset may not occur.
If the power supply voltage (Vcc) falls below Vpor = 100 mV, a power-on reset occurs.
Rev. 4.00 Mar. 15, 2006 Page 409 of 556
REJ09B0026-0400
Section 19 Power-On Reset and Low-Voltage Detection Circuits (Optional)
VCC
Vreset
VLVDRmin
VSS
LVDRES
PSS-reset
signal
OVF
Internal reset
signal
131,072 cycles
PSS counter starts
Reset released
Figure 19.3 Operational Timing of LVDR Circuit
LVDI (Interrupt by Low Voltage Detect) Circuit:
Figure 19.4 shows the timing of LVDI functions. The LVDI enters the module-standby state after
a power-on reset is canceled. To operate the LVDI, set the LVDE bit in LVDCR to 1, wait for 50
µs (tLVDON) until the reference voltage and the low-voltage-detection power supply have stabilized
by a software timer, etc., then set the LVDDE and LVDUE bits in LVDCR to 1. After that, the
output settings of ports must be made. To cancel the low-voltage detection circuit, first the
LVDDE and LVDUE bits should all be cleared to 0 and then the LVDE bit should be cleared to 0.
The LVDE bit must not be cleared to 0 at the same timing as the LVDDE and LVDUE bits
because incorrect operation may occur.
When the power-supply voltage falls below Vint (D) (typ. = 3.7 V) voltage, the LVDI clears the
LVDINT signal to 0 and the LVDDF bit in LVDSR is set to 1. If the LVDDE bit is 1 at this time,
an IRQ0 interrupt request is simultaneously generated. In this case, the necessary data must be
saved in the external EEPROM, etc, and a transition must be made to standby mode or subsleep
mode. Until this processing is completed, the power supply voltage must be higher than the lower
limit of the guaranteed operating voltage.
When the power-supply voltage does not fall below Vreset1 (typ. = 2.3 V) voltage but rises above
Vint (U) (typ. = 4.0 V) voltage, the LVDI sets the LVDINT signal to 1. If the LVDUE bit is 1 at
Rev. 4.00 Mar. 15, 2006 Page 410 of 556
REJ09B0026-0400
Section 19 Power-On Reset and Low-Voltage Detection Circuits (Optional)
this time, the LVDUF bit in LVDSR is set to 1 and an IRQ0 interrupt request is simultaneously
generated.
If the power supply voltage (Vcc) falls below Vreset1 (typ. = 2.3 V) voltage, the LVDR function
is performed.
Vint (U)
Vint (D)
Vcc
Vreset1
VSS
LVDINT
LVDDE
LVDDF
LVDUE
LVDUF
IRQ0 interrupt generated IRQ0 interrupt generated
Figure 19.4 Operational Timing of LVDI Circuit
Rev. 4.00 Mar. 15, 2006 Page 411 of 556
REJ09B0026-0400
Section 19 Power-On Reset and Low-Voltage Detection Circuits (Optional)
Procedures for Clearing Settings when Using LVDR and LVDI:
To operate or release the low-voltage detection circuit normally, follow the procedure described
below. Figure 19.5 shows the timing for the operation and release of the low-voltage detection
circuit.
1. To operate the low-voltage detection circuit, set the LVDE bit in LVDCR to 1.
2. Wait for 50 µs (tLVDON) until the reference voltage and the low-voltage-detection power supply
have stabilized by a software timer, etc. Then, clear the LVDDF and LVDUF bits in LVDSR
to 0 and set the LVDRE, LVDDE, and LVDUE bits in LVDCR to 1, as required.
3. To release the low-voltage detection circuit, start by clearing all of the LVDRE, LVDDE, and
LVDUE bits to 0. Then clear the LVDE bit to 0. The LVDE bit must not be cleared to 0 at the
same timing as the LVDRE, LVDDE, and LVDUE bits because incorrect operation may occur.
LVDE
LVDRE
LVDDE
LVDUE
tLVDON
Figure 19.5 Timing for Operation/Release of Low-Voltage Detection Circuit
Rev. 4.00 Mar. 15, 2006 Page 412 of 556
REJ09B0026-0400
Section 20 Power Supply Circuit
Section 20 Power Supply Circuit
This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the
internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the
voltage of the power supply connected to the external VCC pin. As a result, the current consumed
when an external power supply is used at 3.0 V or above can be held down to virtually the same
low level as when used at approximately 3.0 V. If the external power supply is 3.0 V or below, the
internal voltage will be practically the same as the external voltage. It is, of course, also possible
to use the same level of external power supply voltage and internal power supply voltage without
using the internal power supply step-down circuit.
20.1
When Using Internal Power Supply Step-Down Circuit
Connect the external power supply to the VCC pin, and connect a capacitance of approximately 0.1
µF between VCL and VSS, as shown in figure 20.1. The internal step-down circuit is made effective
simply by adding this external circuit. In the external circuit interface, the external power supply
voltage connected to VCC and the GND potential connected to VSS are the reference levels. For
example, for port input/output levels, the VCC level is the reference for the high level, and the VSS
level is that for the low level. The A/D converter analog power supply is not affected by the
internal step-down circuit.
VCC
Step-down circuit
Internal
logic
VCC = 3.0 to 5.5 V
VCL
Stabilization
capacitance
(approx. 0.1 µF)
Internal
power
supply
VSS
Figure 20.1 Power Supply Connection when Internal Step-Down Circuit is Used
Rev. 4.00 Mar. 15, 2006 Page 413 of 556
REJ09B0026-0400
Section 20 Power Supply Circuit
20.2
When Not Using Internal Power Supply Step-Down Circuit
When the internal power supply step-down circuit is not used, connect the external power supply
to the VCL pin and VCC pin, as shown in figure 20.2. The external power supply is then input directly
to the internal power supply. The permissible range for the power supply voltage is 3.0 V to 3.6 V.
Operation cannot be guaranteed if a voltage outside this range (less than 3.0 V or more than 3.6 V)
is input.
VCC
Step-down circuit
Internal
logic
VCC = 3.0 to 3.6 V
VCL
Internal
power
supply
VSS
Figure 20.2 Power Supply Connection when Internal Step-Down Circuit is Not Used
Rev. 4.00 Mar. 15, 2006 Page 414 of 556
REJ09B0026-0400
Section 21 List of Registers
Section 21 List of Registers
The register list gives information on the on-chip I/O register addresses, how the register bits are
configured, and the register states in each operating mode. The information is given as shown
below.
1. Register addresses (address order)
• Registers are listed from the lower allocation addresses.
• The symbol  in the register-name column represents a reserved address or range of reserved
addresses.
Do not attempt to access reserved addresses.
• When the address is 16-bit wide, the address of the upper byte is given in the list.
• Registers are classified by functional modules.
• The data bus width is indicated.
• The number of access states is indicated.
2.
•
•
•
Register bits
Bit configurations of the registers are described in the same order as the register addresses.
Reserved bits are indicated by  in the bit name column.
When registers consist of 16 bits, bits are described from the MSB side.
3. Register states in each operating mode
• Register states are described in the same order as the register addresses.
• The register states described here are for the basic operating modes. If there is a specific reset
for an on-chip peripheral module, refer to the section on that on-chip peripheral module.
Rev. 4.00 Mar. 15, 2006 Page 415 of 556
REJ09B0026-0400
Section 21 List of Registers
21.1
Register Addresses (Address Order)
The data-bus width column indicates the number of bits. The access-state column shows the
number of states of the selected basic clock that is required for access to the register.
Note: Access to undefined or reserved addresses should not take place. Correct operation of the
access itself or later operations is not guaranteed when such a register is accessed.
Data
Bus
Width
Access
State
H'F000 to 
H'F5FF


8
H'F600
TinyCAN
8
4
GSR
8
H'F601
TinyCAN
8
4
Bit configuration register 1
BCR1
8
H'F602
TinyCAN
8
4
Bit configuration register 0
BCR0
8
H'F603
TinyCAN
8
4
Mailbox configuration register
MBCR
8
H'F604
TinyCAN
8
4
Register Name
Abbreviation
Bit No Address



Master control register
MCR
General status register
Module
Name
TinyCAN module control register
TCMR
8
H'F605
TinyCAN
8
4
Transmit pending register
TXPR
8
H'F606
TinyCAN
8
4
Transmit pending cancel register
TXCR
8
H'F608
TinyCAN
8
4
Transmit acknowledge register
TXACK
8
H'F60A
TinyCAN
8
4
Abort acknowledge register
ABACK
8
H'F60C
TinyCAN
8
4
Receive complete register
RXPR
8
H'F60E
TinyCAN
8
4
Remote request register
RFPR
8
H'F610
TinyCAN
8
4
TinyCAN interrupt register 1
TCIRR1
8
H'F612
TinyCAN
8
4
TinyCAN interrupt register 0
TCIRR0
8
H'F613
TinyCAN
8
4
Mailbox interrupt mask register
MBIMR
8
H'F614
TinyCAN
8
4
TinyCAN interrupt mask register 1
TCIMR1
8
H'F616
TinyCAN
8
4
TinyCAN interrupt mask register 0
TCIMR0
8
H'F617
TinyCAN
8
4
Receive error counter
REC
8
H'F618
TinyCAN
8
4
Transmit error counter
TEC
8
H'F619
TinyCAN
8
4
Test control register
TCR
8
H'F61A
TinyCAN
8
4
Unread message status register
UMSR
8
H'F61B
TinyCAN
8
4
Message control 0 [0]
MC0[0]
8
H'F620
TinyCAN
8
4
Rev. 4.00 Mar. 15, 2006 Page 416 of 556
REJ09B0026-0400
Section 21 List of Registers
Bit No Address
Module
Name
Data
Bus
Width
Access
State
MC0[4]
8
H'F624
TinyCAN
8
4
Message control 0 [5]
MC0[5]
8
H'F625
TinyCAN
8
4
Message control 0 [6]
MC0[6]
8
H'F626
TinyCAN
8
4
Message control 0 [7]
MC0[7]
8
H'F627
TinyCAN
8
4
Message control 1 [0]
MC1[0]
8
H'F628
TinyCAN
8
4
Message control 1 [4]
MC1[4]
8
H'F62C
TinyCAN
8
4
Message control 1 [5]
MC1[5]
8
H'F62D
TinyCAN
8
4
Message control 1 [6]
MC1[6]
8
H'F62E
TinyCAN
8
4
Message control 1 [7]
MC1[7]
8
H'F62F
TinyCAN
8
4
Message control 2 [0]
MC2[0]
8
H'F630
TinyCAN
8
4
Message control 2 [4]
MC2[4]
8
H'F634
TinyCAN
8
4
Message control 2 [5]
MC2[5]
8
H'F635
TinyCAN
8
4
Message control 2 [6]
MC2[6]
8
H'F636
TinyCAN
8
4
Message control 2 [7]
MC2[7]
8
H'F637
TinyCAN
8
4
Message control 3 [0]
MC3[0]
8
H'F638
TinyCAN
8
4
Message control 3 [4]
MC3[4]
8
H'F63C
TinyCAN
8
4
Message control 3 [5]
MC3[5]
8
H'F63D
TinyCAN
8
4
Message control 3 [6]
MC3[6]
8
H'F63E
TinyCAN
8
4
Register Name
Abbreviation
Message control 0 [4]
Message control 3 [7]
MC3[7]
8
H'F63F
TinyCAN
8
4
Message data 0 [0]
MD0[0]
8
H'F640
TinyCAN
8
4
Message data 0 [1]
MD0[1]
8
H'F641
TinyCAN
8
4
Message data 0 [2]
MD0[2]
8
H'F642
TinyCAN
8
4
Message data 0 [3]
MD0[3]
8
H'F643
TinyCAN
8
4
Message data 0 [4]
MD0[4]
8
H'F644
TinyCAN
8
4
Message data 0 [5]
MD0[5]
8
H'F645
TinyCAN
8
4
Message data 0 [6]
MD0[6]
8
H'F646
TinyCAN
8
4
Message data 0 [7]
MD0[7]
8
H'F647
TinyCAN
8
4
Message data 1 [0]
MD1[0]
8
H'F648
TinyCAN
8
4
Message data 1 [1]
MD1[1]
8
H'F649
TinyCAN
8
4
Message data 1 [2]
MD1[2]
8
H'F64A
TinyCAN
8
4
Message data 1 [3]
MD1[3]
8
H'F64B
TinyCAN
8
4
Rev. 4.00 Mar. 15, 2006 Page 417 of 556
REJ09B0026-0400
Section 21 List of Registers
Register Name
Abbreviation
Module
Bit No Address Name
Data
Bus
Access
Width State
Message data 1 [4]
MD1[4]
8
H'F64C
TinyCAN
8
4
Message data 1 [5]
MD1[5]
8
H'F64D
TinyCAN
8
4
Message data 1 [6]
MD1[6]
8
H'F64E
TinyCAN
8
4
Message data 1 [7]
MD1[7]
8
H'F64F
TinyCAN
8
4
Message data 2 [0]
MD2[0]
8
H'F650
TinyCAN
8
4
Message data 2 [1]
MD2[1]
8
H'F651
TinyCAN
8
4
Message data 2 [2]
MD2[2]
8
H'F652
TinyCAN
8
4
Message data 2 [3]
MD2[3]
8
H'F653
TinyCAN
8
4
Message data 2 [4]
MD2[4]
8
H'F654
TinyCAN
8
4
Message data 2 [5]
MD2[5]
8
H'F655
TinyCAN
8
4
Message data 2 [6]
MD2[6]
8
H'F656
TinyCAN
8
4
Message data 2 [7]
MD2[7]
8
H'F657
TinyCAN
8
4
Message data 3 [0]
MD3[0]
8
H'F658
TinyCAN
8
4
Message data 3 [1]
MD3[1]
8
H'F659
TinyCAN
8
4
Message data 3 [2]
MD3[2]
8
H'F65A
TinyCAN
8
4
Message data 3 [3]
MD3[3]
8
H'F65B
TinyCAN
8
4
Message data 3 [4]
MD3[4]
8
H'F65C
TinyCAN
8
4
Message data 3 [5]
MD3[5]
8
H'F65D
TinyCAN
8
4
Message data 3 [6]
MD3[6]
8
H'F65E
TinyCAN
8
4
Message data 3 [7]
MD3[7]
8
H'F65F
TinyCAN
8
4
Local acceptance filter mask L01
LAFML01 8
H'F660
TinyCAN
8
4
Local acceptance filter mask L00
LAFML00 8
H'F661
TinyCAN
8
4
Local acceptance filter mask H01
LAFMH01 8
H'F662
TinyCAN
8
4
Local acceptance filter mask H00
LAFMH00 8
H'F663
TinyCAN
8
4
Local acceptance filter mask L11
LAFML11 8
H'F664
TinyCAN
8
4
Local acceptance filter mask L10
LAFML10 8
H'F665
TinyCAN
8
4
Local acceptance filter mask H11
LAFMH11 8
H'F666
TinyCAN
8
4
Local acceptance filter mask H10
LAFMH10 8
H'F667
TinyCAN
8
4
Local acceptance filter mask L21
LAFML21 8
H'F668
TinyCAN
8
4
Local acceptance filter mask L20
LAFML20 8
H'F669
TinyCAN
8
4
Rev. 4.00 Mar. 15, 2006 Page 418 of 556
REJ09B0026-0400
Section 21 List of Registers
Register Name
Abbreviation
Module
Bit No Address Name
Data
Bus
Access
Width State
Local acceptance filter mask H21
LAFMH21
8
H'F66A
TinyCAN
8
4
Local acceptance filter mask H20
LAFMH20
8
H'F66B
TinyCAN
8
4
Local acceptance filter mask L31
LAFML31
8
H'F66C
TinyCAN
8
4
Local acceptance filter mask L30
LAFML30
8
H'F66D
TinyCAN
8
4
Local acceptance filter mask H31
LAFMH31
8
H'F66E
TinyCAN
8
4
Local acceptance filter mask H30
LAFMH30
8
H'F66F
TinyCAN
8
4



H'F670 to 
H'F69F


SS control register H
SSCRH
8
H'F6A0
SSU
8
4
SS control register L
SSCRL
8
H'F6A1
SSU
8
4
SS mode register
SSMR
8
H'F6A2
SSU
8
4
SS enable register
SSER
8
H'F6A3
SSU
8
4
SS status register
SSSR
8
H'F6A4
SSU
8
4
SS receive data register
SSRDR
8
H'F6A9
SSU
8
4
SS transmit data register
SSTDR
8
H'F6AB
SSU
8
4
Subtimer control register
SBTCTL
8
H'F6B0
Subtimer
8
4
Subtimer counter
SBTDCNT 8
H'F6B1
Subtimer
8
4
Ring oscillator prescaler setting
register
ROPCR
8
H'F6B2
Subtimer
8
4



H'F6B3 to 
H'F6FF


Timer control register_0
TCR_0
8
H'F700
Timer Z
8
2
Timer I/O control register A_0
TIORA_0
8
H'F701
Timer Z
8
2
Timer I/O control register C_0
TIORC_0 8
H'F702
Timer Z
8
2
Timer status register_0
TSR_0
8
H'F703
Timer Z
8
2
Timer interrupt enable register_0
TIER_0
8
H'F704
Timer Z
8
2
PWM mode output level control
register_0
POCR_0
8
H'F705
Timer Z
8
2
Timer counter_0
TCNT_0
16
H'F706
Timer Z
16
2
General register A_0
GRA_0
16
H'F708
Timer Z
16
2
General register B_0
GRB_0
16
H'F70A
Timer Z
16
2
Rev. 4.00 Mar. 15, 2006 Page 419 of 556
REJ09B0026-0400
Section 21 List of Registers
Register Name
Abbreviation
Module
Bit No Address Name
Data
Bus
Access
Width State
General register C_0
GRC_0
16
H'F70C
Timer Z
16
2
General register D_0
GRD_0
16
H'F70E
Timer Z
16
2
Timer control register_1
TCR_1
8
H'F710
Timer Z
8
2
Timer I/O control register A_1
TIORA_1 8
H'F711
Timer Z
8
2
Timer I/O control register C_1
TIORC_1 8
H'F712
Timer Z
8
2
Timer status register_1
TSR_1
8
H'F713
Timer Z
8
2
Timer interrupt enable register_1
TIER_1
8
H'F714
Timer Z
8
2
PWM mode output level control
register_1
POCR_1 8
H'F715
Timer Z
8
2
Timer counter_1
TCNT_1 16
H'F716
Timer Z
16
2
General register A_1
GRA_1
16
H'F718
Timer Z
16
2
General register B_1
GRB_1
16
H'F71A
Timer Z
16
2
General register C_1
GRC_1
16
H'F71C
Timer Z
16
2
General register D_1
GRD_1
16
H'F71E
Timer Z
16
2
Timer start register
TSTR
8
H'F720
Timer Z
8
2
Timer mode register
TMDR
8
H'F721
Timer Z
8
2
Timer PWM mode register
TPMR
8
H'F722
Timer Z
8
2
Timer function control register
TFCR
8
H'F723
Timer Z
8
2
Timer output master enable register TOER
8
H'F724
Timer Z
8
2
Timer output control register
TOCR
8
H'F725
Timer Z
8
2
—
—
—
H'F726 to —
H'F72F
—
—
Low-voltage-detection control
register
LVDCR
8
H'F730
LVDC*1
8
2
Low-voltage-detection status
register
LVDSR
8
H'F731
LVDC*1
8
2
—
—
—
H'F732 to —
H'F73F
—
—
Serial mode register_2
SMR_2
8
H'F740
SCI3_2*3
8
3
3
8
3
3
8
3
3
8
3
Bit rate register_2
BRR_2
8
H'F741
SCI3_2*
Serial control register 3_2
SCR3_2 8
H'F742
SCI3_2*
Transmit data register_2
TDR_2
Rev. 4.00 Mar. 15, 2006 Page 420 of 556
REJ09B0026-0400
8
H'F743
SCI3_2*
Section 21 List of Registers
Register Name
Abbreviation
Bit No Address
Module
Name
Serial status register_2
SSR_2
8
SCI3_2*
SCI3_2*
H'F744
Data
Bus
Width
Access
State
3
8
3
3
8
3
Receive data register_2
RDR_2
8
H'F745
—
—
—
H'F746 to —
H'F75F
—
—
Timer mode register B1
TMB1
8
H'F760
Timer B1
8
2
Timer counter B1
TCB1
8
H'F761
Timer B1
8
2
Timer load register B1
TLB1
8
H'F761
Timer B1
8
2
—
—
—
H'F762 to —
H'FF8F
—
—
Flash memory control register 1
FLMCR1
8
H'FF90
ROM
8
2
Flash memory control register 2
FLMCR2
8
H'FF91
ROM
8
2
Flash memory power control
register
FLPWCR 8
H'FF92
ROM
8
2
Erase block register 1
EBR1
8
H'FF93
ROM
8
2
—
—
—
H'FF94 to —
H'FF9A
—
—
Flash memory enable register
FENR
8
H'FF9B
8
2
—
—
—
H'FF9C to —
H'FF9F
—
—
Timer control register V0
TCRV0
8
H'FFA0
Timer V
8
3
Timer control/status register V
TCSRV
8
H'FFA1
Timer V
8
3
Time constant register A
TCORA
8
H'FFA2
Timer V
8
3
Time constant register B
TCORB
8
H'FFA3
Timer V
8
3
Timer counter V
TCNTV
8
H'FFA4
Timer V
8
3
Timer control register V1
TCRV1
8
H'FFA5
Timer V
8
3
—
—
—
H'FFA6,
H'FFA7
—
—
—
Serial mode register
SMR
8
H'FFA8
SCI3
8
3
Bit rate register
BRR
8
H'FFA9
SCI3
8
3
Serial control register 3
SCR3
8
H'FFAA
SCI3
8
3
Transmit data register
TDR
8
H'FFAB
SCI3
8
3
Serial status register
SSR
8
H'FFAC
SCI3
8
3
ROM
Rev. 4.00 Mar. 15, 2006 Page 421 of 556
REJ09B0026-0400
Section 21 List of Registers
Address
Module
Name
Data
Bus
Width
Access
State
8
H'FFAD
SCI3
8
3
—
—
H'FFAE,
H'FFAF
—
—
—
A/D data register A
ADDRA
16
H'FFB0
A/D
converter
8
3
A/D data register B
ADDRB
16
H'FFB2
A/D
converter
8
3
A/D data register C
ADDRC
16
H'FFB4
A/D
converter
8
3
A/D data register D
ADDRD
16
H'FFB6
A/D
converter
8
3
A/D control/status register
ADCSR
8
H'FFB8
A/D
converter
8
3
A/D control register
ADCR
8
H'FFB9
A/D
converter
8
3
—
—
—
H'FFBA to
H'FFBF
—
—
—
Timer control/status register WD
TCSRWD 8
H'FFC0
WDT*2
8
2
2
Register Name
Abbreviation
Bit No
Receive data register
RDR
—
Timer counter WD
TCWD
8
H'FFC1
WDT*
8
2
Timer mode register WD
TMWD
8
H'FFC2
WDT*2
8
2
—
—
—
H'FFC3 to
H'FFC7
—
—
—
Address break control register
ABRKCR
8
H'FFC8
Address
break
8
2
Address break status register
ABRKSR
8
H'FFC9
Address
break
8
2
Break address register H
BARH
8
H'FFCA
Address
break
8
2
Break address register L
BARL
8
H'FFCB
Address
break
8
2
Break data register H
BDRH
8
H'FFCC
Address
break
8
2
Break data register L
BDRL
8
H'FFCD
Address
break
8
2
Rev. 4.00 Mar. 15, 2006 Page 422 of 556
REJ09B0026-0400
Section 21 List of Registers
Module
Name
Data
Bus
Width
Access
State
H'FFCE,
H'FFCF
—
—
—
8
H'FFD0
I/O port
8
2
PUCR5
8
H'FFD1
I/O port
8
2
—
—
—
H'FFD2,
H'FFD3
—
—
—
Port data register 1
PDR1
8
H'FFD4
I/O port
8
2
Port data register 2
PDR2
8
H'FFD5
I/O port
8
2
—
—
—
H'FFD6,
H'FFD7
—
—
—
Port data register 5
PDR5
8
H'FFD8
I/O port
8
2
Port data register 6
PDR6
8
H'FFD9
I/O port
8
2
Port data register 7
PDR7
8
H'FFDA
I/O port
8
2
Port data register 8
PDR8
8
H'FFDB
I/O port
8
2
Port data register 9
PDR9
8
H'FFDC
I/O port
8
2
Register Name
Abbreviation
Bit No
Address
—
—
—
Port pull-up control register 1
PUCR1
Port pull-up control register 5
Port data register B
PDRB
8
H'FFDD
I/O port
8
2
—
—
—
H'FFDE,
H'FFDF
—
—
—
Port mode register 1
PMR1
8
H'FFE0
I/O port
8
2
Port mode register 5
PMR5
8
H'FFE1
I/O port
8
2
Port mode register 3
PMR3
8
H'FFE2
I/O port
8
2
—
—
—
H'FFE3
—
—
—
Port control register 1
PCR1
8
H'FFE4
I/O port
8
2
Port control register 2
PCR2
8
H'FFE5
I/O port
8
2
—
—
—
H'FFE6,
H'FFE7
—
—
—
Port control register 5
PCR5
8
H'FFE8
I/O port
8
2
Port control register 6
PCR6
8
H'FFE9
I/O port
8
2
Port control register 7
PCR7
8
H'FFEA
I/O port
8
2
Port control register 8
PCR8
8
H'FFEB
I/O port
8
2
Port control register 9
PCR9
8
H'FFEC
I/O port
8
2
Rev. 4.00 Mar. 15, 2006 Page 423 of 556
REJ09B0026-0400
Section 21 List of Registers
Data
Bus
Width
Access
State
H'FFED to —
H'FFEF
—
—
8
H'FFF0
Powerdown
8
2
SYSCR2
8
H'FFF1
Powerdown
8
2
IEGR1
8
H'FFF2
Interrupt
8
2
Interrupt edge select register 2
IEGR2
8
H'FFF3
Interrupt
8
2
Interrupt enable register 1
IENR1
8
H'FFF4
Interrupt
8
2
Interrupt enable register 2
IENR2
8
H'FFF5
Interrupt
8
2
Interrupt flag register 1
IRR1
8
H'FFF6
Interrupt
8
2
Interrupt flag register 2
IRR2
8
H'FFF7
Interrupt
8
2
Wakeup interrupt flag register
IWPR
8
H'FFF8
Interrupt
8
2
Module standby control register 1 MSTCR1
8
H'FFF9
Powerdown
8
2
Module standby control register 2 MSTCR2
8
H'FFFA
Powerdown
8
2
—
—
H'FFFB to
H'FFFF
—
—
—
Register Name
Abbreviation
Bit No
Address
—
—
—
System control register 1
SYSCR1
System control register 2
Interrupt edge select register 1
Notes: 1.
2.
3.
—
LVDC: Low-voltage detection circuits (optional)
WDT: Watchdog timer
The H8/36037 Group does not have the SCI3_2.
Rev. 4.00 Mar. 15, 2006 Page 424 of 556
REJ09B0026-0400
Module
Name
Section 21 List of Registers
21.2
Register Bits
The addresses and bit names of the registers in the on-chip peripheral modules are listed below.
The 16-bit register is indicated in two rows, 8 bits for each row.
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
TinyCAN
MCR
—
—
—
—
—
—
HLTRQ
RSTRQ
GSR
—
—
ERPS
HALT
RESET
TCMPL
ECWRG
BOFF
BCR1
—
TSG22
TSG21
TSG20
TSG13
TSG12
TSG11
TSG10
BCR0
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BPR0
MBCR
—
—
—
—
MB3
MB2
MB1
—
TCMR
MSTTC
—
—
—
—
—
PMR97
PMR96
TXPR
—
—
—
—
MB3
MB2
MB1
—
TXCR
—
—
—
—
MB3
MB2
MB1
—
TXACK
—
—
—
—
MB3
MB2
MB1
—
ABACK
—
—
—
—
MB3
MB2
MB1
—
RXPR
—
—
—
—
MB3
MB2
MB1
MB0
RFPR
—
—
—
—
MB3
MB2
MB1
MB0
TCIRR1
—
—
—
WUPI
—
—
OVRI
EMPI
TCIRR0
OVLI
BOFI
EPI
ROWI
TOWI
RFRI
DFRI
RHI
MBIMR
—
—
—
—
MB3
MB2
MB1
MB0
TCIMR1
—
—
—
WUPIM
—
—
OVRIM
EMPIM
TCIMR0
OVLIM
BOFIM
EPIM
ROWIM
TOWIM
RFRIM
DFRIM
RHIM
REC
REC7
REC6
REC5
REC4
REC3
REC2
REC1
REC0
TEC
TEC7
TEC6
TEC5
TEC4
TEC3
TEC2
TEC1
TEC0
TCR
TSTMD
WREC
FERPS
ATACK
DEC
DRXIN
DTXOT
INTILE
UMSR
—
—
—
—
MB3
MB2
MB1
MB0
MC 0 [0]
DART
NMC
—
—
DLC3
DLC2
DLC1
DLC0
MC 0 [4]
ID20
ID19
ID18
RTR
IDE
—
ID17
ID16
MC 0 [5]
ID28
ID27
ID26
ID25
ID24
ID23
ID22
ID21
MC 0 [6]
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
MC 0 [7]
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
MC 1 [0]
DART
NMC
—
—
DLC3
DLC2
DLC1
DLC0
Rev. 4.00 Mar. 15, 2006 Page 425 of 556
REJ09B0026-0400
Section 21 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
MC 1 [4]
ID20
ID19
ID18
RTR
IDE
—
ID17
ID16
TinyCAN
MC 1 [5]
ID28
ID27
ID26
ID25
ID24
ID23
ID22
ID21
MC 1 [6]
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
MC 1 [7]
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
MC 2 [0]
DART
NMC
—
—
DLC3
DLC2
DLC1
DLC0
MC 2 [4]
ID20
ID19
ID18
RTR
IDE
—
ID17
ID16
MC 2 [5]
ID28
ID27
ID26
ID25
ID24
ID23
ID22
ID21
MC 2 [6]
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
MC 2 [7]
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
MC 3 [0]
DART
NMC
—
—
DLC3
DLC2
DLC1
DLC0
MC 3 [4]
ID20
ID19
ID18
RTR
IDE
—
ID17
ID16
MC 3 [5]
ID28
ID27
ID26
ID25
ID24
ID23
ID22
ID21
MC 3 [6]
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
MC 3 [7]
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
MD 0 [0]
MD07
MD06
MD05
MD04
MD03
MD02
MD01
MD00
MD 0 [1]
MD17
MD16
MD15
MD14
MD13
MD12
MD11
MD10
MD 0 [2]
MD27
MD26
MD25
MD24
MD23
MD22
MD21
MD20
MD 0 [3]
MD37
MD36
MD35
MD34
MD33
MD32
MD31
MD30
MD 0 [4]
MD47
MD46
MD45
MD44
MD43
MD42
MD41
MD40
MD 0 [5]
MD57
MD56
MD55
MD54
MD53
MD52
MD51
MD50
MD 0 [6]
MD67
MD66
MD65
MD64
MD63
MD62
MD61
MD60
MD 0 [7]
MD77
MD76
MD75
MD74
MD73
MD72
MD71
MD70
MD 1 [0]
MD07
MD06
MD05
MD04
MD03
MD02
MD01
MD00
MD 1 [1]
MD17
MD16
MD15
MD14
MD13
MD12
MD11
MD10
MD 1 [2]
MD27
MD26
MD25
MD24
MD23
MD22
MD21
MD20
MD 1 [3]
MD37
MD36
MD35
MD34
MD33
MD32
MD31
MD30
MD 1 [4]
MD47
MD46
MD45
MD44
MD43
MD42
MD41
MD40
MD 1 [5]
MD57
MD56
MD55
MD54
MD53
MD52
MD51
MD50
MD 1 [6]
MD67
MD66
MD65
MD64
MD63
MD62
MD61
MD60
MD 1 [7]
MD77
MD76
MD75
MD74
MD73
MD72
MD71
MD70
Rev. 4.00 Mar. 15, 2006 Page 426 of 556
REJ09B0026-0400
Section 21 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
MD 2 [0]
MD07
MD06
MD05
MD04
MD03
MD02
MD01
MD00
TinyCAN
MD 2 [1]
MD17
MD16
MD15
MD14
MD13
MD12
MD11
MD10
MD 2 [2]
MD27
MD26
MD25
MD24
MD23
MD22
MD21
MD20
MD 2 [3]
MD37
MD36
MD35
MD34
MD33
MD32
MD31
MD30
MD 2 [4]
MD47
MD46
MD45
MD44
MD43
MD42
MD41
MD40
MD 2 [5]
MD57
MD56
MD55
MD54
MD53
MD52
MD51
MD50
MD 2 [6]
MD67
MD66
MD65
MD64
MD63
MD62
MD61
MD60
MD 2 [7]
MD77
MD76
MD75
MD74
MD73
MD72
MD71
MD70
MD 3 [0]
MD07
MD06
MD05
MD04
MD03
MD02
MD01
MD00
MD 3 [1]
MD17
MD16
MD15
MD14
MD13
MD12
MD11
MD10
MD 3 [2]
MD27
MD26
MD25
MD24
MD23
MD22
MD21
MD20
MD 3 [3]
MD37
MD36
MD35
MD34
MD33
MD32
MD31
MD30
MD 3 [4]
MD47
MD46
MD45
MD44
MD43
MD42
MD41
MD40
MD 3 [5]
MD57
MD56
MD55
MD54
MD53
MD52
MD51
MD50
MD 3 [6]
MD67
MD66
MD65
MD64
MD63
MD62
MD61
MD60
MD 3 [7]
MD77
MD76
MD75
MD74
MD73
MD72
MD71
MD70
LAFML01
LAFML07
LAFML06
LAFML05
LAFML04
LAFML03
LAFML02
LAFML01 LAFML00
LAFML00
LAFML015 LAFML014 LAFML013 LAFML012 LAFML011 LAFML010 LAFML09 LAFML08
LAFMH01
LAFMH07
LAFMH06
LAFMH00
LAFMH015
LAFMH014 LAFMH013 LAFMH012 LAFMH011 LAFMH010 LAFMH09 LAFMH08
LAFML11
LAFML17
LAFML16
LAFML10
LAFML115 LAFML114 LAFML113 LAFML112 LAFML111 LAFML110 LAFML19 LAFML18
LAFMH11
LAFMH17
LAFMH16
LAFMH10
LAFMH115
LAFMH114 LAFMH113 LAFMH112 LAFMH111 LAFMH110 LAFMH19 LAFMH18
LAFML21
LAFML27
LAFML26
LAFML20
LAFML215 LAFML214 LAFML213 LAFML212 LAFML211 LAFML210 LAFML29 LAFML28
LAFMH21
LAFMH27
LAFMH26
LAFMH20
LAFMH215
LAFMH214 LAFMH213 LAFMH212 LAFMH211 LAFMH210 LAFMH29 LAFMH28
LAFML31
LAFML37
LAFML36
LAFML30
LAFML315 LAFML314 LAFML313 LAFML312 LAFML311 LAFML310 LAFML39 LAFML38
LAFMH31
LAFMH37
LAFMH30
LAFMH315 LAFMH314 LAFMH313 LAFMH312 LAFMH311 MAFMH310 LAFMH39 LAFMH38
LAFMH36
LAFMH05
LAFML15
LAFMH15
LAFML25
LAFMH25
LAFML35
LAFMH35
—
LAFML14
—
LAFML24
—
LAFML34
—
—
LAFML13
—
LAFML23
—
LAFML33
—
—
LAFML12
—
LAFML22
—
LAFML32
—
LAFMH01 LAFMH00
LAFML11 LAFML10
LAFMH11 LAFMH10
LAFML21 LAFML20
LAFMH21 LAFMH20
LAFML31 LAFML30
LAFMH31 LAFMH30
Rev. 4.00 Mar. 15, 2006 Page 427 of 556
REJ09B0026-0400
Section 21 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
SSCRH
MSS
BIDE
SOOS
SOL
SOLP
SCKS
CSS1
CSS0
SSU
SSCRL
MSTSSU
SSUMS
SRES
SCKOS
CSOS
—
—
—
SSMR
MLS
CPOS
CPHS
—
—
CKS2
CKS1
CKS0
SSER
TE
RE
RSSTP
—
TEIE
TIE
RIE
CEIE
SSSR
—
ORER
—
—
TEND
TDRE
RDRF
CE
SSRDR
SSRDR7
SSRDR6
SSRDR5
SSRDR4
SSRDR3
SSRDR2
SSRDR1
SSRDR0
SSTDR
SSTDR7
SSTDR6
SSTDR5
SSTDR4
SSTDR3
SSTDR2
SSTDR1
SSTDR0
SBTCTL
PCEF
—
—
START
OSCEB
SYSCKS
SBTIB
SBTUF
SBTDCNT
SBTDCNT7 SBTDCNT6 SBTDCNT5 SBTDCNT4 SBTDCNT3 SBTDCNT2 SBTDCNT1 SBTDCNT0
ROPCR
ROPCR7
ROPCR6
ROPCR5
ROPCR4
ROPCR3
ROPCR2
ROPCR1
ROPCR0
TCR_0
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
TIORA_0
—
IOB2
IOB1
IOB0
—
IOA2
IOA1
IOA0
TIORC_0
—
IOD2
IOD1
IOD0
—
IOC2
IOC1
IOC0
TSR_0
—
—
—
OVF
IMFD
IMFC
IMFB
IMFA
TIER_0
—
—
—
OVIE
IMIED
IMIEC
IMIEB
IMIEA
POCR_0
—
—
—
—
—
POLD
POLC
POLB
TCNT_0
TCNT0H7
TCNT0H6
TCNT0H5
TCNT0H4
TCNT0H3
TCNT0H2
TCNT0H1
TCNT0H0
TCNT0L7
TCNT0L6
TCNT0L5
TCNT0L4
TCNT0L3
TCNT0L2
TCNT0L1
TCNT0L0
GRA0H7
GRA0H6
GRA0H5
GRA0H4
GRA0H3
GRA0H2
GRA0H1
GRA0H0
GRA0L7
GRA0L6
GRA0L5
GRA0L4
GRA0L3
GRA0L2
GRA0L1
GRA0L0
GRB0H7
GRB0H6
GRB0H5
GRB0H4
GRB0H3
GRB0H2
GRB0H1
GRB0H0
GRB0L7
GRB0L6
GRB0L5
GRB0L4
GRB0L3
GRB0L2
GRB0L1
GRB0L0
GRC0H7
GRC0H6
GRC0H5
GRC0H4
GRC0H3
GRC0H2
GRC0H1
GRC0H0
GRC0L7
GRC0L6
GRC0L5
GRC0L4
GRC0L3
GRC0L2
GRC0L1
GRC0L0
GRD0H7
GRD0H6
GRD0H5
GRD0H4
GRD0H3
GRD0H2
GRD0H1
GRD0H0
GRD0L7
GRD0L6
GRD0L5
GRD0L4
GRD0L3
GRD0L2
GRD0L1
GRD0L0
TCR_1
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
TIORA_1
—
IOB2
IOB1
IOB0
—
IOA2
IOA1
IOA0
GRA_0
GRB_0
GRC_0
GRD_0
TIORC_1
—
IOD2
IOD1
IOD0
—
IOC2
IOC1
IOC0
TSR_1
—
—
UDF
OVF
IMFD
IMFC
IMFB
IMFA
TIER_1
—
—
—
OVIE
IMIED
IMIEC
IMIEB
IMIEA
POCR_1
—
—
—
—
—
POLD
POLC
POLB
Rev. 4.00 Mar. 15, 2006 Page 428 of 556
REJ09B0026-0400
Subtimer
Timer Z
Section 21 List of Registers
Register
Abbreviation Bit 7
TCNT_1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TCNT1H7 TCNT1H6 TCNT1H5 TCNT1H4 TCNT1H3 TCNT1H2 TCNT1H1 TCNT1H0 Timer Z
TCNT1L7
TCNT1L6
TCNT1L5
TCNT1L4
TCNT1L3
TCNT1L2
TCNT1L1
TCNT1L0
GRA1H7
GRA1H6
GRA1H5
GRA1H4
GRA1H3
GRA1H2
GRA1H1
GRA1H0
GRA1L7
GRA1L6
GRA1L5
GRA1L4
GRA1L3
GRA1L2
GRA1L1
GRA1L0
GRB1H7
GRB1H6
GRB1H5
GRB1H4
GRB1H3
GRB1H2
GRB1H1
GRB1H0
GRB1L7
GRB1L6
GRB1L5
GRB1L4
GRB1L3
GRB1L2
GRB1L1
GRB1L0
GRC1H7
GRC1H6
GRC1H5
GRC1H4
GRC1H3
GRC1H2
GRC1H1
GRC1H0
GRC1L7
GRC1L6
GRC1L5
GRC1L4
GRC1L3
GRC1L2
GRC1L1
GRC1L0
GRD1H7
GRD1H6
GRD1H5
GRD1H4
GRD1H3
GRD1H2
GRD1H1
GRD1H0
GRD1L7
GRD1L6
GRD1L5
GRD1L4
GRD1L3
GRD1L2
GRD1L1
GRD1L0
TSTR
—
—
—
—
—
—
STR1
STR0
TMDR
BFD1
BFC1
BFD0
BFC0
—
—
—
SYNC
TPMR
—
PWMD1
PWMC1
PWMB1
—
PWMD0
PWMC0
PWMB0
TFCR
—
STCLK
ADEG
ADTRG
OLS1
OLS0
CMD1
CMD0
TOER
ED1
EC1
EB1
EA1
ED0
EC0
EB0
EA0
TOCR
TOD1
TOC1
TOB1
TOA1
TOD0
TOC0
TOB0
TOA0
LVDCR
LVDE
—
—
—
LVDSEL
LVDRE
LVDDE
LVDUE
LVDSR
—
—
—
—
—
—
LVDDF
LVDUF
SMR_2
COM
CHR
PE
PM
STOP
MP
CKS1
CKS0
BRR_2
BRR7
BRR6
BRR5
BRR4
BRR3
BRR2
BRR1
BRR0
GRA_1
GRB_1
GRC_1
GRD_1
Module
Name
SCR3_2
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
TDR_2
TDR7
TDR6
TDR5
TDR4
TDR3
TDR2
TDR1
TDR0
SSR_2
TDRE
RDRF
OER
FER
PER
TEND
MPBR
MPBT
RDR_2
RDR7
RDR6
RDR5
RDR4
RDR3
RDR2
RDR1
RDR0
TMB1
TMB17
—
—
—
—
TMB12
TMB11
TMB10
TCB1
TCB17
TCB16
TCB15
TCB14
TCB13
TCB12
TCB11
TCB10
TLB1
TLB17
TLB16
TCLB15
TLB14
TLB13
TLB12
TLB11
TLB10
FLMCR1
—
SWE
ESU
PSU
EV
PV
E
P
FLMCR2
FLER
—
—
—
—
—
—
—
FLPWCR
PDWND
—
—
—
—
—
—
—
EBR1
—
EB6
EB5
EB4
EB3
EB2
EB1
EB0
FENR
FLSHE
—
—
—
—
—
—
—
LVDC
1
(optional)*
2
SCI3_2*
Timer B1
ROM
Rev. 4.00 Mar. 15, 2006 Page 429 of 556
REJ09B0026-0400
Section 21 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
TCRV0
CMIEB
CMIEA
OVIE
CCLR1
CCLR0
CKS2
CKS1
CKS0
Timer V
TCSRV
CMFB
CMFA
OVF
—
OS3
OS2
OS1
OS0
TCORA
TCORA7
TCORA6
TCORA5
TCORA4
TCORA3
TCORA2
TCORA1
TCORA0
TCORB
TCORB7
TCORB6
TCORB5
TCORB4
TCORB3
TCORB2
TCORB1
TCORB0
TCNTV
TCNTV7
TCNTV6
TCNTV5
TCNTV4
TCNTV3
TCNTV2
TCNTV1
TCNTV0
TCRV1
—
—
—
TVEG1
TVEG0
TRGE
—
ICKS0
SMR
COM
CHR
PE
PM
STOP
MP
CKS1
CKS0
BRR
BRR7
BRR6
BRR5
BRR4
BRR3
BRR2
BRR1
BRR0
SCR3
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
TDR
TDR7
TDR6
TDR5
TDR4
TDR3
TDR2
TDR1
TDR0
SSR
TDRE
RDRF
OER
FER
PER
TEND
MPBR
MPBT
RDR
RDR7
RDR6
RDR5
RDR4
RDR3
RDR2
RDR1
RDR0
ADDRA
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
—
—
—
—
—
—
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
—
—
—
—
—
—
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
—
—
—
—
—
—
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
—
—
—
—
—
—
ADCSR
ADF
ADIE
ADST
SCAN
CKS
CH2
CH1
CH0
ADCR
TRGE
—
—
—
—
—
—
—
TCSRWD
B6WI
TCWE
B4WI
TCSRWE
B2WI
WDON
B0WI
WRST
TCWD
TCWD7
TCWD6
TCWD5
TCWD4
TCWD3
TCWD2
TCWD1
TCWD0
TMWD
CKS7
—
—
—
CKS3
CKS2
CKS1
CKS0
ABRKCR
RTINTE
CSEL1
CSEL0
ACMP2
ACMP1
ACMP0
DCMP1
DCMP0
ABRKSR
ABIF
ABIE
—
—
—
—
—
—
BARH
BARH7
BARH6
BARH5
BARH4
BARH3
BARH2
BARH1
BARH0
BARL
BARL7
BARL6
BARL5
BARL4
BARL3
BARL2
BARL1
BARL0
BDRH
BDRH7
BDRH6
BDRH5
BDRH4
BDRH3
BDRH2
BDRH1
BDRH0
BDRL
BDRL7
BDRL6
BDRL5
BDRL4
BDRL3
BDRL2
BDRL1
BDRL0
ADDRB
ADDRC
ADDRD
Rev. 4.00 Mar. 15, 2006 Page 430 of 556
REJ09B0026-0400
SCI3
A/D
converter
WDT*3
Address
break
Section 21 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
PUCR1
PUCR17
PUCR16
PUCR15
PUCR14
—
PUCR12
PUCR11
PUCR10
I/O port
PUCR5
—
—
PUCR55
PUCR54
PUCR53
PUCR52
PUCR51
PUCR50
PDR1
P17
P16
P15
P14
—
P12
P11
P10
PDR2
—
—
—
P24
P23
P22
P21
P20
PDR5
P57
P56
P55
P54
P53
P52
P51
P50
PDR6
P67
P66
P65
P64
P63
P62
P61
P60
PDR7
—
P76
P75
P74
—
P72
P71
P70
PDR8
P87
P86
P85
—
—
—
—
—
PDR9
P97
P96
P95
P94
P93
P92
P91
P90
PDRB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
4
PMR1
IRQ3
IRQ2
IRQ1
IRQ0
TXD2*
—
TXD
—
PMR5
POF57
POF56
WKP5
WKP4
WKP3
WKP2
WKP1
WKP0
PMR3
—
—
—
POF24
POF23
—
—
—
PCR1
PCR17
PCR16
PCR15
PCR14
—
PCR12
PCR11
PCR10
PCR2
—
—
—
PCR24
PCR23
PCR22
PCR21
PCR20
PCR5
PCR57
PCR56
PCR55
PCR54
PCR53
PCR52
PCR51
PCR50
PCR6
PCR67
PCR66
PCR65
PCR64
PCR63
PCR62
PCR61
PCR60
PCR7
—
PCR76
PCR75
PCR74
—
PCR72
PCR71
PCR70
PCR8
PCR87
PCR86
PCR85
—
—
—
—
—
PCR9
PCR97
PCR96
PCR95
PCR94
PCR93
PCR92
PCR91
PCR90
SYSCR1
SSBY
STS2
STS1
STS0
—
—
—
—
SYSCR2
SMSEL
LSON
DTON
MA2
MA1
MA0
SA1
SA0
IEGR1
NMIEG
—
—
—
IEG3
IEG2
IEG1
IEG0
IEGR2
—
—
WPEG5
WPEG4
WPEG3
WPEG2
WPEG1
WPEG0
IENR1
IENDT
—
IENWP
—
IEN3
IEN2
IEN1
IEN0
IENR2
—
—
IENTB1
—
—
—
—
—
IRR1
IRRDT
—
—
—
IRRI3
IRRI2
IRRI1
IRRI0
IRR2
—
—
IRRTB1
—
—
—
—
—
IWPR
—
—
IWPF5
IWPF4
IWPF3
IWPF2
IWPF1
IWPF0
MSTCR1
—
—
MSTS3
MSTAD
MSTWD
—
MSTTV
—
—
MSTTB1
—
—
MSTTZ
—
MSTCR2
4
MSTS3_2* —
Powerdown
Interrupt
Powerdown
Rev. 4.00 Mar. 15, 2006 Page 431 of 556
REJ09B0026-0400
Section 21 List of Registers
Notes: 1.
2.
3.
4.
LVDC: Low-voltage detection circuits (optional)
The H8/36037 Group does not have the SCI3_2.
WDT: Watchdog timer
These bits are reserved in the H8/36037 Group.
Rev. 4.00 Mar. 15, 2006 Page 432 of 556
REJ09B0026-0400
Section 21 List of Registers
21.3
Register States in Each Operating Mode
Register
Abbreviation
Reset
Active
Sleep
Subactive
Subsleep
Standby
Module
MCR
Initialized
—
—
—
—
—
TinyCAN
GSR
Initialized
—
—
—
—
—
BCR1
Initialized
—
—
—
—
—
BCR0
Initialized
—
—
—
—
—
MBCR
Initialized
—
—
—
—
—
TCMR
Initialized
—
—
—
—
—
TXPR
Initialized
—
—
—
—
—
TXCR
Initialized
—
—
—
—
—
TXACK
Initialized
—
—
—
—
—
ABACK
Initialized
—
—
—
—
—
RXPR
Initialized
—
—
—
—
—
RFPR
Initialized
—
—
—
—
—
TCIRR1
Initialized
—
—
—
—
—
TCIRR0
Initialized
—
—
—
—
—
MBIMR
Initialized
—
—
—
—
—
TCIMR1
Initialized
—
—
—
—
—
TCIMR0
Initialized
—
—
—
—
—
REC
Initialized
—
—
—
—
—
TEC
Initialized
—
—
—
—
—
TCR
Initialized
—
—
—
—
—
UMSR
Initialized
—
—
—
—
—
MC0[1]
—
—
—
—
—
—
MC0[2]
—
—
—
—
—
—
MC0[3]
—
—
—
—
—
—
MC0[4]
—
—
—
—
—
—
MC0[5]
—
—
—
—
—
—
MC1[1]
—
—
—
—
—
—
MC1[2]
—
—
—
—
—
—
MC1[3]
—
—
—
—
—
—
Rev. 4.00 Mar. 15, 2006 Page 433 of 556
REJ09B0026-0400
Section 21 List of Registers
Register
Abbreviation
Reset
Active
Sleep
Subactive
Subsleep
Standby
Module
MC1[4]
—
—
—
—
—
—
TinyCAN
MC1[5]
—
—
—
—
—
—
MC2[1]
—
—
—
—
—
—
MC2[2]
—
—
—
—
—
—
MC2[3]
—
—
—
—
—
—
MC2[4]
—
—
—
—
—
—
MC2[5]
—
—
—
—
—
—
MC3[1]
—
—
—
—
—
—
MC3[2]
—
—
—
—
—
—
MC3[3]
—
—
—
—
—
—
MC3[4]
—
—
—
—
—
—
MC3[5]
—
—
—
—
—
—
MD0[1]
—
—
—
—
—
—
MD0[2]
—
—
—
—
—
—
MD0[3]
—
—
—
—
—
—
MD0[4]
—
—
—
—
—
—
MD0[5]
—
—
—
—
—
—
MD0[6]
—
—
—
—
—
—
MD0[7]
—
—
—
—
—
—
MD0[8]
—
—
—
—
—
—
MD1[1]
—
—
—
—
—
—
MD1[2]
—
—
—
—
—
—
MD1[3]
—
—
—
—
—
—
MD1[4]
—
—
—
—
—
—
MD1[5]
—
—
—
—
—
—
MD1[6]
—
—
—
—
—
—
MD1[7]
—
—
—
—
—
—
MD1[8]
—
—
—
—
—
—
MD2[1]
—
—
—
—
—
—
MD2[2]
—
—
—
—
—
—
MD2[3]
—
—
—
—
—
—
Rev. 4.00 Mar. 15, 2006 Page 434 of 556
REJ09B0026-0400
Section 21 List of Registers
Register
Abbreviation
Reset
Active
Sleep
Subactive
Subsleep
Standby
Module
MD2[4]
—
—
—
—
—
—
TinyCAN
MD2[5]
—
—
—
—
—
—
MD2[6]
—
—
—
—
—
—
MD2[7]
—
—
—
—
—
—
MD2[8]
—
—
—
—
—
—
MD3[1]
—
—
—
—
—
—
MD3[2]
—
—
—
—
—
—
MD3[3]
—
—
—
—
—
—
MD3[4]
—
—
—
—
—
—
MD3[5]
—
—
—
—
—
—
MD3[6]
—
—
—
—
—
—
MD3[7]
—
—
—
—
—
—
MD3[8]
—
—
—
—
—
—
LAFML0[1]
—
—
—
—
—
—
LAFML0[0]
—
—
—
—
—
—
LAFMH0[1]
—
—
—
—
—
—
LAFMH0[0]
—
—
—
—
—
—
LAFML1[1]
—
—
—
—
—
—
LAFML1[0]
—
—
—
—
—
—
LAFMH1[1]
—
—
—
—
—
—
LAFMH1[0]
—
—
—
—
—
—
LAFML2[1]
—
—
—
—
—
—
LAFML2[0]
—
—
—
—
—
—
LAFMH2[1]
—
—
—
—
—
—
LAFMH2[0]
—
—
—
—
—
—
LAFML3[1]
—
—
—
—
—
—
LAFML3[0]
—
—
—
—
—
—
LAFMH3[1]
—
—
—
—
—
—
LAFMH3[0]
—
—
—
—
—
—
SSCRH
Initialized
—
—
—
—
—
SSCRL
Initialized
—
—
—
—
—
SSU
Rev. 4.00 Mar. 15, 2006 Page 435 of 556
REJ09B0026-0400
Section 21 List of Registers
Register
Abbreviation
Reset
Active
Sleep
Subactive
Subsleep
Standby
Module
SSMR
Initialized
—
—
—
—
—
SSU
SSER
Initialized
—
—
—
—
—
SSSR
Initialized
—
—
—
—
—
SSRDR
Initialized
—
—
—
—
—
SSTDR
Initialized
—
—
—
—
—
SBTCTL
Initialized
—
—
—
—
—
SBTDCNT
Initialized
—
—
—
—
—
ROPCR
Initialized
—
—
—
—
—
TCR_0
Initialized
—
—
—
—
—
TIORA_0
Initialized
—
—
—
—
—
TIORC_0
Initialized
—
—
—
—
—
TSR_0
Initialized
—
—
—
—
—
TIER_0
Initialized
—
—
—
—
—
POCR_0
Initialized
—
—
—
—
—
TCNT_0
Initialized
—
—
—
—
—
GRA_0
Initialized
—
—
—
—
—
GRB_0
Initialized
—
—
—
—
—
GRC_0
Initialized
—
—
—
—
—
GRD_0
Initialized
—
—
—
—
—
TCR_1
Initialized
—
—
—
—
—
TIORA_1
Initialized
—
—
—
—
—
TIORC_1
Initialized
—
—
—
—
—
TSR_1
Initialized
—
—
—
—
—
TIER_1
Initialized
—
—
—
—
—
POCR_1
Initialized
—
—
—
—
—
TCNT_1
Initialized
—
—
—
—
—
GRA_1
Initialized
—
—
—
—
—
GRB_1
Initialized
—
—
—
—
—
GRC_1
Initialized
—
—
—
—
—
GRD_1
Initialized
—
—
—
—
—
TSTR
Initialized
—
—
—
—
—
Rev. 4.00 Mar. 15, 2006 Page 436 of 556
REJ09B0026-0400
Subtimer
Timer Z
Section 21 List of Registers
Register
Abbreviation
Reset
Active
Sleep
Subactive
Subsleep
Standby
Module
TMDR
Initialized
—
—
—
—
—
Timer Z
TPMR
Initialized
—
—
—
—
—
TFCR
Initialized
—
—
—
—
—
TOER
Initialized
—
—
—
—
—
TOCR
Initialized
—
—
—
—
—
LVDCR
Initialized
—
—
—
—
—
LVDSR
Initialized
—
—
—
—
—
SMR_2
Initialized
—
—
Initialized
Initialized
Initialized
BRR_2
Initialized
—
—
Initialized
Initialized
Initialized
SCR3_2
Initialized
—
—
Initialized
Initialized
Initialized
TDR_2
Initialized
—
—
Initialized
Initialized
Initialized
SSR_2
Initialized
—
—
Initialized
Initialized
Initialized
LVDC
(optional)*1
3
RDR_2
Initialized
—
—
Initialized
Initialized
Initialized
TMB1
Initialized
—
—
—
—
—
TCB1
Initialized
—
—
—
—
—
Tlb1
Initialized
—
—
—
—
—
FLMCR1
Initialized
—
—
Initialized
Initialized
Initialized
FLMCR2
Initialized
—
—
—
—
—
FLPWCR
Initialized
—
—
—
—
—
EBR1
Initialized
—
—
Initialized
Initialized
Initialized
FENR
Initialized
—
—
—
—
—
TCRV0
Initialized
—
—
Initialized
Initialized
Initialized
TCSRV
Initialized
—
—
Initialized
Initialized
Initialized
TCORA
Initialized
—
—
Initialized
Initialized
Initialized
TCORB
Initialized
—
—
Initialized
Initialized
Initialized
TCNTV
Initialized
—
—
Initialized
Initialized
Initialized
TCRV1
Initialized
—
—
Initialized
Initialized
Initialized
SMR
Initialized
—
—
Initialized
Initialized
Initialized
BRR
Initialized
—
—
Initialized
Initialized
Initialized
SCR3
Initialized
—
—
Initialized
Initialized
Initialized
TDR
Initialized
—
—
Initialized
Initialized
Initialized
SCI3_2*
Timer B1
ROM
Timer V
SCI3
Rev. 4.00 Mar. 15, 2006 Page 437 of 556
REJ09B0026-0400
Section 21 List of Registers
Register
Abbreviation
Reset
Active
Sleep
Subactive
Subsleep
Standby
Module
SSR
Initialized
—
—
Initialized
Initialized
Initialized
SCI3
RDR
Initialized
—
—
Initialized
Initialized
Initialized
ADDRA
Initialized
—
—
Initialized
Initialized
Initialized
ADDRB
Initialized
—
—
Initialized
Initialized
Initialized
ADDRC
Initialized
—
—
Initialized
Initialized
Initialized
ADDRD
Initialized
—
—
Initialized
Initialized
Initialized
ADCSR
Initialized
—
—
Initialized
Initialized
Initialized
ADCR
Initialized
—
—
Initialized
Initialized
Initialized
TCSRWD
Initialized
—
—
—
—
—
TCWD
Initialized
—
—
—
—
—
TMWD
Initialized
—
—
—
—
—
ABRKCR
Initialized
—
—
—
—
—
ABRKSR
Initialized
—
—
—
—
—
BARH
Initialized
—
—
—
—
—
BARL
Initialized
—
—
—
—
—
BDRH
Initialized
—
—
—
—
—
BDRL
Initialized
—
—
—
—
—
PUCR1
Initialized
—
—
—
—
—
PUCR5
Initialized
—
—
—
—
—
PDR1
Initialized
—
—
—
—
—
PDR2
Initialized
—
—
—
—
—
PDR5
Initialized
—
—
—
—
—
PDR6
Initialized
—
—
—
—
—
PDR7
Initialized
—
—
—
—
—
PDR8
Initialized
—
—
—
—
—
PDR9
Initialized
—
—
—
—
—
PDRB
Initialized
—
—
—
—
—
PMR1
Initialized
—
—
—
—
—
PMR5
Initialized
—
—
—
—
—
PMR3
Initialized
—
—
—
—
—
PCR1
Initialized
—
—
—
—
—
Rev. 4.00 Mar. 15, 2006 Page 438 of 556
REJ09B0026-0400
A/D converter
WDT*2
Address
break
I/O port
Section 21 List of Registers
Register
Abbreviation
Reset
Active
Sleep
Subactive
Subsleep
Standby
Module
PCR2
Initialized
—
—
—
—
—
I/O port
PCR5
Initialized
—
—
—
—
—
PCR6
Initialized
—
—
—
—
—
PCR7
Initialized
—
—
—
—
—
PCR8
Initialized
—
—
—
—
—
PCR9
Initialized
—
—
—
—
—
SYSCR1
Initialized
—
—
—
—
—
SYSCR2
Initialized
—
—
—
—
—
IEGR1
Initialized
—
—
—
—
—
IEGR2
Initialized
—
—
—
—
—
IENR1
Initialized
—
—
—
—
—
IENR2
Initialized
—
—
—
—
—
IRR1
Initialized
—
—
—
—
—
IRR2
Initialized
—
—
—
—
—
IWPR
Initialized
—
—
—
—
—
MSTCR1
Initialized
—
—
—
—
—
MSTCR2
Initialized
—
—
—
—
—
Power-down
Interrupt
Power-down
Notes: 1. LVDC: Low-voltage detection circuits (optional)
2. WDT: Watchdog timer
3. The H8/36037 Group does not have the SCI3_2.
Rev. 4.00 Mar. 15, 2006 Page 439 of 556
REJ09B0026-0400
Section 21 List of Registers
Rev. 4.00 Mar. 15, 2006 Page 440 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
Section 22 Electrical Characteristics
22.1
Absolute Maximum Ratings
Table 22.1 Absolute Maximum Ratings
Item
Symbol Value
Unit
Note
Power supply voltage
VCC
–0.3 to +7.0
V
*
Analog power supply voltage
AVCC
–0.3 to +7.0
V
Input voltage
VIN
Other than port B
Port B
Operating temperature
Topr
–0.3 to VCC +0.3
V
–0.3 to AVCC +0.3
V
Regular specifications:
–20 to +75
°C
Wide-range specifications:
–40 to +85
Storage temperature
Note:
*
Tstg
–55 to +125
°C
Permanent damage may result if absolute maximum ratings are exceeded. Normal
operation should be under the conditions specified in Electrical Characteristics.
Exceeding these values can result in incorrect operation and reduced reliability.
Rev. 4.00 Mar. 15, 2006 Page 441 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
22.2
Electrical Characteristics (F-ZTAT™ Version)
22.2.1
Power Supply Voltage and Operating Ranges
Power Supply Voltage and Oscillation Frequency Range:
φOSC (MHz)
φOSC (MHz)
20.0
850.0
10.0
2.0
64.0
3.0
4.0
5.5
VCC (V)
4.0
5.5
VCC (V)
AVCC = 3.3 to 5.5 V
• Active mode
• Sleep mode
• Subactive mode
• Subsleep mode
AVCC = 3.3 to 5.5 V
• Active mode
• Sleep mode
Note: This frequency range is supplied by the on-chip
oscillator for the subtimer and is guaranteed.
Power Supply Voltage and Operating Frequency Range:
φ (MHz)
φ (kHz)
20.0
2500
10.0
1250
1.0
78.125
3.0
4.0
5.5
VCC (V)
AVCC = 3.3 to 5.5 V
• Active mode
• Sleep mode
(When MA2 in SYSCR2 = 0 )
Rev. 4.00 Mar. 15, 2006 Page 442 of 556
REJ09B0026-0400
3.0
4.0
5.5
VCC (V)
AVCC = 3.3 to 5.5 V
• Active mode
• Sleep mode
(When MA2 in SYSCR2 = 1 )
Section 22 Electrical Characteristics
Analog Power Supply Voltage and A/D Converter Accuracy Guarantee Range:
φ (MHz)
20.0
10.0
2.0
3.3
4.0
AVCC (V)
5.5
VCC = 3.0 to 5.5 V
• Active mode
• Sleep mode
Range of Power Supply Voltage and Oscillation Frequency when Low-Voltage Detection
Circuit is Used:
φosc (MHz)
20.0
16.0
2.0
Vcc(V)
3.0
4.5
5.5
Operation guarantee range
Operation guarantee range except
A/D conversion accuracy
Rev. 4.00 Mar. 15, 2006 Page 443 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
Range of Power Supply Voltage and Oscillation Frequency when Subtimer is Used:
φ (MHz)
φSUB (kHz)
20.0
106.25*
1.0
4.0
4.0
5.5
AVcc = 4.0 to 5.5 V
• Active mode
• Sleep mode
Vcc(V)
4.0
AVcc = 4.0 to 5.5 V
• Subactive mode
• Subsleep mode
Note: * Reference value
Rev. 4.00 Mar. 15, 2006 Page 444 of 556
REJ09B0026-0400
5.5
Vcc(V)
Section 22 Electrical Characteristics
22.2.2
DC Characteristics
Table 22.2 DC Characteristics (1)
VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C
(wide-range specifications), unless otherwise indicated.
Values
Item
Symbol
Input high VIH
voltage
Applicable Pins
Test Condition
RES, NMI,
WKP0 to WKP5,
IRQ0 to IRQ3,
ADTRG,TMRIV,
TMCIV, FTIOA0
to FTIOD0,
FTIOA1 to
FTIOD1, SCK3,
1
SCK3_2* , SCS,
SSCK, TRGV,
TMIB1
Min.
Typ.
Max.
Unit
VCC = 4.0 to 5.5 V VCC × 0.8
—
VCC + 0.3
V
VCC × 0.9
—
VCC + 0.3
VCC = 4.0 to 5.5 V VCC × 0.7
RXD, RXD_2* ,
SSI, SSO, HRXD,
P10 to P12,
P14 to P17,
P20 to P24,
P50 to P57,
P60 to P67,
VCC × 0.8
P70 to P72,
P74 to P76,
P85 to P87,
P90 to P97
—
VCC + 0.3
—
VCC + 0.3
PB0 to PB7
VCC = 4.0 to 5.5 V VCC × 0.7
—
AVCC + 0.3 V
VCC × 0.8
—
AVCC + 0.3
OSC1
VCC = 4.0 to 5.5 V VCC – 0.5
—
VCC + 0.3
VCC – 0.3
—
VCC + 0.3
VCC = 4.0 to 5.5 V –0.3
—
VCC × 0.2
–0.3
—
VCC × 0.1
1
Input low
voltage
VIL
RES, NMI,
WKP0 to WKP5,
IRQ0 to IRQ3,
ADTRG, TMRIV,
TMCIV, FTIOA0
to FTIOD0,
FTIOA1 to
FTIOD1, SCK3,
1
SCK3_2* , SCS,
SSCK, TRGV,
TMIB1
Notes
V
V
V
Rev. 4.00 Mar. 15, 2006 Page 445 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
Values
Item
Input low
voltage
Symbol
VIL
Applicable Pins
OSC1
VOH
Typ.
Max.
Unit
—
VCC × 0.3
V
—
VCC × 0.2
VCC = 4.0 to 5.5 V –0.3
—
VCC × 0.3
–0.3
—
VCC × 0.2
VCC = 4.0 to 5.5 V –0.3
—
0.5
–0.3
—
0.3
—
—
P10 to P12,
P14 to P17,
P20 to P24,
P50 to P55,
P60 to P67,
P70 to P72,
P74 to P76,
P85 to P87,
P90 to P97
VCC = 4.0 to 5.5 V VCC – 1.0
VCC – 0.5
—
—
P56, P57
VCC = 4.0 to 5.5 V VCC – 2.5
–IOH = 0.1 mA
—
—
VCC = 3.0 to 4.0 V VCC – 2.0
–IOH = 0.1 mA
—
—
V
V
V
–IOH = 1.5 mA
–IOH = 0.1 mA
Rev. 4.00 Mar. 15, 2006 Page 446 of 556
REJ09B0026-0400
Min.
VCC = 4.0 to 5.5 V –0.3
RXD, RXD_2* ,
SSI, SSO, HRXD,
P10 to P12,
P14 to P17,
P20 to P24,
P50 to P57,
P60 to P67,
–0.3
P70 to P72,
P74 to P76,
P85 to P87
P90 to P97
PB0 to PB7
Output
high
voltage
Test Condition
1
V
Notes
Section 22 Electrical Characteristics
Values
Item
Symbol
Applicable Pins
Test Condition
Output
low
voltage
VOL
P10 to P12,
P14 to P17,
P20 to P24,
P50 to P57,
P70 to P72,
P74 to P76,
P85 to P87
P90 to P97
P60 to P67
Input/
output
leakage
current
| IIL |
Min.
Typ.
Max.
Unit
VCC = 4.0 to 5.5 V —
IOL = 1.6 mA
—
0.6
V
IOL = 0.4 mA
—
—
0.4
VCC = 4.0 to 5.5 V —
IOL = 20.0 mA
—
1.5
VCC = 4.0 to 5.5 V —
IOL = 10.0 mA
—
1.0
VCC = 4.0 to 5.5 V —
IOL = 1.6 mA
—
0.4
IOL = 0.4 mA
—
—
0.4
OSC1, RES, NMI, VIN = 0.5 V or
WKP0 to WKP5, higher
IRQ0 to IRQ3,
(VCC – 0.5 V)
ADTRG, TRGV,
TMRIV, TMCIV,
FTIOA0 to
FTIOD0, FTIOA1
to FTIOD1, RXD,
1
SCK3, RXD_2* ,
1
SCK3_2* , SSCK,
SCS, SSI, SSO,
HRXD
—
—
1.0
µA
P10 to P12,
P14 to P17,
P20 to P24,
P50 to P57,
P60 to P67,
P70 to P72,
P74 to P76,
P85 to P87,
P90 to P97
VIN = 0.5 V or
higher
(VCC – 0.5 V)
—
—
1.0
µA
PB0 to PB7
VIN = 0.5 V or
higher
(AVCC – 0.5 V)
—
—
1.0
µA
Notes
V
Rev. 4.00 Mar. 15, 2006 Page 447 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
Values
Item
Symbol
Applicable Pins
Pull-up
MOS
current
–Ip
VCC = 5.0 V,
P10 to P12,
P14 to P17,P50 to VIN = 0.0 V
P55
VCC = 3.0 V,
VIN = 0.0 V
Input
capacitance
Cin
All input pins
except power
supply pins
Active
mode
supply
current
IOPE1
VCC
IOPE2
Sleep
mode
supply
current
ISLEEP1
ISLEEP2
Subactive
mode
supply
current
ISUB
Subsleep
mode
supply
current
ISUBSP
VCC
VCC
VCC
VCC
VCC
Test Condition
Min.
Typ.
Max.
Unit
50.0
—
300.0
µA
—
60.0
—
f = 1 MHz,
VIN = 0.0 V,
Ta = 25°C
—
—
15.0
pF
Active mode 1
VCC = 5.0 V,
fOSC = 20 MHz
—
25.0
35.0
mA
Active mode 1
VCC = 3.0 V,
fOSC = 10 MHz
—
10.0
—
Active mode 2
VCC = 5.0 V,
fOSC = 20 MHz
—
1.2
3.0
Active mode 2
VCC = 3.0 V,
fOSC = 10 MHz
—
0.8
—
Sleep mode 1
VCC = 5.0 V,
fOSC = 20 MHz
—
14.0
22.5
Sleep mode 1
VCC = 3.0 V,
fOSC = 10 MHz
—
6.3
—
Sleep mode 2
VCC = 5.0 V,
fOSC = 20 MHz
—
1.0
2.7
Sleep mode 2
VCC = 3.0 V,
fOSC = 10 MHz
—
0.7
—
VCC = 5.0 V
(φSUB = φW/2)
—
60.0
100.0
VCC = 5.0 V
(φSUB = φW/8)
—
46.0
—
VCC = 5.0 V
(φSUB = φW/2)
—
50.0
80.0
Rev. 4.00 Mar. 15, 2006 Page 448 of 556
REJ09B0026-0400
Notes
Reference
value
3
*
3
*
Reference
value
mA
3
*
3
*
Reference
value
mA
3
*
3
*
Reference
value
mA
3
*
3
*
Reference
value
µA
3
*
3
*
Reference
value
µA
3
*
Section 22 Electrical Characteristics
Values
Item
Symbol
Applicable Pins
Test Condition
Min.
Typ.
Max.
Unit
Notes
Standby
mode
supply
current
ISTBY
VCC
Subtimer, WDT,
2
and LVD* not
used
—
—
5.0
µA
*
RAM data
retaining
voltage
VRAM
VCC
2.0
—
—
V
Note:
3
Connect the TEST pin to Vss.
1. The H8/36037 Group does not have these pins.
2. The LVD is optional.
3. Pin states during supply current measurement are given below (excluding current in the
pull-up MOS transistors and output buffers).
Mode
RES Pin
Active mode 1
VCC
Active mode 2
Sleep mode 1
Internal State
Other Pins Oscillator Pins
Operates
VCC
Operates
(φOSC/64)
VCC
Sleep mode 2
Only timers operate
Main clock:
ceramic or crystal
resonator
VCC
Only timers operate
(φOSC/64)
Subactive mode
VCC
Operates
VCC
Subsleep mode
VCC
Only timers operate
VCC
Standby mode
VCC
CPU and timers
both stop
VCC
Main clock:
on-chip oscillator
Main clock:
ceramic or crystal
resonator
Rev. 4.00 Mar. 15, 2006 Page 449 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
Table 22.2 DC Characteristics (2)
VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C
(wide-range specifications), unless otherwise indicated.
Item
Symbol
Allowable output low
current (per pin)
IOL
Allowable output low
current (total)
∑IOL
Applicable
Pins
Typ.
Max.
Unit
VCC = 4.0 to 5.5 V —
—
2.0
mA
Port 6
—
—
20.0
Output pins
except port 6
—
—
0.5
Port 6
—
—
10.0
VCC = 4.0 to 5.5 V —
—
40.0
Port 6
—
—
80.0
Output pins
except port 6
—
—
20.0
Output pins
except port 6
Output pins
except port 6
Port 6
Allowable output high –IOH
current (per pin)
All output pins
Allowable output high ∑–IOH
current (total)
All output pins
Rev. 4.00 Mar. 15, 2006 Page 450 of 556
REJ09B0026-0400
Values
Test Condition
Min.
—
—
40.0
VCC = 4.0 to 5.5 V —
—
2.0
—
—
0.2
VCC = 4.0 to 5.5 V —
—
30.0
—
—
8.0
mA
mA
mA
Section 22 Electrical Characteristics
22.2.3
AC Characteristics
Table 22.3 AC Characteristics
VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C
(wide-range specifications), unless otherwise indicated.
Values
Item
Symbol
Applicable
Pins
System clock
oscillation
frequency
fOSC
OSC1, OSC2 VCC = 4.0 to 5.5 V
System clock (•)
cycle time
tcyc
Test Condition
Min.
Typ.
Max.
Unit
Reference
Figure
2.0
—
20.0
MHz
*
2.0
—
10.0
1
—
64
tOSC
*
—
—
12.8
µs
Subclock oscillator fRO
oscillation
frequency
VCC = 4.0 to 5.5 V
64.0
—
850.0
kHz
Subclock oscillator tRO
(φw) cycle time
VCC = 4.0 to 5.5 V
1.18
—
15.6
µs
Subclock (φsub)
cycle time
VCC = 4.0 to 5.5 V
2
—
8
φw
2
—
—
tcyc
tsubcyc
tsubcyc
Instruction cycle
time
trc
OSC1,
OSC2
—
—
10.0
ms
trc
Oscillation
stabilization time
(ceramic resonator)
OSC1,
OSC2
—
—
5.0
ms
External clock high tCPH
width
OSC1
20.0
—
—
ns
40.0
—
—
External clock low
width
tCPL
OSC1
VCC = 4.0 to 5.5 V
20.0
—
—
40.0
—
—
External clock rise
time
tCPr
OSC1
VCC = 4.0 to 5.5 V
—
—
10.0
—
—
15.0
External clock fall
time
tCPf
OSC1
VCC = 4.0 to 5.5 V
—
—
10.0
—
—
15.0
Oscillation
stabilization time
(crystal resonator)
VCC = 4.0 to 5.5 V
1
2
Figure 22.1
ns
ns
ns
Rev. 4.00 Mar. 15, 2006 Page 451 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
Item
Symbol
Applicable
Pins
RES pin low
width
tREL
RES
Values
Typ.
Max.
Unit
Reference
Figure
At power-on and in trc
modes other than
those below
—
—
ms
Figure 22.2
In active mode and 1500
sleep mode
operation
—
—
ns
Test Condition
Min.
Input pin high
width
tIH
NMI,
IRQ0 to
IRQ3,
WKP0 to
WKP5,
TMCIV,
TMRIV,
TRGV,
ADTRG,
FTIOA0 to
FTIOD0,
FTIOA1 to
FTIOD1
2
—
—
tcyc
tsubcyc
Input pin low
width
tIL
NMI,
IRQ0 to
IRQ3,
WKP0 to
WKP5,
TMCIV,
TMRIV,
TRGV,
ADTRG,
FTIOA0 to
FTIOD0,
FTIOA1 to
FTIOD1
2
—
—
tcyc
tsubcyc
Figure 22.3
Notes: 1. When an external clock is input, the minimum system clock oscillation frequency is 1.0
MHz.
2. Determined by the MA2, MA1, MA0, SA1, and SA0 bits in the system control register 2
(SYSCR2).
Rev. 4.00 Mar. 15, 2006 Page 452 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
Table 22.4 Serial Communication Interface (SCI) Timing
VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C
(wide-range specifications), unless otherwise indicated.
Item
Symbol
Asynchronous
Input
clock
cycle
tscyc
Applicable
Pins
Values
Test Condition
SCK3,
SCK3_2*
Clocked
synchronous
Input clock pulse
width
tSCKW
SCK3,
SCK3_2*
Transmit data delay
time (clocked
synchronous)
tTXD
TXD,
TXD_2*
VCC = 4.0 to 5.5 V
Receive data setup
time (clocked
synchronous)
tRXS
RXD,
RXD_2*
VCC = 4.0 to 5.5 V
Receive data hold
time (clocked
synchronous)
tRXH
RXD,
RXD_2*
VCC = 4.0 to 5.5 V
Note:
*
Min.
Typ. Max.
Unit
Reference
Figure
4
—
—
tcyc
Figure 22.4
6
—
—
0.4
—
0.6
tscyc
—
—
1
tcyc
—
—
1
50.0
—
—
100.0
—
—
50.0
—
—
100.0
—
—
Figure 22.5
ns
ns
The H8/36037 Group does not have these pins.
Rev. 4.00 Mar. 15, 2006 Page 453 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
Table 22.5 Controller Area Network for Tiny (TinyCAN) Timing
VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C
(wide-range specifications), unless otherwise indicated.
Typ.
Max.
Unit
Reference
Figure
HTXD
—
—
50
ns
Figure 22.6
tHRXS
HRXD
50
—
—
ns
tHRXH
HRXD
50
—
—
ns
Symbol
Transmit
data delay
time*
tHTXD
Receive
data setup
time*
Receive
data hold
time*
Note:
*
Values
Min.
Item
Applicable
Pins
Test
Condition
Although the TinyCAN input/output signal is asynchronous, its state is determined to
have changed at the rising-edge (two clock cycles) of the CK clock shown in figure
22.6.
Rev. 4.00 Mar. 15, 2006 Page 454 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
Table 22.6 Synchronous Communication Unit (SSU) Timing
VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C
(wide-range specifications), CL = 100 pF, unless otherwise indicated.
Item
Applicable
Symbol Pins
Clock cycle
tSUCYC
Test
Condition Min.
Values
Typ.
Max.
Unit
SSCK
4
—
—
tCYC
Clock high pulse width tHI
SSCK
0.4
—
0.6
tSUCYC
Clock low pulse width
tLO
SSCK
0.4
—
0.6
tSUCYC
Clock rise
time
tRISE
SSCK
—
—
1
tCYC
—
—
1.0
µs
—
1
tCYC
Clock fall
time
Master
Slave
Master
tFALL
SSCK
—
—
—
1.0
µs
Data input setup time
tSU
SSO,
SSI
1
—
—
tCYC
Data input hold time
tH
SSO,
SSI
1
—
—
tCYC
SCS setup
time
Slave
tLEAD
SCS
1 tCYC +
100
—
—
ns
SCS hold
time
Slave
tLAG
SCS
1 tCYC +
100
—
—
ns
Data output delay time tOD
SSO,
SSI
—
—
1
tCYC
Slave access time
tSA
SSI
—
—
1 tCYC +
100
ns
Slave out release time tOR
SSI
—
—
1 tCYC +
100
ns
Slave
Reference
Figure
Figures 22.7
to 22.11
Rev. 4.00 Mar. 15, 2006 Page 455 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
22.2.4
A/D Converter Characteristics
Table 22.7 A/D Converter Characteristics
VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C
(wide-range specifications), unless otherwise indicated.
Item
Symbol
Applicable
Pins
Test
Condition
Values
Min.
Typ. Max.
Unit
Reference
Figure
V
*
Analog power supply AVCC
voltage
AVCC
3.3
VCC
5.5
Analog input voltage AVIN
AN0 to
AN7
VSS – 0.3
—
AVCC + 0.3 V
Analog power supply AIOPE
current
AVCC
—
2.0
mA
AVCC = 5.0 V —
1
fOSC =
20 MHz
2
AISTOP1
AVCC
—
50
—
µA
*
Reference
value
AISTOP2
AVCC
—
—
5.0
µA
*
Analog input
capacitance
CAIN
AN0 to
AN7
—
—
30.0
pF
Allowable signal
source impedance
RAIN
AN0 to
AN7
—
—
5.0
kΩ
10
10
10
bit
—
—
tcyc
Resolution (data
length)
Conversion time
(single mode)
AVCC = 3.3 to 134
5.5 V
Nonlinearity error
—
—
±7.5
LSB
Offset error
—
—
±7.5
LSB
Full-scale error
—
—
±7.5
LSB
Quantization error
—
—
±0.5
LSB
Absolute accuracy
—
—
±8.0
LSB
AVCC = 4.0 to 70
5.5 V
—
—
tcyc
Nonlinearity error
—
—
±7.5
LSB
Offset error
—
—
±7.5
LSB
Full-scale error
—
—
±7.5
LSB
Quantization error
—
—
±0.5
LSB
Absolute accuracy
—
—
±8.0
LSB
Conversion time
(single mode)
Rev. 4.00 Mar. 15, 2006 Page 456 of 556
REJ09B0026-0400
3
Section 22 Electrical Characteristics
Item
Symbol
Applicable
Pins
Conversion time
(single mode)
Test
Condition
Values
Min.
AVCC = 4.0 to 134
5.5 V
Typ. Max.
Unit
—
—
tcyc
Nonlinearity error
—
—
±3.5
LSB
Offset error
—
—
±3.5
LSB
Full-scale error
—
—
±3.5
LSB
Quantization error
—
—
±0.5
LSB
Absolute accuracy
—
—
±4.0
LSB
Reference
Figure
Notes: 1. Set AVCC = VCC when the A/D converter is not used.
2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle.
3. AISTOP2 is the current at reset and in standby, subactive, and subsleep modes while the
A/D converter is idle.
22.2.5
Watchdog Timer Characteristics
Table 22.8 Watchdog Timer Characteristics
VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C
(wide-range specifications), unless otherwise indicated.
Item
Symbol
Internal
oscillator
overflow
time
tOVF
Note:
*
Applicable
Pins
Test
Condition
Values
Min.
Typ.
Max.
Unit
Reference
Figure
0.2
0.4
—
s
*
Indicates the time to count from 0 to 255, at which point an internal reset is generated,
when the internal oscillator is selected.
Rev. 4.00 Mar. 15, 2006 Page 457 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
22.2.6
Flash Memory Characteristics
Table 22.9 Flash Memory Characteristics
VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C
(wide-range specifications), unless otherwise indicated.
Test
Condition
Values
Min.
Typ.
tP
—
7
200
ms
tE
—
100
1200
ms
Reprogramming count
NWEC
1000
10000
—
Times
Programming
Wait time after SWE bit
1
setting*
x
1
—
—
µs
Wait time after PSU bit
1
setting*
y
50
—
—
µs
Wait time after P bit setting
z1
1≤n≤6
28
30
32
µs
z2
7 ≤ n ≤ 1000
198
200
202
µs
z3
Additionalprogramming
8
10
12
µs
Item
Symbol
1 2 4
Programming time (per 128 bytes)* * *
1 3 6
Erase time (per block) * * *
1 4
**
Max.
Unit
Wait time after P bit clear*
α
5
—
—
µs
Wait time after PSU bit
1
clear*
β
5
—
—
µs
Wait time after PV bit
1
setting*
γ
4
—
—
µs
Wait time after dummy
1
write*
ε
2
—
—
µs
Wait time after PV bit clear*
η
2
—
—
µs
Wait time after SWE bit
1
clear*
θ
100
—
—
µs
Maximum programming
1 4 5
count * * *
N
—
—
1000
Times
1
1
Rev. 4.00 Mar. 15, 2006 Page 458 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
Item
Erasing
Symbol
Test
Condition
Values
Min.
Typ.
Max.
Unit
Wait time after SWE bit
1
setting*
x
1
—
—
µs
Wait time after ESU bit
1
setting*
y
100
—
—
µs
Wait time after E bit
1 6
setting* *
z
10
—
100
ms
Wait time after E bit clear*
α
10
—
—
µs
Wait time after ESU bit
1
clear*
β
10
—
—
µs
Wait time after EV bit
1
setting*
γ
20
—
—
µs
Wait time after dummy
1
write*
ε
2
—
—
µs
Wait time after EV bit clear*
η
4
—
—
µs
Wait time after SWE bit
1
clear*
θ
100
—
—
µs
N
—
—
120
Times
1
1
1 6 7
Maximum erase count * * *
Notes: 1. Make the time settings in accordance with the program/erase algorithms.
2. The programming time for 128 bytes. (Indicates the total time for which the P bit in the
flash memory control register 1 (FLMCR1) is set. The program-verify time is not
included.)
3. The time required to erase one block. (Indicates the time for which the E bit in the flash
memory control register 1 (FLMCR1) is set. The erase-verify time is not included.)
4. Programming time maximum value (tP (max.)) = wait time after P bit setting (z) ×
maximum programming count (N)
5. Set the maximum programming count (N) according to the actual set values of z1, z2,
and z3, so that it does not exceed the programming time maximum value (tP (max.)).
The wait time after P bit setting (z1, z2) should be changed as follows according to the
value of the programming count (n).
Programming count (n)
1≤n≤6
z1 = 30 µs
7 ≤ n ≤ 1000 z2 = 200 µs
6. Erase time maximum value (tE (max.)) = wait time after E bit setting (z) × maximum
erase count (N)
7. Set the maximum erase count (N) according to the actual set value of (z), so that it
does not exceed the erase time maximum value (tE (max.)).
Rev. 4.00 Mar. 15, 2006 Page 459 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
22.2.7
Power-Supply-Voltage Detection Circuit Characteristics (Optional)
Table 22.10 Power-Supply-Voltage Detection Circuit Characteristics
VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C (wide-range
specifications), unless otherwise indicated.
Values
Item
Symbol
Test
Condition
Power-supply falling detection voltage
Vint (D)
LVDSEL = 0
3.3
3.7
—
V
Power-supply rising detection voltage
Vint (U)
LVDSEL = 0
—
4.0
4.5
V
1
Vreset1
LVDSEL = 0
—
2.3
2.7
V
2
Vreset2
LVDSEL = 1
3.0
3.6
4.2
V
1.0
—
—
V
50
—
—
µs

LVDE = 1,
Vcc = 5.0 V,
subtimer and
WDT not used
—
350
µA
Reset detection voltage 1*
Reset detection voltage 2*
3
Lower-limit voltage of LVDR operation*
VLVDRmin
LVD stabilization time
tLVDON
Supply current in standby mode
ISTBY
Min.
Typ.
Max.
Unit
Notes: 1. This voltage should be used when the falling and rising voltage detection function is
used.
2. Select the low-voltage reset 2 when only the low-voltage detection reset is used.
3. When the power-supply voltage (Vcc) falls below VLVDRmin = 1.0 V and then rises, a reset
may not occur. Therefore sufficient evaluation is required.
22.2.8
Power-On Reset Circuit Characteristics (Optional)
Table 22.11 Power-On Reset Circuit Characteristics
VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C (wide-range
specifications), unless otherwise indicated.
Typ.
Max.
Unit
RRES
100
150
—
kΩ
Vpor
—
—
100
mV
Symbol
Pull-up resistance of RES pin
Power-on reset start voltage*
*
Values
Min.
Item
Note:
Test
Condition
The power-supply voltage (Vcc) must fall below Vpor = 100 mV and then rise after
charge of the RES pin is removed completely. In order to remove charge of the RES
pin, it is recommended that the diode be placed in the Vcc side. If the power-supply
voltage (Vcc) rises from the point over 100 mV, a power-on reset may not occur.
Rev. 4.00 Mar. 15, 2006 Page 460 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
22.3
Electrical Characteristics (Masked ROM Version)
22.3.1
Power Supply Voltage and Operating Ranges
Power Supply Voltage and Oscillation Frequency Range:
φOSC (MHz)
φOSC (MHz)
20.0
850.0
10.0
2.0
64.0
2.7
4.0
5.5
VCC (V)
4.0
VCC (V)
5.5
AVCC = 3.3 to 5.5 V
• Active mode
• Sleep mode
• Subactive mode
• Subsleep mode
AVCC = 3.3 to 5.5 V
• Active mode
• Sleep mode
Note: This frequency range is supplied by the on-chip
oscillator for the subtimer and is guaranteed.
Power Supply Voltage and Operating Frequency Range:
φ (MHz)
φ (kHz)
20.0
2500
10.0
1250
1.0
78.125
2.7
4.0
5.5
VCC (V)
AVCC = 3.3 to 5.5 V
• Active mode
• Sleep mode
(When MA2 in SYSCR2 = 0 )
2.7
4.0
5.5
VCC (V)
AVCC = 3.3 to 5.5 V
• Active mode
• Sleep mode
(When MA2 in SYSCR2 = 1 )
Rev. 4.00 Mar. 15, 2006 Page 461 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
Analog Power Supply Voltage and A/D Converter Accuracy Guarantee Range:
φ (MHz)
20.0
10.0
2.0
3.3
4.0
5.5
AVCC (V)
VCC = 2.7 to 5.5 V
• Active mode
• Sleep mode
Range of Power Supply Voltage and Oscillation Frequency when Low-Voltage Detection
Circuit is Used:
φosc (MHz)
20.0
16.0
2.0
Vcc(V)
3.0
4.5
5.5
Operation guarantee range
Operation guarantee range except
A/D conversion accuracy
Rev. 4.00 Mar. 15, 2006 Page 462 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
Range of Power Supply Voltage and Oscillation Frequency when Subtimer is Used:
φ (MHz)
φSUB (kHz)
20.0
106.25*
1.0
4.0
4.0
AVcc = 4.0 to 5.5 V
• Active mode
• Sleep mode
5.5
Vcc(V)
4.0
5.5
Vcc(V)
AVcc = 4.0 to 5.5 V
• Subactive mode
• Subsleep mode
Note: * Reference value
Rev. 4.00 Mar. 15, 2006 Page 463 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
22.3.2
DC Characteristics
Table 22.12 DC Characteristics (1)
VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C
(wide-range specifications), unless otherwise indicated.
Values
Item
Symbol
Input high VIH
voltage
Applicable Pins
Test Condition
RES, NMI,
WKP0 to WKP5,
IRQ0 to IRQ3,
ADTRG,TMRIV,
TMCIV, FTIOA0
to FTIOD0,
FTIOA1 to
FTIOD1, SCK3,
1
SCK3_2* , SCS,
SSCK, TRGV,
TMIB1
Min.
Typ.
Max.
Unit
VCC = 4.0 to 5.5 V VCC × 0.8
—
VCC + 0.3
V
VCC × 0.9
—
VCC + 0.3
VCC = 4.0 to 5.5 V VCC × 0.7
RXD, RXD_2* ,
SSI, SSO, HRXD,
P10 to P12,
P14 to P17,
P20 to P24,
P50 to P57,
P60 to P67,
VCC × 0.8
P70 to P72,
P74 to P76,
P85 to P87
P90 to P97
—
VCC + 0.3
—
VCC + 0.3
VCC = 4.0 to 5.5 V VCC × 0.7
—
AVCC + 0.3 V
VCC × 0.8
—
AVCC + 0.3
VCC = 4.0 to 5.5 V VCC – 0.5
—
VCC + 0.3
VCC – 0.3
—
VCC + 0.3
1
VIH
PB0 to PB7
OSC1
Rev. 4.00 Mar. 15, 2006 Page 464 of 556
REJ09B0026-0400
V
V
Notes
Section 22 Electrical Characteristics
Values
Item
Symbol
Applicable Pins
Test Condition
Input low
voltage
VIL
RES, NMI,
WKP0 to WKP5,
IRQ0 to IRQ3,
ADTRG, TMRIV,
TMCIV, FTIOA0
to FTIOD0,
FTIOA1 to
FTIOD1, SCK3,
1
SCK3_2* , SCS,
SSCK, TRGV,
TMIB1
Min.
Typ.
Max.
Unit
VCC = 4.0 to 5.5 V –0.3
—
VCC × 0.2
V
–0.3
—
VCC × 0.1
VCC = 4.0 to 5.5 V –0.3
RXD, RXD_2* ,
SSI, SSO, HRXD,
P10 to P12,
P14 to P17,
P20 to P24,
P50 to P57,
P60 to P67,
–0.3
P70 to P72,
P74 to P76,
P85 to P87,
P90 to P97
—
VCC × 0.3
—
VCC × 0.2
1
PB0 to PB7
OSC1
Output
high
voltage
VOH
VCC = 4.0 to 5.5 V –0.3
—
VCC × 0.3
–0.3
—
VCC × 0.2
VCC = 4.0 to 5.5 V –0.3
—
0.5
–0.3
—
0.3
—
—
P10 to P12,
P14 to P17,
P20 to P24,
P50 to P55,
P60 to P67,
P70 to P72,
P74 to P76,
P85 to P87,
P90 to P97
VCC = 4.0 to 5.5 V VCC – 1.0
VCC – 0.5
—
—
P56, P57
VCC = 4.0 to 5.5 V VCC – 2.5
—
—
—
—
Notes
V
V
V
V
–IOH = 1.5 mA
–IOH = 0.1 mA
V
–IOH = 0.1 mA
VCC = 3.0 to 4.0 V VCC – 2.0
–IOH = 0.1 mA
Rev. 4.00 Mar. 15, 2006 Page 465 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
Values
Item
Symbol
Applicable Pins
Test Condition
Output
low
voltage
VOL
P10 to P12,
P14 to P17,
P20 to P24,
P50 to P57,
P70 to P72,
P74 to P76,
P85 to P87,
P90 to P97
VCC = 4.0 to 5.5 V —
P60 to P67
Min.
Typ.
Max.
Unit
—
0.6
V
—
—
0.4
VCC = 4.0 to 5.5 V —
—
1.5
—
1.0
—
0.4
Notes
IOL = 1.6 mA
IOL = 0.4 mA
V
IOL = 20.0 mA
VCC = 4.0 to 5.5 V —
IOL = 10.0 mA
VCC = 4.0 to 5.5 V —
IOL = 1.6 mA
IOL = 0.4 mA
Input/
output
leakage
current
Pull-up
MOS
current
| IIL |
–Ip
—
—
0.4
OSC1, RES, NMI, VIN = 0.5 V or
WKP0 to WKP5, higher
IRQ0 to IRQ3,
(VCC – 0.5 V)
ADTRG, TRGV,
TMRIV, TMCIV,
FTIOA0 to
FTIOD0, FTIOA1
to FTIOD1, RXD,
1
SCK3, RXD_2* ,
1
SCK3_2* , SSCK,
SCS, SSI, SSO,
HRXD
—
—
1.0
µA
P10 to P12,
P14 to P17,
P20 to P24,
P50 to P57,
P60 to P67,
P70 to P72,
P74 to P76,
P85 to P87,
P90 to P97
VIN = 0.5 V or
higher
(VCC – 0.5 V)
—
—
1.0
µA
PB0 to PB7
VIN = 0.5 V or
higher
(AVCC – 0.5 V)
—
—
1.0
µA
P10 to P12,
P14 to P17,
P50 to P55
VCC = 5.0 V,
VIN = 0.0 V
50.0
—
300.0
µA
VCC = 3.0 V,
VIN = 0.0 V
—
60.0
—
Rev. 4.00 Mar. 15, 2006 Page 466 of 556
REJ09B0026-0400
Reference
value
Section 22 Electrical Characteristics
Values
Item
Symbol
Applicable Pins
Test Condition
Min.
Typ.
Max.
Unit
Input
capacitance
Cin
All input pins
except power
supply pins
f = 1 MHz,
VIN = 0.0 V,
Ta = 25°C
—
—
15.0
pF
Active
mode
supply
current
IOPE1
VCC
Active mode 1
VCC = 5.0 V,
fOSC = 20 MHz
—
25.0
35.0
mA
Active mode 1
VCC = 3.0 V,
fOSC = 10 MHz
—
10.0
—
Active mode 2
VCC = 5.0 V,
fOSC = 20 MHz
—
1.2
3.0
Active mode 2
VCC = 3.0 V,
fOSC = 10 MHz
—
0.8
—
Sleep mode 1
VCC = 5.0 V,
fOSC = 20 MHz
—
14.0
22.5
Sleep mode 1
VCC = 3.0 V,
fOSC = 10 MHz
—
6.3
—
Sleep mode 2
VCC = 5.0 V,
fOSC = 20 MHz
—
1.0
2.7
Sleep mode 2
VCC = 3.0 V,
fOSC = 10 MHz
—
0.7
—
VCC = 5.0 V
(φSUB = φW/2)
—
60.0
100.0
VCC = 5.0 V
(φSUB = φW/8)
—
46.0
—
IOPE2
Sleep
mode
supply
current
ISLEEP1
ISLEEP2
VCC
VCC
VCC
VCC
Notes
3
*
3
*
Reference
value
mA
3
*
3
*
Reference
value
mA
3
*
3
*
Reference
value
mA
3
*
3
*
Reference
value
3
Subactive
mode
supply
current
ISUB
Subsleep
mode
supply
current
ISUBSP
VCC
VCC = 5.0 V
(φSUB = φW/2)
—
50.0
80.0
µA
*
Standby
mode
supply
current
ISTBY
VCC
Subtimer, WDT,
2
and LVD* not
used
—
—
5.0
µA
*
µA
*
3
*
Reference
value
3
3
Rev. 4.00 Mar. 15, 2006 Page 467 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
Values
Item
Symbol
Applicable Pins
RAM data
retaining
voltage
VRAM
VCC
Note:
Test Condition
Min.
Typ.
Max.
Unit Notes
2.0
—
—
V
Connect the TEST pin to Vss.
1. The H8/36037 Group does not have these pins.
2. The LVD is optional.
3. Pin states during supply current measurement are given below (excluding current in the
pull-up MOS transistors and output buffers).
Mode
RES Pin
Active mode 1
VCC
Active mode 2
Sleep mode 1
Internal State
Other Pins
Oscillator Pins
Operates
VCC
Main clock:
ceramic or crystal
resonator
Operates
(φOSC/64)
VCC
Sleep mode 2
Only timers operate
VCC
Only timers operate
(φOSC/64)
Subactive mode
VCC
Operates
VCC
Subsleep mode
VCC
Only timers operate
VCC
Standby mode
VCC
CPU and timers
both stop
VCC
Rev. 4.00 Mar. 15, 2006 Page 468 of 556
REJ09B0026-0400
Main clock:
on-chip oscillator
Main clock:
ceramic or crystal
resonator
Section 22 Electrical Characteristics
Table 22.13 DC Characteristics (2)
VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C
(wide-range specifications), unless otherwise indicated.
Values
Item
Symbol
Applicable Pins Test Condition
Min.
Typ.
Max.
Unit
Allowable output low
current (per pin)
IOL
Output pins
except port 6
—
—
2.0
mA
Port 6
—
—
20.0
Output pins
except port 6
—
—
0.5
Port 6
—
—
10.0
—
—
40.0
Port 6
—
—
80.0
Output pins
except port 6
—
—
20.0
—
—
40.0
—
—
2.0
—
—
0.2
Allowable output low
current (total)
∑IOL
Output pins
except port 6
VCC = 4.0 to 5.5 V
VCC = 4.0 to 5.5 V
Port 6
Allowable output high –IOH
current (per pin)
All output pins
Allowable output high ∑–IOH
current (total)
All output pins
VCC = 4.0 to 5.5 V
VCC = 4.0 to 5.5 V
—
—
30.0
—
—
8.0
mA
mA
mA
Rev. 4.00 Mar. 15, 2006 Page 469 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
22.3.3
AC Characteristics
Table 22.14 AC Characteristics
VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C
(wide-range specifications), unless otherwise indicated.
Values
Applicable
Test Condition
Symbol Pins
Min.
Typ.
Max.
Unit
Reference
Figure
System clock
oscillation
frequency
fOSC
2.0
—
20.0
MHz
*
System clock (φ)
cycle time
tcyc
*
Subclock oscillator
oscillation
frequency
fRO
Subclock oscillator
(φw) cycle time
Subclock (φsub)
cycle time
Item
OSC1,
OSC2
VCC = 4.0 to 5.5 V
2.0
10.0
1
—
64
tOSC
—
—
12.8
µs
VCC = 4.0 to 5.5 V
64.0
—
850.0
kHz
tRO
VCC = 4.0 to 5.5 V
1.18
—
15.6
µs
tsubcyc
VCC = 4.0 to 5.5 V
2
—
8
φw
2
—
—
tcyc
tsubcyc
Instruction cycle
time
trc
OSC1,
OSC2
—
—
10.0
ms
trc
Oscillation
stabilization time
(ceramic resonator)
OSC1,
OSC2
—
—
5.0
ms
20.0
—
—
ns
40.0
—
—
—
—
Oscillation
stabilization time
(crystal resonator)
OSC1
External clock high
width
tCPH
External clock low
width
tCPL
OSC1
VCC = 4.0 to 5.5 V
20.0
40.0
—
—
External clock rise
time
tCPr
OSC1
VCC = 4.0 to 5.5 V
—
—
10.0
—
—
15.0
External clock fall
time
tCPf
OSC1
VCC = 4.0 to 5.5 V
—
—
10.0
—
—
15.0
Rev. 4.00 Mar. 15, 2006 Page 470 of 556
REJ09B0026-0400
VCC = 4.0 to 5.5 V
1
ns
ns
ns
2
Figure 22.1
Section 22 Electrical Characteristics
Item
RES pin low
width
Applicable
Test Condition
Symbol Pins
tREL
RES
At power-on and in
modes other than
those below
Values
Min.
Typ.
Max.
Unit
Reference
Figure
trc
—
—
ms
Figure 22.2
—
—
ns
In active mode and
1500
sleep mode operation
Input pin high
width
tIH
NMI,
IRQ0 to
IRQ3,
WKP0 to
WKP5,
TMCIV,
TMRIV,
TRGV,
ADTRG,
FTIOA0 to
FTIOD0,
FTIOA1 to
FTIOD1
2
—
—
tcyc
tsubcyc
Input pin low
width
tIL
NMI,
IRQ0 to
IRQ3,
WKP0 to
WKP5,
TMCIV,
TMRIV,
TRGV,
ADTRG,
FTIOA0 to
FTIOD0,
FTIOA1 to
FTIOD1
2
—
—
tcyc
tsubcyc
Figure 22.3
Notes: 1. When an external clock is input, the minimum system clock oscillation frequency is 1.0
MHz.
2. Determined by the MA2, MA1, MA0, SA1, and SA0 bits in the system control register 2
(SYSCR2).
Rev. 4.00 Mar. 15, 2006 Page 471 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
Table 22.15 Serial Communication Interface (SCI) Timing
VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C
(wide-range specifications), unless otherwise indicated.
Item
Input
clock
cycle
Symbol
Asynchronous
tscyc
Applicable
Pins
Test Condition
SCK3,
SCK3_2*
Clocked
synchronous
Input clock pulse
width
tSCKW
SCK3,
SCK3_2*
Transmit data delay
time (clocked
synchronous)
tTXD
TXD,
TXD_2*
VCC = 4.0 to 5.5 V
Receive data setup
time (clocked
synchronous)
tRXS
RXD,
RXD_2*
VCC = 4.0 to 5.5 V
Receive data hold
time (clocked
synchronous)
tRXH
RXD,
RXD_2*
VCC = 4.0 to 5.5 V
Note:
*
The H8/36037 Group does not have these pins.
Rev. 4.00 Mar. 15, 2006 Page 472 of 556
REJ09B0026-0400
Values
Min.
Typ. Max. Unit
Reference
Figure
4
—
—
Figure 22.4
6
—
—
0.4
—
0.6
tscyc
—
—
1
tcyc
—
—
1
50.0
—
—
100.0
—
—
50.0
—
—
100.0
—
—
tcyc
ns
ns
Figure 22.5
Section 22 Electrical Characteristics
Table 22.16 Controller Area Network for Tiny (TinyCAN) Timing
VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C
(wide-range specifications), unless otherwise indicated.
Typ.
Max.
Unit
Reference
Figure
HTXD
—
—
50
ns
Figure 22.6
tHRXS
HRXD
50
—
—
ns
tHRXH
HRXD
50
—
—
ns
Symbol
Transmit
data delay
time*
tHTXD
Receive
data setup
time*
Receive
data hold
time*
Note:
*
Values
Min.
Item
Applicable
Pins
Test
Condition
Although the TinyCAN input/output signal is asynchronous, its state is determined to
have changed at the rising-edge (two clock cycles) of the CK clock shown in figure
22.6.
Rev. 4.00 Mar. 15, 2006 Page 473 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
Table 22.17 Synchronous Communication Unit (SSU) Timing
VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C
(wide-range specifications), CL = 100 pF, unless otherwise indicated.
Item
Applicable
Symbol Pins
Clock cycle
tSUCYC
Test
Condition Min.
Values
Typ.
Max.
Unit
SSCK
4
—
—
tCYC
Clock high pulse width tHI
SSCK
0.4
—
0.6
tSUCYC
Clock low pulse width
tLO
SSCK
0.4
—
0.6
tSUCYC
Clock rise
time
tRISE
SSCK
—
—
1
tCYC
—
—
1.0
µs
—
1
tCYC
Clock fall
time
Master
Slave
Master
tFALL
SSCK
—
—
—
1.0
µs
Data input setup time
tSU
SSO,
SSI
1
—
—
tCYC
Data input hold time
tH
SSO,
SSI
1
—
—
tCYC
SCS setup
time
Slave
tLEAD
SCS
1 tCYC +
100
—
—
ns
SCS hold
time
Slave
tLAG
SCS
1 tCYC +
100
—
—
ns
Data output delay time tOD
SSO,
SSI
—
—
1
tCYC
Slave access time
tSA
SSI
—
—
1 tCYC +
100
ns
Slave out release time tOR
SSI
—
—
1 tCYC +
100
ns
Slave
Rev. 4.00 Mar. 15, 2006 Page 474 of 556
REJ09B0026-0400
Reference
Figure
Figures 22.7
to 22.11
Section 22 Electrical Characteristics
22.3.4
A/D Converter Characteristics
Table 22.18 A/D Converter Characteristics
VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C
(wide-range specifications), unless otherwise indicated.
Item
Symbol
Applicable
Pins
Test
Condition
Values
Min.
Typ.
Max.
Unit
Reference
Figure
V
*
Analog power supply AVCC
voltage
AVCC
3.3
VCC
5.5
Analog input voltage AVIN
AN0 to
AN7
VSS –
0.3
—
AVCC + 0.3 V
Analog power supply AIOPE
current
AVCC
—
—
2.0
mA
AVCC = 5.0 V
1
fOSC = 20 MHz
2
AISTOP1
AVCC
—
50
—
µA
*
Reference
value
AISTOP2
AVCC
—
—
5.0
µA
*
Analog input
capacitance
CAIN
AN0 to
AN7
—
—
30.0
pF
Allowable signal
source impedance
RAIN
AN0 to
AN7
—
—
5.0
kΩ
10
10
10
bit
134
—
—
tcyc
—
—
±7.5
LSB
Resolution (data
length)
Conversion time
(single mode)
AVCC = 3.3 to
5.5 V
Nonlinearity error
Offset error
—
—
±7.5
LSB
Full-scale error
—
—
±7.5
LSB
Quantization error
—
—
±0.5
LSB
Absolute accuracy
—
—
±8.0
LSB
70
—
—
tcyc
Nonlinearity error
—
—
±7.5
LSB
Offset error
—
—
±7.5
LSB
Conversion time
(single mode)
AVCC = 4.0 to
5.5 V
Full-scale error
—
—
±7.5
LSB
Quantization error
—
—
±0.5
LSB
Absolute accuracy
—
—
±8.0
LSB
3
Rev. 4.00 Mar. 15, 2006 Page 475 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
Item
Symbol
Applicable
Pins
Conversion time
(single mode)
Values
Test
Condition
AVCC = 4.0 to
5.5 V
Nonlinearity error
Min.
Typ.
Max.
Unit
134
—
—
tcyc
—
—
±3.5
LSB
Offset error
—
—
±3.5
LSB
Full-scale error
—
—
±3.5
LSB
Quantization error
—
—
±0.5
LSB
Absolute accuracy
—
—
±4.0
LSB
Reference
Figure
Notes: 1. Set AVCC = VCC when the A/D converter is not used.
2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle.
3. AISTOP2 is the current at reset and in standby, subactive, and subsleep modes while the
A/D converter is idle.
22.3.5
Watchdog Timer Characteristics
Table 22.19 Watchdog Timer Characteristics
VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C
(wide-range specifications), unless otherwise indicated.
Item
Symbol
Internal
oscillator
overflow
time
tOVF
Note:
*
Applicable
Pins
Test
Condition
Values
Min.
Typ.
Max.
Unit
Reference
Figure
0.2
0.4
—
s
*
Indicates the time to count from 0 to 255, at which point an internal reset is generated,
when the internal oscillator is selected.
Rev. 4.00 Mar. 15, 2006 Page 476 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
22.3.6
Power-Supply-Voltage Detection Circuit Characteristics (Optional)
Table 22.20 Power-Supply-Voltage Detection Circuit Characteristics
VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C (wide-range
specifications), unless otherwise indicated.
Values
Item
Symbol
Test
Condition
Power-supply falling detection voltage
Vint (D)
LVDSEL = 0
3.3
3.7
—
V
Power-supply rising detection voltage
1
Reset detection voltage 1*
2
Reset detection voltage 2*
3
Min.
Typ.
Max.
Unit
Vint (U)
LVDSEL = 0
—
4.0
4.5
V
Vreset1
LVDSEL = 0
—
2.3
2.7
V
Vreset2
LVDSEL = 1
3.0
3.6
4.2
V
Lower-limit voltage of LVDR operation*
VLVDRmin
1.0
—
—
V
LVD stabilization time
tLVDON
50
—
—
µs
Supply current in standby mode
ISTBY

LVDE = 1,
Vcc = 5.0 V,
subtimer and
WDT not used
—
350
µA
Notes: 1. This voltage should be used when the falling and rising voltage detection function is
used.
2. Select the low-voltage reset 2 when only the low-voltage detection reset is used.
3. When the power-supply voltage (Vcc) falls below VLVDRmin = 1.0 V and then rises, a reset
may not occur. Therefore sufficient evaluation is required.
22.3.7
Power-On Reset Circuit Characteristics (Optional)
Table 22.21 Power-On Reset Circuit Characteristics
VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C (wide-range
specifications), unless otherwise indicated.
Typ.
Max.
Unit
RRES
100
150
—
kΩ
Vpor
—
—
100
mV
Symbol
Pull-up resistance of RES pin
Power-on reset start voltage*
*
Values
Min.
Item
Note:
Test
Condition
The power-supply voltage (Vcc) must fall below Vpor = 100 mV and then rise after
charge of the RES pin is removed completely. In order to remove charge of the RES
pin, it is recommended that the diode be placed in the Vcc side. If the power-supply
voltage (Vcc) rises from the point over 100 mV, a power-on reset may not occur.
Rev. 4.00 Mar. 15, 2006 Page 477 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
22.4
Operation Timing
t OSC
VIH
OSC1
VIL
t CPH
t CPL
t CPf
t CPr
Figure 22.1 System Clock Input Timing
VCC
VCC × 0.7
OSC1
tREL
RES
VIL
VIL
tREL
Figure 22.2 RES Low Width Timing
NMI
IRQ0 to IRQ3
WKP0 to WKP5
ADTRG
FTIOA0 to FTIOD0,
FTIOA1 to FTIOD1,
TMCIV, TMRIV
TRGV
VIH
VIL
t IL
t IH
Figure 22.3 Input Timing
Rev. 4.00 Mar. 15, 2006 Page 478 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
t SCKW
SCK3,
SCK3_2*
t Scyc
Note: * The H8/36037 Group does not have this pin.
Figure 22.4 SCK3 Input Clock Timing
t Scyc
2
VIH or VOH *
SCK3,
VIL or VOL *2
SCK3_2*1
t TXD
TXD,
TXD_2*1
(transmit data)
VOH*
2
2
VOL *
t RXS
t RXH
RXD,
RXD_2*1
(receive data)
Notes: 1. The H8/36037 Group does not have these pins.
2. Output timing reference levels
Output high:
V OH= 2.0 V
Output low:
V OL= 0.8 V
Load conditions are shown in figure 22.12.
Figure 22.5 SCI Input/Output Timing in Clocked Synchronous Mode
Rev. 4.00 Mar. 15, 2006 Page 479 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
VOL
VOL
CK
tHTXD
HTXD
(transmit data)
tHTRXS
tHTRXH
HRXD
(receive data)
Figure 22.6 TinyCAN Input/Output Timing
tHI
VIH or VOH
SSCK
VIH or VOH
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
Figure 22.7 SSU Input/Output Timing in Clocked Synchronous Mode
Rev. 4.00 Mar. 15, 2006 Page 480 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
SCS (output)
VIH or VOH
VIH or VOH
tFALL
tHI
tRISE
SSCK (output)
CPOS = 1
tLO
tHI
SSCK (output)
CPOS = 0
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
Figure 22.8 SSU Input/Output Timing
(Four-Line Bus Communication Mode, Master, CPHS = 1)
Rev. 4.00 Mar. 15, 2006 Page 481 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
SCS (output)
VIH or VOH
VIH or VOH
tFALL
tHI
tRISE
SSCK (output)
CPOS = 1
tLO
tHI
SSCK (output)
CPOS = 0
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
Figure 22.9 SSU Input/Output Timing
(Four-Line Bus Communication Mode, Master, CPHS = 0)
Rev. 4.00 Mar. 15, 2006 Page 482 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
SCS (input)
VIH or VOH
VIH or VOH
tLEAD
tFALL
tHI
tRISE
tLAG
SSCK (input)
CPOS = 1
tLO
tHI
SSCK (input)
CPOS = 0
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
Figure 22.10 SSU Input/Output Timing
(Four-Line Bus Communication Mode, Slave, CPHS = 1)
Rev. 4.00 Mar. 15, 2006 Page 483 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
VIH or VOH
SCS (input)
VIH or VOH
tLEAD
tFALL
tHI
tRISE
tLAG
SSCK (input)
CPOS = 1
tLO
tHI
SSCK (input)
CPOS = 0
tSUCYC
tLO
SSO (input)
tSU
tH
SSI (output)
tOD
tSA
tOD
Figure 22.11 SSU Input/Output Timing
(Four-Line Bus Communication Mode, Slave, CPHS = 0)
Rev. 4.00 Mar. 15, 2006 Page 484 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
22.5
Output Load Condition
VCC
2.4 kΩ
LSI output pin
30 pF
12 k Ω
Figure 22.12 Output Load Circuit
Rev. 4.00 Mar. 15, 2006 Page 485 of 556
REJ09B0026-0400
Section 22 Electrical Characteristics
Rev. 4.00 Mar. 15, 2006 Page 486 of 556
REJ09B0026-0400
Appendix
Appendix A Instruction Set
A.1
Instruction List
Condition Code
Symbol
Description
Rd
General destination register
Rs
General source register
Rn
General register
ERd
General destination register (address register or 32-bit register)
ERs
General source register (address register or 32-bit register)
ERn
General register (32-bit register)
(EAd)
Destination operand
(EAs)
Source operand
PC
Program counter
SP
Stack pointer
CCR
Condition-code register
N
N (negative) flag in CCR
Z
Z (zero) flag in CCR
V
V (overflow) flag in CCR
C
C (carry) flag in CCR
disp
Displacement
→
Transfer from the operand on the left to the operand on the right, or transition from
the state on the left to the state on the right
+
Addition of the operands on both sides
–
Subtraction of the operand on the right from the operand on the left
×
Multiplication of the operands on both sides
÷
Division of the operand on the left by the operand on the right
∧
Logical AND of the operands on both sides
∨
Logical OR of the operands on both sides
⊕
Logical exclusive OR of the operands on both sides
¬
NOT (logical complement)
Rev. 4.00 Mar. 15, 2006 Page 487 of 556
REJ09B0026-0400
Appendix
Symbol
Description
( ), < >
Contents of operand
Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers
(R0 to R7 and E0 to E7).
Symbol
Description
↔
Condition Code Notation (cont)
Changed according to execution result
*
Undetermined (no guaranteed value)
0
Cleared to 0
1
Set to 1
—
Not affected by execution of the instruction
∆
Varies depending on conditions, described in notes
Rev. 4.00 Mar. 15, 2006 Page 488 of 556
REJ09B0026-0400
Appendix
Table A.1
Instruction Set
1. Data Transfer Instructions
Condition Code
MOV.B @(d:16, ERs), Rd
B
4
@(d:16, ERs) → Rd8
— —
MOV.B @(d:24, ERs), Rd
B
8
@(d:24, ERs) → Rd8
— —
MOV.B @ERs+, Rd
B
@ERs → Rd8
ERs32+1 → ERs32
— —
MOV.B @aa:8, Rd
B
2
@aa:8 → Rd8
— —
MOV.B @aa:16, Rd
B
4
@aa:16 → Rd8
— —
MOV.B @aa:24, Rd
B
6
@aa:24 → Rd8
— —
MOV.B Rs, @ERd
B
Rs8 → @ERd
— —
MOV.B Rs, @(d:16, ERd)
B
4
Rs8 → @(d:16, ERd)
— —
MOV.B Rs, @(d:24, ERd)
B
8
Rs8 → @(d:24, ERd)
— —
MOV.B Rs, @–ERd
B
ERd32–1 → ERd32
Rs8 → @ERd
— —
MOV.B Rs, @aa:8
B
2
Rs8 → @aa:8
— —
MOV.B Rs, @aa:16
B
4
Rs8 → @aa:16
— —
MOV.B Rs, @aa:24
B
6
Rs8 → @aa:24
— —
MOV.W #xx:16, Rd
W 4
#xx:16 → Rd16
— —
MOV.W Rs, Rd
W
Rs16 → Rd16
— —
MOV.W @ERs, Rd
W
@ERs → Rd16
— —
2
2
2
2
2
2
MOV.W @(d:16, ERs), Rd W
4
@(d:16, ERs) → Rd16
— —
MOV.W @(d:24, ERs), Rd W
8
@(d:24, ERs) → Rd16
— —
@ERs → Rd16
ERs32+2 → @ERd32
— —
MOV.W @ERs+, Rd
W
MOV.W @aa:16, Rd
W
4
@aa:16 → Rd16
— —
MOV.W @aa:24, Rd
W
6
@aa:24 → Rd16
— —
MOV.W Rs, @ERd
W
Rs16 → @ERd
— —
2
2
MOV.W Rs, @(d:16, ERd) W
4
Rs16 → @(d:16, ERd)
— —
MOV.W Rs, @(d:24, ERd) W
8
Rs16 → @(d:24, ERd)
— —
0 —
0 —
0 —
Advanced
— —
B
↔ ↔ ↔ ↔ ↔ ↔
@ERs → Rd8
MOV.B @ERs, Rd
2
↔ ↔ ↔ ↔ ↔ ↔
— —
B
C
0 —
↔ ↔ ↔ ↔ ↔ ↔ ↔
Rs8 → Rd8
MOV.B Rs, Rd
V
↔ ↔ ↔ ↔ ↔ ↔ ↔
Z
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
I
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
N
— —
↔ ↔ ↔ ↔ ↔
H
#xx:8 → Rd8
Normal
—
@@aa
@(d, PC)
Operation
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
2
Rn
B
No. of
States*1
↔ ↔ ↔ ↔ ↔
MOV MOV.B #xx:8, Rd
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
2
0 —
2
0 —
4
0 —
6
0 —
10
0 —
6
4
0 —
6
0 —
8
0 —
4
0 —
6
0 —
10
0 —
6
4
0 —
6
0 —
8
0 —
4
0 —
2
0 —
4
0 —
6
0 —
10
0 —
6
6
0 —
8
0 —
4
0 —
6
0 —
10
Rev. 4.00 Mar. 15, 2006 Page 489 of 556
REJ09B0026-0400
Appendix
No. of
States*1
Condition Code
— —
@(d:24, ERs) → ERd32
— —
@ERs → ERd32
ERs32+4 → ERs32
— —
6
@aa:16 → ERd32
— —
8
@aa:24 → ERd32
— —
ERs32 → @ERd
— —
ERs32 → @(d:16, ERd)
— —
ERs32 → @(d:24, ERd)
— —
ERd32–4 → ERd32
ERs32 → @ERd
— —
6
ERs32 → @aa:16
— —
8
ERs32 → @aa:24
— —
0 —
0 —
POP POP.W Rn
W
2 @SP → Rn16
SP+2 → SP
— —
POP.L ERn
L
4 @SP → ERn32
SP+4 → SP
— —
0 —
PUSH PUSH.W Rn
W
2 SP–2 → SP
Rn16 → @SP
— —
0 —
PUSH.L ERn
L
4 SP–4 → SP
ERn32 → @SP
— —
0 —
MOVFPE
MOVFPE @aa:16, Rd
B
4
Cannot be used in
this LSI
Cannot be used in
this LSI
MOVTPE
MOVTPE Rs, @aa:16
B
4
Cannot be used in
this LSI
Cannot be used in
this LSI
W
MOV.W Rs, @aa:16
W
MOV.W Rs, @aa:24
W
MOV.L #xx:32, ERd
L
MOV.L ERs, ERd
L
MOV.L @ERs, ERd
L
MOV.L @(d:16, ERs), ERd
L
6
MOV.L @(d:24, ERs), ERd
L
10
MOV.L @ERs+, ERd
L
MOV.L @aa:16, ERd
L
MOV.L @aa:24, ERd
L
MOV.L ERs, @ERd
L
MOV.L ERs, @(d:16, ERd)
L
6
MOV.L ERs, @(d:24, ERd)
L
10
MOV.L ERs, @–ERd
L
MOV.L ERs, @aa:16
L
MOV.L ERs, @aa:24
L
2
6
2
4
4
4
Rev. 4.00 Mar. 15, 2006 Page 490 of 556
REJ09B0026-0400
4
Advanced
@(d:16, ERs) → ERd32
↔
— —
↔
@ERs → ERd32
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
— —
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
ERs32 → ERd32
↔ ↔ ↔ ↔ ↔ ↔
— —
↔ ↔ ↔ ↔ ↔ ↔
#xx:32 → ERd32
0 —
↔ ↔ ↔
— —
↔ ↔ ↔
— —
Rs16 → @aa:24
↔
Rs16 → @aa:16
6
C
↔
4
V
↔
Z
↔
I
↔
N
— —
↔
H
ERd32–2 → ERd32
Rs16 → @ERd
0 —
MOV MOV.W Rs, @–ERd
Normal
—
@@aa
@(d, PC)
Operation
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
6
6
0 —
8
0 —
6
0 —
2
0 —
8
0 —
10
0 —
14
0 —
10
10
0 —
12
0 —
8
0 —
10
0 —
14
0 —
10
10
0 —
12
0 —
6
10
6
10
Appendix
2. Arithmetic Instructions
No. of
States*1
Condition Code
Z
V
C
↔ ↔
— (2)
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
ERd32+ERs32 →
ERd32
— (2)
↔
↔
(3)
↔ ↔
Rd16+Rs16 → Rd16
— (1)
ERd32+#xx:32 →
ERd32
2
Rd8+#xx:8 +C → Rd8
—
2
B
2
Rd8+Rs8 +C → Rd8
—
ADDS ADDS.L #1, ERd
L
2
ERd32+1 → ERd32
— — — — — —
2
ADDS.L #2, ERd
L
2
ERd32+2 → ERd32
— — — — — —
2
ADDS.L #4, ERd
L
2
ERd32+4 → ERd32
— — — — — —
2
INC.B Rd
B
2
Rd8+1 → Rd8
— —
INC.W #1, Rd
W
2
Rd16+1 → Rd16
— —
INC.W #2, Rd
W
2
Rd16+2 → Rd16
— —
INC.L #1, ERd
L
2
ERd32+1 → ERd32
— —
INC.L #2, ERd
L
2
ERd32+2 → ERd32
— —
DAA
DAA Rd
B
2
Rd8 decimal adjust
→ Rd8
— *
SUB
SUB.B Rs, Rd
B
2
Rd8–Rs8 → Rd8
—
SUB.W #xx:16, Rd
W 4
Rd16–#xx:16 → Rd16
— (1)
SUB.W Rs, Rd
W
Rd16–Rs16 → Rd16
— (1)
SUB.L #xx:32, ERd
L
SUB.L ERs, ERd
L
W 4
ADD.W Rs, Rd
W
ADD.L #xx:32, ERd
L
ADD.L ERs, ERd
L
ADDX ADDX.B #xx:8, Rd
ADDX.B Rs, Rd
6
2
(3)
2
6
2
—
2
—
2
—
2
—
2
—
2
*
B
2
Rd8–Rs8–C → Rd8
—
SUBS SUBS.L #1, ERd
L
2
ERd32–1 → ERd32
— — — — — —
2
SUBS.L #2, ERd
L
2
ERd32–2 → ERd32
— — — — — —
2
SUBS.L #4, ERd
L
2
ERd32–4 → ERd32
— — — — — —
2
B
2
Rd8–1 → Rd8
— —
DEC.W #1, Rd
W
2
Rd16–1 → Rd16
— —
DEC.W #2, Rd
W
2
Rd16–2 → Rd16
— —
2
ERd32–ERs32 → ERd32 — (2)
Rd8–#xx:8–C → Rd8
—
(3)
(3)
↔ ↔ ↔
DEC DEC.B Rd
2
↔ ↔
SUBX.B Rs, Rd
B
ERd32–#xx:32 → ERd32 — (2)
6
↔ ↔ ↔
SUBX SUBX.B #xx:8, Rd
2
↔ ↔ ↔
2
↔
2
↔ ↔ ↔ ↔ ↔ ↔ ↔
↔
2
4
↔ ↔ ↔ ↔ ↔ ↔ ↔
INC
B
2
2
↔ ↔ ↔ ↔ ↔
ADD.W #xx:16, Rd
2
↔ ↔ ↔ ↔ ↔ ↔
B
↔ ↔ ↔ ↔ ↔
ADD.B Rs, Rd
↔ ↔ ↔ ↔ ↔ ↔ ↔
ADD ADD.B #xx:8, Rd
↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
— (1)
↔ ↔ ↔ ↔ ↔
Rd16+#xx:16 → Rd16
2
↔
—
↔ ↔
Rd8+Rs8 → Rd8
↔
—
Advanced
N
↔ ↔
I
Rd8+#xx:8 → Rd8
Normal
H
↔ ↔
—
@@aa
@(d, PC)
Operation
@aa
@–ERn/@ERn+
@(d, ERn)
2
@ERn
B
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
4
2
6
2
2
2
—
2
—
2
—
2
Rev. 4.00 Mar. 15, 2006 Page 491 of 556
REJ09B0026-0400
Appendix
No. of
States*1
Condition Code
Advanced
V
C
ERd32–1 → ERd32
— —
L
2
ERd32–2 → ERd32
— —
↔ ↔
—
2
DAS.Rd
B
2
Rd8 decimal adjust
→ Rd8
— *
↔ ↔ ↔
2
DEC.L #2, ERd
↔ ↔ ↔
—
* —
2
B
2
Rd8 × Rs8 → Rd16
(unsigned multiplication)
— — — — — —
14
W
2
Rd16 × Rs16 → ERd32
(unsigned multiplication)
— — — — — —
22
B
4
Rd8 × Rs8 → Rd16
(signed multiplication)
— —
↔
W
4
Rd16 × Rs16 → ERd32
(signed multiplication)
— —
B
2
W
DIVXU DIVXU. B Rs, Rd
DIVXU. W Rs, ERd
DIVXS DIVXS. B Rs, Rd
DIVXS. W Rs, ERd
CMP CMP.B #xx:8, Rd
16
— —
24
Rd16 ÷ Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
(unsigned division)
— — (6) (7) — —
14
2
ERd32 ÷ Rs16 → ERd32
(Ed: remainder,
Rd: quotient)
(unsigned division)
— — (6) (7) — —
22
B
4
Rd16 ÷ Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
(signed division)
— — (8) (7) — —
16
W
4
ERd32 ÷ Rs16 → ERd32
(Ed: remainder,
Rd: quotient)
(signed division)
— — (8) (7) — —
24
Rd8–#xx:8
—
Rd8–Rs8
—
Rd16–#xx:16
— (1)
Rd16–Rs16
— (1)
ERd32–#xx:32
— (2)
ERd32–ERs32
— (2)
B
2
CMP.B Rs, Rd
B
CMP.W #xx:16, Rd
W 4
CMP.W Rs, Rd
W
CMP.L #xx:32, ERd
L
CMP.L ERs, ERd
L
2
2
6
2
Rev. 4.00 Mar. 15, 2006 Page 492 of 556
REJ09B0026-0400
↔ ↔ ↔ ↔ ↔ ↔
MULXS. W Rs, ERd
— —
↔ ↔ ↔ ↔ ↔ ↔
MULXS MULXS. B Rs, Rd
↔ ↔ ↔ ↔ ↔ ↔
MULXU. W Rs, ERd
↔ ↔
MULXU MULXU. B Rs, Rd
↔ ↔ ↔ ↔ ↔ ↔
DAS
I
Normal
Z
2
↔
N
L
↔
H
DEC DEC.L #1, ERd
↔
—
@@aa
@(d, PC)
Operation
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
2
2
4
2
4
2
Appendix
No. of
States*1
Condition Code
W
2
0–Rd16 → Rd16
—
NEG.L ERd
L
2
0–ERd32 → ERd32
—
EXTU EXTU.W Rd
W
2
0 → (<bits 15 to 8>
of Rd16)
— — 0
EXTU.L ERd
L
2
0 → (<bits 31 to 16>
of ERd32)
— — 0
EXTS EXTS.W Rd
W
2
(<bit 7> of Rd16) →
(<bits 15 to 8> of Rd16)
— —
EXTS.L ERd
L
2
(<bit 15> of ERd32) →
(<bits 31 to 16> of
ERd32)
— —
Advanced
↔ ↔ ↔
NEG.W Rd
Normal
C
↔ ↔ ↔
—
↔ ↔ ↔
V
↔ ↔ ↔ ↔
0–Rd8 → Rd8
2
0 —
2
↔
2
0 —
2
↔
H
B
0 —
2
↔
Z
↔
I
NEG NEG.B Rd
↔ ↔ ↔
N
↔
—
@@aa
@(d, PC)
Operation
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
0 —
2
2
2
Rev. 4.00 Mar. 15, 2006 Page 493 of 556
REJ09B0026-0400
Appendix
3. Logic Instructions
AND.B Rs, Rd
B
AND.W #xx:16, Rd
W 4
AND.W Rs, Rd
W
AND.L #xx:32, ERd
L
AND.L ERs, ERd
L
OR.B #xx:8, Rd
B
OR.B Rs, Rd
B
OR.W #xx:16, Rd
W 4
OR.W Rs, Rd
W
OR.L #xx:32, ERd
L
OR.L ERs, ERd
L
XOR.B #xx:8, Rd
B
XOR.B Rs, Rd
B
XOR.W #xx:16, Rd
W 4
XOR.W Rs, Rd
W
XOR.L #xx:32, ERd
L
XOR.L ERs, ERd
L
4
ERd32⊕ERs32 → ERd32 — —
NOT.B Rd
B
2
¬ Rd8 → Rd8
— —
NOT.W Rd
W
2
¬ Rd16 → Rd16
— —
NOT.L ERd
L
2
¬ Rd32 → Rd32
— —
Z
Rd8∧Rs8 → Rd8
— —
Rd16∧#xx:16 → Rd16
— —
Rd16∧Rs16 → Rd16
— —
4
2
2
2
6
4
2
2
2
ERd32∧ERs32 → ERd32 — —
Rd8⁄#xx:8 → Rd8
— —
Rd8⁄Rs8 → Rd8
— —
Rd16⁄#xx:16 → Rd16
— —
Rd16⁄Rs16 → Rd16
— —
ERd32⁄#xx:32 → ERd32
— —
ERd32⁄ERs32 → ERd32
— —
Rd8⊕#xx:8 → Rd8
— —
Rd8⊕Rs8 → Rd8
— —
Rd16⊕#xx:16 → Rd16
— —
Rd16⊕Rs16 → Rd16
— —
ERd32⊕#xx:32 → ERd32 — —
6
V
C
Advanced
I
Normal
—
@@aa
@(d, PC)
@aa
N
— —
ERd32∧#xx:32 → ERd32 — —
6
Rev. 4.00 Mar. 15, 2006 Page 494 of 556
REJ09B0026-0400
H
Rd8∧#xx:8 → Rd8
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
2
Operation
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
NOT
2
@(d, ERn)
2
@ERn
B
Rn
#xx
XOR
Condition Code
Operand Size
OR
No. of
States*1
AND.B #xx:8, Rd
Mnemonic
AND
@–ERn/@ERn+
Addressing Mode and
Instruction Length (bytes)
0 —
2
0 —
2
0 —
4
0 —
2
0 —
6
0 —
4
0 —
2
0 —
2
0 —
4
0 —
2
0 —
6
0 —
4
0 —
2
0 —
2
0 —
4
0 —
2
0 —
6
0 —
4
0 —
2
0 —
2
0 —
2
Appendix
4. Shift Instructions
W
2
SHAL.L ERd
L
2
SHAR SHAR.B Rd
B
2
SHAR.W Rd
W
2
SHAR.L ERd
L
2
SHLL SHLL.B Rd
B
2
SHLL.W Rd
W
2
SHLL.L ERd
L
2
SHLR SHLR.B Rd
B
2
SHLR.W Rd
W
2
SHLR.L ERd
L
2
ROTXL ROTXL.B Rd
B
2
ROTXL.W Rd
W
2
ROTXL.L ERd
L
2
B
2
ROTXR.W Rd
W
2
ROTXR.L ERd
L
2
ROTL ROTL.B Rd
B
2
ROTL.W Rd
W
2
ROTL.L ERd
L
2
ROTR ROTR.B Rd
B
2
ROTR.W Rd
W
2
ROTR.L ERd
L
2
ROTXR ROTXR.B Rd
0
MSB
LSB
V
C
— —
— —
— —
C
MSB
— —
LSB
— —
— —
C
0
LSB
MSB
— —
— —
— —
0
C
MSB
LSB
— —
— —
— —
C
— —
MSB
LSB
— —
— —
C
LSB
MSB
— —
— —
— —
C
— —
MSB
LSB
— —
— —
C
MSB
LSB
— —
— —
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Advanced
Z
Normal
—
@@aa
@(d, PC)
@aa
@–ERn/@ERn+
@(d, ERn)
I
C
N
↔ ↔ ↔
SHAL.W Rd
H
— —
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
2
Condition Code
Operation
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
B
No. of
States*1
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
SHAL SHAL.B Rd
@ERn
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Rev. 4.00 Mar. 15, 2006 Page 495 of 556
REJ09B0026-0400
Appendix
5. Bit-Manipulation Instructions
B
BSET #xx:3, @aa:8
B
BSET Rn, Rd
B
BSET Rn, @ERd
B
BSET Rn, @aa:8
B
B
BCLR #xx:3, @ERd
B
BCLR #xx:3, @aa:8
B
BCLR Rn, Rd
B
BCLR Rn, @ERd
B
BCLR Rn, @aa:8
B
BNOT BNOT #xx:3, Rd
B
BNOT #xx:3, @ERd
B
BNOT #xx:3, @aa:8
B
BNOT Rn, Rd
B
BNOT Rn, @ERd
B
BNOT Rn, @aa:8
B
BTST BTST #xx:3, Rd
B
BTST #xx:3, @ERd
B
BTST #xx:3, @aa:8
B
BTST Rn, Rd
B
BTST Rn, @ERd
B
BTST Rn, @aa:8
B
BLD #xx:3, Rd
B
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
H
N
Z
V
C
Advanced
I
Normal
—
@@aa
@(d, PC)
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
2
Rev. 4.00 Mar. 15, 2006 Page 496 of 556
REJ09B0026-0400
Condition Code
Operation
(#xx:3 of Rd8) ← 1
— — — — — —
2
(#xx:3 of @ERd) ← 1
— — — — — —
8
(#xx:3 of @aa:8) ← 1
— — — — — —
8
(Rn8 of Rd8) ← 1
— — — — — —
2
(Rn8 of @ERd) ← 1
— — — — — —
8
(Rn8 of @aa:8) ← 1
— — — — — —
8
(#xx:3 of Rd8) ← 0
— — — — — —
2
(#xx:3 of @ERd) ← 0
— — — — — —
8
(#xx:3 of @aa:8) ← 0
— — — — — —
8
(Rn8 of Rd8) ← 0
— — — — — —
2
(Rn8 of @ERd) ← 0
— — — — — —
8
(Rn8 of @aa:8) ← 0
— — — — — —
8
(#xx:3 of Rd8) ←
¬ (#xx:3 of Rd8)
— — — — — —
2
(#xx:3 of @ERd) ←
¬ (#xx:3 of @ERd)
— — — — — —
8
(#xx:3 of @aa:8) ←
¬ (#xx:3 of @aa:8)
— — — — — —
8
(Rn8 of Rd8) ←
¬ (Rn8 of Rd8)
— — — — — —
2
(Rn8 of @ERd) ←
¬ (Rn8 of @ERd)
— — — — — —
8
(Rn8 of @aa:8) ←
¬ (Rn8 of @aa:8)
— — — — — —
8
¬ (#xx:3 of Rd8) → Z
— — —
¬ (#xx:3 of @ERd) → Z
— — —
¬ (#xx:3 of @aa:8) → Z
— — —
¬ (Rn8 of @Rd8) → Z
— — —
¬ (Rn8 of @ERd) → Z
— — —
¬ (Rn8 of @aa:8) → Z
— — —
(#xx:3 of Rd8) → C
— — — — —
— —
2
— —
6
— —
6
— —
2
— —
6
— —
6
↔
BSET #xx:3, @ERd
BCLR BCLR #xx:3, Rd
BLD
B
No. of
States*1
↔ ↔ ↔ ↔ ↔ ↔
BSET BSET #xx:3, Rd
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
2
Appendix
B
BLD #xx:3, @aa:8
B
BILD BILD #xx:3, Rd
BST
BILD #xx:3, @ERd
B
BILD #xx:3, @aa:8
B
BST #xx:3, Rd
B
BST #xx:3, @ERd
B
BST #xx:3, @aa:8
B
BIST BIST #xx:3, Rd
B
BIST #xx:3, @ERd
B
BIST #xx:3, @aa:8
B
BAND BAND #xx:3, Rd
B
BAND #xx:3, @ERd
B
BAND #xx:3, @aa:8
B
BIAND BIAND #xx:3, Rd
BOR
B
B
BIAND #xx:3, @ERd
B
BIAND #xx:3, @aa:8
B
BOR #xx:3, Rd
B
BOR #xx:3, @ERd
B
BOR #xx:3, @aa:8
B
BIOR BIOR #xx:3, Rd
B
BIOR #xx:3, @ERd
B
BIOR #xx:3, @aa:8
B
BXOR BXOR #xx:3, Rd
B
BXOR #xx:3, @ERd
B
BXOR #xx:3, @aa:8
B
BIXOR BIXOR #xx:3, Rd
B
BIXOR #xx:3, @ERd
B
BIXOR #xx:3, @aa:8
B
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
H
N
Z
V
C
(#xx:3 of @ERd) → C
— — — — —
6
(#xx:3 of @aa:8) → C
— — — — —
¬ (#xx:3 of Rd8) → C
— — — — —
¬ (#xx:3 of @ERd) → C
— — — — —
¬ (#xx:3 of @aa:8) → C
— — — — —
C → (#xx:3 of Rd8)
— — — — — —
2
C → (#xx:3 of @ERd24)
— — — — — —
8
C → (#xx:3 of @aa:8)
— — — — — —
8
¬ C → (#xx:3 of Rd8)
— — — — — —
2
¬ C → (#xx:3 of @ERd24)
— — — — — —
8
¬ C → (#xx:3 of @aa:8)
— — — — — —
8
C∧(#xx:3 of Rd8) → C
— — — — —
2
C∧(#xx:3 of @ERd24) → C
— — — — —
C∧(#xx:3 of @aa:8) → C
— — — — —
C∧ ¬ (#xx:3 of Rd8) → C
— — — — —
C∧ ¬ (#xx:3 of @ERd24) → C
— — — — —
C∧ ¬ (#xx:3 of @aa:8) → C
— — — — —
C∨(#xx:3 of Rd8) → C
— — — — —
C∨(#xx:3 of @ERd24) → C
— — — — —
C∨(#xx:3 of @aa:8) → C
— — — — —
C∨ ¬ (#xx:3 of Rd8) → C
— — — — —
C∨ ¬ (#xx:3 of @ERd24) → C
— — — — —
C∨ ¬ (#xx:3 of @aa:8) → C
— — — — —
C⊕(#xx:3 of Rd8) → C
— — — — —
C⊕(#xx:3 of @ERd24) → C
— — — — —
C⊕(#xx:3 of @aa:8) → C
— — — — —
C⊕ ¬ (#xx:3 of Rd8) → C
— — — — —
C⊕ ¬ (#xx:3 of @ERd24) → C — — — — —
4
4
Advanced
I
Normal
—
@@aa
@(d, PC)
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
Condition Code
Operation
↔ ↔ ↔ ↔ ↔
BLD #xx:3, @ERd
No. of
States*1
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
BLD
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
C⊕ ¬ (#xx:3 of @aa:8) → C
— — — — —
6
2
6
6
6
6
2
6
6
2
6
6
2
6
6
2
6
6
2
6
6
Rev. 4.00 Mar. 15, 2006 Page 497 of 556
REJ09B0026-0400
Appendix
6. Branching Instructions
Bcc
No. of
States*1
Condition Code
BRA d:8 (BT d:8)
—
2
BRA d:16 (BT d:16)
—
4
BRN d:8 (BF d:8)
—
2
BRN d:16 (BF d:16)
—
4
BHI d:8
—
2
BHI d:16
—
4
BLS d:8
—
2
BLS d:16
—
4
BCC d:8 (BHS d:8)
—
2
BCC d:16 (BHS d:16)
—
4
BCS d:8 (BLO d:8)
—
2
BCS d:16 (BLO d:16)
—
4
BNE d:8
—
2
BNE d:16
—
4
BEQ d:8
—
2
BEQ d:16
—
4
BVC d:8
—
2
BVC d:16
—
4
BVS d:8
—
2
BVS d:16
—
4
BPL d:8
—
2
BPL d:16
—
4
BMI d:8
—
2
BMI d:16
—
4
BGE d:8
—
2
BGE d:16
—
4
BLT d:8
—
2
BLT d:16
—
BGT d:8
I
H
N
Z
V
C
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
4
— — — — — —
6
—
2
Z∨ (N⊕V) = 0 — — — — — —
4
BGT d:16
—
4
— — — — — —
6
BLE d:8
—
2
Z∨ (N⊕V) = 1 — — — — — —
4
BLE d:16
—
4
— — — — — —
6
Rev. 4.00 Mar. 15, 2006 Page 498 of 556
REJ09B0026-0400
If condition Always
is true then
PC ← PC+d
Never
else next;
Advanced
Branch
Condition
Normal
—
@@aa
@(d, PC)
Operation
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
C∨ Z = 0
C∨ Z = 1
C=0
C=1
Z=0
Z=1
V=0
V=1
N=0
N=1
N⊕V = 0
N⊕V = 1
Appendix
JMP
BSR
JSR
RTS
JMP @ERn
—
JMP @aa:24
—
JMP @@aa:8
—
BSR d:8
—
BSR d:16
—
JSR @ERn
—
JSR @aa:24
—
JSR @@aa:8
—
RTS
—
No. of
States*1
Condition Code
H
N
Z
V
C
Advanced
I
Normal
—
@@aa
@(d, PC)
Operation
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
PC ← ERn
— — — — — —
PC ← aa:24
— — — — — —
PC ← @aa:8
— — — — — —
8
10
2
PC → @–SP
PC ← PC+d:8
— — — — — —
6
8
4
PC → @–SP
PC ← PC+d:16
— — — — — —
8
10
PC → @–SP
PC ← ERn
— — — — — —
6
8
PC → @–SP
PC ← aa:24
— — — — — —
8
10
PC → @–SP
PC ← @aa:8
— — — — — —
8
12
2 PC ← @SP+
— — — — — —
8
10
2
4
2
2
4
2
4
6
Rev. 4.00 Mar. 15, 2006 Page 499 of 556
REJ09B0026-0400
Appendix
7. System Control Instructions
No. of
States*1
Condition Code
Normal
Advanced
—
CCR ← @SP+
PC ← @SP+
↔
↔
10
—
Transition to powerdown state
— — — — — —
2
#xx:8 → CCR
2
↔
C
↔ ↔ ↔ ↔ ↔
↔
V
↔ ↔ ↔ ↔ ↔
↔
Z
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
↔
N
LDC #xx:8, CCR
B
LDC Rs, CCR
B
LDC @ERs, CCR
W
LDC @(d:16, ERs), CCR
W
6
@(d:16, ERs) → CCR
LDC @(d:24, ERs), CCR
W
10
@(d:24, ERs) → CCR
LDC @ERs+, CCR
W
LDC @aa:16, CCR
W
6
@aa:16 → CCR
LDC @aa:24, CCR
W
8
@aa:24 → CCR
CCR → Rd8
CCR → @ERd
— — — — — —
6
6
8
12
↔
↔
↔
↔
↔ ↔
↔ ↔
↔ ↔
↔ ↔
8
↔
@ERs → CCR
ERs32+2 → ERs32
10
— — — — — —
2
8
W
6
CCR → @(d:16, ERd)
— — — — — —
8
STC CCR, @(d:24, ERd)
W
10
CCR → @(d:24, ERd)
— — — — — —
12
STC CCR, @–ERd
W
ERd32–2 → ERd32
CCR → @ERd
— — — — — —
8
STC CCR, @aa:16
W
6
CCR → @aa:16
— — — — — —
8
STC CCR, @aa:24
W
8
CCR → @aa:24
— — — — — —
10
ANDC ANDC #xx:8, CCR
B
2
CCR∧#xx:8 → CCR
2
B
2
CCR∨#xx:8 → CCR
B
2
CCR⊕#xx:8 → CCR
— — — — — —
2
ORC
ORC #xx:8, CCR
XORC XORC #xx:8, CCR
NOP
NOP
4
4
—
Rev. 4.00 Mar. 15, 2006 Page 500 of 556
REJ09B0026-0400
2 PC ← PC+2
↔ ↔ ↔
STC CCR, @(d:16, ERd)
2
↔ ↔ ↔
W
↔ ↔ ↔
B
STC CCR, @ERd
STC
↔ ↔ ↔
STC CCR, Rd
↔ ↔ ↔
4
2
↔
@ERs → CCR
4
↔ ↔
Rs8 → CCR
2
↔ ↔
2
↔ ↔ ↔
LDC
H
↔ ↔ ↔ ↔ ↔
SLEEP SLEEP
@@aa
RTE
RTE
@(d, PC)
16
@aa
1 — — — — — 14
@ERn
2 PC → @–SP
CCR → @–SP
<vector> → PC
Rn
—
#xx
I
TRAPA TRAPA #x:2
↔ ↔ ↔ ↔ ↔
Operation
—
@–ERn/@ERn+
@(d, ERn)
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
2
2
Appendix
8. Block Transfer Instructions
EEPMOV
No. of
States*1
H
N
Z
V
C
Normal
—
@@aa
@(d, PC)
I
EEPMOV. B
—
4 if R4L ≠ 0 then
repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4L–1 → R4L
until
R4L=0
else next
— — — — — — 8+
4n*2
EEPMOV. W
—
4 if R4 ≠ 0 then
repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4–1 → R4
until
R4=0
else next
— — — — — — 8+
4n*2
Advanced
Condition Code
Operation
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
Notes: 1. The number of states in cases where the instruction code and its operands are located
in on-chip memory is shown here. For other cases, see appendix A.3, Number of
Execution States.
2. n is the value set in register R4L or R4.
(1) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0.
(2) Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0.
(3) Retains its previous value when the result is zero; otherwise cleared to 0.
(4) Set to 1 when the adjustment produces a carry; otherwise retains its previous value.
(5) The number of states required for execution of an instruction that transfers data in
synchronization with the E clock is variable.
(6) Set to 1 when the divisor is negative; otherwise cleared to 0.
(7) Set to 1 when the divisor is zero; otherwise cleared to 0.
(8) Set to 1 when the quotient is negative; otherwise cleared to 0.
Rev. 4.00 Mar. 15, 2006 Page 501 of 556
REJ09B0026-0400
REJ09B0026-0400
Rev. 4.00 Mar. 15, 2006 Page 502 of 556
XOR
SUBX
OR
XOR
AND
MOV
B
C
D
E
F
BILD
CMP
BIAND
BIST
BLD
BST
TRAPA
BEQ
A
BIXOR
BAND
AND
RTE
BNE
MOV.B
Table A.2
(2)
LDC
7
ADDX
BIOR
BXOR
OR
BOR
BSR
BCS
RTS
BCC
AND.B
ANDC
6
9
BTST
DIVXU
BLS
XOR.B
XORC
5
ADD
BCLR
MULXU
BHI
OR.B
ORC
4
8
7
BNOT
DIVXU
MULXU
5
BSET
BRN
BRA
6
LDC
3
Table A.2 Table A.2 Table A.2 Table A.2
(2)
(2)
(2)
(2)
STC
NOP
4
3
2
1
0
2
1
Table A.2
(2)
0
MOV
BVS
9
JMP
BPL
BMI
MOV
BSR
BGE
CMP
C
Table A.2 Table A.2
(2)
(2)
B
MOV
A
Table A.2 Table A.2
(2)
(2)
Table A.2 Table A.2
EEPMOV
(2)
(2)
SUB
ADD
Table A.2
(2)
BVC
8
E
JSR
BGT
SUBX
ADDX
Table A.2
(3)
BLT
D
Instruction when most significant bit of BH is 1.
Instruction when most significant bit of BH is 0.
F
BLE
Table A.2
(2)
Table A.2
(2)
Table A.2
AL
1st byte 2nd byte
AH AL BH BL
A.2
AH
Instruction code:
Appendix
Operation Code Map
Operation Code Map (1)
MOV
BRA
58
7A
DAS
1F
MOV
SUBS
1B
79
DEC
1A
NOT
1
ADD
ADD
BRN
ROTXR
13
17
ROTXL
12
DAA
0F
SHLR
ADDS
0B
11
INC
0A
SHLL
MOV
01
10
0
CMP
CMP
BHI
2
SUB
SUB
BLS
NOT
ROTXR
ROTXL
SHLR
SHLL
3
OR
OR
BCC
LDC/STC
4
1st byte 2nd byte
AH AL BH BL
XOR
XOR
BCS
DEC
EXTU
INC
5
AND
AND
BNE
6
BEQ
DEC
EXTU
INC
7
BVC
SUB
NEG
9
BVS
ROTR
ROTL
SHAR
SHAL
ADDS
SLEEP
8
BPL
A
MOV
BMI
NEG
CMP
SUB
ROTR
ROTL
SHAR
C
D
BGE
BLT
DEC
EXTS
INC
Table A.2 Table A.2
(3)
(3)
ADD
SHAL
B
BGT
E
BLE
DEC
EXTS
INC
Table A.2
(3)
F
Table A.2
BH
AH AL
Instruction code:
Appendix
Operation Code Map (2)
Rev. 4.00 Mar. 15, 2006 Page 503 of 556
REJ09B0026-0400
REJ09B0026-0400
Rev. 4.00 Mar. 15, 2006 Page 504 of 556
DIVXS
3
BSET
7Faa7 * 2
BNOT
BNOT
BCLR
BCLR
Notes: 1. r is the register designation field.
2. aa is the absolute address field.
BSET
7Faa6 * 2
BTST
BCLR
7Eaa7 * 2
BNOT
BTST
BSET
7Dr07 * 1
7Eaa6 * 2
BSET
7Dr06 * 1
BTST
BCLR
MULXS
2
7Cr07 * 1
BNOT
DIVXS
1
BTST
MULXS
0
7Cr06 * 1
01F06
01D05
01C05
01406
CL
BIOR
BOR
BIOR
BOR
OR
4
BIXOR
BXOR
BIXOR
BXOR
XOR
5
BIAND
BAND
BIAND
BAND
AND
6
BIST
BILD
BST
BLD
BIST
BILD
BST
BLD
7
1st byte 2nd byte 3rd byte 4th byte
AH AL BH BL CH CL DH DL
8
LDC
STC
9
A
LDC
STC
B
C
LDC
STC
D
E
LDC
STC
F
Instruction when most significant bit of DH is 1.
Instruction when most significant bit of DH is 0.
Table A.2
AH
ALBH
BLCH
Instruction code:
Appendix
Operation Code Map (3)
Appendix
A.3
Number of Execution States
The status of execution for each instruction of the H8/300H CPU and the method of calculating
the number of states required for instruction execution are shown below. Table A.4 shows the
number of cycles of each type occurring in each instruction, such as instruction fetch and data
read/write. Table A.3 shows the number of states required for each cycle. The total number of
states required for execution of an instruction can be calculated by the following expression:
Execution states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed.
BSET #0, @FF00
From table A.4:
I = L = 2, J = K = M = N= 0
From table A.3:
SI = 2, SL = 2
Number of states required for execution = 2 × 2 + 2 × 2 = 8
When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and
on-chip RAM is used for stack area.
JSR @@ 30
From table A.4:
I = 2, J = K = 1,
L=M=N=0
From table A.3:
SI = SJ = SK = 2
Number of states required for execution = 2 × 2 + 1 × 2+ 1 × 2 = 8
Rev. 4.00 Mar. 15, 2006 Page 505 of 556
REJ09B0026-0400
Appendix
Table A.3
Number of States Required for Execution
Access Location
Execution Status
(Instruction Cycle)
On-Chip Memory
On-Chip Peripheral Module
2
—
Instruction fetch
SI
Branch address read
SJ
Stack operation
SK
Byte data access
SL
2, 3, or 4*
Word data access
SM
2, 3, or 4*
Internal operation
SN
Note:
*
1
Depends on which on-chip peripheral module is accessed. See section 21.1, Register
Addresses (Address Order).
Rev. 4.00 Mar. 15, 2006 Page 506 of 556
REJ09B0026-0400
Appendix
Table A.4
Number of Cycles in Each Instruction
Instruction Mnemonic
Instruction
Fetch
I
ADD
ADD.B #xx:8, Rd
1
ADD.B Rs, Rd
1
ADD.W #xx:16, Rd
2
ADD.W Rs, Rd
1
ADD.L #xx:32, ERd
3
ADD.L ERs, ERd
1
ADDS
ADDS #1/2/4, ERd
1
ADDX
ADDX #xx:8, Rd
1
ADDX Rs, Rd
1
AND.B #xx:8, Rd
1
AND.B Rs, Rd
1
AND.W #xx:16, Rd
2
AND.W Rs, Rd
1
AND.L #xx:32, ERd
3
AND.L ERs, ERd
2
ANDC #xx:8, CCR
1
AND
ANDC
BAND
Bcc
Stack
Branch
Addr. Read Operation
K
J
Byte Data
Access
L
BAND #xx:3, Rd
1
BAND #xx:3, @ERd
2
1
BAND #xx:3, @aa:8
2
1
BRA d:8 (BT d:8)
2
BRN d:8 (BF d:8)
2
BHI d:8
2
BLS d:8
2
BCC d:8 (BHS d:8)
2
BCS d:8 (BLO d:8)
2
BNE d:8
2
BEQ d:8
2
BVC d:8
2
BVS d:8
2
BPL d:8
2
BMI d:8
2
BGE d:8
2
Word Data
Access
M
Internal
Operation
N
Rev. 4.00 Mar. 15, 2006 Page 507 of 556
REJ09B0026-0400
Appendix
Instruction
Branch
Instruction Mnemonic
Fetch
I
Addr. Read Operation
J
K
Bcc
BLT d:8
2
BGT d:8
2
BLE d:8
2
BRA d:16(BT d:16)
2
2
BRN d:16(BF d:16)
2
2
BHI d:16
2
2
BLS d:16
2
2
BCC d:16(BHS d:16)
2
2
BCS d:16(BLO d:16)
2
2
BNE d:16
2
2
BEQ d:16
2
2
BVC d:16
2
2
BVS d:16
2
2
BPL d:16
2
2
BMI d:16
2
2
BGE d:16
2
2
BLT d:16
2
2
BGT d:16
2
2
BLE d:16
2
2
BCLR #xx:3, Rd
1
BCLR #xx:3, @ERd
2
2
BCLR #xx:3, @aa:8
2
2
BCLR Rn, Rd
1
BCLR Rn, @ERd
2
2
BCLR Rn, @aa:8
2
2
BIAND #xx:3, Rd
1
BIAND #xx:3, @ERd
2
1
BIAND #xx:3, @aa:8
2
1
BILD #xx:3, Rd
1
BILD #xx:3, @ERd
2
1
BILD #xx:3, @aa:8
2
1
BCLR
BIAND
BILD
Rev. 4.00 Mar. 15, 2006 Page 508 of 556
REJ09B0026-0400
Stack
Byte Data
Word Data
Internal
Access
L
Access
M
Operation
N
Appendix
Instruction
Branch
Instruction Mnemonic
Fetch
I
Addr. Read Operation
J
K
BIOR
BIOR #xx:8, Rd
1
BIOR #xx:8, @ERd
2
1
BIOR #xx:8, @aa:8
2
1
BIST #xx:3, Rd
1
BIST #xx:3, @ERd
2
2
2
BIST
BIXOR
BLD
BNOT
BOR
BSET
BSR
BST
Stack
Byte Data
Word Data
Internal
Access
L
Access
M
Operation
N
BIST #xx:3, @aa:8
2
BIXOR #xx:3, Rd
1
BIXOR #xx:3, @ERd
2
1
1
BIXOR #xx:3, @aa:8
2
BLD #xx:3, Rd
1
BLD #xx:3, @ERd
2
1
BLD #xx:3, @aa:8
2
1
BNOT #xx:3, Rd
1
BNOT #xx:3, @ERd
2
2
BNOT #xx:3, @aa:8
2
2
BNOT Rn, Rd
1
BNOT Rn, @ERd
2
2
BNOT Rn, @aa:8
2
2
BOR #xx:3, Rd
1
BOR #xx:3, @ERd
2
1
BOR #xx:3, @aa:8
2
1
BSET #xx:3, Rd
1
BSET #xx:3, @ERd
2
2
BSET #xx:3, @aa:8
2
2
BSET Rn, Rd
1
BSET Rn, @ERd
2
2
BSET Rn, @aa:8
2
2
BSR d:8
2
1
BSR d:16
2
1
BST #xx:3, Rd
1
BST #xx:3, @ERd
2
2
BST #xx:3, @aa:8
2
2
2
Rev. 4.00 Mar. 15, 2006 Page 509 of 556
REJ09B0026-0400
Appendix
Instruction
Branch
Instruction Mnemonic
Fetch
I
Addr. Read Operation
J
K
BTST
BTST #xx:3, Rd
1
BTST #xx:3, @ERd
2
1
BTST #xx:3, @aa:8
2
1
BTST Rn, Rd
1
BTST Rn, @ERd
2
1
BTST Rn, @aa:8
2
1
BXOR #xx:3, Rd
1
BXOR #xx:3, @ERd
2
1
BXOR #xx:3, @aa:8
2
1
CMP.B #xx:8, Rd
1
CMP.B Rs, Rd
1
CMP.W #xx:16, Rd
2
CMP.W Rs, Rd
1
CMP.L #xx:32, ERd
3
CMP.L ERs, ERd
1
DAA
DAA Rd
1
DAS
DAS Rd
1
BXOR
CMP
DEC
Stack
Byte Data
Word Data
Internal
Access
L
Access
M
Operation
N
DEC.B Rd
1
DEC.W #1/2, Rd
1
DEC.L #1/2, ERd
1
DIVXS.B Rs, Rd
2
12
DIVXS.W Rs, ERd
2
20
DIVXU
DIVXU.B Rs, Rd
1
12
DIVXU.W Rs, ERd
1
EEPMOV
EEPMOV.B
2
2n+2*1
EEPMOV.W
2
2n+2*1
EXTS.W Rd
1
EXTS.L ERd
1
EXTU.W Rd
1
EXTU.L ERd
1
DUVXS
EXTS
EXTU
Rev. 4.00 Mar. 15, 2006 Page 510 of 556
REJ09B0026-0400
20
Appendix
Instruction
Branch
Instruction Mnemonic
Fetch
I
Addr. Read Operation
J
K
INC
INC.B Rd
1
INC.W #1/2, Rd
1
INC.L #1/2, ERd
1
JMP @ERn
2
JMP @aa:24
2
JMP
JSR
LDC
MOV
Stack
Byte Data
Word Data
Internal
Access
L
Access
M
Operation
N
2
JMP @@aa:8
2
JSR @ERn
2
1
JSR @aa:24
2
1
1
1
2
2
JSR @@aa:8
2
LDC #xx:8, CCR
1
1
LDC Rs, CCR
1
LDC@ERs, CCR
2
1
LDC@(d:16, ERs), CCR
3
1
LDC@(d:24,ERs), CCR
5
1
LDC@ERs+, CCR
2
1
LDC@aa:16, CCR
3
1
1
LDC@aa:24, CCR
4
MOV.B #xx:8, Rd
1
MOV.B Rs, Rd
1
MOV.B @ERs, Rd
1
1
MOV.B @(d:16, ERs), Rd
2
1
MOV.B @(d:24, ERs), Rd
4
1
MOV.B @ERs+, Rd
1
1
MOV.B @aa:8, Rd
1
1
MOV.B @aa:16, Rd
2
1
MOV.B @aa:24, Rd
3
1
MOV.B Rs, @Erd
1
1
MOV.B Rs, @(d:16, ERd)
2
1
MOV.B Rs, @(d:24, ERd)
4
1
MOV.B Rs, @-ERd
1
1
MOV.B Rs, @aa:8
1
1
2
2
2
Rev. 4.00 Mar. 15, 2006 Page 511 of 556
REJ09B0026-0400
Appendix
Instruction
Branch
Instruction Mnemonic
Fetch
I
Addr. Read Operation
J
K
MOV
MOV.B Rs, @aa:16
2
1
MOV.B Rs, @aa:24
3
1
MOV.W #xx:16, Rd
2
MOV.W Rs, Rd
1
MOV.W @ERs, Rd
1
1
MOV.W @(d:16,ERs), Rd
2
1
MOV.W @(d:24,ERs), Rd
4
1
MOV.W @ERs+, Rd
1
1
MOV.W @aa:16, Rd
2
1
MOV.W @aa:24, Rd
3
1
MOV.W Rs, @ERd
1
1
MOV.W Rs, @(d:16,ERd)
2
1
MOV.W Rs, @(d:24,ERd)
4
1
MOV.W Rs, @-ERd
1
1
MOV.W Rs, @aa:16
2
1
MOV.W Rs, @aa:24
3
1
MOV.L #xx:32, ERd
3
MOV.L ERs, ERd
1
MOV.L @ERs, ERd
2
2
MOV.L @(d:16,ERs), ERd
3
2
MOV.L @(d:24,ERs), ERd
5
2
MOV.L @ERs+, ERd
2
2
MOV.L @aa:16, ERd
3
2
MOV.L @aa:24, ERd
4
2
MOV.L ERs,@ERd
2
2
MOV.L ERs, @(d:16,ERd)
3
2
MOV.L ERs, @(d:24,ERd)
5
2
MOV.L ERs, @-ERd
2
2
MOV.L ERs, @aa:16
3
2
MOV
Stack
Byte Data
Word Data
Internal
Access
L
Access
M
Operation
N
MOV.L ERs, @aa:24
4
MOVFPE
MOVFPE @aa:16, Rd*2
2
1
MOVTPE
MOVTPE Rs,@aa:16*2
2
1
Rev. 4.00 Mar. 15, 2006 Page 512 of 556
REJ09B0026-0400
2
2
2
2
2
Appendix
Instruction
Branch
Instruction Mnemonic
Fetch
I
Addr. Read Operation
J
K
MULXS
MULXS.B Rs, Rd
2
12
MULXS.W Rs, ERd
2
20
MULXU.B Rs, Rd
1
12
MULXU.W Rs, ERd
1
20
NEG.B Rd
1
NEG.W Rd
1
NEG.L ERd
1
NOP
1
MULXU
NEG
NOP
NOT
OR
NOT.B Rd
1
NOT.W Rd
1
NOT.L ERd
1
OR.B #xx:8, Rd
1
OR.B Rs, Rd
1
OR.W #xx:16, Rd
2
OR.W Rs, Rd
1
OR.L #xx:32, ERd
3
OR.L ERs, ERd
2
Stack
Byte Data
Word Data
Internal
Access
L
Access
M
Operation
N
ORC
ORC #xx:8, CCR
1
POP
POP.W Rn
1
1
2
POP.L ERn
2
2
2
PUSH
ROTL
ROTR
ROTXL
PUSH.W Rn
1
1
2
PUSH.L ERn
2
2
2
ROTL.B Rd
1
ROTL.W Rd
1
ROTL.L ERd
1
ROTR.B Rd
1
ROTR.W Rd
1
ROTR.L ERd
1
ROTXL.B Rd
1
ROTXL.W Rd
1
ROTXL.L ERd
1
Rev. 4.00 Mar. 15, 2006 Page 513 of 556
REJ09B0026-0400
Appendix
Instruction
Branch
Instruction Mnemonic
Fetch
I
Addr. Read Operation
J
K
Stack
ROTXR
ROTXR.B Rd
1
ROTXR.W Rd
1
Byte Data
Word Data
Internal
Access
L
Access
M
Operation
N
ROTXR.L ERd
1
RTE
RTE
2
2
2
RTS
RTS
2
1
2
SHAL
SHAR
SHLL
SHLR
SHAL.B Rd
1
SHAL.W Rd
1
SHAL.L ERd
1
SHAR.B Rd
1
SHAR.W Rd
1
SHAR.L ERd
1
SHLL.B Rd
1
SHLL.W Rd
1
SHLL.L ERd
1
SHLR.B Rd
1
SHLR.W Rd
1
SHLR.L ERd
1
SLEEP
SLEEP
1
STC
STC CCR, Rd
1
STC CCR, @ERd
2
1
STC CCR, @(d:16,ERd)
3
1
STC CCR, @(d:24,ERd)
5
1
STC CCR,@-ERd
2
1
STC CCR, @aa:16
3
1
STC CCR, @aa:24
4
1
SUB.B Rs, Rd
1
SUB.W #xx:16, Rd
2
SUB.W Rs, Rd
1
SUB.L #xx:32, ERd
3
SUB.L ERs, ERd
1
SUBS #1/2/4, ERd
1
SUB
SUBS
Rev. 4.00 Mar. 15, 2006 Page 514 of 556
REJ09B0026-0400
2
Appendix
Instruction
Branch
Instruction Mnemonic
Fetch
I
Addr. Read Operation
J
K
SUBX
SUBX #xx:8, Rd
1
SUBX. Rs, Rd
1
TRAPA
TRAPA #xx:2
2
XOR
XOR.B #xx:8, Rd
1
XOR.B Rs, Rd
1
XOR.W #xx:16, Rd
2
XOR.W Rs, Rd
1
XOR.L #xx:32, ERd
3
XOR.L ERs, ERd
2
XORC #xx:8, CCR
1
XORC
1
Stack
2
Byte Data
Word Data
Internal
Access
L
Access
M
Operation
N
4
Notes: 1. n: Specified value in R4L and R4. The source and destination operands are accessed
n+1 times respectively.
2. Cannot be used in this LSI.
Rev. 4.00 Mar. 15, 2006 Page 515 of 556
REJ09B0026-0400
Appendix
A.4
Combinations of Instructions and Addressing Modes
Table A.5
Combinations of Instructions and Addressing Modes
@@aa:8
—
—
—
—
—
—
—
WL
—
BWL BWL
—
@(d:16.PC)
—
—
—
@aa:24
—
—
—
B
@aa:16
—
—
—
@aa:8
@ERn+/@ERn
@(d:24.ERn)
@ERn
BWL BWL BWL BWL BWL BWL
—
—
—
—
—
—
—
—
—
—
—
—
@(d:8.PC)
Data
MOV
transfer
POP, PUSH
instructions
MOVFPE,
Rn
Instructions
#xx
Functions
@(d:16.ERn)
Addressing Mode
MOVTPE
Arithmetic
operations
ADD, CMP
SUB
ADDX, SUBX
BWL BWL
WL BWL
B
B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADDS, SUBS
INC, DEC
—
—
L
BWL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DAA, DAS
—
B
—
—
—
—
—
—
—
—
—
—
MULXU,
—
BW
—
—
—
—
—
—
—
—
—
—
—
—
—
BWL
WL
BWL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
NOT
Shift operations
Bit manipulations
—
—
—
BWL
BWL
B
—
—
B
—
—
—
—
—
—
—
—
—
—
—
B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Branching
BCC, BSR
instructions JMP, JSR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B
—
B
—
—
—
—
B
B
—
—
—
—
—
W
W
—
—
—
—
—
W
W
—
—
—
—
—
W
W
—
—
—
—
—
W
W
—
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
—
—
W
W
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BW
—
—
—
MULXS,
DIVXU,
DIVXS
Logical
operations
NEG
EXTU, EXTS
AND, OR, XOR
RTS
System
TRAPA
control
RTE
instructions
SLEEP
LDC
STC
ANDC, ORC,
XORC
NOP
Block data transfer instructions
Rev. 4.00 Mar. 15, 2006 Page 516 of 556
REJ09B0026-0400
—
—
—
—
—
—
—
—
—
Appendix
Appendix B I/O Port Block Diagrams
B.1
I/O Port Block Diagrams
RES goes low in a reset, and SBY goes low at reset and in standby mode.
Internal data bus
RES
SBY
PUCR
Pull-up MOS
PMR
PDR
PCR
IRQ
TRGV
[Legend]
PUCR: Port pull-up control register
PMR: Port mode register
PDR: Port data register
PCR: Port control register
Figure B.1 Port 1 Block Diagram (P17)
Rev. 4.00 Mar. 15, 2006 Page 517 of 556
REJ09B0026-0400
Appendix
Internal data bus
RES
SBY
PUCR
Pull-up MOS
PMR
PDR
PCR
IRQ
[Legend]
PUCR: Port pull-up control register
PMR: Port mode register
PDR: Port data register
PCR: Port control register
Figure B.2 Port 1 Block Diagram (P14, P16)
Rev. 4.00 Mar. 15, 2006 Page 518 of 556
REJ09B0026-0400
Appendix
Internal data bus
RES
SBY
PUCR
Pull-up MOS
PMR
PDR
PCR
IRQ
TMIB1
[Legend]
PUCR : Port pull-up control register
PMR : Port mode register
PDR : Port data register
PCR : Port control register
Figure B.3 Port 1 Block Diagram (P15)
Rev. 4.00 Mar. 15, 2006 Page 519 of 556
REJ09B0026-0400
Appendix
Internal data bus
RES
SBY
PUCR
Pull-up MOS
PDR
PCR
[Legend]
PUCR : Port pull-up control register
PDR : Port data register
PCR : Port control register
Figure B.4 Port 1 Block Diagram (P12, P11, P10)
Rev. 4.00 Mar. 15, 2006 Page 520 of 556
REJ09B0026-0400
Appendix
Internal data bus
SBY
PMR
PDR
PCR
[Legend]
PMR : Port mode register
PDR : Port data register
PCR : Port control register
Figure B.5 Port 2 Block Diagram (P24, P23)
Rev. 4.00 Mar. 15, 2006 Page 521 of 556
REJ09B0026-0400
Appendix
Internal data bus
SBY
PMR
PDR
PCR
SCI3
TxD
[Legend]
PMR : Port mode register
PDR : Port data register
PCR : Port control register
Figure B.6 Port 2 Block Diagram (P22)
Rev. 4.00 Mar. 15, 2006 Page 522 of 556
REJ09B0026-0400
Appendix
SBY
Internal data bus
PDR
PCR
SCI3
RE
RxD
[Legend]
PDR: Port data register
PCR: Port control register
Figure B.7 Port 2 Block Diagram (P21)
Rev. 4.00 Mar. 15, 2006 Page 523 of 556
REJ09B0026-0400
Appendix
SBY
SCI3
SCKIE
SCKOE
Internal data bus
PDR
PCR
SCKO
SCKI
[Legend]
PDR: Port data register
PCR: Port control register
Figure B.8 Port 2 Block Diagram (P20)
Rev. 4.00 Mar. 15, 2006 Page 524 of 556
REJ09B0026-0400
Appendix
Internal data bus
SBY
PMR
PDR
PCR
[Legend]
PMR : Port mode register
PDR : Port data register
PCR : Port control register
Figure B.9 Port 5 Block Diagram (P57, P56)
Rev. 4.00 Mar. 15, 2006 Page 525 of 556
REJ09B0026-0400
Appendix
Internal data bus
RES
SBY
PUCR
Pull-up MOS
PMR
PDR
PCR
WKP
ADTRG
[Legend]
PUCR: Port pull-up control register
PMR: Port mode register
PDR: Port data register
PCR: Port control register
Figure B.10 Port 5 Block Diagram (P55)
Rev. 4.00 Mar. 15, 2006 Page 526 of 556
REJ09B0026-0400
Appendix
Internal data bus
RES
SBY
PUCR
Pull-up MOS
PMR
PDR
PCR
WKP
[Legend]
PUCR: Port pull-up control register
PMR: Port mode register
PDR: Port data register
PCR: Port control register
Figure B.11 Port 5 Block Diagram (P54 to P55)
Rev. 4.00 Mar. 15, 2006 Page 527 of 556
REJ09B0026-0400
Appendix
Internal data bus
SBY
Timer Z
Output control
signals A to D
PDR
PCR
FTIOA to
FTIOD
[Legend]
PDR : Port data register
PCR : Port control register
Figure B.12 Port 6 Block Diagram (P67 to P60)
Rev. 4.00 Mar. 15, 2006 Page 528 of 556
REJ09B0026-0400
Appendix
Internal data bus
SBY
Timer V
OS3
OS2
OS1
OS0
PDR
PCR
TMOV
[Legend]
PDR: Port data register
PCR: Port control register
Figure B.13 Port 7 Block Diagram (P76)
Rev. 4.00 Mar. 15, 2006 Page 529 of 556
REJ09B0026-0400
Appendix
Internal data bus
SBY
PDR
PCR
Timer V
TMCIV
[Legend]
PDR: Port data register
PCR: Port control register
Figure B.14 Port 7 Block Diagram (P75)
Rev. 4.00 Mar. 15, 2006 Page 530 of 556
REJ09B0026-0400
Appendix
Internal data bus
SBY
PDR
PCR
Timer V
TMRIV
[Legend]
PDR: Port data register
PCR: Port control register
Figure B.15 Port 7 Block Diagram (P74)
Rev. 4.00 Mar. 15, 2006 Page 531 of 556
REJ09B0026-0400
Appendix
Internal data bus
SBY
PMR
PDR
PCR
SCI3_2*
TxD
[Legend]
PMR : Port mode register
PDR : Port data register
PCR : Port control register
Note: The H8/36037 Group does not have the SCI3_2.
Figure B.16 Port 7 Block Diagram (P72)
Rev. 4.00 Mar. 15, 2006 Page 532 of 556
REJ09B0026-0400
Appendix
SBY
Internal data bus
PDR
PCR
SCI3_2*
RE
RxD
[Legend]
PDR : Port data register
PCR : Port control register
Note: The H8/36037 Group does not have the SCI3_2.
Figure B.17 Port 7 Block Diagram (P71)
Rev. 4.00 Mar. 15, 2006 Page 533 of 556
REJ09B0026-0400
Appendix
SBY
SCI3_2*
SCKIE
SCKOE
Internal data bus
PDR
PCR
SCKO
SCKI
[Legend]
PDR : Port data register
PCR : Port control register
Note: The H8/36037 Group does not have the SCI3_2.
Figure B.18 Port 7 Block Diagram (P70)
Rev. 4.00 Mar. 15, 2006 Page 534 of 556
REJ09B0026-0400
Appendix
Internal data bus
SBY
PDR
PCR
[Legend]
PDR: Port data register
PCR: Port control register
Figure B.19 Port 8 Block Diagram (P87 to P85)
Rev. 4.00 Mar. 15, 2006 Page 535 of 556
REJ09B0026-0400
Appendix
SBY
TinyCAN
HTXD output
control
Internal data bus
PDR
PCR
HTXD
[Legend]
PDR : Port data register
PCR : Port control register
Figure B.20 Port 9 Block Diagram (P97)
Rev. 4.00 Mar. 15, 2006 Page 536 of 556
REJ09B0026-0400
Appendix
RST SBY
TinyCAN
HRXD input
control
Internal data bus
PDR
PCR
HRXD
HWKPU
[Legend]
PDR : Port data register
PCR : Port control register
Figure B.21 Port 9 Block Diagram (P96)
Rev. 4.00 Mar. 15, 2006 Page 537 of 556
REJ09B0026-0400
Appendix
Internal data bus
SBY
PDR
PCR
[Legend]
PMR : Port mode register
PCR : Port control register
Figure B.22 Port 9 Block Diagram (P94, P95)
Rev. 4.00 Mar. 15, 2006 Page 538 of 556
REJ09B0026-0400
Appendix
SBY
SSU
SSI output control
SSI input control
SSINMOS opendrain output control Internal data bus
PDR
PCR
SSI output
SSI input
[Legend]
PDR : Port data register
PCR : Port control register
Figure B.23 Port 9 Block Diagram (P93)
Rev. 4.00 Mar. 15, 2006 Page 539 of 556
REJ09B0026-0400
Appendix
SBY
SSU
SSO output control
SSO input control
SSONMOS opendrain output control Internal data bus
PDR
PCR
SSO output
SSO input
[Legend]
PDR : Port data register
PCR : Port control register
Figure B.24 Port 9 Block Diagram (P92)
Rev. 4.00 Mar. 15, 2006 Page 540 of 556
REJ09B0026-0400
Appendix
SBY
SSU
SSCK output control
SSCK input control
SSCKNMOS opendrain output control Internal data bus
PDR
PCR
SSCK output
SSCK input
[Legend]
PDR : Port data register
PCR : Port control register
Figure B.25 Port 9 Block Diagram (P91)
Rev. 4.00 Mar. 15, 2006 Page 541 of 556
REJ09B0026-0400
Appendix
SBY
SSU
SCS output control
SCS input control
SCSNMOS opendrain output control Internal data bus
PDR
PCR
SCS output
SCS input
[Legend]
PDR : Port data register
PCR : Port control register
Figure B.26 Port 9 Block Diagram (P90)
Rev. 4.00 Mar. 15, 2006 Page 542 of 556
REJ09B0026-0400
Appendix
Internal data bus
A/D converter
CH3 to CH0
DEC
VIN
Figure B.27 Port B Block Diagram (PB7 to PB0)
Rev. 4.00 Mar. 15, 2006 Page 543 of 556
REJ09B0026-0400
Appendix
B.2
Port States in Each Operating State
Port
Reset
Sleep
Subsleep
Standby
P17 to P14,
P12 to P10
High
impedance
Retained
Retained
High
Functioning
impedance*
Functioning
P24 to P20
High
impedance
Retained
Retained
High
impedance
Functioning
Functioning
P57 to P50
High
impedance
Retained
Retained
High
Functioning
impedance*
Functioning
P67 to P60
High
impedance
Retained
Retained
High
impedance
Functioning
Functioning
P76 to P74,
P72 to P70
High
impedance
Retained
Retained
High
impedance
Functioning
Functioning
P87 to P85
High
impedance
Retained
Retained
High
impedance
Functioning
Functioning
P97 to P90
High
impedance
Retained
Retained
High
impedance
Functioning
Functioning
PB7 to PB0
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
Note:
*
High level output when the pull-up MOS is in on state.
Rev. 4.00 Mar. 15, 2006 Page 544 of 556
REJ09B0026-0400
Subactive
Active
Appendix
Appendix C Product Code Lineup
Package Code
Product Classification
H8/36057
Flash memory
version
Masked ROM
version
H8/36054
Flash memory
version
Masked ROM
version
H8/36037
Flash memory
version
Masked ROM
version
H8/36036
H8/36035
Masked ROM
version
Masked ROM
version
QFP-64 (FP-64A)
LQFP-64 (FP-64K)
Standard
product
HD64F36057H
HD64F36057FZ
Product with
POR & LVDC
HD64F36057GH
HD64F36057GFZ
Standard
product
HD64336057(***)H
HD64336057(***)FZ
Product with
POR & LVDC
HD64336057G(***)H
HD64336057G(***)FZ
Standard
product
HD64F36054H
HD64F36054FZ
Product with
POR & LVDC
HD64F36054GH
HD64F36054GFZ
Standard
product
HD64336054(***)H
HD64336054(***)FZ
Product with
POR & LVDC
HD64336054G(***)H
HD64336054G(***)FZ
Standard
product
HD64F36037H
HD64F36037FZ
Product with
POR & LVDC
HD64F36037GH
HD64F36037GFZ
Standard
product
HD64336037(***)H
HD64336037(***)FZ
Product with
POR & LVDC
HD64336037G(***)H
HD64336037G(***)FZ
Standard
product
HD64336036(***)H
HD64336036(***)FZ
Product with
POR & LVDC
HD64336036G(***)H
HD64336036G(***)FZ
Standard
product
HD64336035(***)H
HD64336035(***)FZ
Product with
POR & LVDC
HD64336035G(***)H
HD64336035G(***)FZ
Rev. 4.00 Mar. 15, 2006 Page 545 of 556
REJ09B0026-0400
Appendix
Package Code
Product Classification
H8/36034
Flash memory
version
Masked ROM
version
H8/36033
H8/36032
Masked ROM
version
Masked ROM
version
QFP-64 (FP-64A)
LQFP-64 (FP-64K)
Standard
product
HD64F36034H
HD64F36034FZ
Product with
POR & LVDC
HD64F36034GH
HD64F36034GFZ
Standard
product
HD64336034(***)H
HD64336034(***)FZ
Product with
POR & LVDC
HD64336034G(***)H
HD64336034G(***)FZ
Standard
product
HD64336033(***)H
HD64336033(***)FZ
Product with
POR & LVDC
HD64336033G(***)H
HD64336033G(***)FZ
Standard
product
HD64336032(***)H
HD64336032(***)FZ
Product with
POR & LVDC
HD64336032G(***)H
HD64336032G(***)FZ
[Legend]
(***): ROM code
POR & LVDC: Power-on reset and low-voltage detection circuits
Rev. 4.00 Mar. 15, 2006 Page 546 of 556
REJ09B0026-0400
Appendix
Appendix D Package Dimensions
The package dimensions that are shown in the Renesas Semiconductor Packages Data Book have
priority.
Unit: mm
12.0 ± 0.2
10
48
33
32
0.5
12.0 ± 0.2
49
64
17
0.08
*Dimension including the plating thickness
Base material dimension
*0.145 ± 0.05
0.125 ± 0.04
1.25
1.40
0.08 M
1.70 Max
16
0.10 ± 0.10
1
*0.20 ± 0.05
0.18 ± 0.04
1.0
0° − 8°
0.5 ± 0.2
Package Code
JEDEC
EIAJ
Mass (reference value)
FP-64K
−
Conforms
0.3 g
Figure D.1 FP-64K Package Dimensions
Rev. 4.00 Mar. 15, 2006 Page 547 of 556
REJ09B0026-0400
Appendix
Unit: mm
17.2 ± 0.3
14
33
48
32
0.8
17.2 ± 0.3
49
64
17
1
0.10
*Dimension including the plating thickness
Base material dimension
*0.17 ± 0.05
0.15 ± 0.04
3.05 Max
1.0
2.70
0.15 M
0.10 +0.15
- 0.10
*0.37 ± 0.08
0.35 ± 0.06
16
REJ09B0026-0400
0° − 8°
0.8 ± 0.3
Package Code
JEDEC
EIAJ
Mass (reference value)
Figure D.2 FP-64A Package Dimensions
Rev. 4.00 Mar. 15, 2006 Page 548 of 556
1.6
FP-64A
−
Conforms
1.2 g
Main Revisions and Additions in this Edition
Item
Page Revision (See Manual for Details)
Preface
vii
Added
When using an on-chip emulator (E7, E8) for H8/36057
and H8/36037 program development and debugging,
the following restrictions must be noted.
Notes
1. The NMI pin is reserved for the E7 or E8, and cannot
be used.
2. Pins P85, P86, and P87 cannot be used. In order to
use these pins, additional hardware must be
provided on the user board.
3. Area H'D000 to H'DFFF is used by the E7 or E8, and
is not available to the user.
4. Area H'F780 to H'FB7F must on no account be
accessed.
5. When the E7 or E8 is used, address breaks can be
set as either available to the user or for use by the
E7 or E8. If address breaks are set as being used by
the E7 or E8, the address break control registers
must not be accessed.
6. When the E7 or E8 is used, NMI is an input/output
pin (open-drain in output mode), P85 and P87 are
input pins, and P86 is an output pin.
Section 8 RAM
109
Added
Note: * When the E7 or E8 is used, area H'F780 to
H'FB7F must not be accessed.
12.3.2 Timer Mode Register
(TMDR)
171
Amended
Bit Bit Name
Description
0
Timer Synchronization
SYNC
0: TCNT_1 and TCNT_0 operate
as a different timer
1: TCNT_1 and TCNT_0 are
synchronized
TCNT_1 and TCNT_0 can be
pre-set or cleared synchronously
Rev. 4.00 Mar. 15, 2006 Page 549 of 556
REJ09B0026-0400
Item
Page Revision (See Manual for Details)
12.3.7 Timer Counter (TCNT)
177
Added
….The TCNT counters cannot be accessed in 8-bit
units; they must always be accessed as a 16-bit unit.
TCNT is initialized to H'0000.
Figure 12.17 Example of Input
Capture Operation
196
Amended
Counter cleared by FTIOB input (falling edge)
Time
12.4.4 Synchronous Operation
199
Added
Figure 12.20 shows an example of synchronous
operation. In this example, …. set for the channel 1
counter clearing source. In addition, the same input
clock has been set as the counter input clock for
channel 0 and channel 1. Two-phase PWM waveforms
are….
Figure 12.44 Example of Output
Disable Timing of Timer Z by
Writing to TOER
229
Amended
T1
T2
φ
Address bus
TOER address
TOER
Timer Z
output pin
Timer output
Timer Z output
Rev. 4.00 Mar. 15, 2006 Page 550 of 556
REJ09B0026-0400
I/O port
I/O port
Item
Page Revision (See Manual for Details)
Figure 12.45 Example of Output
Disable Timing of Timer Z by
External Trigger
230
Amended
φ
WKP4
TOER
N
Timer Z
output pin
13.2.1 Timer Control/Status
Register WD (TCSRWD)
246
H'FF
Timer Z output
I/O port
Amended
Bit
Bit Name
Description
4
TCSRWE
Timer Control/Status Register WD
Write Enable
The WDON and WRST bits can
be written when the TCSRWE bit
is set to 1.
When writing data to this bit, the
value for bit 5 must be 0.
16.5 Usage Note
378
18.3.1 A/D Data Registers A to D
(ADDRA to ADDRD)
394
Figure 19.1 Block Diagram of
404
Power-On Reset Circuit and LowVoltage Detection Circuit
Added
Amended
…. The temporary register contents are transferred
from the ADDR when the upper byte data is read.
Therefore, byte access to ADDR should be done by
reading the upper byte first then the lower one. Word
access is also possible. ADDR is initialized to H'0000.
Amended
RES
CRES
Rev. 4.00 Mar. 15, 2006 Page 551 of 556
REJ09B0026-0400
Item
Page Revision (See Manual for Details)
Table 22.2 DC Characteristics (1) 449
Amended
Table 22.12 DC Characteristics
(1)
Note: 3. Pin states during current consumption
measurement are given below (excluding
current in the pull-up MOS transistors and
output buffers).
Mode
RES Pin Internal State
Active mode 1
VCC
Operates
Active mode 2
Only timers operate
VCC
Sleep mode 2
Figure 22.8 SSU Input/Output
Timing (Four-Line Bus
Communication Mode, Master,
CPHS = 1)
to
Figure 22.11 SSU Input/Output
Timing (Four-Line Bus
Communication Mode, Slave,
CPHS = 0)
481
to
484
tOH deleted
Table A.1 Instruction Set
491
Amended
Only timers operate(φOSC/64)
Rev. 4.00 Mar. 15, 2006 Page 552 of 556
REJ09B0026-0400
H
N
Z
V
C
B — *
*
↔
DAA Rd
Condition Code
↔
DAA
No. of
States*1
↔
Mnemonic
Operand Size
2. Arithmetic Instructions
I
Advanced
Sleep mode 1
Operates (φOSC/64)
Normal
468
2
Index
A
A/D converter ......................................... 391
Sample-and-hold circuit...................... 398
Scan mode........................................... 397
Single mode ........................................ 397
Address break ........................................... 67
Addressing modes..................................... 32
Absolute address................................... 33
Immediate ............................................. 34
Memory indirect ................................... 34
Program-counter relative ...................... 34
Register direct....................................... 32
Register indirect.................................... 33
Register indirect with displacement...... 33
Register indirect with post-increment... 33
Register indirect with pre-decrement.... 33
C
Clock pulse generators.............................. 73
Prescaler S ............................................ 76
System clock generator......................... 74
Condition field.......................................... 31
Condition-code register (CCR)................. 16
Controller area network (TinyCAN)....... 295
Mailbox............................................... 340
Message reception .............................. 336
Message transmission ......................... 327
Time Quanta ....................................... 326
TinyCAN standby transition............... 342
CPU ............................................................ 9
Reset exception handling ...................... 59
Stack status ........................................... 63
Trap instruction..................................... 49
G
General registers ....................................... 15
I
I/O ports .................................................. 111
Instruction set............................................ 21
Arithmetic operations instructions ........ 23
Bit manipulation instructions ................ 26
Block data transfer instructions............. 30
Branch instructions ............................... 28
Data transfer instructions ...................... 22
Logic operations instructions ................ 25
Shift instructions ................................... 25
System control instructions................... 29
Internal power supply Step-down
circuit ...................................................... 413
Interrupt
Internal interrupts.................................. 61
Interrupt response time.......................... 63
IRQ3 to IRQ0 interrupts ....................... 60
NMI interrupt ........................................ 60
WKP5 to WKP0 interrupts ................... 60
Interrupt mask bit...................................... 17
L
E
Effective address....................................... 36
Effective address extension ...................... 31
Exception handling ................................... 49
Large current ports...................................... 2
Low-voltage detection circuit ................. 403
LVDI (interrupt by low voltage detect)
circuit ...................................................... 410
Rev. 4.00 Mar. 15, 2006 Page 553 of 556
REJ09B0026-0400
LVDR (reset by low voltage detect)
circuit...................................................... 409
M
Memory map ............................................ 10
Module standby function .......................... 87
O
On-board Programming modes................. 95
Operation field.......................................... 31
P
Package....................................................... 2
Pin arrangement.......................................... 4
Power-down modes .................................. 77
Sleep mode ........................................... 84
Standby mode ....................................... 84
Subactive mode .................................... 85
Subsleep mode...................................... 85
Power-on reset ........................................ 403
Power-on reset circuit............................. 408
Program counter (PC)............................... 16
R
Register
ABACK .......................309, 416, 425, 433
ABRKCR.......................68, 422, 430, 438
ABRKSR .......................70, 422, 430, 438
ADCR..........................396, 422, 430, 438
ADCSR........................395, 422, 430, 438
ADDRA.......................394, 422, 430, 438
ADDRB .......................394, 422, 430, 438
ADDRC .......................394, 422, 430, 438
ADDRD.......................394, 422, 430, 438
BARH............................70, 422, 430, 438
Rev. 4.00 Mar. 15, 2006 Page 554 of 556
REJ09B0026-0400
BARL............................ 70, 422, 430, 438
BCR0 .......................... 304, 416, 425, 433
BCR1 .......................... 304, 416, 425, 433
BDRH ........................... 70, 422, 430, 438
BDRL............................ 70, 422, 430, 438
BRR ............................ 261, 421, 430, 437
EBR1............................. 93, 421, 429, 437
FENR ............................ 94, 421, 429, 437
FLMCR1....................... 91, 421, 429, 437
FLMCR2....................... 92, 421, 429, 437
FLPWCR ...................... 94, 421, 429, 437
GRA............................ 178, 419, 428, 436
GRB ............................ 178, 419, 428, 436
GRC ............................ 178, 420, 428, 436
GRD............................ 178, 420, 428, 436
GSR............................. 302, 416, 425, 433
IEGR1 ........................... 52, 424, 431, 439
IEGR2 ........................... 53, 424, 431, 439
IENR1 ........................... 54, 424, 431, 439
IENR2 ........................... 55, 424, 431, 439
IRR1.............................. 55, 424, 431, 439
IRR2.............................. 57, 424, 431, 439
IWPR ............................ 57, 424, 431, 439
LAFM ......................... 322, 418, 427, 435
LVDCR....................... 405, 420, 429, 437
LVDSR ....................... 407, 420, 429, 437
MBCR......................... 306, 416, 425, 433
MBIMR....................... 315, 416, 425, 433
MC ...................................... 319, 416, 433
MCR ........................... 300, 416, 425, 433
MD...................................... 323, 417, 434
MSTCR1....................... 80, 424, 431, 439
MSTCR2....................... 81, 424, 431, 439
PCR1........................... 113, 423, 431, 438
PCR2........................... 117, 423, 431, 439
PCR5........................... 122, 423, 431, 439
PCR6........................... 126, 423, 431, 439
PCR7........................... 132, 423, 431, 439
PCR8........................... 135, 423, 431, 439
PCR9........................... 137, 423, 431, 439
PDR1 .......................... 113, 423, 431, 438
PDR2 .......................... 117, 423, 431, 438
PDR5 .......................... 122, 423, 431, 438
PDR6 .......................... 127, 423, 431, 438
PDR7 .......................... 132, 423, 431, 438
PDR8 .......................... 136, 423, 431, 438
PDR9 .......................... 138, 423, 431, 438
PDRB.......................... 141, 423, 431, 438
PMR1.......................... 112, 423, 431, 438
PMR3.......................... 118, 423, 431, 438
PMR5.......................... 121, 423, 431, 438
POCR.......................... 185, 419, 428, 436
PUCR1........................ 114, 423, 431, 438
PUCR5........................ 123, 423, 431, 438
RDR............................ 255, 422, 430, 438
REC ............................ 318, 416, 425, 433
RFPR .......................... 310, 416, 425, 433
ROPCR ....................... 382, 419, 428, 436
RSR..................................................... 255
RXPR.......................... 310, 416, 425, 433
SBTCTL ..................... 381, 419, 428, 436
SBTDCNT .................. 382, 419, 428, 436
SCR3........................... 257, 421, 430, 437
SMR............................ 256, 421, 430, 437
SSCRH ....................... 351, 419, 428, 435
SSCRL........................ 353, 419, 428, 435
SSER........................... 355, 419, 428, 436
SSMR ......................... 354, 419, 428, 436
SSR ............................. 259, 421, 430, 438
SSRDR ....................... 358, 419, 428, 436
SSSR........................... 356, 419, 428, 436
SSTDR........................ 358, 419, 428, 436
SYSCR1 ....................... 78, 424, 431, 439
SYSCR2 ....................... 79, 424, 431, 439
TCB1 .......................... 146, 421, 429, 437
TCIMR0 ..................... 315, 416, 425, 433
TCIMR1 ..................... 315, 416, 425, 433
TCIRR0 ...................... 312, 416, 425, 433
TCIRR1 ...................... 312, 416, 425, 433
TCMR......................... 301, 416, 425, 433
TCNT .......................... 177, 419, 429, 436
TCNTV ....................... 151, 421, 430, 437
TCORA....................... 152, 421, 430, 437
TCORB ....................... 152, 421, 430, 437
TCR............................ 179, 298, 416, 419,
.................................... 425, 428, 433, 436
TCRV0........................ 152, 421, 430, 437
TCRV1........................ 155, 421, 430, 437
TCSRV........................ 154, 421, 430, 437
TCSRWD.................... 246, 422, 430, 438
TCWD......................... 248, 422, 430, 438
TDR ............................ 255, 421, 430, 437
TEC............................. 318, 416, 425, 433
TFCR .......................... 173, 420, 429, 437
TIER............................ 184, 419, 428, 436
TIORA ........................ 180, 419, 428, 436
TIORC ........................ 181, 419, 428, 436
TMB1.......................... 145, 421, 429, 437
TMDR......................... 171, 420, 429, 437
TMWD........................ 248, 422, 430, 438
TOCR.......................... 176, 420, 429, 437
TOER .......................... 175, 420, 429, 437
TPMR.......................... 172, 420, 429, 437
TSR ............................. 182, 419, 428, 436
TSTR........................... 170, 420, 429, 436
TXACK....................... 308, 416, 425, 433
TXCR.......................... 308, 416, 425, 433
TXPR .......................... 307, 416, 425, 433
UMSR ......................... 311, 416, 425, 433
Register field............................................. 31
ROM ......................................................... 89
Boot mode............................................. 96
Boot program ........................................ 95
Erase/erase-verify ............................... 103
Erasing units ......................................... 89
Error protection................................... 105
Hardware protection............................ 105
Power-down states .............................. 106
Program/program-verify ..................... 100
Programmer mode............................... 106
Rev. 4.00 Mar. 15, 2006 Page 555 of 556
REJ09B0026-0400
Programming units ............................... 89
Programming/erasing in user program
mode ..................................................... 98
Software protection............................. 105
S
Serial communication interface 3
(SCI3) ..................................................... 251
Asynchronous mode ........................... 270
Bit rate ................................................ 261
Break .................................................. 292
Clocked synchronous mode................ 278
Framing error...................................... 274
Mark state ........................................... 292
Multiprocessor communication
function............................................... 285
Overrun error ...................................... 274
Parity error.......................................... 274
Stack pointer (SP)..................................... 16
Subsystem timer (Subtimer) ................... 379
Synchronous serial communication unit
(SSU) ...................................................... 349
Clock polarity ..................................... 359
Clocked synchronous communication
mode ................................................... 363
Communication mode......................... 362
Rev. 4.00 Mar. 15, 2006 Page 556 of 556
REJ09B0026-0400
Transfer clock ..................................... 359
T
Timer B1................................................. 143
Auto-reload timer operation................ 147
Event counter operation ...................... 147
Interval timer operation....................... 147
Timer V................................................... 149
Timer Z ................................................... 163
Buffer operation.................................. 221
Complementary PWM mode .............. 210
Input capture function ......................... 195
PWM mode ......................................... 200
Reset synchronous PWM mode .......... 206
Synchronous operation........................ 198
Waveform output by compare
match................................................... 191
V
Vector address........................................... 50
W
Watchdog timer....................................... 245
Renesas 16-Bit Single-Chip Microcomputer
Hardware Manual
H8/36057 Group, H8/36037 Group
Publication Date: Rev.1.00, Jun. 27, 2003
Rev.4.00, Mar. 15, 2006
Published by:
Sales Strategic Planning Div.
Renesas Technology Corp.
Edited by:
Customer Support Department
Global Strategic Communication Div.
Renesas Solutions Corp.
 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
RENESAS SALES OFFICES
http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2730-6071
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
Colophon 6.0
H8/36057 Group, H8/36037 Group
Hardware Manual