RENESAS HD74HC175

HD74HC175
Quad. D-type Flip-Flops (with Clear)
REJ03D0585-0300
Rev.3.00
Jan 31, 2006
Description
Information at the D inputs of the HD74HC175 is transferred to the Q and Q outputs on the positive going edge of the
clock pulse. Both true and compliment outputs from each flip-flop are externally available. All four flip-flops are
controlled by a common clock and a common clear. Clearing is accomplished by a negative pulse at the clear input.
All four Q outputs are cleared to a logic low level and all four Q outputs to a logic high level.
Features
•
•
•
•
•
•
High Speed Operation: tpd (Clock to Q) = 14 ns typ (CL = 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: VCC = 2 to 6 V
Low Input Current: 1 µA max
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
Taping Abbreviation
(Quantity)
PRDP0016AE-B
P
(DP-16FV)
PTSP0016JB-A
HD74HC175TELL
TSSOP-16 pin
T
(TTP-16DAV)
Note: Please consult the sales office for the above package availability.
HD74HC175P
DILP-16 pin
—
ELL (2,000 pcs/reel)
Function Table
H:
L:
X:
Clear
L
H
H
H
High level
Low level
Irrelevant
Inputs
Clock
X
L
Rev.3.00, Jan 31, 2006 page 1 of 6
Output
D
X
H
L
X
Q
H
L
H
Q
L
H
L
no change
HD74HC175
Pin Arrangement
16 VCC
Clear 1
1Q 2
1Q 3
Q CLR
CK
Q
D
CLR Q
CK
Q
D
15 4Q
14 4Q
1D 4
13 4D
2D 5
12 3D
2Q 6
2Q 7
D
Q
CK
CLR Q
D
CK
Q CLR
Q
11 3Q
10 3Q
9 Clock
GND 8
(Top view)
Logic Diagram
1D
Q
1Q
CK CL
1Q
D
CK
Clock
2D
Q
2Q
CK CL
2Q
D
CK
3D
Q
3Q
CK CL
3Q
D
CK
4D
Q
4Q
CK CL
4Q
D
CK
Clear
Rev.3.00, Jan 31, 2006 page 2 of 6
HD74HC175
Absolute Maximum Ratings
Item
Supply voltage range
Input / Output voltage
Input / Output diode current
Output current
VCC, GND current
Power dissipation
Storage temperature
Symbol
VCC
Vin, Vout
IIK, IOK
IO
ICC or IGND
PT
Tstg
Ratings
–0.5 to 7.0
–0.5 to VCC +0.5
±20
±25
±50
500
–65 to +150
Unit
V
V
mA
mA
mA
mW
°C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
Recommended Operating Conditions
Item
Supply voltage
Input / Output voltage
Operating temperature
Symbol
VCC
VIN, VOUT
Ta
Input rise / fall time*1
Ratings
2 to 6
0 to VCC
–40 to 85
0 to 1000
0 to 500
tr, tf
Unit
V
V
°C
ns
0 to 400
Note:
Conditions
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
1. This item guarantees maximum limit when one input switches.
Waveform: Refer to test circuit of switching characteristics.
Electrical Characteristics
Item
Input voltage
Symbol VCC (V)
VIH
VIL
Output voltage
VOH
VOL
Input current
Quiescent supply
current
Iin
ICC
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
Rev.3.00, Jan 31, 2006 page 3 of 6
Min
1.5
3.15
4.2
—
—
—
1.9
4.4
5.9
4.18
5.68
—
—
—
—
—
—
—
Ta = 25°C
Typ Max
—
—
—
—
—
—
2.0
4.5
6.0
—
—
0.0
0.0
0.0
—
—
—
—
—
—
—
0.5
1.35
1.8
—
—
—
—
—
0.1
0.1
0.1
0.26
0.26
±0.1
4.0
Ta = –40 to+85°C
Unit
Min
Max
1.5
3.15
4.2
—
—
—
1.9
4.4
5.9
4.13
5.63
—
—
—
—
—
—
—
—
—
—
0.5
1.35
1.8
—
—
—
—
—
0.1
0.1
0.1
0.33
0.33
±1.0
40
Test Conditions
V
V
V
V
Vin = VIH or VIL IOH = –20 µA
Vin = VIH or VIL
IOH = –4 mA
IOH = –5.2 mA
IOL = 20 µA
IOL = 4 mA
IOL = 5.2 mA
µA Vin = VCC or GND
µA Vin = VCC or GND, Iout = 0 µA
HD74HC175
Switching Characteristics
(CL = 50 pF, Input tr = tf = 6 ns)
Item
Maximum clock
frequency
Propagation delay
time
Symbol VCC (V)
fmax
tPLH, tPHL
Setup time
tsu
Hold time
th
Removal time
Pulse width
Output rise/fall
time
Input capacitance
trem
tw
tTLH, tTHL
Cin
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
—
Ta = 25°C
Ta = –40 to +85°C
Unit
Min
Typ Max
Min
Max
—
—
—
—
—
—
—
—
—
100
20
17
5
5
5
100
20
17
80
16
14
—
—
—
—
—
—
—
—
14
—
—
14
—
—
3
–
—
–1
—
—
–1
—
—
9
—
—
5
—
5
6
30
35
150
30
26
185
37
31
—
—
—
—
—
—
—
—
—
—
—
—
75
15
13
10
—
—
—
—
—
—
—
—
—
125
25
21
5
5
5
125
25
21
100
20
17
—
—
—
—
5
24
28
190
38
33
230
46
39
—
—
—
—
—
—
—
—
—
—
—
—
95
19
16
10
ns
Clock to Q or Q
ns
Clear to Q or Q
ns
Data to Clock
ns
Clock to Data
ns
Clear to Clock
ns
Clock, Clear
ns
pF
Test Circuit
Measurement point
CL*
Note: CL includes the probe and fig capacitance.
Rev.3.00, Jan 31, 2006 page 4 of 6
Test Conditions
MHz
HD74HC175
Waveforms
• Waveform – 1
tr
tf
Data
VCC
90 %
90 %
50 %
50 %
50 %
10 %
10 %
t su
tr
th
t su
0V
th
tf
VCC
90 %
Clock
50 %
50 %
50 %
10 %
10 %
tw
0V
tw
t PHL
t PLH
Q
VOH
90 %
50 %
10 %
90 %
50 %
10 %
t TLH
VOL
t THL
t PHL
t PLH
VOH
90 %
Q
50 %
10 %
50 %
10 %
t TLH
t THL
• Waveform – 2
Clear
VOL
tf
tr
VCC
90 %
50 %
10 %
90 %
50 %
10 %
0V
tw
tf
tr
Clock
t rem
tw
t PHL
90 %
10 %
VOL
t TLH
t PHL
t PLH
90 %
VOH
90 %
50 %
10 %
t TLH
Note : Clock Input : PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns
Data Input : PRR ≤ 500 kHz
Rev.3.00, Jan 31, 2006 page 5 of 6
VOH
50 %
t THL
Q
0V
t PLH
90 %
50 %
10 %
Q
VCC
90 %
50 %
10 %
90 %
50 %
10 %
50 %
10 %
t THL
VOL
HD74HC175
Package Dimensions
JEITA Package Code
P-DIP16-6.3x19.2-2.54
RENESAS Code
PRDP0016AE-B
MASS[Typ.]
1.05g
Previous Code
DP-16FV
D
9
E
16
1
8
b3
0.89
Z
A1
A
Reference
Symbol
L
e
Nom
θ
c
e1
D
19.2
E
6.3
JEITA Package Code
P-TSSOP16-4.4x5-0.65
RENESAS Code
PTSP0016JB-A
*1
Previous Code
TTP-16DAV
7.4
A1
0.51
b
p
0.40
b
3
0.48
0.56
1.30
c
0.19
θ
0°
e
2.29
0.25
0.31
2.54
2.79
15°
1.12
L
2.54
MASS[Typ.]
0.05g
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
D
F
16
20.32
5.06
Z
( Ni/Pd/Au plating )
Max
7.62
1
A
bp
e
Dimension in Millimeters
Min
9
*2
E
HE
c
bp
Reference
Symbol
Terminal cross section
( Ni/Pd/Au plating )
Index mark
Dimension in Millimeters
Min
Nom
Max
D
5.0
5.3
E
4.40
A2
A1
Z
e
*3
bp
L1
0.07
0.10
0.15
0.20
0.25
0.10
0.15
0.20
6.40
6.60
1.10
x
bp
M
b1
c
A
c
A1
θ
L
y
Detail F
1
θ
0°
HE
6.20
8°
0.65
e
x
0.13
y
0.10
0.65
Z
0.4
L
L
Rev.3.00, Jan 31, 2006 page 6 of 6
0.03
A
8
1
1
0.5
1.0
0.6
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