HD74HC680 12-bit Address Comparator REJ03D0641-0200 (Previous ADE-205-527) Rev.2.00 Mar 30, 2006 Description The HD74HC680 address comparator simplifies addressing of memory boards and/or other peripheral devices. The four P inputs are normally hard wired with a preprogrammed address. An internal decoder determines what input information applied to the 12 A inputs must be low or high to cause a low state at the output (Y). For example, a positive-logic bit combination of 0111 (decimal 7) at the P input determines that inputs A1 through A7 must be low and that inputs A8 through A12 must be high to cause the output to go low. Equality of the address applied at the A inputs to the preprogrammed address is indicated by the output being low. The HD74HC680 features a transparent latch and a latch enable input (C). When C is high, the device is in the transparent mode. When C is low, the previous logical state of Y is latched. Features • High Speed Operation • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) • Ordering Information Part Name HD74HC680RPEL Package Type SOP-20 pin (JEDEC) Rev.2.00 Mar 30, 2006 page 1 of 6 Package Code (Previous Code) PRSP0020DC-A (FP-20DBV) Package Abbreviation RP Taping Abbreviation (Quantity) EL (1,000 pcs/reel) HD74HC680 Function Table Inputs C P3 L P2 L P1 L P0 L A1 H A2 H A3 H A4 H A5 H A6 H A7 H A8 H A9 H A10 H A11 H A12 H Output Y H H H L L L L L H H L L L H L H H H H H H H H H H H H H H H H H H H H L L H H L L L H H L H L L L L L L L H L H H H H H H H H H H H H H H H H L L H H L L H H L H H L L L L L L L L L L L H L H H H H H H H H H H H H L L H H L H H L H L H L L L L L L L L L L L L L L L H L H H H H H H H H L L H H H H L L L H H L L L L L L L L L L L L L L L L L L L H L H H H H L L H H H H L H H L H L L L L L L L L L L L L L L L L L L L L L L L H L L L H H H H H H L H H L X X X X X X X X X X X X X X X X X X X X X X X X H H H H H H H H L L L L L L L L L H L L L L All other combinations L H : L : X : Any combination Latched high level low level irrelevant Pin Arrangement A1 1 20 VCC A2 2 19 C A3 3 18 Y A4 4 17 P3 A5 5 16 P2 A6 6 15 P1 A7 7 14 P0 A8 8 13 A12 A9 9 12 A11 GND 10 11 A10 (Top view) Rev.2.00 Mar 30, 2006 page 2 of 6 L HD74HC680 Logic Diagram A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 Q IN Y A11 CK A12 P0 P1 P2 P3 C Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage range Input / Output voltage VCC VIN, VOUT –0.5 to 7.0 –0.5 to VCC +0.5 V V IIK, IOK IOUT ±20 ±25 mA mA ICC or IGND PT ±50 500 mA mW Tstg –65 to +150 °C Input / Output diode current Output current VCC, GND current Power dissipation Storage temperature Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Supply voltage Symbol VCC Ratings 2 to 6 Unit V Input / Output voltage Operating temperature VIN, VOUT Ta 0 to VCC –40 to 85 V °C tr , tf 0 to 1000 0 to 500 Input rise / fall time *1 0 to 400 Note: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Rev.2.00 Mar 30, 2006 page 3 of 6 ns Conditions VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V HD74HC680 Electrical Characteristics Ta = 25°C Item Input voltage Symbol VCC (V) VIH VIL Output voltage VOH VOL Ta = –40 to+85°C 2.0 Min 1.5 Typ — Max — Min 1.5 Max — 4.5 6.0 3.15 4.2 — — — — 3.15 4.2 — — 2.0 4.5 — — — — 0.5 1.35 — — 0.5 1.35 6.0 2.0 — 1.9 — 2.0 1.8 — — 1.9 1.8 — 4.5 6.0 4.4 5.9 4.5 6.0 — — 4.4 5.9 — — 4.5 6.0 4.18 5.68 — — — — 4.13 5.63 — — 2.0 4.5 — — 0.0 0.0 0.1 0.1 — — 0.1 0.1 6.0 4.5 — — 0.0 — 0.1 0.26 — — 0.1 0.33 Input current Iin 6.0 6.0 — — — — 0.26 ±0.1 — — 0.33 ±1.0 Quiescent supply current ICC 6.0 — — 4.0 — 40 Unit Test Conditions V V V Vin = VIH or VIL IOH = –20 µA IOH = –4 mA IOH = –5.2 mA V Vin = VIH or VIL IOL = 20 µA IOL = 4 mA IOL = 5.2 mA µA Vin = VCC or GND µA Vin = VCC or GND, Iout = 0 µA Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Ta = 25°C Item Propagation delay time Symbol VCC (V) Ta = –40 to +85°C tPLH tPHL 2.0 Min — 4.5 6.0 — — 26 — 66 56 — — 82 70 tPLH tPHL 2.0 4.5 — — — 19 210 42 — — 265 53 6.0 2.0 — — — — 36 150 — — 45 190 4.5 6.0 — — 18 — 30 26 — — 38 33 2.0 4.5 100 20 — 12 — — 125 25 — — 6.0 2.0 17 — — — — 75 21 — — 95 4.5 6.0 — — 6 — 15 13 — — 19 16 — — 5 10 — 10 tPLH tPHL Setup time tSU Output rise/fall time tTLH tTHL Input capacitance Cin Rev.2.00 Mar 30, 2006 page 4 of 6 Typ — Max 330 Min — Max 410 Unit Test Conditions ns P to Y ns A to Y ns C to Y ns A to C ns pF HD74HC680 Test Circuit VCC VCC Pulse Generator Zout = 50 Ω See Function Table C Input Output A1 A12 Y CL = 50 pF P0 P3 Note : 1. CL includes probe and jig capacitance. Waveforms • Waveform tr tf VCC 90% 50% 50% C 10% 50% 10% tsu 0V th VCC P or A 50% 50% 50% 50% 0V tPHL tPLH 90% Y 50% 10% tTLH tPLH tPHL VOH 90% 50% 10% 50% 50% tTHL Note : 1. Input waveform : PRR ≤ 1 MHz, duty cycle 50%, tr ≤ 6 ns, tf ≤ 6 ns Rev.2.00 Mar 30, 2006 page 5 of 6 VOL HD74HC680 Package Dimensions JEITA Package Code P-SOP20-7.5x12.8-1.27 RENESAS Code PRSP0020DC-A *1 Previous Code FP-20DBV MASS[Typ.] 0.52g D F 20 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" @ DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT @ INCLUDE TRIM OFFSET. 11 HE c *2 E bp Index mark Terminal cross section ( Ni/Pd/Au plating ) 1 e *3 bp x M L1 A Z Reference Symbol 10 A1 θ L y Detail F Rev.2.00 Mar 30, 2006 page 6 of 6 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Dimension in Millimeters Min Nom Max 12.80 13.2 7.50 0.10 0.20 0.30 2.65 0.34 0.40 0.46 0.20 0.25 0.30 0° 8° 10.00 10.40 10.65 1.27 0.12 0.15 0.935 0.40 0.70 1.27 1.45 Sales Strategic Planning Div. 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