INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4082B gates Dual 4-input AND gate Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4082B gates Dual 4-input AND gate DESCRIPTION The HEF4082B provides the positive dual 4-input AND function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance. Fig.2 Pinning diagram. HEF4082BP(N): 14-lead DIL; plastic (SOT27-1) HEF4082BD(F): 14-lead DIL; ceramic (cerdip) (SOT73) HEF4082BT(D): Fig.1 Functional diagram. 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America Fig.3 Logic diagram (one gate). FAMILY DATA, IDD LIMITS category GATES See Family Specifications January 1995 2 Philips Semiconductors Product specification HEF4082B gates Dual 4-input AND gate AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Propagation delays In → On Output transition times HIGH to LOW LOW to HIGH 5 package (P) MAX. 65 125 ns 38 ns + (0,55 ns/pF) CL 30 60 ns 19 ns + (0,23 ns/pF) CL 25 45 ns 17 ns + (0,16 ns/pF) CL 5 60 120 ns 10 ns + (1,0 ns/pF) CL tPHL; tPLH 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL 5 60 120 ns 10 10 VDD V dissipation per TYPICAL EXTRAPOLATION FORMULA TYP. 15 10 15 Dynamic power SYMBOL tTHL tTLH 10 ns + (1,0 ns/pF) CL 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL TYPICAL FORMULA FOR P (µW) 5 1500 fi + ∑ (foCL) × VDD 2 where 10 6700 fi + ∑ (foCL) × VDD 2 fi = input freq. (MHz) 15 16 800 fi + ∑ (foCL) × VDD 2 fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 3