PHILIPS HEF4555BN Dual 1-of-4 decoder/demultiplexer Datasheet

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4555B
MSI
Dual 1-of-4 decoder/demultiplexer
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
HEF4555B
MSI
Dual 1-of-4 decoder/demultiplexer
DESCRIPTION
The HEF4555B is a dual 1-of-4 decoder/demultiplexer.
Each has two address inputs (A0 and A1), an active LOW
enable input (E) and four mutually exclusive outputs which
are active HIGH (O0 to O3). When used as a decoder,
E when HIGH, forces O0 to O3 LOW. When used as a
demultiplexer, the appropriate output is selected by the
information on A0 and A1 with E as data input. All
unselected outputs are LOW.
Fig.2 Pinning diagram.
HEF4555BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4555BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4555BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
PINNING
E
enable inputs (active LOW)
A0 and A1
address inputs
O0 to O3
outputs (active HIGH)
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
Fig.1 Functional diagram.
January 1995
2
Philips Semiconductors
Product specification
HEF4555B
MSI
Dual 1-of-4 decoder/demultiplexer
Fig.3 Logic diagram (one decoder/multiplexer).
TRUTH TABLE
INPUTS
OUTPUTS
E
A0
A1
O0
O1
O2
O3
L
L
L
H
L
L
L
L
H
L
L
H
L
L
L
L
H
L
L
H
L
L
H
H
L
L
L
H
H
X
X
L
L
L
L
Notes
1. H = HIGH state (the more positive voltage)
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
January 1995
3
Philips Semiconductors
Product specification
HEF4555B
MSI
Dual 1-of-4 decoder/demultiplexer
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
MIN.
TYP.
TYPICAL EXTRAPOLATION
FORMULA
MAX.
Propagation delays
An → On
5
HIGH to LOW
10
tPHL
15
5
LOW to HIGH
10
tPLH
15
En → On
5
HIGH to LOW
10
tPHL
15
5
LOW to HIGH
10
tPLH
15
Output transition times
5
HIGH to LOW
88 ns + (0,55 ns/pF) CL
90 ns
34 ns + (0,23 ns/pF) CL
30
65 ns
22 ns + (0,16 ns/pF) CL
140
280 ns
113 ns + (0,55 ns/pF) CL
55
105 ns
44 ns + (0,23 ns/pF) CL
40
75 ns
32 ns + (0,16 ns/pF) CL
125
250 ns
98 ns + (0,55 ns/pF) CL
50
95 ns
39 ns + (0,23 ns/pF) CL
30
65 ns
22 ns + (0,16 ns/pF) CL
150
295 ns
123 ns + (0,55 ns/pF) CL
55
110 ns
44 ns + (0,23 ns/pF) CL
40
75 ns
32 ns + (0,16 ns/pF) CL
10 ns + ((1,0 ns/pF) CL
60
120 ns
60 ns
9 ns +
(0,42 ns/pF) CL
15
20
40 ns
6 ns +
(0,28 ns/pF) CL
5
60
120 ns
10 ns +
(1,0 ns/pF) CL
30
60 ns
9 ns +
(0,42 ns/pF) CL
20
40 ns
6 ns +
(0,28 ns/pF) CL
10
tTHL
tTLH
15
VDD
V
Dynamic power
230 ns
45
30
10
LOW to HIGH
115
5
TYPICAL FORMULA FOR P (µW)
4500 fi + ∑ (foCL) × VDD2
dissipation per
10
18 800 fi + ∑ (foCL) ×
package (P)
15
45 700 fi + ∑ (foCL) ×
VDD2
VDD2
where
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
APPLICATION INFORMATION
Some examples of applications for the HEF4555B are:
• Code conversion.
• Address decoding.
• Demultiplexing: when using the enable input as data input.
January 1995
4
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