HFA3926 Data Sheet July 1998 File Number 4282.2 2.0GHz - 2.7GHz 250mW Power Amplifier Features The Intersil HFA3926 is an integrated power amplifier in a low cost SSOP 28 plastic package. The power amplifier delivers +27dB of gain with high efficiency and can be operated with voltages as low as 2.7V. • Highly Integrated Power Amplifier ™ The HFA3926 is ideally suited for QPSK, BPSK or other linearly modulated systems in the 2.4GHz Industrial, Scientific, and Medical (ISM) frequency band. It can also be used in GFSK systems where levels of +25dBm are required. Typical applications include Wireless Local Area Network (WLAN) and Wireless Local Loop systems. • Operates Over 2.7V to 6V Supply Voltage • High Linear Output Power (P1dB: +24.5dBm) • Low Cost SSOP-28 Plastic Package Applications • Wireless Local Loop Systems • Systems Targeting IEEE 802.11 Standard • TDD Quadrature-Modulated Communication Systems • Wireless Local Area Networks REMEMBER: Always apply Negative power to the VG pins before applying the Positive VDD bias. Failure to do so may result in the destruction of the HFA3926 Power Amplifier. • PCMCIA Wireless Transceivers Ordering Information Functional Block Diagram PART NUMBER TEMP. RANGE (oC) PACKAGE HFA3926IA -40 to 85 28 Ld SSOP HFA3926IA96 -40 to 85 Tape and Reel • ISM Systems PKG. NO. VDDX(+) VGX(-) M28.15 STAGE BIAS CONTROL Pinout HFA3926 (SSOP) TOP VIEW RF IN GND 1 28 GND GND 2 27 VDD GND 3 26 GND GND 4 25 RF OUT GND 5 24 GND GND 6 23 VDD3 GND 7 22 GND N/C 8 21 GND VG2 9 20 GND STAGE 1 GND 10 19 GND VDD1 11 18 VDD2 GND 12 17 VG3 GND 13 16 GND VG1 14 15 RF IN 2-229 ANT STAGE 2 STAGE 3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 PRISM® is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation. HFA3926 Pin Description PINS SYMBOL 1 GND DC and RF Ground. 2 GND DC and RF Ground. 3 GND DC and RF Ground. 4 GND DC and RF Ground. 5 GND DC and RF Ground. 6 GND DC and RF Ground. 7 GND DC and RF Ground. 8 DESCRIPTION No connect. 9 VG2 Negative bias control for the second PA stage, adjusted to set VDD2 quiescent bias current, which is typically 53mA. Typical voltage at pin = -0.75V. Input impedance: > 1MΩ. 10 GND DC and RF Ground. 11 VDD1 Positive bias for the first stage of the PA, 2.7V to 6V. 12 GND DC and RF Ground. 13 GND DC and RF Ground. 14 VG1 Negative bias control for the first PA stage, adjusted to set VDD1 quiescent bias current, which is typically 20mA. Typical voltage at pin = -0.75V. Input impedance: > 1MΩ. 15 RF IN RF Input of the Power Amplifier. 16S GND DC and RF Ground. 17 VG3 Negative bias control for the third PA stage, adjusted to set VDD3 quiescent bias current, which is typically 90mA. Typical voltage at pin = -0.95V. Input impedance: > 1MΩ. 18 VDD2 Positive bias for the second stage of the PA. 2.7V to 6V. 19-22 GND DC and RF Ground. 23 VDD3 Positive bias for the third stage of the PA. 2.7V to 6V. 24 GND DC and RF Ground. 25 RF OUT 26 GND DC and RF Ground. 27 VDD VDD. 28 GND DC and RF Ground. RF output of power amplifier. NOTE: Process variation will effect VG3 voltage requirement to develop 90mA stage 3 quiescent current, maximum range = -0.69V to -1.04V. 2-230 HFA3926 Absolute Maximum Ratings Thermal Information Maximum Input Power (Note 1) . . . . . . . . . . . . . . . . . . . . . . +23dBm Operating Voltages (Notes 1, 2). . . . . . . . . . . . VDD = 8V, VGG = -8V Thermal Resistance (Typical, Note 3) θJA (oC/W) SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Ambient temperature (TA) = 25oC. 2. |VDD | + |VGG | not to exceed 12V. 3. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications TA = 25oC, Z0 = 50Ω, VDD = +5V, PIN = -30dBm, f = 2.45GHz, Unless Otherwise Specified PARAMETER MIN TYP MAX UNITS 2.0 - 2.7 GHz 2.0GHz - 2.5GHz 27 28 32 dB 2.5GHz - 2.7GHz 23.5 27 - dB VSWR In/Out - 1.75:1 - Input Return Loss - -11.3 - dB Output Return Loss - -11.3 - dB 23 24.5 - dBm Second Harmonic at P1dB - -20 0 dBc Third Harmonic at P1dB - -30 -10 dBc IDD at P1dB (VDD1 + VDD2 + VDD3) - 270 375 mA Power Amplifier Input Frequency Range Linear Gain Output Power at P1dB 2.0GHz - 2.7GHz Typical Performance Curves Power Amplifier Small Signal Performance NOTE: All data measured at TA = 25oC and VG1, VG2 and VG3 adjusted for first stage quiescent current of 20mA, second stage current of 53mA and third stage current of 90mA, respectively. 35 6V -5 4V VDD1 = VDD2 = VDD3 30 -10 RETURN LOSS (dB) 5V GAIN (dB) 3V 25 20 15 -15 5V -20 6V 4V -25 3V 10 2.0 2.2 2.4 2.6 FREQUENCY (GHz) FIGURE 1. LINEAR GAIN 2-231 2.8 3.0 -30 2.0 2.2 2.4 2.6 FREQUENCY (GHz) FIGURE 2. INPUT MATCH 2.8 3.0 HFA3926 Typical Performance Curves (Continued) RETURN LOSS (dB) 0 -5 -10 5V 6V 3V -15 4V -20 2.0 2.2 2.4 2.6 FREQUENCY (GHz) 2.8 3.0 FIGURE 3. OUTPUT MATCH Power Amplifier CW Performance at Various Supply Voltages NOTE: All data measured at TA = 25oC and VG1, VG2 and VG3 adjusted for first stage quiescent current of 20mA, second stage current of 53mA and third stage current of 90mA, respectively. 30 50 2.45GHz, VDD1 = VDD2 = VDD3 2.45GHz, VDD1 = VDD2 = VDD3 5V 5V 6V 25 40 6V EFFICIENCY (%) 3V 20 15 5 -19 4V 30 3V 20 10 10 -14 -9 POWER INPUT (dBm) -4 0 -19 1 FIGURE 4. POWER OUTPUT -14 -9 INPUT POWER (dBm) 6V -1 5V -2 4V -3 3V -4 -5 -6 -7 -19 2.45GHz, VDD1 = VDD2 = VDD3 -14 -9 -4 INPUT POWER (dBm) FIGURE 6. GAIN COMPRESSION 2-232 -4 FIGURE 5. POWER ADDED EFFICIENCY 0 COMPRESSION (dBm) POWER (dBm) 4V 1 1 HFA3926 Typical Performance Curves (Continued) Power Amplifier Temperature Performance NOTE: All data measured at TA = 25oC and VG1, VG2 and VG3 adjusted for first stage quiescent current of 20mA, second stage current of 53mA and third stage current of 90mA, respectively. 35 30 2.45GHz, VDD1 = VDD2 = VDD3 = +5V 25 30 POWER (dBm) 25oC GAIN (dB) -20oC -20oC 25 70oC 20 25oC 20 70oC 15 10 15 5 10 2.0 VDD1 = VDD2 = VDD3 = +5V 2.2 2.4 2.6 FREQUENCY (GHz) 2.8 0 -19 3.0 -14 FIGURE 7. LINEAR GAIN -9 INPUT POWER (dBm) -4 1 FIGURE 8. POWER OUTPUT 0 COMPRESSION (dB) -1 -20oC 70oC -2 25oC -3 -4 2.45GHz, VDD1 = VDD2 = VDD3 = +5V -5 -20 -10 -5 -15 0 5 INPUT POWER (dBm) FIGURE 9. GAIN COMPRESSION Power Amplifier Spurious Response at Various Supply Voltages NOTE: All data measured at TA = 25oC and VG1, VG2 and VG3 adjusted for first stage quiescent current of 20mA, second stage current of 53mA and third stage current of 90mA, respectively. 50 70 2.45GHz, TONE SPACING 600kHz 2.45GHz, VDD1 = VDD2 = VDD3 65 3V 40 60 30 55 dBc IMR (dBc) 5V 6V 5V 6V 50 4V 45 20 3V 4V 40 10 9 13 17 21 FUNDAMENTAL POUT OF TONES (dBm) FIGURE 10. THIRD ORDER INTERMODULATION RATIO 2-233 25 35 15 17 19 21 FUNDAMENTAL POUT (dBm) 23 FIGURE 11. SECOND HARMONIC RATIO 25 HFA3926 Typical Performance Curves (Continued) 60 55 6V dBc 50 5V 45 4V 40 3V 35 15 2.45GHz, VDD1 = VDD2 = VDD3 17 19 21 FUNDAMENTAL POUT (dBm) 23 25 FIGURE 12. THIRD HARMONIC RATIO Typical Application Example VDD C8 N/C VG2 (-) R3 VDD1 (+) R6 C22 C11 C12 C5 VG1 (-) R2 R5 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 C21 RF OUT C24 VDD3 (+) C4 C16 C19 C3 C15 C18 VDD2 (+) C14 R4 R1 C13 RF IN C23 EXTERNAL CIRCUITRY PARTS LIST LABEL VALUE C3 - C5, C7, C8 22pF Bypass (GHz) C23 - C24 22pF DC Block C11 - C16 1000pF Bypass (MHz) C18 - C22 0.01µF Bypass (kHz) R1, R6 1.5kΩ FET Gate Divider Network R3, R5 5kΩ R2 12kΩ R4 1kΩ PURPOSE NOTE: All off-chip components are low cost surface mount components obtainable from multiple sources. (0.020in x 0.040in or 0.030in x 0.050in.) 2-234 VG3 (-) HFA3926 Typical Application Example: Positive Supply, Single Stage 3 Adjustment Circuit 1000pF 5pF GND 28 1 GND HFA3926 2 GND VDD 27 3 GND GND 26 4 GND 25 5 GND GND 24 6 GND VDD3 23 7 GND GND 22 8 GND 21 9 VG2 GND 20 10 GND GND 19 11 VDD1 VDD2 18 12 GND VG3 17 13 GND GND 16 RF OUT 22pF VCC1 0.1µF N/C 715 0.1µF 3.01K 0.1µF 715 14 VG1 0.1µF RF IN RF IN 15 3.01K 22pF VCC2 820Ω - +IN -OUT + TO -V CONVERTER 4.7µF + TANTL 1K MMBT 2222 ALTM VCC1 = +5V + VCC2 = +3.5V 4 3 2 Motorola™ 1 ICL7660SIBA SUPER VOLTAGE CONVERTER 5 6 7 8 0.1µF 10K - 4.7µF TANTL FIGURE 13. POSITIVE, SINGLE STAGE 3 ADJUSTMENT CIRCUIT All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 2-235