Hitachi HM62W8511HJP-15 4m high speed sram (512-kword x 8-bit) Datasheet

HM62W8511H Series
4M High Speed SRAM (512-kword × 8-bit)
ADE-203-750D (Z)
Rev. 1.0
Sep. 15, 1998
Description
The HM62W8511H is a 4-Mbit high speed static RAM organized 512-kword × 8-bit. It has realized high
speed access time by employing CMOS process (4-transistor + 2-poly resistor memory cell) and high speed
circuit designing technology. It is most appropriate for the application which requires high speed, high
density memory and wide bit width configuration, such as cache and buffer memory in system. The
HM62W8511H is packaged in 400-mil 36-pin SOJ for high density surface mounting.
Features
• Single supply : 3.3 V ± 0.3 V
• Access time 12/15 ns (max)
• Completely static memory
 No clock or timing strobe required
• Equal access and cycle times
• Directly TTL compatible
 All inputs and outputs
• Operating current : 150/130 mA (max)
• TTL standby current : 60/50 mA (max)
• CMOS standby current : 5 mA (max)
: 1 mA (max) (L-version)
• Data retension current : 0.6 mA (max) (L-version)
• Data retension voltage : 2 V (min) (L-version)
• Center VCC and VSS type pinout
HM62W8511H Series
Ordering Information
Type No.
Access time
Package
HM62W8511HJP-12
HM62W8511HJP-15
12 ns
15 ns
400-mil 36-pin plastic SOJ (CP-36D)
HM62W8511HLJP-12
HM62W8511HLJP-15
12 ns
15 ns
Pin Arrangement
HM62W8511HJP/HLJP Series
A0
1
36
NC
A1
2
35
A18
A2
3
34
A17
A3
4
33
A16
A4
5
32
A15
CS
6
31
OE
I/O1
7
30
I/O8
I/O2
8
29
I/O7
VCC
9
28
VSS
VSS
10
27
VCC
I/O3
11
26
I/O6
I/O4
12
25
I/O5
WE
13
24
A14
A5
14
23
A13
A6
15
22
A12
A7
16
21
A11
A8
17
20
A10
A9
18
19
NC
(Top View)
2
HM62W8511H Series
Pin Description
Pin name
Function
A0 to A18
Address input
I/O1 to I/O8
Data input/output
CS
Chip select
OE
Output enable
WE
Write enable
VCC
Power supply
VSS
Ground
NC
No connection
Block Diagram
(LSB)
A1
A17
A7
A11
A16
A2
A6
A5
(MSB)
VCC
Row
decoder
Memory matrix
256 rows × 8 columns ×
256 blocks × 8 bit
(4,194,304 bits)
VSS
CS
Column I/O
I/O1
.
.
.
I/O8
Input
data
control
Column decoder
CS
A10 A8 A9 A12 A13 A14 A0 A18 A15 A3 A4
(LSB)
(MSB)
WE
CS
OE
CS
3
HM62W8511H Series
Operation Table
CS
OE
WE
Mode
VCC current
I/O
Ref. cycle
H
×
×
Standby
I SB , I SB1
High-Z
—
L
H
H
Output disable
I CC
High-Z
—
L
L
H
Read
I CC
Dout
Read cycle (1) to (3)
L
H
L
Write
I CC
Din
Write cycle (1)
L
L
Write
I CC
Din
Write cycle (2)
Parameter
Symbol
Value
Supply voltage relative to VSS
VCC
–0.5 to +4.6
L
Note:
×: H or L
Absolute Maximum Ratings
Unit
V
1
2
Voltage on any pin relative to V SS
VT
–0.5* to V CC+0.5*
V
Power dissipation
PT
1.0
W
Operating temperature
Topr
0 to +70
°C
Storage temperature
Tstg
–55 to +125
°C
Storage temperature under bias
Tbias
–10 to +85
°C
Notes: 1. VT (min) = –2.0 V for pulse width (under shoot) ≤ 8 ns
2. VT (max) = VCC+2.0 V for pulse width (over shoot)≤ 8 ns
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
Supply voltage
Input voltage
Min
Typ
Max
Unit
VCC*
3
3.0
3.3
3.6
V
VSS *
4
0
0
0
VIH
VIL
Notes: 1.
2.
3.
4.
4
2.2
1
–0.5*
V
2
—
VCC + 0.5*
V
—
0.8
V
VIL (min) = –2.0 V for pulse width (under shoot) ≤ 8 ns
VIH (max) = VCC+2.0 V for pulse width (over shoot)≤ 8 ns
The supply voltage with all VCC pins must be on the same level.
The supply voltage with all VSS pins must be on the same level.
HM62W8511H Series
DC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0V)
Parameter
Symbol Min
Typ*1
Max
Unit
Test conditions
Input leakage current
IILII
—
—
2
µA
Vin = VSS to V CC
Output leakage current
IILO I
—
—
2
µA
Vin = VSS to V CC
12 ns cycle I CC
—
—
150
mA
Min cycle
CS = VIL, lout = 0 mA
Other inputs = VIH/VIL
15 ns cycle I CC
—
—
130
12 ns cycle I SB
—
—
60
mA
Min cycle
CS = VIH,
Other inputs = VIH/VIL
15 ns cycle I SB
—
—
50
—
0.05
5
mA
f = 0 MHz
VCC ≥ CS ≥ VCC - 0.2 V,
(1) 0 V ≤ Vin ≤ 0.2 V or
(2) VCC ≥ Vin ≥ VCC - 0.2 V
—* 2
0.05*2
1.0*2
VOL
—
—
0.4
V
I OL = 8 mA
VOH
2.4
—
—
V
I OH = –4 mA
Operation power
supply current
Standby power supply
current
I SB1
Output voltage
Notes: 1. Typical values are at VCC = 3.3 V, Ta = +25°C and not guaranteed.
2. This characteristics is guaranteed only for L-version.
Capacitance (Ta = +25°C, f = 1.0 MHz)
Parameter
1
Input capacitance*
Input/output capacitance*
Note:
1
Symbol
Min
Typ
Max
Unit
Test conditions
Cin
—
—
6
pF
Vin = 0 V
CI/O
—
—
8
pF
VI/O = 0 V
1. This parameter is sampled and not 100% tested.
5
HM62W8511H Series
AC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, unless otherwise noted.)
Test Conditions
•
•
•
•
Input pulse levels: 3.0 V/0.0 V
Input rise and fall time: 3 ns
Input and output timing reference levels: 1.5 V
Output load: See figures (Including scope and jig)
3.3 V
319Ω
Dout Zo=50 Ω
Dout
RL=50 Ω
353Ω
1.5 V
Output load (A)
5 pF
Output load (B)
(for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW)
Read Cycle
HM62W8511H
-12
-15
Parameter
Symbol
Min
Max
Min
Max
Unit
Read cycle time
t RC
12
—
15
—
ns
Address access time
t AA
—
12
—
15
ns
Chip select access time
t ACS
—
12
—
15
ns
Output enable to outpput valid
t OE
—
6
—
7
ns
Output hold from address change
t OH
3
—
3
—
ns
Chip select to output in low-Z
t CLZ
3
—
3
—
ns
1
Output enable to output in low-Z
t OLZ
0
—
0
—
ns
1
Chip deselect to output in high-Z
t CHZ
—
6
—
7
ns
1
Output disable to output in high-Z
t OHZ
—
6
—
7
ns
1
6
Notes
HM62W8511H Series
Write Cycle
HM62W8511H
-12
-15
Parameter
Symbol
Min
Max
Min
Max
Unit
Write cycle time
t WC
12
—
15
—
ns
Address valid to end of write
t AW
8
—
10
—
ns
Chip select to end of write
t CW
8
—
10
—
ns
9
Write pulse width
t WP
8
—
10
—
ns
8
Address setup time
t AS
0
—
0
—
ns
6
Write recovery time
t WR
0
—
0
—
ns
7
Data to write time overlap
t DW
6
—
7
—
ns
Data hold from write time
t DH
0
—
0
—
ns
Write disable to output in low-Z
t OW
3
—
3
—
ns
1
Output disable to output in high-Z
t OHZ
—
6
—
7
ns
1
Write enable to output in high-Z
t WHZ
—
6
—
7
ns
1
Note:
Notes
1. Transition is measured ±200 mV from steady voltage with Load (B). This parameter is sampled
and not 100% tested.
2. Address should be valid prior to or coincident with CS transition low.
3. WE and/or CS must be high during address transition time.
4. if CS and OE are low during this period, I/O pins are in the output state. Then, the data input
signals of opposite phase to the outputs must not be applied to them.
5. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition,
output remains a high impedance state.
6. t AS is measured from the latest address transition to the later of CS or WE going low.
7. t WR is measured from the earlier of CS or WE going high to the first address transition.
8. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition
among CS going low and WE going low. A write ends at the earliest transition among CS going
high and WE going high. tWP is measured from the beginnig of write to the end of write.
9. t CW is measured from the later of CS going low to the the end of write.
7
HM62W8511H Series
Timing Waveforms
Read Timing Waveform (1) (WE = VIH)
tRC
Address
Valid address
tOH
tAA
tACS
tCHZ
CS
tOE
tOHZ
OE
tOLZ
tCLZ
Dout
High Impedance
Valid data
Read Timing Waveform (2) (WE = VIH, CS = VIL , OE = VIL )
tRC
Address
Valid address
tAA
tOH
tOH
Dout
8
Valid data
HM62W8511H Series
Read Timing Waveform (3) (WE = VIH, CS = VIL , OE = VIL )*2
tRC
CS
tACS
tCHZ
tCLZ
Dout
High
Impedance
Valid data
High
Impedance
Write Timing Waveform (1) (WE Controlled)
tWC
Valid address
Address
tWR
tAW
OE
tCW
CS*3
tAS
tWP
WE*3
tOHZ
High impedance*5
Dout
tDW
Din
*4
tDH
Valid data
*4
9
HM62W8511H Series
Write Timing Waveform (2) (CS Controlled)
tWC
Valid address
Address
tWR
tCW
CS *3
tAW
tWP
WE *3
tAS
tWHZ
tOW
High impedance*5
Dout
tDW
Din
10
*4
tDH
Valid data
*4
HM62W8511H Series
Low VCC Data Retention Characteristics (Ta = 0 to +70°C)
This characteristics is guaranteed only for L-version.
Parameter
Symbol
Min
Typ*1
Max
Unit
Test conditions
VCC for data retention
VDR
2.0
—
—
V
VCC ≥ CS ≥ VCC – 0.2 V
(1) 0 V ≤ Vin ≤ 0.2 V or
(2) VCC ≥ Vin ≥ VCC – 0.2 V
Data retention current
I CCDR
—
40
600
µA
VCC = 3 V, VCC ≥ CS ≥ VCC – 0.2 V
(1) 0 V ≤ Vin ≤ 0.2 V or
(2) VCC ≥ Vin ≥ VCC – 0.2 V
Chip deselect to data
retention time
t CDR
0
—
—
ns
See retention waveform
Operation recovery time
tR
5
—
—
ms
Note:
1. Typical values are at VCC = 3.0 V, Ta = +25˚C, and not guaranteed.
Low V CC Data Retention Timing Waveform
tCDR
Data retention mode
tR
VCC
3.0 V
VDR
2.2 V
CS
0V
VCC ≥ CS ≥ VCC – 0.2 V
11
HM62W8511H Series
Package Dimensions
HM62W8511HJP/HLJP Series (CP-36D)
Unit: mm
23.25
23.62 Max
10.16 ± 0.13
0.43 ± 0.10
0.41 ± 0.08
1.27
0.10
Dimension including the plating thickness
Base material dimension
12
0.80 +0.25
–0.17
1.30 Max
2.85 ± 0.12
18
0.74
3.50 ± 0.26
1
11.18 ± 0.13
19
36
9.40 ± 0.25
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
CP-36D
Conforms
Conforms
1.4 g
HM62W8511H Series
Cautions
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property rights, in connection with use of the information contained in this document.
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received the latest product standards or specifications before final design, purchase or use.
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contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
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failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
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Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
13
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