Intersil HMP8116CN Ntsc/pal video decoder Datasheet

HMP8116
S E M I C O N D U C T O R
ADVANCE DRAFT
NTSC/PAL Video Decoder
April 1998
Features
Description
• (M) NTSC and (B, D, G, H, I, M, N, NC) PAL Operation
- Optional Auto Detect of Video Standard
- ITU-R BT.601(CCIR601) and Square Pixel Operation
The HMP8115 is a high quality NTSC and PAL decoder with
internal A/D converters. It is compatible with NTSC M, PAL
B, D, G, H, I, M, N, and combination N (NC) video standards.
• Digital Output Formats
- VMI Compatible
- 8-bit, 16-bit 4:2:2 YCbCr
- 15-bit (5,5,5), 16-bit (5,6,5) RGB
- Linear or Gamma-Corrected
- 8-bit BT.656
Both composite and S-video (Y/C) input formats are supported. A 2-line comb filter plus a user-selectable chrominance trap filter provide high quality Y/C separation. User
adjustments include brightness, contrast, saturation, hue,
and sharpness.
Data during the vertical blanking interval (VBI), such as
closed captioning, widescreen signalling and teletext, may
be captured and output as BT.656 ancillary data. Closed
captioning and widescreen signalling information may also
be read out via the I2C interface.
• Analog Input Formats
- Three Analog Composite Inputs
- Analog Y/C (S-video) Input
Ordering Information
• “Raw” (Oversampled) VBI Data Capture
• “Sliced” VBI Data Capture Capabilities
- Closed Captioning
- Widescreen Signalling (WSS)
- BT.653 System B, C and D Teletext
- NABTS (North American Broadcast Teletext)
- WST (World System Teletext)
PART NUMBER
HMP8116CN
HMPVIDEVAL/ISA
TEMP.
RANGE (oC)
0 to 70
PACKAGE
80 Ld PQFP
PKG.NO.
Q80.14x20
Evaluation Board: ISA Frame Grabber
NOTES:
• 2-Line (1H) Comb Filter Y/C Separator
1. PQFP is also known as QFP and MQFP.
• Fast I2C Interface
2. Evaluation Board and Reference Design descriptions are in the
Applications section.
• Two 8-Bit ADCs
Applications
• Multimedia PCs
• Video Conferencing
• Video Compression Systems
• Video Security Systems
• LCD Projectors and Overhead Panels
• Related Products
- NTSC/PAL Encoders: HMP815x, HMP817x
- NTSC/PAL Decoders: HMP8112A
• Related Literature
- AN9644: Composite Video Separation Techniques
- AN9716: Widescreen Signalling
- AN9717: YCbCr to RGB Considerations
- AN9728: BT.656 Video Interface for ICs
- AN9738: VMI Video Interface for ICs
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1998
1
File Number
4510
HMP8116
Table of Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
External Video Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
ANALOG VIDEO INPUTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
ANTI-ALIASING FILTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
Digitization of Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
A/D CONVERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
AGC AND DC RESTORATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
INPUT SIGNAL DETECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
VERTICAL SYNC AND FIELD DETECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Y/C SEPARATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
INPUT SAMPLE RATE CONVERTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
COMB FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
CHROMA DEMODULATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
OUTPUT SAMPLE RATE CONVERTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
CLK2 INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Digital Processing of Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
UV to CbCr Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
DIGITAL COLOR GAIN CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
COLOR KILLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
Y PROCESSING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
CbCr Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
YCbCr Output Format Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
RGB OUTPUT FORMAT PROCESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
BUILT-IN VIDEO GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
Pixel Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
HSYNC AND VSYNC TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
FIELD TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
BLANK AND DVALID TIMING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
PIXEL OUTPUT PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
8-BIT YCbCr OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
16-BIT YCbCr, 15-BIT RGB, OR 16-RGB OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
8-BIT BT.656 OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
Advanced Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CLOSED CAPTIONING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
WIDESCREEN SIGNALLING (WSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
BT.656 ANCILLARY DATA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
BT.656 CLOSED CAPTIONING AND WIDE SCREEN SIGNALLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
TELETEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
REAL TIME CONTROL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
Host Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
HMP8116 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
PCB LAYOUT CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
EVALUATION BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
RELATED APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
2
3
C
CLAMP
LOGIC
AND
GAIN
CONTROL
AGC
AND
CLAMP
LOGIC
INPUT
MUX
EXTERNAL
ANTIALIASING
FILTER
C_CAP
L_CAP
CVBS3/(Y)
CVBS2
CVBS1
+
+
-
YIN
8-BIT
ADC
CLAMP
RESET
INTREQ
MICROPROCESSOR
INTERFACE AND
CONTROL
8-BIT
ADC
DIGITAL COMPARATOR
SYNC LEVEL
BLACK LEVEL
WHITE PEAK LEVEL
DIGITAL COMPARATORS
YOUT
EXTERNAL
ANTIALIASING
FILTER
SDA
SCL
INPUT
SAMPLE
RATE
CONVERTER
COLOR
TRAP
FIELD VSYNC
LINE
LOCK
PLL
VSYNC
DETECT
LOCKED
HSYNC
DETECT
COLOR
ADJUST
USER
ADJUST
CHROMA
PLL
COLOR
DEMODULATION
Y/C
SEPARATION
VBI
DETECTION &
DECODING LOGIC
VBI STATUS BITS
OUTPUT
TIMING
AND
FIFO
OUTPUT
SAMPLE
RATE
CONVERTER
P[15:0]
DVALID
HSYNC
BLANK
VBIVALID
RGB
LOGIC
USER
ADJUST.
HMP8116
Functional Block Diagram
Functional Block Diagram (Continued)
CLK
(24.54, 27.0 or 29.5MHz)
4FSC
CLOCK
HUE
ADJUST
CHROMA
PLL LOOP
FILTER
CHROMA
PLL NCO
FIELD
VSYNC
GENLOCK LOSS
VSYNC
DETECT
CHROMA
PHASE
DETECTOR
HSYNC
DETECT
LINE LOCKED
PLL LOOP FILTER
CLK TO
4FSC RATIO
AGC
ADJUST
LINE LOCKED
NCO
SATURATION
ADJUST
CR[7:0]
C
C,CVBS
DATA
4
INPUT
SAMPLE
RATE
CONVERTER
Y,CVBS
Y DATA
C DATA
LINE
DELAY
COMB
FILTER
CHROMA
DEMODULATOR
U,V
U, V TO CbCr
COLOR
SPACE
CONVERTER
AND COLOR
KILLER
LP FILTER
CbCr
ENABLE
Y DATA
HORIZONTAL
M Y DATA AND VERTICAL
Y DATA U
SHARPNESS
X
ADJUST
SHARPNESS
ADJUST
OUTPUT
SAMPLE
RATE
CONVERTER
CHROMA
TRAP
Y
ENABLE
VBI DETECTION
& DECODING LOGIC
LOCKED
HMP8116
M
U
X
C,CVBS
DATA
HSYNC
M
U
X
SYNC
STRIPPER,
BRIGHTNESS,
& CONTRAST
ADJUST
STANDARD
SELECT
RGB
LOGIC
LP FILTER
MUX
MUX
ENABLE
P[15:0]
HSYNC,VSYNC, BLANK,
FIELD, DVALID, VBIVALID
OUTPUT
TIMING
AND
FIFO
HMP8116
Introduction
toration” section. After digitization, sample rate converters and
a comb filter are used to perform color separation and demodulation.
The HMP8116 is designed to decode baseband composite
or S-video NTSC and PAL signals, and convert them to
either digital YCbCr or RGB data. In addition to performing
the basic decoding operations, the HMP8116 includes hardware to decode different types of VBI data and to generate
digital video patterns for a blue screen, black screen and full
screen color bars.
A/D CONVERSION
Video data is sampled at the CLK2 frequency then processed by the input sample rate converter. The output levels
of the ADC after AGC and DC restoration processing are:
(M) NTSC
(M, N) PAL
The digital PLLs are designed to synchronize to all NTSC
and PAL standards. A chroma PLL is used to maintain
chroma lock for demodulation of the color information; a linelocked PLL is used to maintain vertical spatial alignment.
The PLLs are designed to maintain lock even in the event of
VCR headswitches and multipath noise.
white
black
blank
sync
The HMP8116 contains two 8-bit A/D converters and an I2C
interface for programming internal registers
196
66
56
0
(B, D, G, H, I, NC)
PAL
196
59
59
0
AGC AND DC RESTORATION
The AGC amplifier attenuates or amplifies the analog video
signal to ensure that the blank level generates code 56 or 59
depending on the video standard. The difference from the
ideal blank level of 56 or 59 is used to control the amount of
attenuation or gain of the analog video signal.
External Video Processing
Before a video signal can be digitized the decoder has some
external processing considerations that need to be
addressed. This section discusses those external aspects of
the HMP8116.
DC restoration positions the video signal so that the sync tip
generates a code 0. The internal timing windows for AGC
and DC Restoration are show in Figure 3.
ANALOG VIDEO INPUTS
The HMP8116 supports either three composite or two composite and one S-video input.
Three analog video inputs (CVBS 1-3) are used to select
which one of three composite video sources are to be
decoded. To support S-video applications, the Y channel
drives the CVBS 3 analog input, and the C channel drives
the C analog input.
VIDEO INPUT
The analog inputs must be AC-coupled to the video signals,
as shown in the Applications section.
AGC
ANTI-ALIASING FILTERS
An external anti-alias filter is required to achieve optimum
performance and prevent high frequency components from
being aliased back into the video image.
DC RESTORE
FIGURE 2. AGC AND DC RESTORE INTERNAL TIMING
For the CVBS 1-3 inputs, a single filter is connected between
the YOUT and YIN pins. For the C input, the antialiasing filter
should be connected before the C input. A recommended filter is shown in Figure 1.
R1
YOUT
332
C1
33pF
INPUT SIGNAL DETECTION
It is assumed there is no video input if a horizontal sync is
not detected for 16 consecutive lines. When no video has
been detected, nominal video timing is generated for the
previously detected or programmed video standard. A
maskable interrupt is included to flag when no video has
been detected (bit 6 of the INTERRUPT MASK register 0FH)
allowing for blue/black/color bar output modes to be enabled
if desired. The vertical sync interrupt can be used in determining when a video signal is present on the currently
selected video mux input. Bit 0 of register 0FH is used to
enable vertical sync interrupts.
L1
YIN
8.2uH
C2
82pF
R2
4.02K
FIGURE 1. RECOMMENDED ANTI-ALIASING FILTER
Digitization of Video
Prior to A/D conversion, the video signal is DC restored and
gained to generate known video levels into the digital processing logic. This process is addessed in the “AGC and DC Res-
5
HMP8116
VERTICAL SYNC AND FIELD DETECTION
have a half-line vertical offset from the luma data. This may
be eliminated, vertically aligning the chroma and luma samples, at the expense of vertical resolution of the luma. Bit 0 of
the OUTPUT FORMAT register 02H controls this option.
The vertical sync and field detect circuit uses a low time
counter to detect the vertical sync sequence in the video
data stream. The low time counter accumulates the low time
encountered during any sync pulse, including serration and
equalization pulses. When the low time count exceeds the
vertical sync detect threshold, VSYNC is asserted immediately. FIELD is asserted at the same time that VSYNC is
asserted. FIELD is asserted low for odd fields and high for
even fields. Field is determined from the location in the video
line where VSYNC is detected. If VSYNC is detected in the
first half of the line, the field is odd. If VSYNC is detected in
the second half of a line, the field is even.
CHROMA DEMODULATION
The output of the comb filter is further processed using a
patented frequency domain transform to complete the Y/C
separation and demodulate the chromanance.
Demodulation is done at a virtual 4xfSC sample rate using
the interpolated data samples to generate U and V data. The
demodulation process decimates by 2 the U/V sample rate.
OUTPUT SAMPLE RATE CONVERTER
In the case of lost vertical sync or excessive noise that would
prevent the detection of vertical sync, the FIELD output will continue to toggle. Lost vertical sync is declared if after 337 lines, a
vertical sync period was not detected for 1 or 3 (selectable) successive fields as specified by bit 2 of the GENLOCK CONTROL
register 04H. When this occurs, the PLLs are initialized to the
acquisition state.
The output sample rate converter converts the Y, U and V
data from a virtual 4xfSC sample rate to the desired output
sample rate (i.e., 13.5MHz). It also vertically aligns the samples based on the horizontal sync information embedded in
the digital video data stream. The output sample rate is
determined by the selected video standard and whether
square or rectangular pixels are output. The output format is
4:2:2 for all modes except the RGB modes which use a 4:4:4
output format.
Y/C SEPARATION
A composite video signal has the luma (Y) and chroma (C)
information mixed in the same video signal. The Y/C separation process is responsible for separating the composite
video signal into these two components. The HMP8116 utilizes a comb filter to minimize the artifacts that are associated with the Y/C separation process.
CLK2 INPUT
Note that the color subcarrier is derived from CLK2. Any jitter
on CLK2 will be transferred to the color subcarrier, resulting
in color changes. Thus, CLK2 should be derived from a stable clock source, such as a crystal. The use of a PLL to generate CLK2 is not recommended. CLK2 must have a 50ppm
accuracy and at least a 60/40% duty cycle to ensure proper
operation.
INPUT SAMPLE RATE CONVERTER
The input sample rate converter is used to convert video
data sampled at the CLK2 rate to a virtual 4xfSC sample rate
for comb filtering and color demodulation. An interpolating
filter is used to generate the 4xfSC samples as illustrated in
Figure 3.
The CLK2 clock rate must be one of the following frequencies:
24.54MHz
27.00MHz
29.50MHz
INCOMING VIDEO SAMPLES
The frequency of CLK2 must be 2x the desired output sample rate. The values in table 1 below indicate the CLK2 clock
rate based on the video standard and pixel mode. The output sample rate for the given video standard and pixel mode
is half the CLK2 clock rate.z
TIME
RESAMPLED VIDEO
TABLE 1. VIDEO STANDARD CLOCKRATE SELECTION
SUMMARY
TIME
4xfSC
ALLOWABLE CLK2
FREQUENCIES (MHz)
FIGURE 3. SAMPLE RATE CONVERSION
COMB FILTER
A 2-line comb filter, using a single line delay, is used to perform part of the Y/C separation process. During S-video
operation, the Y signal bypasses the comb filter; the C signal
is processed by the comb filter since it is an integral part of
the chroma demodulator. During PAL operation, the chroma
trap filter should also be enabled for improved performance.
Since a single line store is used, the chroma will normally
6
VIDEO FORMAT
RECTANGULAR
PIXEL MODE
SQUARE
PIXEL MODE
(M) NTSC
27.00
24.54
(B, D, G, H, I, N) PAL
27.00
29.50
(M) PAL
27.00
24.54
(NC) PAL
27.00
29.50
HMP8116
Digital Processing of Video
8-bit code 219.
Once the luma and chroma have been separated the
HMP8116 then performs programmable modifications (i.e.
contrast, coring, color space conversions, color AGC, etc.) to
the decoded video signal.
A chroma trap filter may be used to remove any residual
color subcarrier from the luminance data. The center frequency of the chroma trap is automatically determined from
the video standard being decoded. The chroma trap should
be disabled during S-video operation to maintain maximum
luminance bandwidth. Alternately, a 3MHz lowpass filter may
be used to remove high-frequency Y data. This may make a
noisy image more pleasing to the user, although softer.
UV TO CbCr CONVERSION
The baseband U and V signals are scaled and offset to generate a nominal range of 16-240 for both the Cb and Cr data.
DIGITAL COLOR GAIN CONTROL
Coring of the high-frequency Y data may be done to reduce
low-level high frequency noise.
There are four types of color gain control modes available:
no gain control, automatic gain control, fixed gain control,
and freeze automatic gain control.
Coring of the Y data may also be done to reduce low-level
noise around black. This forces Y data with the following values to a value of 0:
If “no gain control” is selected, the amplitude of the color difference signals (CbCr) is not modified, regardless of variations in the color burst amplitude. Thus, a gain of 1x is
always used for Cb and Cr.
coring = 1: +/- 1
coring = 2: +/- 1, +/- 2
coring = 3: +/- 1, +/- 2. +/- 3
High-frequency components of the luminance signal may be
“peaked” to control the sharpness of the image. Maximum
gain may be selected to occur at either 2.6MHz or the color
subcarrier frequency. This may be used to make the displayed image more pleasing to the user. It should not be
used if the output video will be compressed, as the circuit
introduces high-frequency components that will reduce the
compression ratio.
If “automatic gain control” is selected, the amplitude of the
color difference signals (CbCr) is compensated for variations
in the color burst amplitude. The burst amplitude is averaged
with the two previous lines having a color burst to limit lineto-line variations. A gain of 0.5x to 4x is used for Cb and Cr.
If “fixed gain control” is selected, the amplitude of the color
difference signals (CbCr) is multiplied by a constant, regardless of variations in the color burst amplitude. The constant
gain value is specified by the COLOR GAIN register 1CH. A
gain of 0.5x to 4x is used for Cb and Cr. Limiting the gain to
4x limits the amount of amplified noise.
The brightness control adds or subtracts a user-specified
DC offset to the Y data. The contrast control multiplies the Y
data by a user-specified amount. These may be used to
make the displayed image more pleasing to the user.
If “freeze automatic gain control” is selected, the amplitude
of the color difference signals (CbCr) is multiplied by a constant. This constant is the value the AGC circuitry generated
when the “freeze automatic gain” command was selected.
Finally, a value of 16 is added to generate a nominal range of
16 (black) to 235 (white).
COLOR KILLER
The CbCr data is lowpass filtered to either 0.85 or 1.5MHz.
If “enable color killer” is selected, the color output is turned
off when the running average of the color burst amplitude is
below approximately 25% of nominal for four consecutive
fields. When the running average of the color burst amplitude is above approximately 25% of nominal for four consecutive fields, the color output is turned on. The color output is
also turned off when excessive phase error of the chroma
PLL is present.
Coring of the CbCr data may be done to reduce low-level
noise around zero. This forces CbCr data with the following
values to a value of 128.
CbCr PROCESSING
coring = 1: 127, 129
coring = 2: 126, 127, 129, 130
coring = 3: 125, 126, 127, 129, 130, 131
The saturation control multiplies the CbCr data by a userspecified amount. This may be used to make the displayed
image more pleasing to the user. The CbCr data may also
be optionally multiplied by the contrast value to avoid color
shifts when changing contrast.
If “force color off” is selected, color information is never
present on the outputs.
If “force color on” is selected, color information is present on
the outputs regardless of the color burst amplitude or
chroma PLL phase error.
The hue control provides a user-specified phase offset to the
color subcarrier during decoding. This may be used to correct slight hue errors due to transmission.
Y PROCESSING
The black level is subtracted from the luminance data to
remove sync and any blanking pedestal information. Negative values of Y are supported at this point to allow proper
decoding of “below black” luminance levels.
YCbCr OUTPUT FORMAT PROCESSING
Y has a nominal range of 16 to 235. Cb and Cr have a nominal range of 16 to 240, with 128 corresponding to zero. Values less than 1 are made 1 and values greater than 254 are
Scaling is done to position black at 8-bit code 0 and white at
7
HMP8116
fications specify a gamma of 2.8, a gamma of 2.2 is normally
used. The HMP8116 allows the selection of the gamma to
be either 2.2 or 2.8, independent of the video standard.
made 254.
While BLANK is asserted, Y is forced to have a value of 16,
with Cb and Cr forced to have a value of 128, unless VBI
data is present.
for gamma = 2.2:
for R′B′ < 0.0812*31, G′ < 0.0812*63
RGB OUTPUT FORMAT PROCESSING
The 4:2:2 YCbCr data is converted to 4:4:4 YCbCr data and
then converted to either 15-bit or 16-bit gamma-corrected
RGB (R′G′B′) data. While BLANK is asserted, RGB data is
forced to a value of 0.
R = (31)((R′/31)/4.5)
G = (63)((G′/63)/4.5)
B = (31)((B′/31)/4.5)
for R′B′ >= 0.0812*31, G′ >= 0.0812*63
15-Bit R′G′B′
R = (31)(((R′/31) + 0.099)/1.099)2.2
G = (63)(((G′/63) + 0.099)/1.099)2.2
B = (31)(((B′/31) + 0.099)/1.099)2.2
The following YCbCr to R′G′B′ equations are used to maintain the proper black and white levels:
R′ = 0.142(Y - 16) + 0.194(Cr - 128)
G′ = 0.142(Y - 16) - 0.099(Cr - 128) - 0.048(Cb - 128)
B′ = 0.142(Y - 16) + 0.245(Cb - 128)
for gamma = 2.8:
R = (31)(R′/31)2.8
G = (63)(G′/63)2.8
B = (31)(B′/31)2.8
The resulting 15-bit R′G′B′ data has a range of 0 to 31. Values less than 0 are made 0 and values greater than 31 are
made 31.
BUILT-IN VIDEO GENERATION
The 15-bit R′G′B′ data may be converted to 15-bit linear
RGB, using the following equations. Although the PAL specifications specify a gamma of 2.8, a gamma of 2.2 is normally
used. The HMP8116 allows the selection of the gamma to
be either 2.2 or 2.8, independent of the video standard.
When the blue screen, black screen or color bar output is
selected, a full-screen of blue, black or 75% colorbar output
is generated using the currently selected output format. The
type of screen to be generated is determined by bits 2 and 1
of the OUTPUT FORMAT register 02H. When built-in video
generation is not desired, the bits need to be set for normal
operation to pass decoded video.
for gamma = 2.2:
for R′G′B′ < 0.0812*31
If a video source is input, it will be used to provide the video
timing. If an input video source is not detected, internallygenerated video timing will be used.
R = (31)((R′/31)/4.5)
G = (31)((G′/31)/4.5)
B = (31)((B′/31)/4.5)
Pixel Port Timing
for R′G′B′ >= 0.0812*31
The the timing and format of the output data and control signals is presented in the following sections.
R = (31)(((R′/31) + 0.099)/1.099)2.2
G = (31)(((G′/31) + 0.099)/1.099)2.2
B = (31)(((B′/31) + 0.099)/1.099)2.2
HSYNC AND VSYNC TIMING
The HSYNC and VSYNC output timing is VMI v1.4 compatible. Figures 4-7 illustrate the video timing. The leading edge of
HSYNC is synchronous to the video input signal and has a
fixed latency due to internal pipeline processing. The pulse
width of the HSYNC is defined by the END HSYNC register
36H, where the trailing edge of HSYNC has a programmable
delay of 0-510 CLK2 cycles from the leading edge.
for gamma = 2.8:
R = (31)(R′/31)2.8
G = (31)(G′/31)2.8
B = (31)(B′/31)2.8
16-Bit R′G′B′
The following YCbCr to R′G′B′ equations are used to maintain the proper black and white levels:
The leading edge of VSYNC is asserted approximately half
way through the first serration pulse of each field. For an odd
field, the trailing edge of VSYNC is 5±1 CLK2 cycles after the
trailing edge of the HSYNC that follows the last equalization
pulse. Refer to Figures 4 and 6. For an even field, the trailing
edge of VSYNC is 5±1 CLK2 cycles leading the leading edge
of the HSYNC that follows the last equalization pulse. Refer to
Figures 5 and 7.
R′ = 0.142(Y - 16) + 0.194(Cr - 128)
G′ = 0.288(Y - 16) - 0.201(Cr - 128) - 0.097(Cb - 128)
B′ = 0.142(Y - 16) + 0.245(Cb - 128)
The resulting 16-bit R′G′B′ data has a range of 0 to 31 for R′
and B′, and a range of 0 to 63 for G′. Values less than 0 are
made 0; R′ and B′ values greater than 31 are made 31, G′
values greater than 63 are made 63.
FIELD TIMING
When field information can be determined from the input
video source, the FIELD output pin reflects the video source
The 16-bit R′G′B′ data may be converted to 16-bit linear
RGB, using the following equations. Although the PAL speci-
8
HMP8116
field state. When field information cannot be determined
from the input video source, the FIELD output pin alternates
its state at the beginning of each field. FIELD changes state
5±1 CLK2 cycles before the the leading edge of VSYNC.
NTSC(M)
LINE #
524
525
1
2
3
4
5
6
7
8
9
10
PAL(M)
LINE #
521
522
523
524
525
1
2
3
4
5
6
7
VIDEO
INPUT
HSYNC
VSYNC
FIELD
‘ODD’ FIELD
‘EVEN’ FIELD
NOTE:
3. The trailing edge of VSYNC is 5±1 clocks after the trailing edge of HSYNC to be VMI compatible and to indicate a transition to an odd field.
FIGURE 4. NTSC(M) AND PAL(M) HSYNC, VSYNC AND FIELD TIMING DURING AN EVEN TO ODD FIELD TRANSITION
NTSC(M)
LINE #
PAL(M)
LINE #
262
263
264
265
266
267
268
269
270
271
272
273
259
260
261
262
263
264
265
266
267
268
269
270
VIDEO
INPUT
HSYNC
VSYNC
FIELD
‘ODD’ FIELD
‘EVEN’ FIELD
NOTE:
4. The trailing edge of VSYNC is 5±1 clocks after the leading edge of HSYNC to be VMI compatible and to indicate a transition to an even field.
FIGURE 5. NTSC(M) AND PAL(M) HSYNC, VSYNC AND FIELD TIMING DURING AN ODD TO EVEN FIELD TRANSITION
LINE #
621
622
623
624
625
1
2
3
4
5
6
7
VIDEO
INPUT
HSYNC
VSYNC
FIELD
‘ODD’ FIELD
‘EVEN’ FIELD
NOTE:
5. The trailing edge of VSYNC is 5±1 clocks after the trailing edge of HSYNC is to be VMI compatible and to indicate a transition to an odd field.
FIGURE 6. PAL(B,D,G,H,I,N,NC) HSYNC, VSYNC AND FIELD TIMING DURING AN EVEN TO ODD FIELD TRANSITION
9
HMP8116
LINE #
309
310
311
312
313
314
315
316
317
318
319
320
VIDEO
INPUT
HSYNC
VSYNC
FIELD
‘ODD’ FIELD
‘EVEN’ FIELD
NOTE:
6. The trailing edge of VSYNC is 5±1 clocks after the leading edge of HSYNC to be VMI compatible and to indicate a transition to an even field.
FIGURE 7. PAL(B,D,G,H,I,N,NC) HSYNC, VSYNC AND FIELD TIMING DURING AN ODD TO EVEN FIELD TRANSITION
BLANK AND DVALID TIMING
During active scan lines BLANK is negated when the horizontal pixel count matches the value in the END H_BLANK
register 32H. A count of 00H corresponds to the 50% point of
the leading edge of the sync tip after leaving the part.
BLANK is asserted when the horizontal pixel count matches
the value in the START H_BLANK register 31H/30H. Note
that horizontally, BLANK is programmable with two pixel resolution.
DVALID is asserted when P15-P0 contain valid data. The
timing and behavior of DVALID is dependent on the output
video format and the programmed values for bit 4
(DVLD_DCYC) and bit 5 (DVLD_LTC) of the GENLOCK
CONTROL register 04H. Refer to the specific output video
format sections that follow for the specific behavior for
DVALID.
START V_BLANK register 34H/33H and END V_BLANK register 35H determine which scan lines are blanked for each
field. During inactive scan lines, BLANK is asserted during the
entire scan line. Half-line blanking of the output video cannot
be done. Reference Figure 8 for active video timing and use
Table 2 for typical blanking programming values
BLANK is used to determine if the HMP8116 is generating
active video data. BLANK should be used in conjunction with
DVALID to capture digital data from the decoder. BLANK,
DVALID and the video data are output after the internal pipeline latency and synchronous with the rising edge of CLK2.
TABLE 2. TYPICAL VALUES FOR HBLANK AND VBLANK REGISTERS
VIDEO STANDARD
(MSB/LSB)
ACTIVE
PIXELS/
LINE
TOTAL
PIXELS/
LINE
LAST
PIXEL
COUNT
START
H_BLANK
(31H/30H)
END
H_BLANK
(32H)
START
V_BLANK
(34H/33H)
END
V_BLANK
(35H)
720
720
858
864
857 (0359H)
863 (035FH)
842 (034AH)
852 (0354H)
122 (7AH)
132 (84H)
259 (0103H)
310 (0136H)
19 (13H)
22 (16H)
640
768
780
944
779 (030BH)
943 (03AFH)
758 (02F6H)
922 (039AH)
118 (76H)
154 (9AH)
259 (0103H)
310 (0136H)
19 (13H)
22 (16H)
RECTANGULAR PIXELS
NTSC (M), PAL (M)
PAL (B, D, G, H, I,N, NC)
SQUARE PIXELS
NTSC (M), PAL (M)
PAL (B, D, G, H, I,N, NC)
10
HMP8116
NTSC M
PAL B, D, G, H, I, N, NC
LINES 1 - 22 NOT ACTIVE
LINES 1 - 22 NOT ACTIVE
ODD FIELD
SYNC AND
BACK
PORCH
240 ACTIVE LINES
PER FIELD
(LINES 23-262)
288 ACTIVE LINES
PER FIELD
(LINES 23 - 310)
VERTICAL
BLANKING
480 ACTIVE
LINES/FRAME
(NTSC, PAL M)
EVEN FIELD
LINES 263 - 284 NOT ACTIVE
LINES 311 - 335 NOT ACTIVE
FRONT
PORCH
240 ACTIVE LINES
PER FIELD
(LINES 285 - 524)
LINE 525
NOT ACTIVE
576 ACTIVE
LINES/FRAME
(PAL)
288 ACTIVE LINES
PER FIELD
(LINES 336 - 623)
NUMBER OF PIXELS
RECTANGULAR (SQUARE)
NTSC
LINES 624-625
NOT ACTIVE
PAL
TOTAL PIXELS
858 (780)
864 (944)
TOTAL PIXELS
ACTIVE PIXELS
720 (640)
720 (768)
ACTIVE PIXELS
NOTE:
7. The line numbering for PAL (M) followings NTSC (M) line count minus 3 per the video standards.
FIGURE 8. TYPICAL ACTIVE VIDEO REGIONS
TABLE 3. PIXEL OUTPUT FORMATS
PIN NAME
8-BIT, 4:2:2, YCbCr
16-BIT, 4:2:2, YCbCr
15-BIT, RGB, (5,5,5)
16-BIT, RGB, (5,6,5)
BT.656
P0
P1
P2
P3
P4
P5
P6
P7
0 [0]
0 [0]
0 [0]
0 [0]
0 [0]
0 [0]
0 [0]
0 [0]
Cb0, Cr0 [D0n+1]
Cb1, Cr1 [D1n+1]
Cb2, Cr2 [D2n+1]
Cb3, Cr3 [D3n+1]
Cb4, Cr4 [D4n+1]
Cb5, Cr5 [D5n+1]
Cb6, Cr6 [D6n+1]
Cb7, Cr7 [D7n+1]
B0 [D0n+1]
B1 [D1n+1]
B2 [D2n+1]
B3 [D3n+1]
B4 [D4n+1]
G0 [D5n+1]
G1 [D6n+1]
G2 [D7n+1]
B0 [D0n+1]
B1 [D1n+1]
B2 [D2n+1]
B3 [D3n+1]
B4 [D4n+1]
G0 [D5n+1]
G1 [D6n+1]
G2 [D7n+1]
0 [0]
0 [0]
0 [0]
0 [0]
0 [0]
0 [0]
0 [0]
0 [0]
P8
P9
P10
P11
P12
P13
P14
P15
Y0, Cb0, Cr0 [D0]
Y1, Cb1, Cr1 [D1]
Y2, Cb2, Cr2 [D2]
Y3, Cb3, Cr3 [D3]
Y4, Cb4, Cr4 [D4]
Y5, Cb5, Cr5 [D5]
Y6, Cb6, Cr6 [D6]
Y7, Cb7, Cr7 [D7]
Y0 [D0n]
Y1 [D1n]
Y2 [D2n]
Y3 [D3n]
Y4 [D4n]
Y5 [D5n]
Y6 [D6n]
Y7 [D7n]
G3 [D0n]
G4 [D1n]
R0 [D2n]
R1 [D3n]
R2 [D4n]
R3 [D5n]
R4 [D6n]
0 [D7n]
G3 [D0n]
G4 [D1n]
G5 [D2n]
R0 [D3n]
R1 [D4n]
R2 [D5n]
R3 [D6n]
R4 [D7n]
YCbCr Data,
Ancillary Data,
SAV and EAV
Sequences
[D0 - D7, where
P8 corresponds
to D0]
NOTE:
8. Definitions in brackets are port definitions during raw VBI data transfers. Refer to the section on teletext for more information on raw VBI.
PIXEL OUTPUT PORT
asserted indicates valid pixel data is present on the P15-P8
pixel outputs. DVALID is never asserted during the blanking
intervals. Refer to Figure 9.
Pixel data is output via the P0-P15 pins. Refer to Table 3 for
the output pin definition as a function of the output mode.
If DLVD_LTC=1, DVALID has the same internal timing as the
first mode, but is ANDed with the CLK2 signal, and the result
is output onto the DVALID pin. This results in a gated CLK2
signal being output during the active video time on active
scan lines. Refer to Figure 10.
8-BIT YCbCr OUTPUT
The DVALID output pin may be configured to operate in one
of two ways. The configuration is determined by the
DVLD_LTC bit (bit 4) of the GENLOCK CONTROL register
04H.
If 8-bit YCbCr data is generated, it is output following each
rising edge of CLK2. The YCbCr data is multiplexed as [Cb Y
Cr Y′ Cb Y Cr Y′...], with the first active data each scan line
containing Cb data. The pixel output timing is shown in Fig-
If DVLD_LTC=0, the DVALID output is continuously asserted
during the entire active video time on active scan lines if CLK2
is exactly 2x the desired output sample rate. DVALID being
11
HMP8116
ures 9 and 10.
is asserted and VBIVALID is deasserted, the YCbCr outputs
have a value of 16 for Y and 128 for Cb and Cr.
BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD
are output following the rising edge of CLK2. When BLANK
CLK
DVALID
BLANK
Cb0
P[15-8]
NOTE:
Y0
Cr0
Y1
Cb2
Y2
Cr2
Y3
Cb4
Y4
tDVLD
9. Y0 is the first active luminance pixel data of a line. Cb0 and Cr0 are first active chrominance pixel data in a line. Cb and Cr will alternate
every cycle due to the 4:2:2 subsampling. Pixel data is not output during the blanking period, but the values on the ports are forced to
blanking levels.
FIGURE 9. OUTPUT TIMING FOR 8-BIT YCbCr MODE (DVLD_LTC = 0)
CLK
DVALID
BLANK
Cb0
P[15-8]
NOTES:
Y0
Cr0
Y1
Cb2
Y2
Cr2
Y3
Cb4
Y4
tDVLD
10. Y0 is the first active luminance pixel data of a line. Cb0 and Cr0 are first active chrominance pixel data in a line. Cb and Cr will alternate
every cycle due to the 4:2:2 subsampling. Pixel data is not output during the blanking period, but the values on the ports are forced to
blanking levels.
11. When DVLD_LTC is set to 1, the polarity of DVALID needs to be set to active low, otherwise DVALID will stay low during active video and
be gated with the clock only during the blanking interval.
FIGURE 10. OUTPUT TIMING FOR 8-BIT YCbCr MODE (DVLD_LTC = 1)
16-BIT YCbCr, 15-BIT RGB, OR 16-RGB OUTPUT
In these output modes, DVALID may be configured to operate in one of four modes as controlled by the DVLD_LTC and
DVLD_DCYC bits of the GENLOCK CONTROL register
(04H). Bit 4 is the DVLD_LTC bit and bit 5 is the
DVLD_DCYC bit.
same as the first mode, with the exception that DVALID does
not have a 50% duty cycle. This mode is intended for backward compatibility with HMP8112(A) timing dependancies in
which DVALID did not have a 50% duty cycle timing and
other timing variations. The timing diagrams for this mode
can be found in figures 13 and 14.
If DVLD_LTC=0 and DVLD_DCYC=0 , DVALID is present
only during the active video time on active scan lines. Thus,
DVALID being asserted indicates valid pixel data is present
on the P0-P15 pixel outputs. DVALID is never asserted during the blanking intervals. In this mode DVALID will have a
50% duty cycle only during the active video times. The timing diagrams for this mode can be found in figures 11 and
12.
If DVLD_LTC=1 and DVLD_DCYC=0, DVALID is present the
entire line time on all scan lines. DVALID may occasionally
be negated for two consecutive CLK2 cycles just prior to
active video. In this mode DVALID is guaranteed have a 50%
duty cycle only during the active video times. The timing for
this mode differs from the timing shown in figures 11 and 12
only in that DVALID will also be asserted during the blanking
portion of the video line time as described above.
If DVLD_LTC=0 and DVLD_DCYC=1, DVALID behaves the
12
HMP8116
If DVLD_LTC=1 and DVLD_DCYC=1, DVALID is present
during the entire line time on all scan lines. DVALID is
asserted during the blanking intervals as needed to ensure a
constant number of total samples per line. The timing for this
mode differs from the timing shown in figures 13 and 14 only
in that DVALID will also be asserted during the blanking portion of the video line time as described above.
DVALID is asserted. Either linear or gamma-corrected RGB
data may be output. The pixel output timing is shown in Figures 11 to 14.
BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD
are output following the rising edge of CLK2. When BLANK
is asserted and VBIVALID is deasserted, the YCbCr outputs
have a value of 16 for Y and 128 for Cb and Cr; the RGB outputs have a value of 0.
If 16-bit YCbCr, 15-bit RGB data, or 16-bit RGB data is generated, it is output following the rising edge of CLK2 while
CLK
DVALID
BLANK
P15-P8
Y0
Y1
Y2
Y3
Y4
P7-P0
Cb0
Cr0
Cb2
Cr2
Cb4
tDVLD
NOTES:
12. Y0 is the first active luminance pixel data of a line. Cb0 and Cr0 are first active chrominance pixel data in a line. Cb and Cr will alternate
every cycle due to the 4:2:2 subsampling.
13. BLANK is asserted per Figure 8.
FIGURE 11. OUTPUT TIMING FOR 16-BIT YCbCr MODE (DVLD_LTC = 0, DVLD_DCYC = 0)
CLK
DVALID
P15-P11
[P14-P10]
R0
R1
R2
R3
R4
P10-P5
[P9-P5]
G0
G1
G2
G3
G4
P4-P0
B0
B1
B2
B3
B4
tDVLD
NOTE:
14. BLANK is asserted per Figure 8.
FIGURE 12. OUTPUT TIMING FOR 16-BIT [15-BIT] RGB MODE (DVLD_LTC = 0, DVLD_DCYC = 0)
13
HMP8116
CLK
DVALID
P15-P8
P7-P0
Y0
Y1
Y2
Y3
Y4
Cb0
Cr0
Cb2
Cr2
Cb4
tDVLD
NOTES:
15. Y0 is the first active luminance pixel of a line. Cb0 and Cr0 are first active chrominance pixels in a line. Cb and Cr will alternate every
cycle due to the 4:2:2 subsampling.
16. BLANK is asserted per Figure 8.
17. DVALID is asserted for every valid pixel during both active and blanking regions. DVALID is not a 50% duty cycle synchronous output and
will appear to jitter as the Output Sample Rate converter adjusts the output timing for various data rates and clock frequency inputs.
FIGURE 13. OUTPUT TIMING FOR 16-BIT YCbCr MODE (DVLD_LTC = 0, DVLD_DCYC = 1)
CLK
DVALID
BLANK
P15-P11
[P14-P10]
R0
R1
R2
R3
R4
P10-P5
[P9-P5]
G0
G0
G2
G2
G4
P4-P0
B0
B1
B2
B3
B4
NOTES:
tDVLD
18. BLANK is asserted per Figure 8.
19. DAVLID is asserted for every valid pixel during both active and blanking regions. DVALID is not a 50% duty cycle synchronous output
and will appear to jitter as the Output Sample Rate converter adjusts the output timing for various data rates and clock frequency inputs.
FIGURE 14. OUTPUT TIMING FOR 16-BIT [15-BIT] RGB MODE (DVLD_LTC = 0, DVLD_DCYC = 1)
8-BIT BT.656 OUTPUT
During the blanking intervals, the YCbCr outputs have a
value of 16 for Y and 128 for Cb and Cr, unless ancillary data
is present.
If BT.656 data is generated, it is output following each rising
edge of CLK2. The BT.656 EAV and SAV formats are shown
in Table 4 and the pixel output timing is shown in Figure 15.
The EAV and SAV timing is determined by the programmed
horizontal and vertical blank timing
Due to the use of digital PLLs and source video timing the
total # of samples per line may not equal exactly 1716
(NTSC) or 1728 (PAL). The active video portion of the
BT.656 data stream is always exactly 1440 continous samples. Any line-to-line timing difference from nominal # of
samples per line, plus or minus, is accomodated in the horizontal blanking interval.
BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD
are output following the rising edge of CLK2.
For proper operation, CLK2 must be exactly 2x the desired
output sample rate. The DVALID output is continuously
asserted during the entire active video time.
14
HMP8116
.
CLK
DVALID
BLANK
P[15-8]
FF
00
00
Status
Cb0
Y0
Cr0
Y1
Cb2
Y2
tDVLD
NOTES:
20. Y0 is the first active luminance pixel data of a line. Cb0 and Cr0 are first active chrominance pixel data in a line. Cb and Cr will alternate
every cycle due to the 4:2:2 subsampling. Pixel data is not output during the blanking period.
21. Notice that DVALID is not asserted during the preamble and that BLANK is still asserted.
22. See table 4 for Status bit definitions.
FIGURE 15. OUTPUT TIMING FOR 8-BIT BT.656 MODE
TABLE 4. BT.656 EAV AND SAV SEQUENCES
PIXEL INPUT
P15
P14
P13
P12
P11
P10
P9
P8
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
F
V
H
P3
P2
P1
P0
Preamble
Status Word
NOTES:
23. P3 = V xor H; P2 = F xor H; P1 = F xor V; P0 = F xor V xor H
24. F: “0” = field 1; “1” = field 2
25. V: “1” during vertical blanking
26. H: “0” at SAV (start of active video); “1” at EAV (end of active video)
Advanced Features
The closed caption decoder monitors the appropriate scan
lines looking for the clock run-in and start bits used by captioning. If found, it locks to the clock run-in, the caption data
is sampled and loaded into shift registers, and the data is
then transferred to the caption data registers.
In addition to digitizing an analog video signal the HMP8116
has hardware to process different types of Vertical Blanking
Interval (VBI) data as described in the following sections.
If the clock run-in and start bits are not found, it is assumed
the scan line contains video data unless other VBI information is detected, such as teletext.
“SLICED” VBI DATA CAPTURE
The HMP8116 implements “sliced” data capture of select
types of VBI data. The VBI decoders incorporate detection
hysteresis to prevent them from rapidly turning on and off
due to noise and transmission errors. In order to handle realworld signals, the VBI decoders also compensate for DC offsets and amplitude variations.
Once the clock run-in and start bits are found on the appropriate scan line for four consecutive odd fields, the Closed
Captioning odd field Detect status bit is set to “1”. It is reset
to “0” when the clock run-in and start bits are not found on
the appropriate scan lines for four consecutive odd fields.
CLOSED CAPTIONING
During closed captioning capture, the scan lines containing
captioning information are monitored. If closed captioning is
enabled and captioning data is present, the caption data is
loaded into the caption data registers.
Once the clock run-in and start bits are found on the appropriate scan line for four consecutive even fields, the Closed
Captioning even field Detect status bit is set to “1”. It is reset
to “0” when the clock run-in and start bits are not found on
the appropriate scan lines for four consecutive even fields.
Detection of Closed Captioning
Reading the Caption Data
15
HMP8116
loaded into the WSS data registers.
The caption data registers may be accessed in two ways: via
the I2C interface or as BT.656 ancillary data.
Detection of WSS
Captioning Disabled on Both Lines
The WSS decoder monitors the appropriate scan lines looking for the run-in and start codes used by WSS. If found, it
locks to the run-in code, the WSS data is sampled and
loaded into shift registers, and the data is then transferred to
the WSS data registers.
In this case, any caption data present is ignored.
The Caption odd field Read status bit and the Caption even
field Read status bit are always a “0”.
Odd Field Captioning
If the run-in and start codes are not found, it is assumed the
scan line contains video data unless other VBI information is
detected, such as teletext.
In this case, any caption data present on line 284 (or line 281
or 335 in the PAL modes) is ignored. Caption data present
on line 21 (or line 18 or 22 in the PAL modes) is captured
into a shift register then transferred to CLOSED
CAPTION_ODD_A
register
20H
and
CLOSED
CAPTION_ODD_B register 21H.
Once the run-in and start codes are found on the appropriate
scan line for four consecutive odd fields, the WSS Line 20
Detect status bit is set to “1”. It is reset to “0” when the run-in
and start codes are not found on the appropriate scan lines
for four consecutive odd fields.
The Caption even field Read status bit is always a “0”. The
Caption odd field Read status bit is set to “1” after data has
been transferred from the shift register to the CLOSED
CAPTION_ODD_A and CLOSED CAPTION_ODD_B registers. It is set to “0” after the data has been read out.
Once the run-in and start codes are found on the appropriate
scan line for four consecutive even fields, the WSS Line 283
Detect status bit is set to “1”. It is reset to “0” when the clock
run-in and start bits are not found on the appropriate scan
lines for four consecutive even fields.
Even Field Captioning
Reading the WSS Data
In this case, any caption data present on line 21 (or line 18
or 22 in the PAL modes) is ignored. Caption data present on
line 284 (or line 281 or 335 in the PAL modes) is captured
into a shift register then transferred to CLOSED
CAPTION_EVEN_A
register
22H
and
CLOSED
CAPTION_EVEN_B register 23H.
The WSS data registers may be accessed in two ways: via
the I2C interface or as BT.656 ancillary data.
WSS Disabled on Both Lines
In this case, any WSS data present is ignored.
The Caption odd field Read status bit is always a “0”. The
Caption even field Read status bit is set to “1” after data has
been transferred from the shift register to the CLOSED
CAPTION_EVEN_A and CLOSED CAPTION_EVEN_B registers. It is set to “0” after the data has been read out.
The WSS odd field Read status bit and the WSS even field
Read status bit are always a “0”.
Odd Field WSS
In this case, any WSS data present on line 283 (or line 280
or 336 in the PAL modes) is ignored. WSS data present on
line 20 (or line 17 or 23 in the PAL modes) is captured into a
shift register then transferred to the WSS_ODD_A and
WSS_ODD_B data registers.
Odd and Even Field Captioning
Caption data present on line 21 (or line 18 or 22 in the PAL
modes) is captured into a shift register then transferred to
the
CLOSED
CAPTION_ODD_A
and
CLOSED
CAPTION_ODD_B registers. Caption data present on line
284 (or line 281 or 335 in the PAL modes) is captured into a
shift register then transferred to the CLOSED
CAPTION_EVEN_A and CLOSED CAPTION_EVEN_B registers.
The WSS even field Read status bit is always a “0”. The
WSS odd field Read status bit is set to “1” after data has
been
transferred from the shift register to the WSS_ODD_A and
WSS_ODD_B registers. It is set to “0” after the data has
been read out.
The Caption odd field Read status bit is set to “1” after data
has been transferred from the shift register to the CLOSED
CAPTION_ODD_A and CLOSED CAPTION_ODD_B registers. It is set to “0” after the data has been read out.
Even Field WSS
In this case, any WSS data present on line 20 (or line 17 or
23 in the PAL modes) is ignored. WSS data present on line
283 (or line 280 or 336 in the PAL modes) is captured into a
shift register then transferred to the WSS_EVEN_A and
WSS_EVEN_B data registers.
The Caption even field Read status bit is set to “1” after data
has been transferred from the shift register to the CLOSED
CAPTION_EVEN_A and CLOSED CAPTION_EVEN_B registers. It is set to “0” after the data has been read out.
The WSS odd field Read status bit is always a “0”. The WSS
even field Read status bit is set to “1” after data has been
transferred from the shift register to the WSS_EVEN_A and
WSS_EVEN_B registers. It is set to “0” after the data has
been read out.
WIDESCREEN SIGNALLING (WSS)
During WSS capture (ITU-R BT.1119 and EIAJ CPX-1204),
the scan lines containing WSS information are monitored. If
WSS is enabled and WSS data is present, the WSS data is
16
HMP8116
Real-Time Control Interface (RTCI) information. Teletext and
RTCI data is only available as BT.656 ancillary data.
Odd and Even WSS
WSS data present on line 20 (or line 17 or 23 in the PAL
modes) is captured into a shift register then transferred to
the WSS_ODD_A and WSS_ODD_B registers. WSS data
present on line 283 (or line 280 or 336 in the PAL modes) is
captured into a shift register then transferred to the
WSS_EVEN_A and WSS_EVEN_B registers.
VBIVALID OUTPUT TIMING
The VBIVALID output is asserted when outputting closed
captioning, widescreen signalling, teletext or RTCI data as
BT.656 ancillary data. It is asserted during the entire BT.656
ancillary data packet time, including the preamble.
The WSS odd field Read status bit is set to “1” after data has
been transferred from the shift register to the WSS_ODD_A
and WSS_ODD_B registers. It is set to “0” after the data has
been read out.
BT.656 CLOSED CAPTIONING AND WIDE SCREEN
SIGNALLING
Table 5 illustrates the format when outputting the caption
data registers as BT.656 ancillary data. The ancillary data is
present during the horizontal blanking interval after the line
containing the captioning information.
The WSS even field Read status bit is set to “1” after data
has been transferred from the shift register to the
WSS_EVEN_A and WSS_EVEN_B registers. It is set to “0”
after the data has been read out.
Table 6 illustrates the format when outputting the WSS data
registers as BT.656 ancillary data. The ancillary data is
present during the horizontal blanking interval after the line
containing the WSS information.
BT.656 ANCILLARY DATA
Through the BT.656 interface the HMP8116 can generate
non-active video data which contains CC, WSS, teletext or
CLK
VBIVALID
P[15-8]
00
FF
FF
DATA ID
BLK #
# BYTES/4
BYTE #1
BYTE #2
BYTE #3
BYTE #4
tDVLD
NOTES:
27. BT.656 VBI ancillary starts with a 00H, FFH and FFH sequence which is opposite to the SAV/EAV sequence of FFH, 00H and 00H.
28. During active VBI data intervals, DVALID is deasserted and BLANK is asserted.
FIGURE 16. OUTPUT TIMING FOR BT.656 VBI DATA TRANSFERS (CC, WSS, TELETEXT, RTCI)
TABLE 5. READING THE CLOSED CAPTION DATA AS BT.656 ANCILLARY DATA
PIXEL OUTPUT
P15
P14
P13
P12
P11
P10
P9
P8
Preamble
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Data ID
P14
ep
1
1
0
0
0
0 = odd field data
1 = even field data
Data Block Number
P14
ep
0
0
0
0
0
1
Data Word Count
P14
ep
0
0
0
0
0
1
Caption Data
P14
ep
0
0
bit 15
bit 14
bit 13
bit 12
P14
ep
0
0
bit 11
bit 10
bit 9
bit 8
P14
ep
0
0
bit 7
bit 6
bit 5
bit 4
P14
ep
0
0
bit 3
bit 2
bit 1
bit 0
P14
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CRC
NOTES:
29. ep = even parity for P8-P13.
30. CRC = Sum of P8-P14 of Data ID through last user data word. Preset to all zeros, carry is ignored.
17
HMP8116
TABLE 6. OUTPUTTING THE SLICED WSS DATA AS BT.656 ANCILLARY DATA
PIXEL OUTPUT
P15
P14
P13
P12
P11
P10
P9
P8
Preamble
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Data ID
P14
ep
1
1
0
0
1
0 =odd field data
1 =even field data
Data Block Number
P14
ep
0
0
0
0
0
1
Data Word Count
P14
ep
0
0
0
0
1
0
WSS Data
P14
ep
0
0
0
0
bit 13
bit 12
P14
ep
0
0
bit 11
bit 10
bit 9
bit 8
P14
ep
0
0
bit 7
bit 6
bit 5
bit 4
P14
ep
0
0
bit 3
bit 2
bit 1
bit 0
P14
ep
0
0
0
0
bit 5
bit 4
P14
ep
0
0
bit 3
bit 2
bit 1
bit 0
P14
ep
0
0
0
0
0
0
P14
ep
0
0
0
0
0
0
P14
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
WSS CRC
Data
CRC
NOTES:
31. ep = even parity for P8-P13.
32. WSS CRC data = “00 0000” during PAL operation.
33. CRC = Sum of P8-P14 of Data ID through last user data word. Preset to all zeros, carry is ignored.
TELETEXT
Table 7 illustrates the teletext BT.656 ancillary data format
and Figure 16 depicts the portion of the incoming teletext
signal which is sliced and output as part of the ancillary data
stream. The teletext data is present during the horizontal
blanking interval after the line containing the teletext information. The actual BT.656 bytes that contain teletext data
only contain 4 bits of the actual data packet. Note that only
the data packet of Figure 17 is sent as ancillary data; the
clock run-in is not included in the data stream.
The HMP8116 supports ITU-R BT.653 625-line and 525-line
teletext system B, C and D capture. NABTS (North American
Broadcast Teletext Specification) is the same as BT.653 525line system C, which is also used to transmit Intel Intercast™
information. WST (World System Teletext) is the same as
BT.653 system B. Figure 17 shows the basic structure of a
video signal that contains teletext data.
The scan lines containing teletext information are monitored.
If teletext is enabled and teletext data is present, the teletext
data is output as BT.656 ancillary data.
Detection of Teletext
The teletext decoder monitors the scan lines, looking for the
16-bit clock run-in (sometimes refered to as the clock synchronization code) used by teletext. If found, it locks to the
clock run-in, the teletext data is sampled and loaded into
shift registers, and the data is then transferred to internal
holding registers.
If the clock run-in is not found, it is assumed the scan line
contains video data unless other VBI information is detected,
such as WSS.
If a teletext clock run-in is found before line 23 or line 289 for
NTSC and (M) PAL, or line 336 for (B, D, G, H, I, N, NC) PAL,
the VBI Teletext Detect status bit is immediately set to “1”. If
not found by these lines, the status bit is immediately reset to
“0”.
Accessing the Teletext Data
The teletext data must be output as BT.656 ancillary data.
The I2C interface does not have the bandwidth to output
teletext information when needed.
Intercast™ is a trademark of Intel Corporation.
18
HMP8116
CLOCK
RUN-IN
DATA PACKET
Bit 0
MSB
NOTES:
34. The MSB is bit number: 271 for system C, 279 for system B 525-line and 343 for system B 625-line.
35. The clock run-in is 16 bits wide for both systems and is not included in the BT.656 ancillary data stream.
36. The bit rate is 5.727272 Mbits/second for system B and C on 525/60 systems and 6.9375 and 5.734375 Mbits/second respectively for
625/50 systems.
FIGURE 17. TELETEXT VBI VIDEO SIGNAL
TABLE 7. OUTPUTTING THE SLICED TELETEXT DATA AS BT.656 ANCILLARY DATA
PIXEL INPUT
P15
P14
P13
P12
P11
P10
P9
P8
Preamble
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Data ID
P14
ep
1
1
0
1
0
0
Data Block Number
P14
ep
0
0
0
0
0
1
Data Word Count
P14
ep
0
1
0
1
1
0
Teletext Data
(B, 625-line = 43 bytes)
(B, 525-line = 35 bytes)
(C = 34 bytes)
P14
ep
0 = 525-line
1 = 625-line
0 = system B
1 = system C
bit 343
bit 342
bit 341
bit 340
P14
ep
0
0
bit 339
bit 338
bit 337
bit 336
P14
ep
0
0
bit 7
bit 6
bit 5
bit 4
P14
ep
0
0
bit 3
bit 2
bit 1
bit 0
P14
ep
0
0
0
0
0
0
:
Reserved
CRC
P14
ep
0
0
0
0
0
0
P14
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
NOTES:
37. ep = even parity for P8-P13.
38. CRC = Sum of P8-P14 of Data ID through last user data word. Preset to all zeros, carry is ignored.
39. For 525-line system B, bits 280-343 are “0”.
40. For system C, bits 272-343 are “0”.
“Raw” VBI Data Capture
lines 10 and 272, and the last possible lines are the last
blanked scan lines. Lines 1-9 and 264-271 are always
blanked.
“Raw” data capture of VBI data during blanked scan lines
may be optionally implemented. In this instance, the active
line time of blanked scan lines are sampled at the CLK2 rate,
and output onto the pixel outputs. This permits software
decoding of the VBI data to be done.
During PAL (B, D, G, H, I, N, NC) operation, the first possible
line of VBI data are lines 6 and 318, and the last possible
lines are the last blanked scan lines. Lines 623-5 and 311317 are always blanked.
The line mask registers specify on which scan lines to generate “raw” VBI data. If the RAW VBI All bit is enabled, all the
video lines are treated as raw VBI data, excluding the equalization and serration lines.
During PAL (M) operation, the first possible line of VBI data
is lines 7 and 269, and the last possible lines are the last
blanked scan lines. Lines 523-6 and 261-268 are always
blanked.
The start and end timing of capturing “raw” VBI data on a
scan line is determined by the Start and End Raw VBI Registers. This allows the proper capture of “raw” VBI data
regardless of the BLANK# output timing for active video.
REAL TIME CONTROL INTERFACE
The Real Time Control Interface (RTCI) outputs timing information for a NTSC/PAL encoder as BT.656 ancillary data.
This allows the encoder to generate “clean” output video.
The blanking level is subtracted from the “raw” VBI data
samples, and the result is output onto the pixel outputs.
Note both “sliced” and “raw” VBI data may be available on
the same line.
During NTSC operation, the first possible line of VBI data is
19
HMP8116
RTCI information via BT.656 ancillary data is shown in Table
8. If enabled, this transfer occurs once per line and is completed before the start of the SAV sequence.
The PSW bit is always a “0” for NTSC encoding. During PAL
encoding, it indicates the sign of V (“0” = negative; “1” = positive) for that scan line.
TABLE 8. OUTPUTTING RTCI AS BT.656 ANCILLARY DATA
PIXEL INPUT
P15
P14
P13
P12
P11
P10
P9
P8
Preamble
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Data ID
P14
ep
1
1
0
1
0
1
Data Block Number
P14
ep
0
0
0
0
0
1
Data Word Count
P14
ep
0
0
0
0
1
1
HPLL
Increment
P14
ep
0
0
0
0
0
0
P14
ep
0
0
0
0
0
0
P14
ep
0
0
0
0
0
0
P14
ep
0
0
0
0
0
0
P14
ep
PSW
0
bit 31
bit 30
bit 29
bit 28
P14
ep
F2 = 0
F1 = 0
bit 27
bit 26
bit 25
bit 24
P14
ep
0
0
bit 7
bit 6
bit 5
bit 4
FSCPLL
Increment
:
CRC
P14
ep
0
0
bit 3
bit 2
bit 1
bit 0
P14
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
NOTES:
41. ep = even parity for P8-P13.
42. CRC = Sum of P8-P14 of Data ID through last user data word. Preset to all zeros, carry is ignored.
20
HMP8116
During I2C write cycles, the first data byte after the slave
address is treated as the control register sub address and is
written into the internal address register. Any remaining data
bytes sent during an I2C write cycle are written to the control
registers, beginning with the register specified by the
address register as given in the first byte. The address register is then autoincremented after each additional data byte
sent on the I2C bus during a write cycle. Writes to reserved
bits within registers or reserved registers are ignored.
Host Interface
All internal registers may be written to or read by the host
processor at any time, except for those bits identified as
read-only. The bit descriptions of the control registers are
listed in Tables 8-57.
The HMP8116 supports the fast-mode (up to 400 kbps) I2C
interface consisting of the SDA and SCL pins. The device
acts as a slave for receiving and transmitting data over the
serial interface. When the interface is not active, SCL and
SDA must be pulled high using external 4kΩ pull-up resistors. The slave address for the HMP8116 is 88H.
In order to perform a read from a specific control register
within the HMP8116, an I2C bus write must first be performed to properly setup the address register. Then an I2C
bus read can be performed to read from the desired control
register(s). As a result of needing the write cycle for a read
cycle there are actually two START conditions as shown in
Figure 20. The address register is then autoincremented
after each byte read during the I2C read cycle. Reserved
registers return a value of 00H .
Data is placed on the SDA line when the SCL line is low and
held stable when the SCL line is pulled high. Changing the
state of the SDA line while SCL is high will be interpreted as
either an I2C bus START or STOP condition as indicated by
Figure 19.
tSU:DATA
tBUF
SDA
tHD:DATA
SCL
tLOW
tHIGH
tR
tF
tSU:STOP
FIGURE 18. I2C TIMING DIAGRAM
SDA
SCL
8
1-7
S
START
CONDITION
9
R/W
ADDRESS
1-7
ACK
8
DATA
9
P
ACK
STOP
CONDITION
FIGURE 19. I2C SERIAL DATA FLOW
DATA WRITE
1000 1000
S
CHIP ADDR
FROM MASTER
A
SUB ADDR
A
0x88
DATA READ
S
DATA
A
REGISTER
POINTED
TO BY
SUB ADDR
DATA
A
P
FROM HMP8116
OPTIONAL FRAME
MAY BE REPEATED
n TIMES
1000 1000 (R/W)
CHIP ADDR
0x88
A
SUB ADDR
A
S
CHIP ADDR
A
0x89
DATA
REGISTER
POINTED
TO BY
SUB ADDR
A
DATA
OPTIONAL FRAME
MAY BE REPEATED
n TIMES
FIGURE 20. REGISTER WRITE/READ FLOW
21
NA
P
S = START CYCLE
P = STOP CYCLE
A = ACKNOWLEDGE
NA = NO ACKNOWLEDGE
HMP8116
HMP8116 Control Registers
TABLE 9. 8116 REGISTER SUMMARY (Continued)
TABLE 9. 8116 REGISTER SUMMARY
SUBADDRESS
00H
01H
CONTROL REGISTER
PRODUCT ID
INPUT FORMAT
RESET/
DEFAULT
VALUE
RESET/
DEFAULT
VALUE
SUBADDRESS
15H
34H
START V_BLANK HIGH
01H
18H
35H
END V_BLANK
12H
36H
END HSYNC
40H
HSYNC DETECT WINDOW
FFH
CONTROL REGISTER
02H
OUTPUT FORMAT
00H
03H
OUTPUT CONTROL
00H
37H
04H
GENLOCK CONTROL
01H
38H-3FH
Reserved
-
40H-7FH
Test and Unused
-
05H
ANALOG INPUT CONTROL
00H
06H
COLOR PROCESSING
52H
07H
RESERVED
08H
LUMA PROCESSING
04H
09H
Reserved
0AH
SLICED VBI DATA ENABLE
00H
-
0BH
SLICED VBI DATA OUTPUT
00H
0CH
VBI DATA STATUS
00H
0DH
Reserved
0EH
VIDEO STATUS
00H
0FH
INTERRUPT MASK
00H
10H
INTERRUPT STATUS
00H
11H
RAW VBI CONTROL
00H
12H
RAW VBI START COUNT
7AH
13H
RAW VBI STOP COUNT(LSB)
4AH
14H
RAW VBI STOP COUNT(MSB)
03H
15H
RAW VBI Line Mask_7_0
FEH
16H
RAW VBI Line Mask_15_8
1FH
17H
RAW VBI Line Mask_18_16
00H
18H
BRIGHTNESS
00H
-
19H
CONTRAST
80H
1AH
HUE
00H
1BH
SATURATION
80H
1CH
COLOR GAIN
40H
1DH
Reserved
1EH
SHARPNESS
10H
1FH
HOST CONTROL
00H
20H
CLOSED CAPTION_ODD_A
80H
21H
CLOSED CAPTION_ODD_B
80H
22H
CLOSED CAPTION_EVEN_A
80H
23H
CLOSED CAPTION_EVEN_B
80H
24H
WSS_ODD_A
00H
25H
WSS_ODD_B
00H
26H
WSS_CRC_ODD
00H
27H
WSS_EVEN_A
00H
28H
WSS_EVEN_B
00H
29H
WSS_CRC_EVEN
00H
2AH-2FH
Reserved
-
-
30H
START H_BLANK LOW
4AH
31H
START H_BLANK HIGH
03H
32H
END H_BLANK
7AH
33H
START V_BLANK LOW
02H
22
HMP8116
23
HMP8116
TABLE 10. PRODUCT ID REGISTER
SUB ADDRESS = 00H
BIT
NO.
7-0
FUNCTION
Product ID
DESCRIPTION
This 8-bit register specifies the last two digits of the product number.
It is a read-only register. Data written to it is ignored.
RESET
STATE
16H
TABLE 11. INPUT FORMAT REGISTER
SUB ADDRESS = 01H
BIT
NO.
7
6-5
FUNCTION
DESCRIPTION
Reserved
RESET STATE
0B
Video Timing Standard
These bits are read only unless D4 = “0”.
00 = (M) NTSC
01 = (B, D, G, H, I, N) PAL
10 = (M) PAL
11 = Combination (N) PAL; also called (NC) PAL
00B
4
Auto Detect
Video Standard
0 = Manual selection of video timing standard
1 = Auto detect of video timing standard
1B
3
Setup Select
Typically, this bit should be a “1” during (M) NTSC and (M, N) PAL
operation. Otherwise, it should be a “0”.
0 = Video source has a 0 IRE blanking pedestal
1 = Video source has a 7.5 IRE blanking pedestal
1B
2-1
0
Reserved
Adaptive Sync
Slice Enable
00B
This bit specifies whether to use fixed or adaptive sync slicing. Adaptive sync slicing automatically determines the mid-point of the sync
amplitude to determine timing.
0 = Fixed sync slicing
1 = Adaptive sync slicing
1B
TABLE 12. OUTPUT FORMAT REGISTER
SUB ADDRESS = 02H
BIT
NO.
FUNCTION
DESCRIPTION
RESET STATE
7-5
Output
Color
Format
000 = 16-bit 4:2:2 YCbCr
001 = 8-bit 4:2:2 YCbCr
010 = 8-bit BT.656
011 = 15-bit RGB
100 = 16-bit RGB
101 = reserved
110 = reserved
111 = reserved
000B
4-3
RGB
Gamma
Select
These bits are ignored except during RGB output modes.
00 = Linear RGB (gamma of input source = 2.2)
01 = Linear RGB (gamma of input source = 2.8)
10 = Gamma-corrected RGB (gamma = gamma of input source)
11 = reserved
00B
2-1
Output
Color
Select
00 = Normal operation
01 = Output blue field
10 = Output black field
11 = Output 75% color bars
00B
Vertical Pixel
Siting
This bit specifies whether or not the chrominance pixels have a halfline pixel offset from their associated luminance pixels.
0 = Half-line offset
1 = Aligned
0B
0
24
HMP8116
TABLE 13. OUTPUT CONTROL REGISTER
SUB ADDRESS = 03H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7
Video Data
Output Enable
This bit is used to enable the P0-P15 outputs.
0 = Outputs 3-stated
1 = Outputs enabled
0B
6
Video Timing
Output Enable
This bit is used to enable the HSYNC, VSYNC, BLANK, FIELD, VBIVALID, DVALID, and
INTREQ outputs.
0 = Outputs 3-stated
1 = Outputs enabled
0B
5
FIELD Polarity
0 = Active low (low during odd fields)
1 = Active high (high during odd fields)
0B
4
Polarity
BLANK
0 = Active low (low during blanking)
1 = Active high (high during blanking)
0B
3
HSYNC Polarity
0 = Active low (low during horizontal sync)
1 = Active high (high during horizontal sync)
0B
2
VSYNC Polarity
0 = Active low (low during vertical sync)
1 = Active high (high during vertical sync)
0B
1
DVALID Polarity
0 = Active low (low during valid pixel data)
1 = Active high (high during valid pixel data)
0B
0
VBIVALID
Polarity
0 = Active low (low during VBI data)
1 = Active high (high during VBI data)
0B
25
HMP8116
TABLE 14. GENLOCK CONTROL REGISTER
SUB ADDRESS = 04H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7
Aspect Ratio
Mode
0 = Rectangular (BT.601) pixels
1 = Square pixels
0B
6
Freeze Output
Timing Enable
Setting this bit to a “1” freezes the output timing at the end of the field. Resetting this bit
to a “0” resumes normal operation at the start of the next field.
0 = Normal operation
1 = Freeze output timing
0B
5
DVALID Duty Cycle
Control
(DVLD_DCYC)
This bit is ignored during the 8-bit YCbCr and BT.656 output modes.
During 16-bit YCbCr, 15-bit RGB, or 16-bit RGB output modes, this bit is defined as:
0 = DVALID has 50/50 duty cycle at the pixel output datarate
1 = DVALID goes active based on linelock. This will cause DVALID to not have a 50/50
duty cycle. This bit is intended to be used in maintaining backward compatibilty with the
HMP8112A DVALID output timing.
0B
4
DVALID Line Timing During 16-bit YCbCr, 15-bit RGB, or 16-bit RGB output modes, this bit is defined as:
Control
0 = DVALID present only during active video time on active scan lines
(DVLD_LTC)
1 = DVALID present the entire scan line time on all scan lines
During the 8-bit YCbCr and BT.656 output modes, this bit defines the DVALID output signal as:
0 = Normal timing
1 = DVALID signal ANDed with CLK2
0B
3
Missing HSYNC
Detect Select
This bit specifies the number of missing horizontal sync pulses before the device goes into
the horizontal lock acquisition mode. In mode “0”, the default value of the HPLL Adjust
register should be used. In mode “1”, the typical values the HPLL Adjust register should
be 10H to 20H.
0 = 12 pulses
1 = 1 pulse
0B
2
Missing VSYNC
Detect Select
This bit specifies the number of missing vertical sync pulses before the device goes into
the vertical lock acquisition mode.
0 = 3 pulses
1 = 1 pulse
0B
1-0
CLK2 Frequency
This bit indicates the frequency of the CLK2 input clock.
00 = 24.54MHz
01 = 27.0MHz
10 = 29.5MHz
11 = Reserved
01B
26
HMP8116
TABLE 15. ANALOG INPUT CONTROL REGISTER
SUB ADDRESS = 05H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-6
Lock Loss
Video Gain
Select
If bits 5-4 do not equal “01”, these bits indicate what mode the AGC circuitry will be after
loss of sync. If bits 5-4 equal “01”, these bits are ignored.
00 = Automatic gain control: bits 5-4 will be reset to “01”
01 = Maintain fixed gain: bits 5-4 will not be changed
10 = Normal AGC switching to fixed gain after lock achieved: bits 5-4 will not be reset to
“01” unless they indicated “freeze automatic gain control”
11 = reserved
00B
5-4
Video Gain
Control Select
If a value of “10”, the video gain adjust register is used to specify the amount of video gain
to be applied.
00 = Fixed 1x gain
01 = Automatic gain control
10 = Fixed gain control
11 = Freeze automatic gain control
01B
Digital Anti-Aliasing
Filter Control
0 = Internal digital anti-aliasing filter is active.
1 = Internal digital anti- aliasing filter is by-passed.
0B
Video Signal
Input Select
000 = NTSC/PAL 1
001 = NTSC/PAL 2
010 = NTSC/PAL 3
011 = S-video
100 = reserved
101 = reserved
110 = reserved
111 = reserved
3
2-0
000B
TABLE 16. COLOR PROCESSING REGISTER
SUB ADDRESS = 06H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-6
Color Gain
Control Select
If a value of “10”, the color gain adjust register is used to specify the amount of color gain
to be applied.
00 = No gain control (gain = 1x)
01 = Automatic gain control
10 = Fixed gain control
11 = Freeze automatic gain control
01B
5-4
Color Killer
Select
00 = Force color on
01 = Enable color killer
10 = reserved
11 = Force color off
01B
3-2
Color Coring
Select
Coring may be used to reduce low-level noise around zero (code 128) in the CbCr signals.
00 = No coring
01 = 1 code coring
10 = 2 code coring
11 = 3 code coring
00B
1
Contrast Control
Select
This bit specifies whether the contrast control affects just the Y data (“0”) or both the Y
and CbCr data (“1”). To avoid color shifts when changing contrast, this bit should be a “1”.
0 = Contrast controls only Y data
1 = Contrast controls Y and CbCr data
1B
0
Color Lowpass
Filter Select
This bit selects the bandwidth of the CbCr data.
0 = 850kHz
1 = 1.5MHz
0B
27
HMP8116
TABLE 17. LUMA PROCESSING REGISTER
SUB ADDRESS = 08H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-6
Y Filtering
Select
The chroma trap filter may be used to remove any residual color subcarrier information
from the Y channel. During S-video operation, it should be disabled. During PAL operation, it should be enabled. The 3MHz lowpass filter may be used to remove high-frequency
noise.
00 = No filtering
01 = Enable chroma trap filter
10 = Enable 3.0MHz lowpass filter
11 = reserved
00B
5-4
Black Level Y
Coring Select
Coring may be used to reduce low-level noise around black in the Y signal.
00 = No coring
01 = 1 code coring
10 = 2 code coring
11 = 3 code coring
00B
3-2
High Frequency Y
Coring Select
Coring may be used to reduce high-frequency low-level noise in the Y signal.
00 = No coring
01 = 1 code coring
10 = 2 code coring
11 = 3 code coring
01B
1-0
Sharpness
Frequency Select
If a value of “01” or “10”, the sharpness adjust register is used to specify the amount of
sharpness to be applied.
00 = Bypass sharpness control
01 = Maximum gain at 2.6MHz
10 = Maximum gain at color subcarrier frequency
11 = reserved
00B
TABLE 18. SLICED VBI DATA ENABLE REGISTER
SUB ADDRESS = 0AH
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-6
Sliced
Closed Captioning
Enable
00 = Closed caption disabled
01 = Closed caption enabled for odd fields: line 21 for NTSC, line 18 for (M) PAL, or line
22 for (B, D, G, H, I, N, NC) PAL
10 = Closed caption enabled for even fields: line 284 for NTSC, line 281 for (M) PAL, or
line 335 for (B, D, G, H, I, N, NC) PAL
11 = Closed caption enabled for both odd and even fields
00B
5-4
Sliced
WSS Enable
00 = WSS disabled
01 = WSS enabled for odd fields: line 20 for NTSC; line 17 for (M) PAL, or line 23 for (B,
D, G, H, I, N, NC) PAL
10 = WSS enabled for even fields: line 283 for NTSC, line 280 for (M) PAL, or line 336 for
(B, D, G, H, I, N, NC) PAL
11 = WSS enabled for both odd and even fields
00B
3-2
Sliced
Teletext
Enable
00 = Teletext disabled
01 = Teletext system B enabled
10 = Teletext system C enabled
11 = Teletext system D enabled
00B
1-0
Reserved
00B
28
HMP8116
TABLE 19. SLICED VBI DATA OUTPUT REGISTER
SUB ADDRESS = 0BH
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7
Sliced
Closed Caption
BT.656 Output
Enable
This bit specifies whether or not to output the caption data registers as BT.656 ancillary
data. It is ignored unless captioning is enabled. Access via the I2C interface is always
available.
0 = Do not output as BT.656 ancillary data
1 = Output as BT.656 ancillary data
0B
6
Sliced WSS
BT.656 Output
Enable
This bit specifies whether or not to output the WSS data registers as BT.656 ancillary
data. It is ignored unless WSS is enabled. Access via the I2C interface is always available.
0 = Do not output as BT.656 ancillary data
1 = Output as BT.656 ancillary data
0B
5
Sliced Teletext
BT.656 Output
Enable
This bit specifies whether or not to output teletext data as BT.656 ancillary data. It is ignored unless teletext is enabled.
0 = Do not output as BT.656 ancillary
1 = Output as BT.656 ancillary data
0B
4-1
0
Reserved
RTCI
BT.656 Output
Enable
0000B
This bit specifies whether or not to output RTCI data as BT.656 ancillary data.
0 = Do not output as BT.656 ancillary
1 = Output as BT.656 ancillary data
0B
TABLE 20. VBI DATA STATUS REGISTER
SUB ADDRESS = 0CH
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7
Closed Captioning
Odd Field
Detect Status
This bit is read-only. Data written to this bit is ignored.
0 = Closed captioning not detected
1 = Closed captioning detected
0B
6
Closed Captioning
Even Field
Detect Status
This bit is read-only. Data written to this bit is ignored.
0 = Closed captioning not detected
1 = Closed captioning detected
0B
5
WSS
Odd Field
Detect Status
This bit is read-only. Data written to this bit is ignored.
0 = WSS not detected
1 = WSS detected
0B
4
WSS
Even Field
Detect Status
This bit is read-only. Data written to this bit is ignored.
0 = WSS not detected
1 = WSS detected
0B
3
VBI Teletext
Detect Status
This bit is read-only. Data written to this bit is ignored.
0 = Teletext not detected during vertical blanking interval
1 = Teletext detected during vertical blanking interval
0B
2-0
Reserved
000B
29
HMP8116
TABLE 21. VIDEO STATUS REGISTER
SUB ADDRESS = 0EH
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7
Vertical Lock
Status
This bit is read-only. Data written to this bit is ignored.
0 = Not vertically locked
1 = Vertically locked
0B
6
Horizontal Lock
Status
This bit is read-only. Data written to this bit is ignored.
0 = Not horizontally locked
1 = Horizontally locked
0B
5
Color Lock
Status
This bit is read-only. Data written to this bit is ignored.
0 = Not color locked
1 = Color locked
0B
4
Input Video
Detect Status
This bit is read-only. Data written to this bit is ignored.
0 = Input video not detected on selected video input
1 = Input video detected on selected video input
0B
3-1
0
Reserved
Auto Detect
Video Standard
Status
000B
This bit is set when automatic detection of the video standard is enabled, and the
HMP8116 has determined the input format of the video signal. This bit is read-only. Data
written to this bit is ignored.
0 = Video standard not determined on selected video input
1 = Video standard determined on selected video input
0B
TABLE 22. INTERRUPT MASK REGISTER
SUB ADDRESS = 0FH
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7
Genlock Loss
Interrupt Mask
If this bit is a “1”, an interrupt is generated when genlock is lost.
0 = Interrupt disabled
1 = Interrupt enabled
0B
6
Input Signal Loss
Interrupt Mask
If this bit is a “1”, an interrupt is generated when a video signal is no longer detected on
the selected video input.
0 = Interrupt disabled
1 = Interrupt enabled
0B
5
Closed Caption
Interrupt Mask
If this bit is a “1”, an interrupt is generated when the Caption_ODD_A and
Caption_ODD_B or the Caption_EVEN_A and Caption_EVEN_B data registers contain
new data.
0 = Interrupt disabled
1 = Interrupt enabled
0B
4
WSS
Interrupt Mask
If this bit is a “1”, an interrupt is generated when the WSS_ODD_A and WSS_ODD_B or
the WSS_EVEN_A and WSS_EVEN_B data registers contain new data.
0 = Interrupt disabled
1 = Interrupt enabled
0B
3
Teletext
Interrupt Mask
If this bit is a “1”, an interrupt is generated when teletext information is first detected at the
beginning of each field.
0 = Interrupt disabled
1 = Interrupt enabled
0B
2
Reserved
1
Auto Detect
Video Standard
Interrupt Mask
If this bit is a “1”, an interrupt is generated when the video standard has been automatically determined.
0 = Interrupt disabled
1 = Interrupt enabled
0B
0
Vertical Sync
Interrupt Mask
If this bit is a “1”, an interrupt is generated at the beginning of each field.
0 = Interrupt disabled
1 = Interrupt enabled
0B
0B
30
HMP8116
TABLE 23. INTERRUPT STATUS REGISTER
SUB ADDRESS = 10H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7
Genlock Loss
Interrupt Status
If this bit is a “1”, the reason for the interrupt request was that genlock was lost. To clear
the interrupt request, a “1” must be written to this bit.
0B
6
Input Signal Loss
Interrupt Status
If this bit is a “1”, the reason for the interrupt request was that the input video source is no
longer present. To clear the interrupt request, a “1” must be written to this bit.
0B
5
Closed Caption
Interrupt Status
If this bit is a “1”, the reason for the interrupt request was that the Caption_ODD_A and
Caption_ODD_B or the Caption_EVEN_A and Caption_EVEN_B data registers contain
new data. To clear the interrupt request, a “1” must be written to this bit.
0B
4
WSS
Interrupt Status
If this bit is a “1”, the reason for the interrupt request was that the WSS_ODD_A and
WSS_ODD_B or the WSS_EVEN_A and WSS_EVEN_B data registers contain new data.
To clear the interrupt request, a “1” must be written to this bit.
0B
3
Teletext
Interrupt Status
If this bit is a “1”, the reason for the interrupt request was that teletext data has been detected in the current field. To clear the interrupt request, a “1” must be written to this bit.
0B
2
Reserved
1
Auto Detect
Video Standard
Interrupt Status
If this bit is a “1”, the reason for the interrupt request was that the video standard has been
automatically determined. To clear the interrupt request, a “1” must be written to this bit.
0B
0
Vertical Sync
Interrupt Status
If this bit is a “1”, the reason for the interrupt request was that a new field was started. To
clear the interrupt request, a “1” must be written to this bit.
0B
0B
TABLE 24. RAW VBI CONTROL REGISTER
SUB ADDRESS = 11H
BIT
NO.
7-4
FUNCTION
DESCRIPTION
Reserved
RESET
STATE
0000B
3
RAW Preamble Enable
If this bit is a “1”, the RAW VBI data stream will have a preamble consisting of four bytes.
Which are FFH, CNT1, CNT2 and 00H. Where CNT1 = even parity bar, even parity[5-0],
0, Field (0=Odd, 1=Even), linecount[8-4] and CNT2 = even parity bar, even parity [50],0,0,linecount[3-0].
0B
2
RAW VBI All
If this bit is a “1”, all the video lines excluding the lines used for equalization and serration
pulses are converted to RAW VBI data.
If this bit is a “0”, only the lines enbled in the RAW VBI LINE MASK registers are converted
to RAW VBI data.
0B
1
RAW VBI Even
Field
If this bit is a “1”, the even field lines are converted to RAW VBI data as specified by the
RAW VBI All bit and the RAW VBI Line Mask registers.
If this bit is a “0”, the even field lines are not included in the lines to be converted to RAW
VBI data.
0B
0
RAW VBI Odd Field If this bit is a “1”, the odd field lines are converted to RAW VBI data as specified by the
RAW VBI All bit and the RAW VBI Line Mask registers.
If this bit is a “0”, the odd field lines are not included in the lines to be converted to RAW
VBI data.
0B
TABLE 25. RAW VBI START COUNT REGISTER
SUB ADDRESS = 12H
BIT
NO.
7-0
FUNCTION
Raw VBI Start
Count
DESCRIPTION
Specifies where to start generating raw VBI data in two sample clock steps from the 50%
point of the leading edge of HSYNC.
31
RESET
STATE
7AH
HMP8116
TABLE 26. RAW VBI STOP COUNT_LSB REGISTER
SUB ADDRESS = 13H
BIT
NO.
7-0
FUNCTION
DESCRIPTION
Raw VBI Stop Count This register contains the LSBs of the count specifying where to stop generating raw VBI
LSB
data in two sample clock steps from the 50% point of the leading edge of HSYNC.
RESET
STATE
4AH
TABLE 27. RAW VBI STOP COUNT_MSB REGISTER
SUB ADDRESS = 14H
BIT
NO.
FUNCTION
DESCRIPTION
7-2
Reserved
1-0
Raw VBI Stop Count This register contains the MSBs of the count specifying where to stop generating raw VBI
MSB
data in two sample clock steps from the 50% point of the leading edge of HSYNC.
RESET
STATE
000000B
11B
TABLE 28. RAW VBI LINE MASK_7_0 REGISTER
SUB ADDRESS = 15H
BIT
NO.
7-0
FUNCTION
Raw VBI Line
Mask_7_0
DESCRIPTION
For a “1” in each bit position, the line that the bit corresponds to will be converted into raw
A/D data. A “0” in the bit position will disable the line from being converted to raw A/D data.
Bit 0 corresponds to line 9 (odd field) and 272 (even field) for 525 line systems and to line
5 (odd field) and 318 (even field) for 625 line systems. Bit 7 corresponds to line 16 (odd
field) and 279 (even field) for 525 line systems and to line 12 (odd field) and 325 (even
field) for 625 line systems.
RESET
STATE
FEH
TABLE 29. RAW VBI LINE MASK_15_8 REGISTER
SUB ADDRESS = 16H
BIT
NO.
7-0
FUNCTION
Raw VBI Line
Mask_15_8
DESCRIPTION
For a “1” in each bit position, the line that the bit corresponds to will be converted into raw
A/D data. A “0” in the bit position will disable the line from being converted to raw A/D data.
Bit 0 corresponds to line 17 (odd field) and 280 (even field) for 525 line systems and to
line 13 (odd field) and 326 (even field) for 625 line systems. Bit 7 corresponds to line 24
(odd field) and 287 (even field) for 525 line systems and to line 20 (odd field) and 333
(even field) for 625 line systems.
RESET
STATE
1FH
TABLE 30. RAW VBI LINE MASK_18_16 REGISTER
SUB ADDRESS = 17H
BIT
NO.
FUNCTION
7-3
Reserved
2-0
Raw VBI Line
Mask_18_16
DESCRIPTION
RESET
STATE
00000B
For a “1” in each bit position, the line that the bit corresponds to will be converted into raw
A/D data. A “0” in the bit position will disable the line from being converted to raw A/D data.
Bit 0 corresponds to line 25 (odd field) and 288 (even field) for 525 line systems and to
line 21 (odd field) and 334 (even field) for 625 line systems. Bit 2 corresponds to line 27
(odd field) and 290 (even field) for 525 line systems and to line 23 (odd field) and 336
(even field) for 625 line systems.
32
000B
HMP8116
TABLE 31. BRIGHTNESS REGISTER
SUB ADDRESS = 18H
BIT
NO.
FUNCTION
7
Reserved
6-0
Brightness
Adjust
DESCRIPTION
RESET
STATE
0B
These bits control the brightness. They may have a value of +63 (“011 1111”) to -64 (“100
0000”), with positive values increasing brightness. A value of 0 (“000 0000”) has no effect
on the data.
0000000B
TABLE 32. CONTRAST REGISTER
SUB ADDRESS = 19H
BIT
NO.
7-0
FUNCTION
Contrast
Adjust
DESCRIPTION
These bits control the contrast. They may have a value of 0x (“0000 0000”) to 1.992x
(“1111 1111”). A value of 1x (“1000 0000”) has no effect on the data.
RESET
STATE
80H
TABLE 33. HUE REGISTER
SUB ADDRESS = 1AH
BIT
NO.
7-0
FUNCTION
Hue
Adjust
DESCRIPTION
These bits control the color hue. They may have a value of +30 degrees (“0111 1111”) to
-30 degrees (“1111 1111”). A value of 0 degrees (“0000 0000”) has no effect on the color
data.
RESET
STATE
00H
TABLE 34. SATURATION REGISTER
SUB ADDRESS = 1BH
BIT
NO.
7-0
FUNCTION
Saturation
Adjust
DESCRIPTION
These bits control the color saturation. They may have a value of 0x (“0000 0000”) to
1.992x (“1111 1111”). A value of 1x (“1000 0000”) has no effect on the color data. A value
of 0x (“0000 0000”) disables the color information.
RESET
STATE
80H
TABLE 35. COLOR GAIN REGISTER
SUB ADDRESS = 1CH
BIT
NO.
7-0
FUNCTION
Color Gain
Adjust
DESCRIPTION
These bits control the amount of gain control for the color difference (CbCr) signals. They
may have a value of 0.5x (“0010 0000”) to 3.98x (“1111 1111”). A value of 1x (“0100
0000”) has no effect on the data. This register is ignored unless the color gain control
mode selection is “fixed gain control”.
RESET
STATE
40H
TABLE 36. VIDEO GAIN ADJUST REGISTER
SUB ADDRESS = 1DH
BIT
NO.
7-0
FUNCTION
Video Gain
Adjust
DESCRIPTION
These bits control the amount of gain control for the video signals. They may have a value
of 0.5x (“1100 1110”) to 1.99x (“0011 0011”). A value of 1x (“0110 0111”) has no effect.
Refer to the look-up table following register definitions for other values to load for different
gains. This register is ignored unless the video gain control mode selection is “fixed gain
control”.
33
RESET
STATE
80H
HMP8116
TABLE 37. SHARPNESS REGISTER
SUB ADDRESS = 1EH
BIT
NO.
FUNCTION
7-6
Reserved
5-0
Sharpness
Adjust
DESCRIPTION
RESET
STATE
00B
These bits control the amount of gain control of high frequency luminance signals (either
2.6MHz or Fsc). They may have a value of +12dB (“11 1111”) to -12dB (“00 0100”). A value of 0dB (“01 0000”) has no effect on the data. This register is ignored if the sharpness
mode selection is “disable sharpness control” or “reserved”.
010000B
TABLE 38. HOST CONTROL REGISTER
SUB ADDRESS = 1FH
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7
Software Reset
When this bit is set to 1, the entire device except the I2C bus is reset to a known state
exactly like the RESET input going active. The software reset will initialize all register bits
to their reset state. Once set this bit is self clearing. This bit is cleared on power-up by the
external RESET pin.
0B
6
Power Down
When this bit is set to a 1, the entire device is shut down except the I2C bus by gating off
the clock. For normal decoding operations this bit should be set to a 0.
0B
5
Closed Caption
Odd Field
Read Status
This bit is read-only. Data written to this bit is ignored. The bit is cleared when the caption
data has been read out via the I2C interface or as BT.656 ancillary data.
0 = No new caption data
1 = Caption_ODD_A and Caption_ODD_B data registers contain new data.
0B
4
Closed Caption
Even Field
Read Status
This bit is read-only. Data written to this bit is ignored. The bit is cleared when the caption
data has been read out via the I2C interface or as BT.656 ancillary data.
0 = No new caption data
1 = Caption_EVEN_A and Caption_EVEN_B data registers contain new data.
0B
3
WSS
Odd Field
Read Status
This bit is read-only. Data written to this bit is ignored. The bit is cleared when the WSS
data has been read out via the I2C interface or as BT.656 ancillary data.
0 = No new WSS data
1 = WSS_ODD_A and WSS_ODD_B data registers contain new data.
0B
2
WSS
Even Field
Read Status
This bit is read-only. Data written to this bit is ignored. The bit is cleared when the WSS
data has been read out via the I2C interface or as BT.656 ancillary data.
0 = No new WSS data
1 = WSS_EVEN_A and WSS_EVEN_B data registers contain new data.
0B
1-0
Reserved
00B
TABLE 39. CLOSED CAPTION_ODD_A DATA REGISTER
SUB ADDRESS = 20H
BIT
NO.
7-0
FUNCTION
Odd Field
Caption Data
DESCRIPTION
If odd field captioning is enabled and present, this register is loaded with the first eight bits
of caption data on line 18, 21, or 22. Bit 0 corresponds to the first bit of caption information.
Data written to this register is ignored.
RESET
STATE
80H
TABLE 40. CLOSED CAPTION_ODD_B DATA REGISTER
SUB ADDRESS = 21H
BIT
NO.
15-8
FUNCTION
Odd Field
Caption Data
DESCRIPTION
If odd field captioning is enabled and present, this register is loaded with the second eight
bits of caption data on line 18, 21, or 22. Data written to this register is ignored.
34
RESET
STATE
80H
HMP8116
TABLE 41. CLOSED CAPTION_EVEN_A DATA REGISTER
TABLE 42. SUB ADDRESS = 22H
BIT
NO.
7-0
FUNCTION
Even Field
Caption Data
DESCRIPTION
If even field captioning is enabled and present, this register is loaded with the first eight
bits of caption data on line 281, 284, or 335. Bit 0 corresponds to the first bit of caption
information. Data written to this register is ignored.
RESET
STATE
80H
TABLE 43. CLOSED CAPTION_EVEN_B DATA REGISTER
SUB ADDRESS = 23H
BIT
NO.
15-8
FUNCTION
Even Field
Caption Data
DESCRIPTION
If even field captioning is enabled and present, this register is loaded with the second eight
bits of caption data on line 281, 284, or 335. Data written to this register is ignored.
RESET
STATE
80H
TABLE 44. WSS_ODD_A DATA REGISTER
SUB ADDRESS = 24H
BIT
NO.
7-0
FUNCTION
Odd Field
WSS Data
DESCRIPTION
If odd field WSS is enabled and present, this register is loaded with the first eight bits of
WSS information on line 17, 20, or 23. Bit 0 corresponds to the first bit of WSS information.
Data written to this register is ignored.
RESET
STATE
00H
TABLE 45. WSS_ODD_B DATA REGISTER
SUB ADDRESS = 25H
BIT
NO.
FUNCTION
15-14
Reserved
13-8
Odd Field
WSS Data
DESCRIPTION
RESET
STATE
00B
If odd field WSS is enabled and present, this register is loaded with the second six bits of
WSS information on line 17, 20, or 23. Data written to this register is ignored.
000000B
TABLE 46. WSS_CRC_ODD DATA REGISTER
SUB ADDRESS = 26H
BIT
NO.
FUNCTION
7-6
Reserved
5-0
Odd Field
WSS CRC Data
DESCRIPTION
RESET
STATE
00B
If odd fiedl WSS is enabled and present during NTSC operation, this register is loaded
with the six bits of CRC information on line 20. It is always a “000000” during PAL operation. Data written to this register is ignored.
000000B
TABLE 47. WSS_EVEN_A DATA REGISTER
SUB ADDRESS = 27H
BIT
NO.
7-0
FUNCTION
Even Field
WSS Data
DESCRIPTION
If even field WSS is enabled and present, this register is loaded with the first eight bits of
WSS information on line 280, 283, or 336. Bit 0 corresponds to the first bit of WSS information. Data written to this register is ignored.
35
RESET
STATE
00H
HMP8116
TABLE 48. WSS_EVEN_B DATA REGISTER
SUB ADDRESS = 28H
BIT
NO.
FUNCTION
15-14
Reserved
13-8
Even Field
WSS Data
DESCRIPTION
RESET
STATE
00B
If even field WSS is enabled and present, this register is loaded with the second six bits
of WSS information on line 280, 283, or 336. Data written to this register is ignored.
000000B
TABLE 49. WSS_CRC_EVEN DATA REGISTER
SUB ADDRESS = 29H
BIT
NO.
FUNCTION
7-6
Reserved
5-0
Even Field
WSS CRC Data
DESCRIPTION
RESET
STATE
00B
If even field WSS is enabled and present during NTSC operation, this register is loaded
with the six bits of CRC information on line 283. It is always a “000000” during PAL operation. Data written to this register is ignored.
000000B
TABLE 50. START H_BLANK LOW REGISTER
SUB ADDRESS = 30H
BIT
NO.
7-0
FUNCTION
Assert BLANK
Output Signal
DESCRIPTION
This 8-bit register is cascaded with Start H_Blank High Register to form a 10-bit
start_horizontal_blank REGISTER. It specifies the horizontal count (in 1x clock cycles) at
which to assert BLANK each scan line. Bit 0 is always a “0”, so the start of horizontal
blanking may only be done with two pixel resolution. The leading edge of HSYNC is count
000H.
RESET
STATE
4AH
TABLE 51. START H_BLANK HIGH REGISTER
SUB ADDRESS = 31H
BIT
NO.
15-10
9-8
FUNCTION
DESCRIPTION
Reserved
Assert BLANK
Output Signal
RESET
STATE
000000B
This 2-bit register is cascaded with Start H_Blank Low Register to form a 10-bit
start_horizontal_blank register. It specifies the horizontal count (in 1x clock cycles) at
which to assert BLANK each scan line. The leading edge of HSYNC is count 000H.
11B
TABLE 52. END H_BLANK REGISTER
SUB ADDRESS = 32H
BIT
NO.
7-0
FUNCTION
Negate BLANK
Output Signal
DESCRIPTION
This 8-bit register specifies the horizontal count (in 1x clock cycles) at which to negate
BLANKeach scan line. Bit 0 is always a “0”, so the end of horizontal blanking may only be
done with two pixel resolution. The leading edge of HSYNC is count 000H.
RESET
STATE
7AH
TABLE 53. START V_BLANK LOW REGISTER
SUB ADDRESS = 33H
BIT
NO.
7-0
FUNCTION
Assert BLANK
Output Signal
DESCRIPTION
This 8-bit register is cascaded with Start V_Blank High Register to form a 9-bit
start_vertical_blank register. It specifies the line number to assert BLANK each field.
For NTSC operation, it occurs on line (n + 5) on odd fields and line (n + 268) on even
fields. For PAL operation, it occurs on line (n + 5) on odd fields and line (n + 318) on even
fields.
36
RESET
STATE
02H
HMP8116
TABLE 54. START V_BLANK HIGH REGISTER
SUB ADDRESS = 34H
BIT
NO.
15-9
8
FUNCTION
RESET
STATE
DESCRIPTION
Reserved
0000000B
Assert BLANK
Output Signal
This 1-bit register is cascaded with Start V_Blank Low Register to form a 9-bit
start_vertical_blank register.
1B
TABLE 55. END V_BLANK REGISTER
SUB ADDRESS = 35H
BIT
NO.
7-0
FUNCTION
RESET
STATE
DESCRIPTION
Negate BLANK
Output Signal
This 8-bit register specifies the line number to negate BLANK each field.
12H
For NTSC operation, it occurs on line (n + 5) on odd fields and line (n + 268) on even
fields. For PAL operation, it occurs on line (n + 5) on odd fields and line (n + 318) on even
fields.
TABLE 56. END HSYNC REGISTER
SUB ADDRESS = 36H
BIT
NO.
7-0
FUNCTION
RESET
STATE
DESCRIPTION
Negate HSYNC
Output Signal
This 8-bit register specifies the horizontal count at which to negate HSYNC each scan
line. Values may range from 0 (0000 0000) to 510 (1111 1111) CLK2 cycles. The leading
edge of HSYNC is count 00H.
40H
TABLE 57. HSYNC DETECT WINDOW REGISTER
SUB ADDRESS = 37H
BIT
NO.
7-0
FUNCTION
RESET
STATE
DESCRIPTION
Horizontal Sync De- This 8-bit register specifies the width of the window (in 1x clock samples) to look for hortect Window
izontal sync pulses each line. The window is centered about where the horizontal sync
pulse should be located.
If the horizontal sync pulse falls inside this window, the digital PLL will lock to it. If the horizontal sync pulse falls outside this window, the digital PLL is immediately reset to have
the same timing.
TABLE 58. VIDEO GAIN REGISTER LOOK-UP TABLE
Video
Gain
Reg.
Value
Video
Gain
Reg.
Value
Video
Gain
Reg.
Value
Video
Gain
Reg.
Value
Video
Gain
Reg.
Value
Video
Gain
Reg.
Value
0.50
0.51
0.52
0.53
0.54
0.55
206/CEH
202/CAH
197/C5H
193/C1H
191/BFH
187/BBH
0.67
0.68
0.69
0.70
0.71
0.72
153/99H
151/97H
150/96H
147/93H
145/91H
143/8FH
0.84
0.85
0.86
0.87
0.88
0.89
206/7BH
206/79H
206/77H
206/76H
206/75H
206/73H
1.03
1.04
1.05
1.06
1.07
1.08
206/64H
206/63H
206/62H
206/61H
206/60H
206/5FH
1.23
1.25
1.27
1.28
1.30
1.31
206/53H
206/52H
206/51H
206/50H
206/4FH
206/4EH
1.55
1.57
1.59
1.63
1.65
1.67
206/42H
206/41H
206/40H
206/3FH
206/3EH
206/3DH
0.56
0.57
0.58
0.59
0.60
0.61
183/B7H
180/B4H
178/B2H
174/AEH
171/ABH
169/A9H
0.73
0.74
0.75
0.76
0.77
0.78
141/8DH
139/8BH
137/89H
136/88H
134/86H
132/84H
0.90
0.91
0.92
0.94
0.95
0.96
206/72H
206/71H
206/6FH
206/6EH
206/6DH
206/6BH
1.09
1.10
1.12
1.13
1.14
1.15
206/5EH
206/5DH
206/5CH
206/5BH
206/5AH
206/59H
1.33
1.34
1.37
1.38
1.40
1.42
206/4DH
206/4CH
206/4BH
206/4AH
206/49H
206/48H
1.70
1.73
1.76
1.79
1.82
1.86
206/3CH
206/3BH
206/3AH
206/39H
206/38H
206/37H
0.62
0.63
0.64
0.65
0.66
167/A7H
164/A4H
161/A1H
159/9FH
156/9CH
0.79
0.80
0.81
0.82
0.83
130/82H
128/80H
127/7EH
206/7DH
206/7CH
0.97
0.98
1.00
1.01
1.02
206/6AH
206/68H
206/67H
206/66H
206/65H
1.16
1.18
1.20
1.21
1.22
206/58H
206/57H
206/56H
206/55H
206/54H
1.44
1.46
1.48
1.51
1.52
206/47H
206/46H
206/45H
206/44H
206/43H
1.89
1.93
1.97
1.99
206/36H
206/35H
206/34H
206/33H
37
FFH
HMP8116
Pinout
GND
VCC
REF_CAP
NC
LCAP
VCC
NC
NC
GND
HSYNC
VSYNC
GND
VCC
FIELD
DVALID
BLANK
80 LEAD PQFP
TOP VIEW
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
AGND
VAA
AGND
NC
CVBS3(Y)
CVBS2
CVBS1
YIN
YOUT
AGND
AGND
VAA
NC
VAA
AGND
AGND
A/D_TEST
NC
C
NC
AGND
AGND
AGND
AGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P15
P14
GND
VBIVALID
P13
VCC
P12
P11
P10
P9
P8
GND
VCC
P7
P6
P5
P4
P3
GND
P2
INTREQ
P1
P0
SCL
GND
VCC
NC
RSET
CCAP
NC
VCC
NC
GND
RESET
GND
GND
VCC
CLK2
GND
SDA
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Applications Information
each group of VAA and VCC pins to ground. These capacitors should be located as close to the power and ground pins
as possible, using short, wide traces.
PCB LAYOUT CONSIDERATIONS
A PCB board with a minimum of 4 layers is recommended, with
layers 1 and 4 (top and bottom) for signals and layers 2 and 3
for power and ground. The PCB layout should implement the
lowest possible noise on the power and ground planes by providing excellent decoupling.
Digital Ground Plane
All GND pins on the HMP8116 should be connected to the
digital ground plane of the board.
Analog Ground Plane
The optimum layout places the HMP8116 as close as possible
to the power supply connector and the video input connector.
A separate analog ground plane for the HMP8116 is recommended. All AGND pins on the HMP8116 should be connected to the analog ground plane. This analog ground
plane should be connected to the board’s digital ground
plane at a single point.
Component Placement
External components should be positioned as close as possible to the appropriate pin, ideally such that traces can be
connected point to point. Chip capacitors are recommended
where possible, with radial lead ceramic capacitors the second-best choice.
Analog Power Plane
The HMP8116 should have its own VAA power plane that is
isolated from the common power plane of the board, with a
gap between the two power planes of at least 1/8 inch. All
VAA pins on the HMP8116 must be connected to this analog
Power supply decoupling should be done using a 0.1µF
ceramic capacitor in parallel with a 0.01µF chip capacitor for
38
HMP8116
EVALUATION BOARD
power plane. The analog power plane should be connected
to the board’s normal VCC power plane at a single point
though a low-resistance ferrite bead, such as a Ferroxcube
5659065-3B, Fair-Rite 2743001111, or TDK BF45-4001. The
ferrite bead provides resistance to switching currents,
improving the performance of HMP8116. A single 47µF
capacitor should also be used between the analog power
plane and the ground plane to control low-frequency power
supply ripple.
HMPVIDEVAL/ISA
The HMPVIDEVAL/ISA evaluation board allows connecting
the HMP8116 into a PC ISA slot for evaluation. It includes
the HMP8115 NTSC/PAL decoder, 3MB of VRAM, and a
NTSC/PAL encoder. The board accepts composite or Svideo input and displays video on a standard TV. The ISA
bus and evaluation software allow easy performance evaluation of the HMP8116 using tools such as the Tektronix
VM700 video test system.
If a separate linear regulator is used to provide power to the
analog power plane, the power-up sequence should be
designed to ensure latchup will not occur. A separate linear regulator is recommended if the power supply noise on the VAA
pins exceeds 200mV.
RELATED APPLICATION NOTES
Application Notes are also available on the Harris Multimedia web site at http://www.semi.harris.com/mmedia.
Analog Signals
AN9644: Composite Video Separation Techniques
AN9716: Widescreen Signalling
AN9717: YCbCr to RGB Considerations
AN9728: BT.656 Video Interface for ICs
AN9738: VMI Video Interface for ICs
Traces containing digital signals should not be routed over,
under, or adjacent to the analog output traces to minimize
crosstalk. If this is not possible, coupling can be minimized
by routing the digital signals at a 90 degree angle to the analog signals. The analog input traces should also not overlay
the VAA power plane to maximize high-frequency power supply rejection.
U1
C1
7
CVBS 1
1.0µF
C2
6
CVBS 2
1.0µF
5 CVBS 3 (Y)
C3
1.0µF
CVBS1
CVBS2
CVBS3/Y
R3
75
R2
75
R1
75
ANTI-ALIAS
FILTER
CHROMA
R4
75
HMP8116
19
C4
1.0µF
C
ANTI-ALIAS
FILTER
8
9
YIN
YOUT
76
C6
0.1µF
P7
P6
P5
P4
P3
P2
P1
P0
LCAP
29 CCAP
C7
0.1µF
P15
P14
P13
P12
P11
P10
P9
P8
BLANK
DVALID
FIELD
HSYNC
VSYNC
VBIVALID
INTREQ
78
REF_CAP
C8
1.0µF
28
RSET
64
63
60
58
57
56
55
54
P[15..8]
VCC
R16
4K
R17
4K
BLANK
DVALID
FIELD
HSYNC
VSYNC
VBIVALID
44
INTREQ
RESET
27MHz
R8
50
C12
15pF
FIGURE 21. HMP8116 REFERENCE SCHEMATICS
39
VCC VCC
RP1
10K
65
66
67
71
70
61
34
RESET
40
SDA
41
SCL
38
CLK2
R6
12K
P[7..0]
51
50
49
48
47
45
43
42
SDA
SCL
27MHz
HMP8116
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage (VCC to GND) . . . . . . . . . . . . . . . . . . . . 7.0V
Analog Supply Voltage (VAA to GND) . . . . . . . . . . . . . . . . . . . . 7.0V
Digital Input Voltages . . . . . . . . . . . . . . . GND - 0.5V to VCC + 0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance (Typical, See Note 1)
θJA (oC/W)
PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
Maximum Power Dissipation
HMP8116CN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9W
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Junction Temperatures . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Operating Temperature Range
HMP8116CN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air. Dissipation rating assumes device is mounted with
all leads soldered to printed circuit board.
Electrical Specifications
VCC = VAA = 5.0V, TA = 25oC
PARAMETER
SYMBOL
TEST CONDITION
MIN
TYP
MAX
UNITS
4.75
5
5.25
V
-
280
315
mA
-
105
115
mA
-
175
200
mA
-
1.47
1.66
W
POWER SUPPLY CHARACTERISTICS
Power Supply Voltage Range
VCC, VAA
Total Power Supply Current
ITOT
Digital Power Supply Current
ICC
Analog Power Supply Current
IAA
Total Power Dissipation
PTOT
(Note 2)
CLK2 = 29.5MHz,
VCC = VAA = 5.25V
Outputs Not Loaded
CLK2 = 29.5MHz,
VCC = VAA = 5.25V,
Outputs Not Loaded
DC CHARACTERISTICS: DIGITAL I/O (EXCEPT CLK2 and I2C INTERFACE)
Input Logic High Voltage
VIH
VCC = Max
2.0
-
-
V
Input Logic Low Voltage
VIL
VCC = Min
-
-
0.8
V
2.4
-
-
V
Output Logic High Voltage
VOH
IOH = -4mA, VCC = Max
Output Logic Low Voltage
VOL
IOL = 4mA, VCC = Min
-
-
0.4
V
VCC = Max
Input = 0V or 5V
-
-
10
µA
f = 1MHz, (Note 2)
All Measurements Referenced to
Ground, TA = 25o C
-
8
-
pF
-
-
10
µA
Input Leakage Current
Input/Output Capacitance
IIH, IIL
CIN, COUT
Three-State Output Current
Leakage
IOZ
DC CHARACTERISTICS: CLK2 DIGITAL INPUT
Input Logic High Voltage
VIH
VCC = Max
0.7xVCC
-
-
V
Input Logic Low Voltage
VIL
VCC = Min
-
-
0.3xVCC
V
Input Leakage Current
IIH
VCC = Max
Input = 0V or VCC
-
-
10
µA
- 450
-
-
µA
-
8
-
pF
IIL
Input Capacitance
CIN
CLK2 = 1MHz, (Note 2)
All Measurements Referenced to
Ground, TA = 25o C
Input Logic High Voltage
VIH
VCC = Max
0.7xVCC
-
-
V
Input Logic Low Voltage
VIL
VCC = Min
-
-
0.3xVCC
V
Output Logic High Voltage
VOH
IOH = -1mA, VCC = Max
3.0
-
-
V
DC CHARACTERISTICS: I2C INTERFACE
40
HMP8116
Electrical Specifications
PARAMETER
VCC = VAA = 5.0V, TA = 25oC (Continued)
SYMBOL
Output Logic Low Voltage
Input Leakage Current
Input/Output Capacitance
VOL
IIH, IIL
CIN, COUT
TEST CONDITION
MIN
TYP
MAX
UNITS
IOL = 3mA, VCC = Min
0
-
0.4
V
VCC = Max
Input = 0V or 5V
-
-
10
µA
SCL = 400kHz, (Note 2)
All Measurements Referenced
to GND, TA = 25oC
-
8
-
pF
20
-
29.5
MHz
40
-
60
%
AC CHARACTERISTICS: DIGITAL I/O (EXCEPT I2C INTERFACE)
CLK2 Frequency
CLK2 Waveform Symmetry
(Note 2)
CLK2 Pulse Width High
tPWH
13
-
-
ns
CLK2 Pulse Width Low
tPWL
13
-
-
ns
10
-
-
ns
Data and Control Setup Time
tSU
Data and Control Hold Time
tHD
0
-
-
ns
tDVLD
0
5
8
ns
-
2
6
ns
CLK2 to Output Delay
Data and Control Rise/Fall Time
tr, tf
(Note 3)
(Note 2)
AC CHARACTERISTICS: I2C INTERFACE
SCL Clock Frequency
fSCL
0
-
400
kHz
SCL Pulse Width Low
tLOW
1.3
-
-
µs
SCL Pulse Width High
tHIGH
0.6
-
-
µs
Data Hold Time
tHD:DATA
0
-
-
ns
Data Setup Time
tSU:DATA
100
-
-
ns
-
-
300
ns
-
-
300
ns
SDA, SCL Rise Time
tR
SDA, SCL Fall Time
tF
(Note 2)
ANALOG INPUT PERFORMANCE
Composite Video Input Amplitude
(Sync Tip to White Level)
Input Termination of 75Ω and
1.0µF AC-Coupled
0.5
1.0
2.0
VP-P
Luminance (Y) Video
Input Amplitude
(Sync Tip to White Level)
Input Termination of 75Ω and
1.0µF AC-Coupled
0.5
1.0
2.0
VP-P
Chrominance (C) Video Input
Amplitude (Burst Amplitude)
Input Termination of 75Ω and
1.0µF AC-Coupled, Note 2
0.143
0.286
0.6
VP-P
200
-
-
kΩ
5
-
-
MHz
AIN FULL SCALE
-
1
-
VP-P
AIN OFFSET
-
1.5
-
V
-
2
-
LSB
-
0.35
-
LSB
-
2
-
%
-
1
-
Deg.
-
2
-
Deg.
-
2
-
%
Video Input Impedance
RAIN
Video Input Bandwidth
BW
ADC Input Range
ADC Integral Nonlinearity
INL
ADC Differential Nonlinearity
DNL
Note 2
1VP-P Sine Wave Input to
-3dBc Reduction, (Note 2)
Best Fit Linearity
VIDEO PERFORMANCE
Differential Gain
DG
Differential Phase
DP
Hue Accuracy
Modulated Ramp (Note 2)
75% Color Bars (Note 2)
Color Saturation Accuracy
41
HMP8116
Electrical Specifications
PARAMETER
VCC = VAA = 5.0V, TA = 25oC (Continued)
SYMBOL
Luminance Nonlinearity
SNR
SNRL WEIGHTED
TEST CONDITION
MIN
TYP
MAX
UNITS
NTC-7 Composite (Note 2)
-
2
-
%
Pedestal Input (Note 2)
-
50
-
dB
Time from Initial Lock
Acquisition to an Error of
1 Pixel. (Note 2)
2
3
-
Fields
-
5
%
1 or 12
1 or 12
1 or 12
Hsyncs
1 or 3
1 or 3
1 or 3
Vsyncs
GENLOCK PERFORMANCE
Horizontal Locking Time
tLOCK
Long-Term horizontal Sync
Lock Range
Range over specified pixel jitter
is maintained. Assumes line
time changes by amount indicated slowly between over one
field. (Note 2)
Number of Missing Horizontal
Syncs
Before Lost Lock Declared
HSYNC LOST
Number of Missing Vertical Syncs
Before Lost Lock Declared
VSYNC LOST
Programmable via register 04H
(Note 2)
-
Long-Term Color Subcarrier
Lock Range
Range over color subcarrier
locking time and accuracy specifications are maintained. Subcarrier frequency changes by
amount indicated slowly over 24
hours. (Note 2)
-
±200
±400
Hz
Vertical Sample Alignment
(Notes 2, 4)
-
1/8
-
Pixel
-
10
-
ns
NOTES:
2. Guaranteed by design or characterization.
3. Test performed with CL = 40pF, IOL = 4mA, IOH = -4mA. Input reference level is 1.5V for all inputs. VIH = 3.0V, VIL = 0V.
4. This should not be confused with Clock Jitter, since the HMP8116 does not generate the sample clock. Thus, clock jitter is solely dependent on the source of the CLK2 signal. The Vertical Sample Alignment parameter specifies how accurately samples align vertically from
one scan line to the next.
42
HMP8116
Metric Plastic Quad Flatpack Packages (MQFP/PQFP)
Q80.14x20 (JEDEC MO-108CB-1 ISSUE A)
D
80 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE
D1
-D-
-B-
-AE E1
e
PIN 1
SEATING
A PLANE
-H-
0.10
0.004
0.40
0.016 MIN
-C-
5o-16o
0.20
A-B S
0.008 M C
0o MIN
A2 A1
0o-7o
L
5o-16o
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.134
-
3.40
-
A1
0.010
-
0.25
-
-
A2
0.100
0.120
2.55
3.05
-
B
0.012
0.018
0.30
0.45
6
B1
0.012
0.016
0.30
0.40
-
D
0.904
0.923
22.95
23.45
3
D1
0.783
0.791
19.90
20.10
4, 5
E
0.667
0.687
16.95
17.45
3
E1
0.547
0.555
13.90
14.10
4, 5
L
0.026
0.037
0.65
0.95
N
80
80
7
e
0.032 BSC
0.80 BSC
-
ND
24
24
-
NE
16
16
Rev. 0 1/94
NOTES:
D S
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
B
2. All dimensions and tolerances per ANSI Y14.5M-1982.
B1
3. Dimensions D and E to be determined at seating plane -C- .
4. Dimensions D1 and E1 to be determined at datum plane
-H- .
0.13/0.17
0.005/0.007
5. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.
BASE METAL
WITH PLATING
6. Dimension B does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total.
0.13/0.23
0.005/0.009
7. “N” is the number of terminal positions.
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Harris Semiconductor products are sold by description only. Harris Semiconductor reserves the right to make changes in circuit design and/or specifications at
any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is
believed to be accurate and reliable. However, no responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of patents or other
rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Harris or its subsidiaries.
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43
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