204pin DDR3L SDRAM SODIMM
DDR3L SDRAM
Unbuffered SODIMMs
Based on 4Gb A-die
HMT425S6AFR6A
HMT451S6AFR6A
HMT451S6AFR8A
HMT41GS6AFR8A
*SK hynix reserves the right to change products or specifications without notice.
Rev. 1.1 / Aug. 2013
1
Revision History
Revision No.
History
Draft Date
0.1
Initial Release
Jul. 2012
1.0
Change module maximum thickness
to reflect the measured maximum
Jul.2013
1.1
Added 1866Mbps specification
Aug.2013
Rev. 1.1 / Aug. 2013
Remark
2
Description
SK hynbix Unbuffered Small Outline DDR3L SDRAM DIMMs (Unbuffered Small Outline Double Data Rate
Synchronous DRAM Dual In-Line Memory Modules) are low power, high-speed operation memory modules
that use DDR3L SDRAM devices. These Unbuffered DDR3L SDRAM SODIMMs are intended for use as main
memory when installed in systems such as mobile personal computers.
Features
• Power Supply: VDD=1.35V (1.283V to 1.45V)
• VDDQ = 1.35V (1.283V to 1.45V)
• VDDSPD=3.0V to 3.6V
• Backward Compatible with 1.5V DDR3 Memory module
• 8 internal banks
• Data transfer rates: PC3-14900, PC3-12800, PC3-10600, PC3-8500
• Bi-directional Differential Data Strobe
• 8 bit pre-fetch
• Burst Length (BL) switch on-the-fly: BL 8 or BC (Burst Chop) 4
• On Die Termination (ODT) supported
• This product is in Compliance with the RoHS directive
Ordering Information
Part Number
Density
Organization
Component Composition
# of
ranks
HMT425S6AFR6A-G7/H9/PB/RD
2GB
256Mx64
256Mx16(H5TC4G63AFR)*4
1
HMT451S6AFR6A-G7/H9/PB/RD
4GB
512Mx64
256Mx16(H5TC4G63AFR)*8
2
HMT451S6AFR8A-G7/H9/PB/RD
4GB
512Mx64
512Mx8(H5TC4G83AFR)*8
1
HMT41GS6AFR8A-G7/H9/PB/RD
8GB
1Gx64
512Mx8(H5TC4G83AFR)*16
2
Rev. 1.1 / Aug. 2013
3
Key Parameters
MT/s
Grade
tCK
(ns)
CAS
Latency
(tCK)
tRCD
(ns)
tRP
(ns)
tRAS
(ns)
tRC
(ns)
CL-tRCD-tRP
DDR3L-1066
-G7
1.875
7
13.125
13.125
37.5
50.625
7-7-7
DDR3L-1333
-H9
1.5
9
13.5
13.5
(13.125)* (13.125)*
36
49.5
(49.125)*
9-9-9
DDR3L-1600
-PB
1.25
11
13.75
13.75
(13.125)* (13.125)*
35
48.75
(48.125)*
11-11-11
DDR3L-1866
-RD
1.07
13
13.91
13.91
(13.125)* (13.125)*
34
47.91
(47.125)*
13-13-13
*SK hynix DRAM devices support optional downbinning to CL11, CL9 and CL7. SPD setting is programmed to match.
Speed Grade
Frequency [MHz]
Grade
Remark
CL5
CL6
CL7
CL8
-G7
667
800
1066
1066
-H9
667
800
1066
-PB
667
800
800
-RD
CL9
CL10
CL11
1066
1333
1333
1066
1066
1333
1333
1600
1066
1066
1333
1333
1600
CL12
CL13
1866
Address Table
2GB(1Rx16)
4GB(2Rx16)
4GB(1Rx8)
8GB(2Rx8)
Refresh Method
8K/64ms
8K/64ms
8K/64ms
8K/64ms
Row Address
A0-A14
A0-A14
A0-A15
A0-A15
Column Address
A0-A9
A0-A9
A0-A9
A0-A9
Bank Address
BA0-BA2
BA0-BA2
BA0-BA2
BA0-BA2
Page Size
2KB
2KB
1KB
1KB
Rev. 1.1 / Aug. 2013
4
Pin Descriptions
Pin Name
Description
Num
ber
Pin Name
Num
ber
Description
CK[1:0]
Clock Input, positive line
2
DQ[63:0]
Data Input/Output
64
CK[1:0]
Clock Input, negative line
2
DM[7:0]
Data Masks
8
CKE[1:0]
Clock Enables
2
DQS[7:0]
Data strobes
8
RAS
Row Address Strobe
1
DQS[7:0]
Data strobes, negative line
8
CAS
Column Address Strobe
1
EVENT
Temperature event pin
1
WE
Write Enable
1
TEST
S[1:0]
Chip Selects
2
RESET
Address Inputs
14
A10/AP
Address Input/Autoprecharge
1
A12/BC
Address Input/Burst chop
1
BA[2:0]
SDRAM Bank Addresses
3
VREFDQ
ODT[1:0]
On Die Termination Inputs
2
VREFCA
1
VTT
SPD Data Input/Output
1
VDDSPD
SPD Address Inputs
2
NC
A[9:0],A11,
A[15:13]
SCL
SDA
SA[1:0]
Serial Presence Detect (SPD)
Clock Input
Logic Analyzer specific test pin (No
connect on SODIMM)
1
Reset Pin
1
VDD
Core and I/O Power
18
VSS
Ground
52
Input/Output Reference
1
1
Termination Voltage
2
SPD Power
1
Reserved for future use
2
Total: 204
Rev. 1.1 / Aug. 2013
5
Input/Output Functional Descriptions
Symbol
Type
Polarity
Function
The system clock inputs. All address and command lines are sampled on the cross point
of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is
Cross Point
driven from the clock inputs and output timing for read operations is synchronized to the
input clock.
CK0/CK0
CK1/CK1
IN
CKE[1:0]
IN
Active
High
S[1:0]
IN
Active
Low
ODT[1:0]
IN
Active
High
Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR3L
SDRAM mode register.
RAS, CAS, WE
IN
Active
Low
When sampled at the cross point of the rising edge of CK, signals CAS, RAS, and WE
define the operation to be executed by the SDRAM.
VREFDQ
VREFCA
Supply
BA[2:0]
IN
Activates the DDR3L SDRAM CK signal when high and deactivates the CK signal when
low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self
Refresh mode.
Enables the associated DDR3L SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new commands
are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is
selected by S1.
Reference voltage for SSTL15 inputs.
—
Selects which SDRAM internal bank of eight is activated.
A[9:0],
A10/AP,
A11,
A12/BC
A[15:13]
IN
—
During a Bank Activate command cycle, defines the row address when sampled at the
cross point of the rising edge of CK and falling edge of CK. During a Read of Write command cycle, defines the column address when sampled at the cross point of the rising
edge of CK and falling edge of CK. In addition to the column address, AP is used to
invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high
autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low,
autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction
with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used
to define which bank to precharge. A12(BC) is samples during READ and WRITE commands to determine if burst chop (on-the-fly) will be performed (HIGH, no burst chop:
LOW, burst chopped).
DQ[63:0]
I/O
—
Data Input/Output pins.
DM[7:0]
IN
Active
High
VDD, VDDSPD
VSS
Supply
DQS[7:0],
DQS[7:0]
I/O
SA[1:0]
IN
Rev. 1.1 / Aug. 2013
The data write masks, associated with one data byte. In Write mode, DM operates as a
byte mask by allowing input data to be written if it is low but blocks the write operation
if it is high. In Read mode, DM lines have no effect.
Power supplies for core, I/O, Serial Presence Detect, and ground for the module.
The data strobes, associated with one data byte, sourced with data transfers. In Write
mode, the data strobe is sourced by the controller and is centered in the data window.
Cross Point In Read mode, the data strobe is sourced by the DDR3L SDRAMs and is sent at the leading edge of the data window. DQS signals are complements, and timing is relative to the
crosspoint of respective DQS and DQS.
—
These signals are tied at the system planar to either VSS or VDDSPD to configure the
serial SPD EEPROM address range.
6
Symbol
Type
Polarity
Function
SDA
I/O
—
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to VDDSPD on the system planar to act as a
pullup.
SCL
IN
—
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to VDDSPD on the system planar to act as a pullup.
EVENT
OUT
(open
drain)
VDDSPD
Supply
Serial EEPROM positive power supply wired to a separate power pin at the connector
which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation.
RESET
IN
The RESET pin is connected to the RESET pin on the register and to the RESET pin on
the DRAM.
TEST
Rev. 1.1 / Aug. 2013
This signal indicates that a thermal event has been detected in the thermal sensing
device.The system should guarantee the electrical level requirement is met for the
Active Low
EVENT pin on TS/SPD part.
No pull-up resister is provided on DIMM.
Used by memory bus analysis tools (unused (NC) on memory DIMMs)
7
Pin Assignments
Pin
#
Front
Side
Pin
#
Back
Side
Pin
#
Front
Side
Pin
#
Back
Side
Pin
#
Front
Side
Pin
#
Back
Side
Pin
#
Front
Side
Pin
#
Back
Side
1
VREFDQ
2
VSS
53
DQ19
54
VSS
105
VDD
106
VDD
157
DQ42
158
DQ46
3
VSS
4
DQ4
55
VSS
56
DQ28
107 A10/AP
108
BA1
159
DQ43
160
DQ47
5
DQ0
6
DQ5
57
DQ24
58
DQ29
109
BA0
110
RAS
161
VSS
162
VSS
7
DQ1
8
VSS
59
DQ25
60
VSS
111
VDD
112
VDD
163
DQ48
164
DQ52
9
VSS
10
DQS0
61
VSS
62
DQS3
113
WE
114
S0
165
DQ49
166
DQ53
11
DM0
12
DQS0
63
DM3
64
DQS3
115
CAS
116
ODT0
167
VSS
168
VSS
13
VSS
14
VSS
65
VSS
66
VSS
117
VDD
118
VDD
169
DQS6
170
DM6
15
DQ2
16
DQ6
67
DQ26
68
DQ30
119
A132
120
ODT1
171
DQS6
172
VSS
17
DQ3
18
DQ7
69
DQ27
70
DQ31
121
S1
122
NC
173
VSS
174
DQ54
19
VSS
20
VSS
71
VSS
72
VSS
123
VDD
124
VDD
175
DQ50
176
DQ55
21
DQ8
22
DQ12
73
CKE0
74
CKE1
125
TEST
126 VREFCA 177
DQ51
178
VSS
23
DQ9
24
DQ13
75
VDD
76
VDD
127
VSS
128
VSS
179
VSS
180
DQ60
25
VSS
26
VSS
77
NC
78
A152
129
DQ32
130
DQ36
181
DQ56
182
DQ61
27
DQS1
28
DM1
79
BA2
80
A142
131
DQ33
132
DQ37
183
DQ57
184
VSS
29
DQS1
30
RESET
81
VDD
82
VDD
133
VSS
134
VSS
185
VSS
186
DQS7
31
VSS
32
VSS
83 A12/BC
84
A11
135
DQS4
136
DM4
187
DM7
188
DQS7
33
DQ10
34
DQ14
85
A9
86
A7
137
DQS4
138
VSS
189
VSS
190
VSS
35
DQ11
36
DQ15
87
VDD
88
VDD
139
VSS
140
DQ38
191
DQ58
192
DQ62
37
VSS
38
VSS
89
A8
90
A6
141
DQ34
142
DQ39
193
DQ59
194
DQ63
39
DQ16
40
DQ20
91
A5
92
A4
143
DQ35
144
VSS
195
VSS
196
VSS
41
DQ17
42
DQ21
93
VDD
94
VDD
145
VSS
146
DQ44
197
SA0
198
EVENT
43
VSS
44
VSS
95
A3
96
A2
147
DQ40
148
DQ45
199 VDDSPD 200
SDA
45
DQS2
46
DM2
97
A1
98
A0
149
DQ41
150
VSS
201
SA1
202
SCL
47
DQS2
48
VSS
99
VDD
100
VDD
151
VSS
152
DQS5
203
VTT
204
VTT
49
VSS
50
DQ22
101
CK0
102
CK1
153
DM5
154
DQS5
51
DQ18
52
DQ23
103
CK0
104
CK1
155
VSS
156
VSS
NC = No Connect; RFU = Reserved Future Use
1. TEST (pin 125) is reserved for bus analysis probes and is NC on normal memory modules.
2. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be connected to the termination resistor.
Rev. 1.1 / Aug. 2013
8
Functional Block Diagram
SPD/TS
VREFCA
VREFDQ
D0–D3
VDD
D0–D3
D0–D3
VSS
D0–D3, SPD, Temp sensor
CK0
D0–D3
CK0
D0–D3
Terminated at near
card edge
ODT1
NC
S1
NC
EVENT
Temp Sensor
RESET
D0-D3
D0
D1
D2
D3
Vtt
A[O:N]/BA[O:N]
ODT
Vtt
VDDSPD
CK1
A[O:N]/BA[O:N]
ODT
SDA
WP
CK1
240ohm
+/-1%
ODT
CKE
Address and Control Lines
A[O:N]/BA[O:N]
CK
CKE
(SPD)
Vtt
240ohm
+/-1%
D3
CK
A[O:N]/BA[O:N]
ODT
CK
CKE
CK
CKE
CK
CK
A[O:N]/BA[O:N]
ODT0
CK0
CKE0
WE
CK0
CK
WE
CAS
CAS
WE
ZQ
SCL
A0
A1
A2
SCL
SA0
SA1
240ohm
+/-1%
D2
WE
CK
CAS
ZQ
SDA
The SPD may be
integrated with the Temp
Sensor or may be
a separate component
EVENT
D1
WE
CAS
RAS
CS
LDQS
LDQS
LDM
DQ [0:7]
UDQS
UDQS
UDM
DQ [8:15]
CS
DQS6
DQS6
DM6
DQ [48:55]
DQS7
DQS7
DM7
DQ [56:63]
ZQ
SCL
Sensor
A0 Temp
(with SPD)
A1
A2
EVENT
SCL
SA0
SA1
240ohm
+/-1%
D0
LDQS
LDQS
LDM
DQ [0:7]
UDQS
UDQS
UDM
DQ [8:15]
CS
DQS4
DQS4
DM4
DQ [32:39]
DQS5
DQS5
DM5
DQ [40:47]
ZQ
LDQS
LDQS
LDM
DQ [0:7]
UDQS
UDQS
UDM
DQ [8:15]
RAS
DQS2
DQS2
DM2
DQ [16:23]
DQS3
DQS3
DM3
DQ [24:31]
RAS
CS
LDQS
LDQS
LDM
DQ [0:7]
UDQS
UDQS
UDM
DQ [8:15]
RAS
DQS0
DQS0
DM0
DQ [0:7]
DQS1
DQS1
DM1
DQ [8:15]
CAS
S0
RAS
2GB, 256Mx64 Module(1Rank of x16)
NOTES
1. DQ wiring may differ from that shown
however, DQ, DM, DQS, and DQS relationships are maintained as shown
Rank 0
Vtt
Vtt
VDD
Rev. 1.1 / Aug. 2013
9
ODT1
240ohm
+/-1%
SDA
The SPD may be
integrated with the Temp
Sensor or may be
a separate component
EVENT
ODT
CK
CKE
D4
SCL
A0
A1
A2
SCL
SA0
SA1
(SPD)
SDA
WP
Vtt
SPD/TS
VREFCA
VREFDQ
D0–D7
VDD
D0–D7
VSS
D0–D7, SPD, Temp sensor
D0–D7
CK0
D0–D3
CK1
D0–D7
CK0
D0–D3
CK1
D0–D7
EVENT
Temp Sensor
RESET
D0-D7
D4
V1
D0
V2
V2
D5
D1
V3
V3
D6
D2
V4
V4
D7
Vtt
A[O:N]/BA[O:N]
ODT
ODT
CK
CKE
CK
A[O:N]/BA[O:N]
240ohm
+/-1%
D7
WE
A[O:N]/BA[O:N]
ODT
CK
CKE
V1
CK
CKE
CK
ZQ
Vtt
VDDSPD
240ohm
+/-1%
D6
LDQS
LDQS
LDM
DQ [0:7]
UDQS
UDQS
UDM
DQ [8:15]
CAS
CK
ZQ
WE
CAS
RAS
CS
240ohm
+/-1%
D5
WE
CAS
RAS
CS
ZQ
LDQS
LDQS
LDM
DQ [0:7]
UDQS
UDQS
UDM
DQ [8:15]
RAS
ODT
CK
D3
LDQS
LDQS
LDM
DQ [0:7]
UDQS
UDQS
UDM
DQ [8:15]
CS
ODT
240ohm
+/-1%
A[O:N]/BA[O:N]
CK
CKE
CK
A[O:N]/BA[O:N]
240ohm
+/-1%
D2
ZQ
A[O:N]/BA[O:N]
ODT
CK
CKE
CK
WE
ZQ
CKE
CAS
RAS
CS
240ohm
+/-1%
D1
WE
LDQS
LDQS
LDM
DQ [0:7]
UDQS
UDQS
UDM
DQ [8:15]
CAS
DQS6
DQS6
DM6
DQ [48:55]
DQS7
DQS7
DM7
DQ [56:63]
RAS
LDQS
LDQS
LDM
DQ [0:7]
UDQS
UDQS
UDM
DQ [8:15]
CS
DQS4
DQS4
DM4
DQ [32:39]
DQS5
DQS5
DM5
DQ [40:47]
ZQ
WE
CK
CAS
RAS
LDQS
LDQS
LDM
DQ [0:7]
UDQS
UDQS
UDM
DQ [8:15]
CS
DQS2
DQS2
DM2
DQ [16:23]
DQS3
DQS3
DM3
DQ [24:31]
D3
Vtt
WE
SCL
A0 Temp Sensor
(with SPD)
A1
A2
EVENT
SCL
SA0
SA1
A[O:N]/BA[O:N]
CK1
ZQ
CK
CAS
CK1
CKE1
S1
RAS
LDQS
LDQS
LDM
DQ [0:7]
UDQS
UDQS
UDM
DQ [8:15]
CS
A[O:N]/BA[O:N]
ODT0
ODT
CK
CKE
A[O:N]/BA[O:N]
WE
CK0
CKE0
240ohm
+/-1%
D0
CK
CAS
CK0
ZQ
WE
CAS
RAS
LDQS
LDQS
LDM
DQ [0:7]
UDQS
UDQS
UDM
DQ [8:15]
CS
DQS0
DQS0
DM0
DQ [0:7]
DQS1
DQS1
DM1
DQ [8:15]
RAS
S0
4GB, 512Mx64 Module(2Rank of x16)
Address and Control Lines
NOTES
1. DQ wiring may differ from that shown
however, DQ, DM, DQS, and DQS relationships are maintained as shown
Rank 0
Rank 1
Vtt
Vtt
Vtt
VDD
Rev. 1.1 / Aug. 2013
VDD
10
240ohm
+/-1%
SCL
A0 Temp Sensor
(with SPD)
A1
A2
EVENT
SCL
SA0
SA1
A[O:N]/BA[O:N]
ODT
EVENT
CK
CKE
SCL
A0
A1
A2
SCL
SA0
SA1
The SPD may be
integrated with the Temp
Sensor or may be
a separate component
(SPD)
SDA
WP
Vtt
240ohm
+/-1%
ZQ
A[O:N]/BA[O:N]
ODT
CK
CKE
ZQ
A[O:N]/BA[O:N]
ODT
CK
CKE
CK
SPD/TS
VREFCA
VREFDQ
D0–D7
VDD
D0–D7
VSS
D0–D7, SPD, Temp sensor
CK0
D0–D7
CK0
D0–D7
ZQ
S1
NC
ODT1
CKE1
NC
EVENT
Temp Sensor
RESET
D0-D7
NC
V1
D4
V2
V2
A[O:N]/BA[O:N]
ODT
CK
CKE
CK
D5
D1
V3
V3
D6
D2
V4
V4
D7
D3
240ohm
+/-1%
D7
WE
CAS
DQS
DQS
DM
DQ [0:7]
RAS
DQS7
DQS7
DM7
DQ[56:63]
CS
A[O:N]/BA[O:N]
ODT
CK
CKE
CK
D3
WE
CAS
RAS
CS
ZQ
240ohm
+/-1%
Terminated near
card edge
CK1
D0
DQS
DQS
DM
DQ [0:7]
D0–D7
CK1
V1
DQS6
DQS6
DM6
DQ[48:55]
Vtt
VDDSPD
240ohm
+/-1%
D6
WE
CAS
DQS
DQS
DM
DQ [0:7]
CK
WE
D5
CAS
RAS
CS
DQS5
DQS5
DM5
DQ[40:47]
A[O:N]/BA[O:N]
ODT
CK
CKE
DQS
DQS
DM
DQ [0:7]
RAS
A[O:N]/BA[O:N]
ODT
CK
WE
CK
CKE
240ohm
+/-1%
D2
CK
CAS
ZQ
WE
CAS
D1
DQS3
DQS3
DM3
DQ[24:31]
CS
ZQ
DQS
DQS
DM
DQ [0:7]
CS
DQS4
DQS4
DM4
DQ[32:39]
RAS
CS
DQS
DQS
DM
DQ [0:7]
RAS
DQS2
DQS2
DM2
DQ[16:23]
240ohm
+/-1%
Vtt
WE
D4
SDA
Vtt
ZQ
CK
A[O:N]/BA[O:N]
ODT
CK
CKE
CK
WE
D0
DQS
DQS
DM
DQ [0:7]
CAS
DQS1
DQS1
DM1
DQ[8:15]
RAS
240ohm
+/-1%
CS
CK0
CKE0
ODT0
WE
CK0
CAS
ZQ
CAS
RAS
DQS
DQS
DM
DQ [0:7]
CS
DQS0
DQS0
DM0
DQ[0:7]
RAS
S0
4GB, 512Mx64 Module(1Rank of x8)
Address and Control Lines
NOTES
1. DQ wiring may differ from that
shown however, DQ, DM, DQS, and
DQS relationships are maintained as
shown
Rank 0
Rev. 1.1 / Aug. 2013
11
VDD
SCL
A0
A1
A2
D9
(SPD)
SDA
WP
SCL
A0 Temp Sensor
(with SPD)
A1
A2
EVENT
SDA
D0
EVENT
NOTES
1. DQ wiring may differ from that shown
however, DQ, DM, DQS, and DQS relationships are maintained as shown
Rev. 1.1 / Aug. 2013
D3
V1
V9
D12
V8
V3
D8
SCL
SA0
SA1
V2
V7
V4
V4
V5
D10
V5
D2
Rank 1
D1
D5
D13
V6
V6
Vtt
V3
Rank 0
D6
V2
D11
V1
D7
D15
V7
V9
D4
V8
D14
A[O:N]/BA[O:N]
ODT
WE
CK
CAS
DQS6
DQS6
DM6
DQ[48:55]
A[O:N]/BA[O:N]
ODT
CK
CKE
CK
WE
A[O:N]/BA[O:N]
ODT
CK
CKE
CK
D7
WE
240ohm
+/-1%
DQS
DQS
DM
DQ [0:7]
ZQ
DQS5
DQS5
DM5
DQ[40:47]
A[O:N]/BA[O:N]
ODT
WE
D5
CK
CKE
CAS
DQS7
DQS7
DM7
DQ[56:43]
ZQ
CK
RAS
CS
CK
CKE
240ohm
+/-1%
240ohm
+/-1%
DQS
DQS
DM
DQ [0:7]
RAS
DQS4
DQS4
DM4
DQ[32:39]
D6
CAS
RAS
CS
ZQ
Vtt
The SPD may be
integrated with the Temp SCL
SA0
Sensor or may be
SA1
a separate component
240ohm
+/-1%
D12
CAS
A[O:N]/BA[O:N]
ODT
CK
CKE
D13
ZQ
DQS
DQS
DM
DQ [0:7]
CS
A[O:N]/BA[O:N]
ODT
240ohm
+/-1%
ZQ
DQS
DQS
DM
DQ [0:7]
RAS
A[O:N]/BA[O:N]
ODT
CK
CKE
CK
CKE
CK
WE
CAS
D15
Vtt
CS
A[O:N]/BA[O:N]
ODT
CK
CKE
WE
CK
CK
WE
CAS
240ohm
+/-1%
ZQ
CAS
CS
240ohm
+/-1%
D14
WE
RAS
CS
CAS
ZQ
DQS
DQS
DM
DQ [0:7]
A[O:N]/BA[O:N]
ODT
CK
CKE
RAS
CS
A[O:N]/BA[O:N]
ODT
CK
CK
CKE
240ohm
+/-1%
240ohm
+/-1%
D4
DQS
DQS
DM
DQ [0:7]
D10
CK
RAS
CS
A[O:N]/BA[O:N]
ODT
CK
CKE
240ohm
+/-1%
RAS
CK0
ODT0
A[O:N]/BA[O:N]
ODT
CK
CKE
WE
CAS
CK
CK
WE
CAS
CAS
WE
ZQ
ZQ
DQS
DQS
DM
DQ [0:7]
D8
WE
CAS
CS
A[O:N]/BA[O:N]
ODT
CK
CKE
240ohm
+/-1%
ZQ
Cterm
Vtt
DQS
DQS
DM
DQ [0:7]
D9
DQS
DQS
DM
DQ [0:7]
D2
CK
RAS
CS
240ohm
+/-1%
240ohm
+/-1%
ZQ
VDD
Vtt
D3
DQS
DQS
DM
DQ [0:7]
A[O:N]/BA[O:N]
ODT
CK
CKE
CK
WE
ZQ
RAS
CS
A[O:N]/BA[O:N]
ODT
CK
WE
CK
CKE
240ohm
+/-1%
D0
WE
CAS
CAS
CAS
DQS
DQS
DM
DQ [0:7]
ZQ
ZQ
DQS
DQS
DM
DQ [0:7]
D1
CK0
CKE0
S0
CS
A[O:N]/BA[O:N]
ODT
240ohm
+/-1%
RAS
DQS
DQS
DM
DQ [0:7]
RAS
ZQ
Cterm
CK
A[O:N]/BA[O:N]
CK1
CKE1
ODT1
CK
CKE
CK
WE
CAS
RAS
RAS
CS
RAS
DQS
DQS
DM
DQ [0:7]
CS
DQS0
DQS0
DM0
DQ[0:7]
RAS
240ohm
+/-1%
D11
DQS
DQS
DM
DQ [0:7]
CS
WE
ZQ
DQS1
DQS1
DM1
DQ[8:15]
DQS2
DQS2
DM2
DQ[6:23]
CK1
CAS
DQS
DQS
DM
DQ [0:7]
CS
DQS3
DQS3
DM3
DQ[24:31]
RAS
S1
8GB, 1Gx64 Module(2Rank of x8)
Vtt
VDDSPD
SPD/TS
VREFCA
VREFDQ
D0–D15
VDD
D0–D15
VSS
D0–D15, SPD, Temp sensor
CK0
D0–D7
CK1
D8–D15
CK0
D0–D7
CK1
D8–D15
D0–D15
CKE0
D0-D7
CKE1
D8-D15
S0
D0–D7
S1
D8–D15
ODT0
D0–D7
ODT1
D8–D15
EVENT
Temp Sensor
RESET
D0-D15
12
Absolute Maximum Ratings
Absolute Maximum DC Ratings
Absolute Maximum DC Ratings
Symbol
VDD
VDDQ
Parameter
Rating
Units
Notes
Voltage on VDD pin relative to Vss
- 0.4 V ~ 1.8 V
V
1, 3
Voltage on VDDQ pin relative to Vss
- 0.4 V ~ 1.8 V
V
1, 3
V
1
VIN, VOUT Voltage on any pin relative to Vss
TSTG
- 0.4 V ~ 1.8 V
o
-55 to +100
Storage Temperature
C
1, 2
Notes:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement
conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than
0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
DRAM Component Operating Temperature Range
Temperature Range
Symbol
TOPER
Parameter
Normal Operating Temperature Range
Extended Temperature Range
Rating
Units
Notes
0 to 85
oC
1,2
85 to 95
oC
1,3
Notes:
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions.
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC
case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:
a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It
is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range.
Please refer to the DIMM SPD for option availability
b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to use the
Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b).
DDR3 SDRAMs support Extended Temperature Range and please refer to component datasheet and/or the
DIMM SPD for tFEFI requirements in the Extended Temperature Range.
Rev. 1.1 / Aug. 2013
13
AC & DC Operating Conditions
Recommended DC Operating Conditions
Recommended DC Operating Conditions - DDR3L (1.35V) operation
Symbol
VDD
VDDQ
Parameter
Rating
Units
Notes
1.45
V
1,2,3,4
1.45
V
1,2,3,4
Min.
Typ.
Max.
Supply Voltage
1.283
1.35
Supply Voltage for Output
1.283
1.35
Notes:
1. Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDDQ (t) over a
very long period of time (e.g., 1 sec).
2. If maximum limit is exceeded, input levels shall be governed by DDR3 specifications.
3. Under these supply voltages, the device operates to this DDR3L specification.
4. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while VDD and
VDDQ are changed for DDR3 operation (see Figure 0).
Recommended DC Operating Conditions - - DDR3 (1.5V) operation
Symbol
VDD
VDDQ
Parameter
Rating
Units
Notes
1.575
V
1,2,3
1.575
V
1,2,3
Min.
Typ.
Max.
Supply Voltage
1.425
1.5
Supply Voltage for Output
1.425
1.5
Notes:
1. If minimum limit is exceeded, input levels shall be governed by DDR3L specifications.
2. Under 1.5V operation, this DDR3L device operates to the DDR3 specifications under the same speed timings as
defined for this device.
3. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and
VDDQ are changed for DDR3L operation (see Figure 0).
Rev. 1.1 / Aug. 2013
14
Ta
Tb
Tc
Td
Te
Tf
Tg
Th
Ti
Tj
Tk
CK,CK#
VDD, VDDQ (DDR3)
tCKSRX
Tmin = 10ns
VDD, VDDQ (DDR3L)
Tmin = 10ns
Tmin = 200us
T = 500us
RESET#
Tmin = 10ns
CKE
VALID
tDLLK
tIS
COMMAND
READ
BA
READ
1)
tXPR
tMRD
tMRD
tMRD
tMOD
MRS
MRS
MRS
MRS
MR2
MR3
MR1
MR0
tZQinit
ZQCL
1)
VALID
VALID
tIS
ODT
READ
tIS
Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW
VALID
RTT
NOTE 1: From time point “Td” until “Tk” NOP or DES commands must be applied
between MRS and ZQCL commands.
TIME BREAK
DON’T CARE
Figure 0 - VDD/VDDQ Voltage Switch Between DDR3L and DDR3
Rev. 1.1 / Aug. 2013
15
AC & DC Input Measurement Levels
AC and DC Logic Input Levels for Single-Ended Signals
AC and DC Input Levels for Single-Ended Command and Address Signals
Single Ended AC and DC Input Levels for Command and Address
Symbol
VIH.CA(DC90)
VIL.CA(DC90)
VIH.CA(AC160)
VIL.CA(AC160)
VIH.CA(AC135)
VIL.CA(AC135)
VIH.CA(AC125)
VIL.CA(AC125)
VRefCA(DC)
Parameter
DDR3L-800/1066
Min
Max
DDR3L-1333/1600
Min
Max
DDR3L-1866
Min
Max
DC input logic high Vref + 0.09
VDD
Vref + 0.09
VDD
Vref + 0.09
VDD
DC input logic low
VSS
Vref - 0.09
VSS
Vref - 0.09
VSS
Vref - 0.09
AC input logic high Vref + 0.160 Note2 Vref + 0.160 Note2
AC input logic low
Note2 Vref - 0.160 Note2 Vref - 0.160
AC Input logic high Vref + 0.135 Note2 Vref + 0.135 Note2 Vref + 0.135 Note2
AC input logic low
Note2 Vref - 0.135 Note2 Vref - 0.135 Note2 Vref - 0.135
AC Input logic high
Vref + 0.125 Note2
AC input logic low
Note2 Vref - 0.125
Reference Voltage for
0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD
ADD, CMD inputs
Unit Notes
V
V
V
V
V
V
V
V
1
1
1,2,5
1,2,5
1,2,5
1,2,5
1,2,5
1,2,5
V
3,4
Notes:
1. For input only pins except RESET, Vref = VrefCA (DC).
2. Refer to "Overshoot and Undershoot Specifications" on page 29.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefCA(DC) by more than +/-1% VDD (for
ence: approx. +/- 13.5 mV).
refer-
4. For reference: approx. VDD/2 +/- 13.5 mV
5. These levels apply for 1.35 volt (see table above) operation only. If the device is operated at 1.5V (table "Single
Ended AC and DC Input Levels for DQ and DM" on page 17), the respective levels in JESD79-3 (VIH/L.CA(DC100),
VIH/L.CA(AC175), VIH/L.CA(AC150), VIH/L.CA(AC135), VIH/L.CA(AC125) etc.) apply. The 1.5V levels (VIH/
L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC150), VIH/L.CA(AC135), VIH/L.CA(AC125) etc.) do not apply when
the device is operated in the 1.35 voltage range.
Rev. 1.1 / Aug. 2013
16
AC and DC Input Levels for Single-Ended Signals
DDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066s specified in table below.
DDR3 SDRAM will also support corresponding tDS values (Table 43 and Table 50 in “DDR3L Device Operation”) as well as derating tables Table 46 in “DDR3L Device Operation” depending on Vih/Vil AC levels.
Single Ended AC and DC Input Levels for DQ and DM
Symbol
VIH.DQ(DC90)
VIL.DQ(DC90)
VIH.DQ(AC160)
VIL.DQ(AC160)
VIH.DQ(AC135)
VIL.DQ(AC135)
VIH.DQ(AC130)
VIL.DQ(AC130)
VRefDQ(DC)
Parameter
DDR3L-800/1066
Min
Max
DDR3L-1333/1600
Min
Max
DDR3L-1866
Min
Max
DC input logic high Vref + 0.09
VDD
Vref + 0.09
VDD
Vref + 0.09
VDD
DC input logic low
VSS
Vref - 0.09
VSS
Vref - 0.09
VSS
Vref - 0.09
AC input logic high Vref + 0.160
Note2
AC input logic low
Note2
Vref - 0.160
AC Input logic high Vref + 0.135
Note2
Vref + 0.135
Note2
AC input logic low
Note2
Vref - 0.135
Note2
Vref - 0.135
AC Input logic high
Vref + 0.130
Note2
AC input logic low
Note2
Vref - 0.130
Reference Voltage
0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD
for DQ, DM inputs
Unit Notes
V
V
V
V
V
V
V
V
1
1
1, 2, 5
1, 2, 5
1, 2, 5
1, 2, 5
1, 2, 5
1, 2, 5
V
3, 4
Notes:
1. Vref = VrefDQ (DC).
2. Refer to "Overshoot and Undershoot Specifications" on page 29.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference:
approx. +/- 13.5 mV). 4. For reference: approx. VDD/2 +/- 13.5 mV
4. For reference: approx. VDD/2 +/- 13.5 mV
5. These levels apply for 1.35 volt (table "Single Ended AC and DC Input Levels for Command and Address" on
page 16) operation only. If the device is operated at 1.5V (table above), the respective levels in JESD79-3 (VIH/
L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), VIH/L.DQ(AC135) etc.) apply. The 1.5V levels (VIH/
L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), VIH/L.DQ(AC135) etc.) do not apply when the device is
operated in the 1.35 voltage range.
Rev. 1.1 / Aug. 2013
17
Vref Tolerances
The dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in
figure below. It shows a valid reference voltage VRef (t) as a function of time. (VRef stands for VRefCA and
VRefDQ likewise).
VRef (DC) is the linear average of VRef (t) over a very long period of time (e.g. 1 sec). This average has to
meet the min/max requirements in the table "Differential Input Slew Rate Definition" on page 24. Furthermore VRef (t) may temporarily deviate from VRef (DC) by no more than +/- 1% VDD.
voltage
VDD
VRef ac-noise
VRef(DC)
VRef(t)
VRef(DC)max
VDD/2
VRef(DC)min
VSS
time
Illustration of VRef(DC) tolerance and VRef ac-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and VIL(DC) are dependent on VRef.
“VRef ” shall be understood as VRef(DC), as defined in figure above.
This clarifies that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid
high or low level and therefore the time to which setup and hold is measured. System timing and voltage
budgets need to account for VRef(DC) deviations from the optimum position within the data-eye of the input
signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and
voltage associated with VRefac-noise. Timing and voltage effects due to ac-noise on VRef up to the specified limit (+/- 1% of VDD) are included in DRAM timings and their associated deratings.
Rev. 1.1 / Aug. 2013
18
AC and DC Logic Input Levels for Differential Signals
Differential signal definition
tDVAC
Differential Input Voltage(i.e.DQS - DQS#, CK - CK#)
VIL.DIFF.AC.MIN
VIL.DIFF.MIN
0
half cycle
VIL.DIFF.MAX
VIL.DIFF.AC.MAX
tDVAC
time
Definition of differential ac-swing and “time above ac-level” tDVAC
Rev. 1.1 / Aug. 2013
19
Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)
Differential AC and DC Input Levels
DDR3L-800, 1066, 1333, 1600, 1866
Symbol
Parameter
VIHdiff
VILdiff
Differential input high
Differential input logic low
Differential input high ac
Differential input low ac
VIHdiff (ac)
VILdiff (ac)
Min
Max
+ 0.180
Note 3
2 x (VIH (ac) - Vref)
Note 3
Note 3
- 0.180
Note 3
2 x (VIL (ac) - Vref)
Unit Notes
V
V
V
V
1
1
2
2
Notes:
1. Used to define a differential signal slew-rate.
2. For CK - CK use VIH/VIL (ac) of AADD/CMD and VREFCA; for DQS - DQS, DQSL, DQSL, DQSU, DQSU use VIH/VIL
(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low levels is used for a signal group, then the reduced level
applies also here.
3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU
need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specifications" on page 29.
Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS
DDR3L-800/1066/1333/1600
Slew Rate
[V/ns]
tDVAC [ps]
@ |VIH/Ldiff
(ac)| = 320mV
min
max
tDVAC [ps]
@ |VIH/Ldiff
(ac)| = 270mV
min
max
DDR3L-1866
tDVAC [ps]
@ |VIH/Ldiff
(ac)| = 270mV
min
max
tDVAC [ps]
@ |VIH/Ldiff
(ac)| = 250mV
min
max
tDVAC [ps]
@ |VIH/Ldiff
(ac)| = 260mV
min
max
> 4.0
189
-
201
-
163
-
168
-
176
-
4.0
189
-
201
-
163
-
168
-
176
-
3.0
162
-
179
-
140
-
147
-
154
-
2.0
109
-
134
1.8
91
-
119
-
80
-
91
-
97
-
1.6
69
-
100
-
62
-
74
-
78
-
1.4
40
-
76
-
37
-
52
-
56
-
1.2
note
-
44
-
5
-
22
-
24
-
1.0
note
-
note
-
note
-
note
-
note
-
< 1.0
note
-
note
-
note
-
note
-
note
-
95
105
111
note : Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become
equal to or less than VIL(ac) level.
Rev. 1.1 / Aug. 2013
20
Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, of DQSU)also
has to comply with certain requirements for single-ended signals.
CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH
(ac) / VIL (ac)) for ADD/CMD signals) in every half-cycle.
DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels (VIH (ac)
/ VIL (ac)) for DQ signals) in every half-cycle preceding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g., if
VIH.CA(AC150)/VIL.CA(AC150) is used for ADD/CMD signals, then these ac-levels apply also for the singleended signals CK and CK.
VDD or VDDQ
VSEHmin
VSEH
VDD/2 or VDDQ/2
CK or DQS
VSELmax
VSS or VSSQ
VSEL
time
Single-ended requirements for differential signals.
Note that, while ADD/CMD and DQ signal requirements are with respect to Vref, the single-ended components of differential signals have a requirement with respect to VDD / 2; this is nominally the same. the
transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended
components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing,
but adds a restriction on the common mode characteristics of these signals.
Rev. 1.1 / Aug. 2013
21
Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU
Symbol
VSEH
VSEL
Parameter
Single-ended high level for strobes
Single-ended high level for Ck, CK
Single-ended low level for strobes
Single-ended low level for CK, CK
DDR3L-800, 1066, 1333, 1600, 1866
Min
Max
(VDD / 2) + 0.175
(VDD /2) + 0.175
Note 3
Note 3
Note 3
Note 3
(VDD / 2) - 0.175
(VDD / 2) - 0.175
Unit Notes
V
V
V
V
1,2
1,2
1,2
1,2
Notes:
1. For CK, CK use VIH/VIL (ac) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL (ac)
of DQs.
2. VIH (ac)/VIL (ac) for DQs is based on VREFDQ; VIH (ac)/VIL (ac) for ADD/CMD is based on VREFCA; if a reduced
ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU
need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specifications" on page 29.
Rev. 1.1 / Aug. 2013
22
Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and
strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the
requirements in the table below. The differential input cross point voltage VIX is measured from the actual
cross point of true and complement signals to the midlevel between of VDD and VSS
Vix Definition
Vix Definition
Cross point voltage for differential input signals (CK, DQS)
Symbol
Parameter
VIX(CK)
VIX(DQS)
DDR3L-800, 1066, 1333, 1600, 1866
Unit Notes
Min
Max
Differential Input Cross Point Voltage
relative to VDD/2 for CK, CK
-150
-175
150
175
mV
mV
2
1
Differential Input Cross Point Voltage
relative to VDD/2 for DQS, DQS
-150
150
mV
2
Notes:
1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CK and CK are monotonic
with a single-ended swing VSEL / VSEH of at least VDD/2 +/-250 mV, and when the differential slew rate of CK CK is larger than 3 V/ns.
2. The relation between Vix Min/Max and VSEL/VSEH should satisfy following.
(VDD/2) + Vix (Min) - VSEL 25mV
VSEH - ((VDD/2) + Vix (Max)) 25mV
Rev. 1.1 / Aug. 2013
23
Slew Rate Definitions for Single-Ended Input Signals
See 7.5 “Address / Command Setup, Hold and Derating” in “DDR3L Device Operation” for single-ended
slew rate definitions for address and command signals.
See 7.6 “Data Setup, Hold and Slew Rate Derating” in “DDR3L Device Operation” for single-ended slew
rate definition for data signals.
Slew Rate Definitions for Differential Input Signals
Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in table
and figure below.
Differential Input Slew Rate Definition
Measured
Description
Differential input slew rate for rising edge
(CK-CK and DQS-DQS)
Differential input slew rate for falling edge
(CK-CK and DQS-DQS)
Defined by
Min
Max
VILdiffmax
VIHdiffmin
[VIHdiffmin-VILdiffmax] / DeltaTRdiff
VIHdiffmin
VILdiffmax
[VIHdiffmin-VILdiffmax] / DeltaTFdiff
Differential Input Voltage (i.e. DQS-DQS; CK-CK)
Notes:
The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds.
Delta
TRdiff
VIHdiffmin
0
VILdiffmax
Delta
TFdiff
Differential Input Slew Rate Definition for DQS, DQS and CK, CK
Rev. 1.1 / Aug. 2013
24
AC & DC Output Measurement Levels
Single Ended AC and DC Output Levels
Table below shows the output levels used for measurements of single ended signals.
Single-ended AC and DC Output Levels
Symbol
Parameter
VOH(DC)
DC output high measurement level (for IV curve linearity)
VOM(DC)
DC output mid measurement level (for IV curve linearity)
VOL(DC)
DC output low measurement level (for IV curve linearity)
VOH(AC)
AC output high measurement level (for output SR)
VOL(AC)
AC output low measurement level (for output SR)
DDR3L-800, 1066,
1333, 1600, 1866
0.8 x VDDQ
Unit
Notes
V
0.5 x VDDQ
0.2 x VDDQ
V
VTT + 0.1 x VDDQ
VTT - 0.1 x VDDQ
V
1
V
1
V
Notes:
1. The swing of ±0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with
a driver impedance of 40 Ω and an effective test load of 25 Ω to VTT = VDDQ / 2.
Differential AC and DC Output Levels
Table below shows the output levels used for measurements of single ended signals.
Differential AC and DC Output Levels
Symbol
VOHdiff (AC)
VOLdiff (AC)
Parameter
DDR3L-800, 1066,
1333, 1600, 1866
+ 0.2 x VDDQ
AC differential output high measurement level (for output SR)
- 0.2 x VDDQ
AC differential output low measurement level (for output SR)
Unit
Notes
V
1
V
1
Notes:
1. The swing of ±0.2 x VDDQ is based on approximately 50% of the static differential output high or low swing with
a driver impedance of 40 Ω and an effective test load of 25 Ω to VTT = VDDQ/2 at each of the differential outputs.
Rev. 1.1 / Aug. 2013
25
Single Ended Output Slew Rate
When the Reference load for timing measurements, output slew rate for falling and rising edges is defined
and measured between VOL(AC) and VOH(AC) for single ended signals are shown in table and Figure below.
Single-ended Output slew Rate Definition
Measured
Description
Defined by
From
To
Single-ended output slew rate for rising edge
VOL(AC)
VOH(AC)
[VOH(AC)-VOL(AC)] / DeltaTRse
Single-ended output slew rate for falling edge
VOH(AC)
VOL(AC)
[VOH(AC)-VOL(AC)] / DeltaTFse
Notes:
1. Output slew rate is verified by design and characterisation, and may not be subject to production test.
Single Ended Output Voltage(l.e.DQ)
Delta TRse
VOH(AC)
V∏
VOl(AC)
Delta TFse
Single Ended Output slew Rate Definition
Output Slew Rate (single-ended)
DDR3L-800 DDR3L-1066DDR3L-1333DDR3L-1600DDR3L-1866
Parameter
Symbol Min
Single-ended Output Slew Rate SRQse
1.75
Max
Min
Max
Min
Max
Min
Max
Min
Max
51)
1.75
51)
1.75
51)
1.75
51)
1.75
51)
Units
V/ns
Description: SR; Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
se: Single-ended Signals
For Ron = RZQ/7 setting
Note 1): In two cases, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.
Case 1 is a defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high
to low or low to high) while all remaining DQ signals in the same byte lane are static (i.e. they stay at either high or low).
Case 2 is a defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high
to low or low to high) while all remaining DQ signals in the same byte lane switching into the opposite direction (i.e. from
low to high of high to low respectively). For the remaining DQ signal switching in to the opposite direction, the regular
maximum limite of 5 V/ns applies.
Rev. 1.1 / Aug. 2013
26
Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined
and measured between VOLdiff (AC) and VOHdiff (AC) for differential signals as shown in table and figure
below.
Differential Output Slew Rate Definition
Measured
Description
Defined by
From
To
Differential output slew rate for rising edge
VOLdiff (AC)
VOHdiff (AC)
[VOHdiff (AC)-VOLdiff (AC)] / DeltaTRdiff
Differential output slew rate for falling edge
VOHdiff (AC)
VOLdiff (AC)
[VOHdiff (AC)-VOLdiff (AC)] / DeltaTFdiff
Notes:
1. Output slew rate is verified by design and characterization, and may not be subject to production test.
Differential Output Voltage(i.e. DQS-DQS)
Delta
TRdiff
VOHdiff(AC)
O
VOLdiff(AC)
Delta
TFdiff
Differential Output slew Rate Definition
Differential Output Slew Rate
DDR3L-800 DDR3L-1066 DDR3L-1333 DDR3L-1600 DDR3L-1866
Parameter
Symbol Min
Max
Min
Max
Min
Differential Output Slew Rate SRQdiff 3.5
12
3.5
12
3.5
Description: SR; Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
se: Single-ended Signals
For Ron = RZQ/7 setting
Rev. 1.1 / Aug. 2013
Max
Min
Max
Min
Max
12
3.5
12
3.5
12
Units
V/ns
27
Reference Load for AC Timing and Output Slew Rate
Figure below represents the effective reference load of 25 ohms used in defining the relevant AC timing
parameters of the device as well as output slew rate measurements.
It is not intended as a precise representation of any particular system environment or a depiction of the
actual load presented by a production tester. System designers should use IBIS or other simulation tools to
correlate the timing reference load to a system environment. Manufacturers correlate to their production
test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.
VDDQ
CK, CK
DUT
DQ
DQS
DQS
25 Ohm
VTT = VDDQ/2
Reference Load for AC Timing and Output Slew Rate
Rev. 1.1 / Aug. 2013
28
Overshoot and Undershoot Specifications
Address and Control Overshoot and Undershoot Specifications
AC Overshoot/Undershoot Specification for Address and Control Pins
DDR3 DDR3 DDR3 DDR3 DDR3
Parameter
L-800 L-1066 L-1333 L-1600 L-1866
Maximum peak amplitude allowed for overshoot area. (See Figure below)
0.4
Maximum peak amplitude allowed for undershoot area. (See Figure below) 0.4
Maximum overshoot area above VDD (See Figure below)
0.67
Maximum undershoot area below VSS (See Figure below)
0.67
(A0-A15, BA0-BA3, CS, RAS, CAS, WE, CKE, ODT)
See figure below for each parameter definition
0.4
0.4
0.5
0.5
0.4
0.4
0.4
0.4
0.4
0.4
0.33
0.33
Units
0.4
V
0.4
V
0.28 V-ns
0.28 V-ns
Maximum Amplitude
Overshoot Area
Volts
(V)
VDD
VSS
Undershoot Area
Maximum Amplitude
Time (ns)
Address and Control Overshoot and Undershoot Definition
Rev. 1.1 / Aug. 2013
29
Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications
AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask
DDR3 DDR3 DDR3 DDR3 DDR3
Parameter
L-800 L-1066L-1333L-1600L-1866
Maximum peak amplitude allowed for overshoot area. (See Figure below)
0.4
Maximum peak amplitude allowed for undershoot area. (See Figure below)
0.4
Maximum overshoot area above VDD (See Figure below)
0.25
Maximum undershoot area below VSS (See Figure below)
0.25
(CK, CK, DQ, DQS, DQS, DM)
See figure below for each parameter definition
0.4
0.4
0.19
0.19
0.4
0.4
0.15
0.15
0.4
0.4
0.13
0.13
Units
0.4
V
0.4
V
0.11 V-ns
0.11 V-ns
Maximum Amplitude
Overshoot Area
Volts
(V)
VDDQ
VSSQ
Undershoot Area
Maximum Amplitude
Time (ns)
Clock, Data, Strobe and Mask Overshoot and Undershoot Definition
Rev. 1.1 / Aug. 2013
30
Refresh parameters by device density
Refresh parameters by device density
Parameter
REF command ACT or
REF command time
Average periodic
refresh interval
RTT_Nom Setting
512Mb
1Gb
2Gb
4Gb
8Gb
Units
tRFC
90
110
160
260
350
ns
7.8
7.8
7.8
7.8
7.8
us
3.9
3.9
3.9
3.9
3.9
us
tREFI
0 C TCASE 85 C
85 C TCASE 95 C
Notes:
1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices
support the following options or requirements referred to in this materia.
Rev. 1.1 / Aug. 2013
31
Standard Speed Bins
DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
DDR3L-800 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 37.
Speed Bin
DDR3L-800E
CL - nRCD - nRP
6-6-6
Unit
Notes
Parameter
Symbol
min
max
Internal read command to first data
tAA
15
20
ns
ACT to internal read or write delay time
tRCD
15
—
ns
PRE command period
tRP
15
—
ns
ACT to ACT or REF command period
tRC
52.5
—
ns
ACT to PRE command period
tRAS
37.5
9 * tREFI
ns
CWL = 5
tCK(AVG)
3.0
3.3
ns
1, 2, 3, 4, 11
CWL = 5
tCK(AVG)
2.5
3.3
ns
1, 2, 3
Supported CL Settings
5, 6
nCK
10
Supported CWL Settings
5
nCK
CL = 5
CL = 6
Rev. 1.1 / Aug. 2013
32
DDR3L-1066 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 37.
Speed Bin
DDR3L-1066F
CL - nRCD - nRP
Parameter
Symbol
Unit
7-7-7
min
max
Note
Internal read command to
first data
tAA
13.125
20
ns
ACT to internal read or
write delay time
tRCD
13.125
—
ns
PRE command period
tRP
13.125
—
ns
ACT to ACT or REF
command period
tRC
50.625
—
ns
ACT to PRE command
period
tRAS
37.5
9 * tREFI
ns
CWL = 5
tCK(AVG)
3.0
3.3
ns
1, 2, 3, 4, 6, 11
CWL = 6
tCK(AVG)
ns
4
CWL = 5
tCK(AVG)
ns
1, 2, 3, 6
CWL = 6
tCK(AVG)
Reserved
ns
1, 2, 3, 4
CWL = 5
tCK(AVG)
Reserved
ns
4
CWL = 6
tCK(AVG)
ns
1, 2, 3, 4
CWL = 5
tCK(AVG)
ns
4
CWL = 6
tCK(AVG)
ns
1, 2, 3
5, 6, 7, 8
nCK
10
5, 6
nCK
CL = 5
CL = 6
CL = 7
CL = 8
Supported CL Settings
Supported CWL Settings
Rev. 1.1 / Aug. 2013
Reserved
2.5
3.3
1.875
< 2.5
Reserved
1.875
< 2.5
33
DDR3L-1333 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 37.
Speed Bin
DDR3L-1333H
CL - nRCD - nRP
Parameter
Symbol
Unit
9-9-9
min
max
Note
Internal read
command to first data
tAA
13.5
(13.125)5,10
20
ns
ACT to internal read or
write delay time
tRCD
13.5
(13.125)5,10
—
ns
PRE command period
tRP
13.5
(13.125)5,10
—
ns
ACT to ACT or REF
command period
tRC
49.5
(49.125)5,10
—
ns
ACT to PRE command
period
tRAS
36
9 * tREFI
ns
CWL = 5
tCK(AVG)
3.0
3.3
ns
1, 2, 3, 4, 7, 11
CWL = 6, 7
tCK(AVG)
ns
4
CWL = 5
tCK(AVG)
ns
1, 2, 3, 7
CWL = 6
tCK(AVG)
Reserved
ns
1, 2, 3, 4, 7
CWL = 7
tCK(AVG)
Reserved
ns
4
CWL = 5
tCK(AVG)
Reserved
ns
4
CWL = 6
tCK(AVG)
ns
1, 2, 3, 4, 7
CWL = 7
tCK(AVG)
Reserved
ns
1, 2, 3, 4
CWL = 5
tCK(AVG)
Reserved
ns
4
CWL = 6
tCK(AVG)
ns
1, 2, 3, 7
CWL = 7
tCK(AVG)
Reserved
ns
1, 2, 3, 4
CWL = 5, 6
tCK(AVG)
Reserved
ns
4
CWL = 7
tCK(AVG)
ns
1, 2, 3, 4
CWL = 5, 6
tCK(AVG)
ns
4
CWL = 7
tCK(AVG)
ns
ns
1, 2, 3
(Optional)
Supported CL Settings
6, (7), 8, 9, 10
nCK
Supported CWL Settings
5, 6, 7
nCK
CL = 5
CL = 6
CL = 7
CL = 8
CL = 9
CL = 10
Rev. 1.1 / Aug. 2013
Reserved
2.5
3.3
1.875
< 2.5
(Optional)5,10
1.875
< 2.5
1.5
<1.875
Reserved
1.5
<1.875
34
DDR3L-1600 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 37.
Speed Bin
DDR3L-1600K
CL - nRCD - nRP
Parameter
Symbol
Unit
11-11-11
min
max
Internal read
command to first data
tAA
13.75
(13.125)5,10
20
ns
ACT to internal read or
write delay time
tRCD
13.75
(13.125)5,10
—
ns
PRE command period
tRP
13.75
(13.125)5,10
—
ns
ACT to ACT or REF
command period
tRC
48.75
(48.125)5,10
—
ns
ACT to PRE command
period
tRAS
35
9 * tREFI
ns
CWL = 5
tCK(AVG)
3.0
3.3
ns
CWL = 6, 7
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CL = 5
CWL = 5
CL = 6
CWL = 6
CWL = 7
CWL = 5
CL = 7
CWL = 6
tCK(AVG)
CWL = 7
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 8
CWL = 5
CL = 8
CWL = 6
CWL = 7
CWL = 8
CWL = 5, 6
CL = 9
CWL = 7
tCK(AVG)
tCK(AVG)
CWL = 5, 6 tCK(AVG)
tCK(AVG)
CL = 10 CWL = 7
tCK(AVG)
CWL = 8
CWL = 5, 6,7 tCK(AVG)
CL = 11
tCK(AVG)
CWL = 8
Supported CL Settings
Supported CWL Settings
Rev. 1.1 / Aug. 2013
ns
1, 2, 3, 4,
8, 11
4
ns
1, 2, 3, 8
Reserved
ns
1, 2, 3, 4, 8
Reserved
ns
4
ns
4
ns
1, 2, 3, 4, 8
ns
1, 2, 3, 4, 8
Reserved
2.5
3.3
Reserved
1.875
< 2.5
(Optional)5,10
Reserved
Reserved
Reserved
1.875
< 2.5
Reserved
Reserved
Reserved
1.5
<1.875
(Optional)5,10
Reserved
CWL = 8
Note
Reserved
1.5
<1.875
Reserved
Reserved
1.25
<1.5
5, 6, (7), 8, (9), 10, 11
5, 6, 7, 8
ns
4
ns
4
ns
1, 2, 3, 8
ns
1, 2, 3, 4, 8
ns
1, 2, 3, 4
ns
4
ns
1, 2, 3, 4, 8
ns
1, 2, 3, 4
ns
4
ns
1, 2, 3, 8
ns
1, 2, 3, 4
ns
4
ns
nCK
nCK
1, 2, 3
35
DDR3L-1866 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 37.
Speed Bin
DDR3L-1866M
CL - nRCD - nRP
Parameter
Symbol
Internal read command
tAA
to first data
ACT to internal read or
tRCD
write delay time
PRE command period
tRP
ACT to PRE command
period
ACT to ACT or PRE
command period
tRAS
tRC
tCK(AVG)
CWL = 6,7,8,9 tCK(AVG)
tCK(AVG)
CWL = 5
tCK(AVG)
CWL = 6
CL = 6
CWL = 7,8,9 tCK(AVG)
tCK(AVG)
CWL = 5
CL = 5
CL = 7
CL = 8
CWL = 5
CWL = 6
tCK(AVG)
CWL = 7,8,9
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 5
CWL = 6
CWL = 7
CWL = 8,9
CWL = 5, 6
CL = 9
CWL = 7
tCK(AVG)
CWL = 8
CWL = 5,6,7
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 8
tCK(AVG)
CWL = 9
CL = 10
CWL = 5, 6
CWL = 7
CWL = 8
CL = 11
tCK(AVG)
CWL = 5,6,7,8 tCK(AVG)
CL = 12
tCK(AVG)
CWL = 9
CWL = 5,6,7,8 tCK(AVG)
CL = 13
tCK(AVG)
CWL = 9
Supported CL Settings
Supported CWL Settings
Note
max
13.91
(13.125)5,12
13.91
(13.125)5,12
13.91
(13.125)5,12
34
20
ns
—
ns
—
ns
9 * tREFI
ns
-
ns
47.91
(47.125)5,12
3.0
3.3
Reserved
2.5
3.3
ns
1, 2, 3, 4, 9
ns
4
ns
1, 2, 3, 9
Reserved
ns
1, 2, 3, 4, 9
Reserved
ns
4
ns
4
ns
1, 2, 3, 4, 9
Reserved
ns
4
Reserved
ns
ns
4
1, 2, 3, 9
Reserved
ns
1, 2, 3, 4, 9
Reserved
ns
4
Reserved
ns
4
ns
1, 2, 3, 4, 9
Reserved
ns
1, 2, 3, 4, 9
Reserved
ns
4
Reserved
ns
ns
4
1, 2, 3, 9
Reserved
ns
1, 2, 3, 4, 9
Reserved
ns
4
ns
1, 2, 3, 4, 9
ns
1, 2, 3, 4
Reserved
1.875
< 2.5
(Optinal)
1.875
< 2.5
1.5
<1.875
(Optinal)
1.5
<1.875
1.25
<1.5
(Optinal)
Reserved
CWL = 9
Rev. 1.1 / Aug. 2013
Unit
13-13-13
min
Reserved
ns
4
Reserved
ns
1,2,3,4
ns
ns
4
1, 2, 3
Reserved
1.07
<1.25
6, 7, 8, 9, 10, 11,13
5, 6, 7, 8, 9
nCK
nCK
36
Speed Bin Table Notes
Absolute Specification (TOPER; VDDQ = VDD = 1.35V +0.100/- 0.067 V);
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should
use the next smaller JEDEC standard tCK(AVG) value (3.0, 2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next ‘Supported CL’, where tCK(AVG) =
3.0 ns should only be used for CL = 5 calculation.
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG)
down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is
tCK(AVG).MAX corresponding to CL SELECTED.
4. ‘Reserved’ settings are not allowed. User must program a different value.
5. ‘Optional’ settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to DIMM data sheet and/or the DIMM SPD information if and how this setting is
supported.
6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
9. Any DDR3-1866 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
10. DDR3 SDRAM devices supporting optional down binning to CL=7 and CL=9, and tAA/tRCD/tRP must
be 13.125 ns or lower. SPD settings must be programmed to match. For example, DDR3-1333H
devices supporting down binning to DDR3-1066F should program 13.125 ns in SPD bytes for tAAmin
(Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600K devices supporting down binning to
DDR3-1333H or DDR3-1600F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin
(Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23)
also should be programmed accordingly. For example, 49.125ns (tRASmin + tRPmin = 36 ns + 13.125
ns) for DDR3-1333H and 48.125ns (tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3-1600K.
11. For CL5 support, refer to DIMM SPD information. DRAM is required to support CL5. CL5 is not mandatory in SPD coding.
12. DDR3 SDRAM devices supporting optional down binning to CL=11, CL=9 and CL=7, tAA/tRCD/tRPmin
must be 13.125ns. SPD setting must be programed to match. For example, DDR3-1866M devices supporting down binning to DDR3-1600K or DDR3-1333H or 1066F should program 13.125ns in SPD
bytes for tAAmin(byte16), tRCDmin(byte18) and tRPmin(byte20). Once tRP (byte20) is programmed
to
13.125ns, tRCmin(byte 21,23) also should be programmed accordingly. For example,
47.125ns(tRASmin + tRPmin = 34ns + 13.125ns)
Rev. 1.1 / Aug. 2013
37
Environmental Parameters
Symbol
Parameter
Rating
TOPR
Operating temperature
0 to 65
HOPR
Operating humidity (relative)
10 to 90
TSTG
Storage temperature
HSTG
Storage humidity (without condensation)
PBAR
Barometric Pressure (operating & storage)
Units
o
Notes
C
1, 3
%
1
o
C
1
5 to 95
%
1
105 to 69
K Pascal
1, 2
-50 to +100
Note:
1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and
device functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum
rating conditions for extended periods may affect reliablility.
2. Up to 9850 ft.
3. The designer must meet the case temperature specifications for individual module components.
Rev. 1.1 / Aug. 2013
38
IDD and IDDQ Specification Parameters and Test Conditions
IDD and IDDQ Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure
1. shows the setup and test load for IDD and IDDQ measurements.
•
IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R,
IDD4W, IDD5B, IDD6, IDD6ET and IDD7) are measured as time-averaged currents with all VDD balls
of the DDR3L SDRAM under test tied together. Any IDDQ current is not included in IDD currents.
•
IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all
VDDQ balls of the DDR3L SDRAM under test tied together. Any IDD current is not included in IDDQ
currents.
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3L SDRAM. They can
be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In
DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one
merged-power layer in Module PCB.
For IDD and IDDQ measurements, the following definitions apply:
•
”0” and “LOW” is defined as VIN <= VILAC(max).
•
”1” and “HIGH” is defined as VIN >= VIHAC(max).
•
“MID_LEVEL” is defined as inputs are VREF = VDD/2.
•
Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1.
•
Basic IDD and IDDQ Measurement Conditions are described in Table 2.
•
Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10.
•
IDD Measurements are done after properly initializing the DDR3L SDRAM. This includes but is not limited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0B (Output Buffer enabled in MR1);
RTT_Nom = RZQ/6 (40 Ohm in MR1);
RTT_Wr = RZQ/2 (120 Ohm in MR2);
TDQS Feature disabled in MR1
•
Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time
before actual IDD or IDDQ measurement is started.
•
Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}
•
Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}
Rev. 1.1 / Aug. 2013
39
IDDQ (optional)
IDD
VDD
VDDQ
RESET
CK/CK
DDR3L
SDRAM
CKE
CS
RAS, CAS, WE
DQS, DQS
DQ, DM,
TDQS, TDQS
A, BA
ODT
ZQ
VSS
RTT = 25 Ohm
VDDQ/2
VSSQ
Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements
[Note: DIMM level Output test load condition may be different from above
Application specific
memory channel
environment
IDDQ
Test Load
Channel
IO Power
Simulation
IDDQ
Simulation
IDDQ
Simulation
Correction
Channel IO Power
Number
Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported
by IDDQ Measurement
Rev. 1.1 / Aug. 2013
40
Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns
Symbol
tCK
DDR3L-1066
DDR3L-1333
DDR3L-1600
DDR3L-1866
7-7-7
9-9-9
11-11-11
13-13-13
1.875
1.5
1.25
1.07
Unit
ns
CL
7
9
11
13
nCK
nRCD
7
9
11
13
nCK
nRC
27
33
39
45
nCK
nRAS
20
24
28
32
nCK
nRP
7
9
11
13
nCK
1KB page size
20
20
24
26
nCK
2KB page size
27
30
32
33
nCK
1KB page size
4
4
5
5
nCK
nFAW
nRRD
6
5
6
6
nCK
nRFC -512Mb
2KB page size
48
60
72
85
nCK
nRFC-1 Gb
59
74
88
103
nCK
nRFC- 2 Gb
86
107
128
150
nCK
nRFC- 4 Gb
139
174
208
243
nCK
nRFC- 8 Gb
187
234
280
328
nCK
Table 2 -Basic IDD and IDDQ Measurement Conditions
Symbol
Description
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT and
IDD0
PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: MID-LEVEL;
DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 3.
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT,
IDD1
RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4; DM:
stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and
RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 4.
Rev. 1.1 / Aug. 2013
41
Symbol
Description
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
IDD2N
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details:
see Table 5.
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
IDD2NT Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: toggling according to Table 6;
Pattern Details: see Table 6.
Precharge Power-Down Current Slow Exit
IDD2P0
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exitc)
Precharge Power-Down Current Fast Exit
IDD2P1
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exitc)
Precharge Quiet Standby Current
IDD2Q
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
Active Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
IDD3N
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see
Table 5.
Active Power-Down Current
IDD3P
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer
and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
Rev. 1.1 / Aug. 2013
42
Symbol
Description
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Command, Address,
IDD4R
Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different
data between one burst and the next one according to Table 7; DM: stable at 0; Bank Activity: all banks open,
RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer and RTT: Enabled in Mode
Registersb); ODT Signal: stable at 0; Pattern Details: see Table 7.
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between WR; Command, Address,
IDD4W
Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst with different
data between one burst and the next one according to Table 8; DM: stable at 0; Bank Activity: all banks open,
WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buffer and RTT: Enabled in Mode
Registersb); ODT Signal: stable at HIGH; Pattern Details: see Table 8.
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8a); AL: 0; CS: High between REF; Command,
IDD5B
Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM: stable at 0;
Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in Mode Registersb);
ODT Signal: stable at 0; Pattern Details: see Table 9.
Self-Refresh Current: Normal Temperature Range
TCASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale); CKE:
IDD6
Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Output Buffer
and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL
Self-Refresh Current: Extended Temperature Range
TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Extendede);
IDD6ET
CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Temperature Self-Refresh
operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL
Rev. 1.1 / Aug. 2013
43
Symbol
Description
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8a,f); AL: CL-1; CS:
High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according to Table
IDD7
10; Data IO: read data burst with different data between one burst and the next one according to Table 10;
DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with different addressing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern
Details: see Table 10.
a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B;
RTT_Wr enable: set MR2 A[10,9] = 10B
c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable
e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range
f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B
Rev. 1.1 / Aug. 2013
44
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
0
ACT
0
0
1
1
0
0
00
0
0
0
0
-
1,2
D, D
1
0
0
0
0
0
00
0
0
0
0
-
D, D
1
1
1
1
0
0
00
0
0
0
0
-
0
0
0
-
0
F
0
-
Cycle
Number
Datab)
Sub-Loop
CKE
CK, CK
Table 3 - IDD0 Measurement-Loop Patterna)
0
3,4
...
nRAS
...
Static High
toggling
1*nRC+0
repeat pattern 1...4 until nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
00
0
repeat pattern 1...4 until nRC - 1, truncate if necessary
ACT
0
0
1
1
0
0
00
0
1*nRC+1, 2
D, D
1
0
0
0
0
0
00
0
0
F
0
-
1*nRC+3, 4
D, D
1
1
1
1
0
0
00
0
0
F
0
-
0
-
...
1*nRC+nRAS
repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
00
0
0
...
repeat pattern 1...4 until 2*nRC - 1, truncate if necessary
1
2*nRC
repeat Sub-Loop 0, use BA[2:0] = 1 instead
2
4*nRC
repeat Sub-Loop 0, use BA[2:0] = 2 instead
3
6*nRC
repeat Sub-Loop 0, use BA[2:0] = 3 instead
4
8*nRC
repeat Sub-Loop 0, use BA[2:0] = 4 instead
5
10*nRC
repeat Sub-Loop 0, use BA[2:0] = 5 instead
6
12*nRC
repeat Sub-Loop 0, use BA[2:0] = 6 instead
7
14*nRC
repeat Sub-Loop 0, use BA[2:0] = 7 instead
F
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Rev. 1.1 / Aug. 2013
45
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
0
ACT
0
0
1
1
0
0
00
0
0
0
0
-
1,2
D, D
1
0
0
0
0
0
00
0
0
0
0
-
D, D
1
1
1
1
0
0
00
0
0
0
0
-
0
0
00000000
0
0
0
-
Cycle
Number
Datab)
Sub-Loop
CKE
CK, CK
Table 4 - IDD1 Measurement-Loop Patterna)
0
3,4
...
nRCD
...
nRAS
Static High
toggling
...
repeat pattern 1...4 until nRCD - 1, truncate if necessary
RD
0
1
0
1
0
0
00
0
0
repeat pattern 1...4 until nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
00
0
repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0
ACT
0
0
1
1
0
0
00
0
0
F
0
-
1*nRC+1,2
D, D
1
0
0
0
0
0
00
0
0
F
0
-
D, D
1
1
1
1
0
0
00
0
0
F
0
-
1*nRC+3,4
...
1*nRC+nRCD
...
1*nRC+nRAS
repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary
RD
0
1
0
1
0
0
00
0
0
F
0
00110011
repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
00
0
0
F
...
repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary
1
2*nRC
repeat Sub-Loop 0, use BA[2:0] = 1 instead
2
4*nRC
repeat Sub-Loop 0, use BA[2:0] = 2 instead
3
6*nRC
repeat Sub-Loop 0, use BA[2:0] = 3 instead
4
8*nRC
repeat Sub-Loop 0, use BA[2:0] = 4 instead
5
10*nRC
repeat Sub-Loop 0, use BA[2:0] = 5 instead
6
12*nRC
repeat Sub-Loop 0, use BA[2:0] = 6 instead
7
14*nRC
repeat Sub-Loop 0, use BA[2:0] = 7 instead
0
-
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID_LEVEL.
Rev. 1.1 / Aug. 2013
46
Static High
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
0
D
1
0
0
0
0
0
0
0
0
0
0
-
1
D
1
0
0
0
0
0
0
0
0
0
0
-
2
D
1
1
1
1
0
0
0
0
0
F
0
-
3
D
1
1
1
1
0
0
0
0
0
F
0
-
Cycle
Number
Command
0
toggling
Datab)
Sub-Loop
CKE
CK, CK
Table 5 - IDD2N and IDD3N Measurement-Loop Patterna)
1
4-7
repeat Sub-Loop 0, use BA[2:0] = 1 instead
2
8-11
repeat Sub-Loop 0, use BA[2:0] = 2 instead
3
12-15
repeat Sub-Loop 0, use BA[2:0] = 3 instead
4
16-19
repeat Sub-Loop 0, use BA[2:0] = 4 instead
5
20-23
repeat Sub-Loop 0, use BA[2:0] = 5 instead
6
24-17
repeat Sub-Loop 0, use BA[2:0] = 6 instead
7
28-31
repeat Sub-Loop 0, use BA[2:0] = 7 instead
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Static High
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
0
D
1
0
0
0
0
0
0
0
0
0
0
-
1
D
1
0
0
0
0
0
0
0
0
0
0
-
2
D
1
1
1
1
0
0
0
0
0
F
0
-
3
D
1
1
1
1
0
0
0
0
0
F
0
-
Cycle
Number
Command
0
toggling
Datab)
Sub-Loop
CKE
CK, CK
Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Patterna)
1
4-7
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1
2
8-11
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2
3
12-15
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3
4
16-19
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4
5
20-23
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5
6
24-17
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6
7
28-31
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Rev. 1.1 / Aug. 2013
47
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
0
RD
0
1
0
1
0
0
00
0
0
0
0
00000000
1
D
1
0
0
0
0
0
00
0
0
0
0
-
2,3
D,D
1
1
1
1
0
0
00
0
0
0
0
-
4
RD
0
1
0
1
0
0
00
0
0
F
0
00110011
D
1
0
0
0
0
0
00
0
0
F
0
-
D,D
1
1
1
1
0
0
00
0
0
F
0
-
Cycle
Number
Datab)
Sub-Loop
CKE
CK, CK
Table 7 - IDD4R and IDDQ4R Measurement-Loop Patterna)
0
Static High
toggling
5
6,7
1
8-15
repeat Sub-Loop 0, but BA[2:0] = 1
2
16-23
repeat Sub-Loop 0, but BA[2:0] = 2
3
24-31
repeat Sub-Loop 0, but BA[2:0] = 3
4
32-39
repeat Sub-Loop 0, but BA[2:0] = 4
5
40-47
repeat Sub-Loop 0, but BA[2:0] = 5
6
48-55
repeat Sub-Loop 0, but BA[2:0] = 6
7
56-63
repeat Sub-Loop 0, but BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
A[2:0]
1
1
1
1
1
1
=
=
=
=
=
=
=
A[6:3]
ODT
WE
CAS
RAS
CS
0
1
0
0
1
0
0
0
1
1
1
1
0
1
0
0
1
0
0
0
1
1
1
1
Sub-Loop 0, but BA[2:0]
Sub-Loop 0, but BA[2:0]
Sub-Loop 0, but BA[2:0]
Sub-Loop 0, but BA[2:0]
Sub-Loop 0, but BA[2:0]
Sub-Loop 0, but BA[2:0]
Sub-Loop 0, but BA[2:0]
A[9:7]
WR
D
D,D
WR
D
D,D
repeat
repeat
repeat
repeat
repeat
repeat
repeat
A[10]
1
2
3
4
5
6
7
1
2,3
4
5
6,7
8-15
16-23
24-31
32-39
40-47
48-55
56-63
A[15:11]
0
BA[2:0]
0
Command
Cycle
Number
Sub-Loop
CKE
Static High
toggling
CK, CK
Table 8 - IDD4W Measurement-Loop Patterna)
Datab)
0
0
0
0
0
0
00
00
00
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
F
0
0
0
0
0
0
00000000
00110011
-
1
2
3
4
5
6
7
a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
Rev. 1.1 / Aug. 2013
48
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
0
0
REF
0
0
0
1
0
0
0
0
0
0
0
-
1
1.2
D, D
1
0
0
0
0
0
00
0
0
0
0
-
D, D
1
1
1
1
0
0
00
0
0
F
0
-
Cycle
Number
Datab)
Sub-Loop
CKE
CK, CK
Table 9 - IDD5B Measurement-Loop Patterna)
Static High
toggling
3,4
2
5...8
repeat cycles 1...4, but BA[2:0] = 1
9...12
repeat cycles 1...4, but BA[2:0] = 2
13...16
repeat cycles 1...4, but BA[2:0] = 3
17...20
repeat cycles 1...4, but BA[2:0] = 4
21...24
repeat cycles 1...4, but BA[2:0] = 5
25...28
repeat cycles 1...4, but BA[2:0] = 6
29...32
repeat cycles 1...4, but BA[2:0] = 7
33...nRFC-1
repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Rev. 1.1 / Aug. 2013
49
Table 10 - IDD7 Measurement-Loop Patterna)
2
3
4
Static High
5
6
7
8
9
10
4*nRRD
nFAW
nFAW+nRRD
nFAW+2*nRRD
nFAW+3*nRRD
nFAW+4*nRRD
2*nFAW+0
2*nFAW+1
2&nFAW+2
11
2*nFAW+nRRD
2*nFAW+nRRD+1
2&nFAW+nRRD+2
12
13
2*nFAW+2*nRRD
2*nFAW+3*nRRD
14
2*nFAW+4*nRRD
15
16
17
18
3*nFAW
3*nFAW+nRRD
3*nFAW+2*nRRD
3*nFAW+3*nRRD
19
3*nFAW+4*nRRD
00110011
-
0
-
0
-
0
0
0
00110011
-
0
0
0
00000000
-
0
-
0
-
A[10]
0
0
0
ODT
00000000
-
WE
0
0
0
CAS
ACT
0
0
1
1
0
0
00
0
0
0
RDA
0
1
0
1
0
0
00
1
0
0
D
1
0
0
0
0
0
00
0
0
0
repeat above D Command until nRRD - 1
ACT
0
0
1
1
0
1
00
0
0
F
RDA
0
1
0
1
0
1
00
1
0
F
D
1
0
0
0
0
1
00
0
0
F
repeat above D Command until 2* nRRD - 1
repeat Sub-Loop 0, but BA[2:0] = 2
repeat Sub-Loop 1, but BA[2:0] = 3
D
1
0
0
0
0
3
00
0
0
F
Assert and repeat above D Command until nFAW - 1, if necessary
repeat Sub-Loop 0, but BA[2:0] = 4
repeat Sub-Loop 1, but BA[2:0] = 5
repeat Sub-Loop 0, but BA[2:0] = 6
repeat Sub-Loop 1, but BA[2:0] = 7
0
0
7
00
0
0
F
D
1
0
0
Assert and repeat above D Command until 2* nFAW - 1, if necessary
ACT
0
0
1
1
0
0
00
0
0
F
RDA
0
1
0
1
0
0
00
1
0
F
D
1
0
0
0
0
0
00
0
0
F
Repeat above D Command until 2* nFAW + nRRD - 1
ACT
0
0
1
1
0
1
00
0
0
0
RDA
0
1
0
1
0
1
00
1
0
0
D
1
0
0
0
0
1
00
0
0
0
Repeat above D Command until 2* nFAW + 2* nRRD - 1
repeat Sub-Loop 10, but BA[2:0] = 2
repeat Sub-Loop 11, but BA[2:0] = 3
D
1
0
0
0
0
3
00
0
0
0
Assert and repeat above D Command until 3* nFAW - 1, if necessary
repeat Sub-Loop 10, but BA[2:0] = 4
repeat Sub-Loop 11, but BA[2:0] = 5
repeat Sub-Loop 10, but BA[2:0] = 6
repeat Sub-Loop 11, but BA[2:0] = 7
D
1
0
0
0
0
7
00
0
0
0
Assert and repeat above D Command until 4* nFAW - 1, if necessary
RAS
Datab)
CS
A[9:7]
A[15:11]
BA[2:0]
Command
A[2:0]
1
0
1
2
...
nRRD
nRRD+1
nRRD+2
...
2*nRRD
3*nRRD
A[6:3]
0
toggling
Cycle
Number
Sub-Loop
CKE
CK, CK
ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Rev. 1.1 / Aug. 2013
50
IDD Specifications (Tcase: 0 to 95oC)
* Module IDD values in the datasheet are only a calculation based on the component IDD spec.
The actual measurements may vary according to DQ loading cap.
2GB, 256M x 64 SO-DIMM: HMT425S6AFR6A
Symbol
IDD0
IDD1
IDD2N
IDD2NT
IDD2P0
DDR3L 1066
164
204
80
92
48
DDR3L 1333
168
212
80
96
48
DDR3L 1600
172
212
88
108
48
DDR3L 1866
176
216
92
116
52
Unit
mA
mA
mA
mA
mA
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDD4W
IDD5B
IDD6
IDD6ET
IDD7
56
80
104
72
360
400
800
60
72
680
56
84
108
72
440
480
800
60
72
780
56
92
116
76
500
540
800
60
72
800
60
96
116
80
560
620
800
60
72
820
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
DDR3L 1866
292
332
184
232
104
120
192
232
160
676
736
916
120
144
936
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
note
4GB, 512M x 64 SO-DIMM: HMT451S6AFR6A
Symbol
IDD0
IDD1
IDD2N
IDD2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDD4W
IDD5B
IDD6
IDD6ET
IDD7
Rev. 1.1 / Aug. 2013
DDR3L 1066
244
284
160
184
96
112
160
208
144
440
480
880
120
144
760
DDR3L 1333
248
292
160
192
96
112
168
216
144
520
560
880
120
144
860
DDR3L 1600
288
328
176
216
96
112
184
232
152
616
656
916
120
144
916
note
51
4GB, 512M x 64 SO-DIMM: HMT451S6AFR8A
Symbol
IDD0
DDR3L 1066
240
DDR3L 1333
256
DDR3L 1600
264
DDR3L 1866
272
Unit
mA
IDD1
IDD2N
IDD2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDD4W
296
120
144
64
72
128
192
136
520
560
1600
96
128
880
312
128
160
64
80
136
200
136
600
640
1600
96
128
1040
320
136
168
64
80
136
208
144
680
720
1600
96
128
1080
328
144
176
64
88
136
216
144
760
800
1600
96
128
1160
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
DDR3L 1600
472
528
272
336
128
160
272
416
288
888
928
1808
192
256
1288
DDR3L 1866
488
544
288
352
128
176
272
432
288
976
1016
1816
192
256
1376
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD5B
IDD6
IDD6ET
IDD7
note
8GB, 1G x 64 SO-DIMM: HMT41GS6AFR8A
Symbol
IDD0
IDD1
IDD2N
IDD2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDD4W
IDD5B
IDD6
IDD6ET
IDD7
Rev. 1.1 / Aug. 2013
DDR3L 1066
360
416
240
288
128
144
256
384
272
640
680
1720
192
256
1000
DDR3L 1333
384
440
256
320
128
160
272
400
272
728
768
1728
192
256
1168
note
52
Module Dimensions
256Mx64 - HMT425S6AFR6A
Front
Side
67.60mm
3.59mm max
2.0
30.0mm
4.00 0.10
Detail-A
pin 1
2.15
2 X 1.80 0.10
pin 203
21.00
20.0mm
6.00
SPD
1.00 0.08 mm
39.00
1.65 0.10
3.00
Back
0.3~1.0
0.45 0.03
0.60
2.55
0.3 0.15
4.00 0.10
Detail of Contacts A
1.00 0.05
Note:
1. 0.13 tolerance on all dimensions unless otherwise stated.
Units: millimeters
Rev. 1.1 / Aug. 2013
53
512Mx64 - HMT451S6AFR6A
Front
Side
67.60mm
3.37mm max
2.0
30.0mm
4.00 0.10
Detail-A
pin 1
2.15
2 X 1.80 0.10
pin 203
21.00
20.0mm
6.00
SPD
1.00 0.08 mm
39.00
1.65 0.10
3.00
Back
2.55
0.3 0.15
4.00 0.10
Detail of Contacts A
0.3~1.0
0.45 0.03
0.60
1.00 0.05
Note:
1. 0.13 tolerance on all dimensions unless otherwise stated.
Units: millimeters
Rev. 1.1 / Aug. 2013
54
512Mx64 - HMT451S6AFR8A
Front
Side
67.60mm
3.37mm max
2.0
30.0mm
4.00 0.10
Detail-A
pin 1
2.15
2 X 1.80 0.10
pin 203
21.00
20.0mm
6.00
SPD
1.00 0.08 mm
39.00
1.65 0.10
3.00
Back
2.55
0.3 0.15
4.00 0.10
Detail of Contacts A
0.3~1.0
0.45 0.03
0.60
1.00 0.05
Note:
1. 0.13 tolerance on all dimensions unless otherwise stated.
Units: millimeters
Rev. 1.1 / Aug. 2013
55
1Gx64 - HMT41GS6AFR8A
Front
Side
67.60mm
3.37mm max
2.0
Detail- A
Detail-B
pin 1
pin 203
21.00
1.65 0.10
2.15
2 X 1.80 0.10
20.0mm
6.00
30.0mm
4.00 0.10
1.00 0.08 mm
39.00
3.00
Back
SPD
0.3~1.0
0.45 0.03
0.60
2.55
0.3 0.15
4.00 0.10
Detail of Contacts A
1.00 0.05
Note:
1. 0.13 tolerance on all dimensions unless otherwise stated.
Units: millimeters
Rev. 1.1 / Aug. 2013
56