HS-0506RH, HS-0507RH NS ESIG D N EW OR 547RH ter at F D DE S-0 Ce n c MEN 6RH, H ervice .com/ts M O 4 l S i 5 C l s 0 E a r R ni c HS nt e Radiation Hardened Single 16/Differential NOT See ur Tech r www.i o o t L c I S ta September 1997 8 Channel CMOS Analog Multiplexer con -INTER 8 8 8 1® Features Description • Low On Resistance 400Ω Max These radiation hardened monolithic CMOS multiplexers each include an array of sixteen analog switches, a digital decode circuit for channel selection, voltage reference for logic thresholds, and an ENABLE input for device selection when several multiplexers are present. • Wide Analog Signal Range ±15V • TTL/CMOS Compatible 2.4V (Logic “1”) • Access Time 1000ns Max The Dielectric Isolation (DI) process used in fabrication of these devices eliminates the problem of latchup. Also, DI offers much lower substate leakage and parasitic capacitance than conventional junction isolated CMOS. The switching threshold for each digital input is established by an internal +5V reference, providing a guaranteed minimum 2.4V for logic “1” and maximum 0.8V for logic “0”. This allows direct interface without pullup resistors to signals from most logic families: CMOS, TTL, DTL and some PMOS. For protection against transient overvoltage, the digital inputs include a series 200Ω resistor and diode clamp to each supply. The HS-0506RH is a sixteen channel single-ended multiplexer, and the HS-0507RH is an eight channel differential version. If input overvoltage protection is needed, the HS-0506RH or HS-0507RH multiplexers are recommended. For further information see Application Notes 520 and 521. • 44V Maximum Power Supply • Break-Before-Make Switching • No Latch-up • Gamma Dose 1 x 104 RAD (Si) Applications • Data Acquisition Systems • Precision Instrumentation • Demultiplexing • Selector Switch Ordering Information PART NUMBER TEMPERATURE RANGE o o PACKAGE HS1-0506RH-Q -55 C to 125 C 28 Lead CerDIP HS1-0507RH-Q -55oC 28 Lead CerDIP to 125oC Pinouts VSUPPLY 1 28 OUT HS-0507RH 28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE (CerDIP) MIL-STD-1835 GDIP1-T28 TOP VIEW +VSUPPLY 1 28 OUT A 27 -VSUPPLY NC 2 27 -VSUPPLY NC 3 26 IN 8 NC 3 26 IN 8A IN 16 4 25 IN 7 IN 8B 4 25 IN 7A IN 15 5 24 IN 6 IN 7B 5 24 IN 6A IN 14 6 23 IN 5 IN 6B 6 23 IN 5A IN 13 7 22 IN 4 IN 5B 7 22 IN 4A IN 12 8 21 IN 3 IN 4B 8 21 IN 3A IN 11 9 20 IN 2 IN 3B 9 20 IN 2A IN 10 10 19 IN 1 IN 2B 10 19 IN 1A 18 ENABLE IN 1B 11 18 ENABLE IN 9 11 OUT B 2 GND 12 17 ADDRESS A0 GND 12 17 ADDRESS A0 NC 13 16 ADDRESS A1 NC 13 16 ADDRESS A1 ADDRESS A3 14 15 ADDRESS A2 NC 14 15 ADDRESS A2 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 1 Spec Number File Number 518860 4028.1 DB NA HS-0506RH 28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE (CerDIP) MIL-STD-1835 GDIP1-T28 TOP VIEW HS-0506RH, HS-0507RH Functional Diagrams HS-0506RH HS-0507RH IN1 IN1A OUT OUT A IN8A IN2 DECODER/ DRIVER IN1B OUT B DECODER/ DRIVER IN8B IN16 5V REF 5V REF LEVEL SHIFT † †DIGITAL INPUT PROTECTION † † † † LEVEL SHIFT † † † † A0 A1 A2 EN †DIGITAL INPUT PROTECTION A0 A1 A2 A3 EN HS-0507RH TRUTH TABLE HS-0506RH TRUTH TABLE A2 A1 A0 EN “ON” CHANNEL PAIR A3 A2 A1 A0 EN “ON” CHANNEL X X X X L NONE X X X L NONE L L L L H 1 L L L H 1 L L L H H 2 L L H H 2 L L H L H 3 L H L H 3 L L H H H 4 L H H H 4 L H L L H 5 H L L H 5 L H L H H 6 H L H H 6 L H H L H 7 H H L H 7 L H H H H 8 H H H H 8 H L L L H 9 H L L H H 10 H L H L H 11 H L H H H 12 H H L L H 13 H H L H H 14 H H H L H 15 H H H H H 16 Spec Number 2 518860 Specifications HS-0506RH, HS-0507RH Absolute Maximum Ratings Reliability Information Voltage Between Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . +44V +VSUPPLY to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +22V -VSUPPLY to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V Analog Input Overvoltage: +VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VSUPPLY +2V -VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VSUPPLY -2V Digital Input Overvoltage: +VEN, +VA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VSUPPLY +4V -VEN, -VA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VSUPPLY -4V or 20mA, Whichever Occurs First Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Peak Current, S or D (Pulsed at 1ms, 10% Duty Cycle Maximum . . . . . . . . . . . . . 40mA Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +275oC Thermal Resistance θJA θJC CerDIP Package . . . . . . . . . . . . . . . . . . . 51oC/W 18oC/W Maximum Package Power Dissipation at +125oC CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.98W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.6mW/oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC Operating Supply Voltage (±VSUPPLY). . . . . . . . . . . . . . . . . . ±15V Analog Input Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY Logic Low Level (VAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 0.8V Logic High Level (VAH). . . . . . . . . . . . . . . . . . . . +4V to +VSUPPLY Max RMS Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8mA TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS Device tested at +VSUPPLY = +15V. -VSUPPLY = -15V, VEN = 2.4V, Unless Otherwise Specified. PARAMETERS Input Leakage Current SYMBOL IIH GROUP A SUBGROUPS CONDITIONS Measure Inputs Sequentially GND All Unused Inputs IIL Leakage Current into the Source Terminal of an ‘‘OFF’’ Switch +IS(OFF) -IS(OFF) Leakage Current into the Drain Terminal of an “OFF” Switch +ID(OFF) VS = +10V, VD = -10V, VEN = 0.8V, All Unused Inputs = -10V VD = +10V, VEN = 0.8V All Unused Inputs = -10V VD = -10V, VEN = 0.8V All Unused Inputs = +10V +ID(ON) VS = VD = +10V All Unused Inputs = 10V VS = VD = -10V All Unused Inputs = +10V MIN MAX UNITS 1.0 µA 1, 2, 3 +25oC, +125oC, -55oC -1.0 1.0 µA 1 +25oC -10 +10 nA -50 +50 nA -10 +10 nA -50 +50 nA +125oC, -55oC +25oC +125oC, -55oC HS-0506RH HS-0507RH 1 +25oC -10 +10 nA HS-0506RH 2, 3 +125oC, -55oC -300 +300 nA 2, 3 +125oC, -200 +200 nA -10 +10 nA -55oC +25o HS-0506RH HS-0507RH 1 HS-0506RH 2, 3 +125oC, -55oC -300 +300 nA 2, 3 +125o -200 +200 nA -10 +10 nA -300 +300 nA C o C, -55 C o HS-0506RH HS-0507RH 1 +25 C HS-0506RH 2, 3 +125oC, -55oC HS-0507RH -ID(ON) o -1.0 2, 3 HS-0507RH Leakage Current F from an “ON” Driver into the Switch (Drain) o +25 C, +125 C, -55oC 1 HS-0507RH -ID(OFF) TEMPERATURE 1, 2, 3 2, 3 VS = -10V, VD = +10V, VEN = 0.8V All Unused Inputs = +10V LIMITS o o 2, 3 +125 C, -55 C -200 +200 nA HS-0506RH HS-0507RH 1 +25oC -10 +10 nA HS-0506RH 2, 3 +125oC, -55oC -300 +300 nA 2, 3 +125oC, -200 +200 nA HS-0507RH -55oC Spec Number 3 518860 Specifications HS-0506RH, HS-0507RH TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device tested at +VSUPPLY = +15V. -VSUPPLY = -15V, VEN = 2.4V, Unless Otherwise Specified. PARAMETERS SYMBOL GROUP A SUBGROUPS CONDITIONS LIMITS TEMPERATURE MAX UNITS - 3.0 mA Positive Supply Current I(+) VA = 0V, VEN = 2.4V 1, 2, 3 Negative Supply Current I(-) VA = 0V, VEN = 2.4V 1, 2, 3 +25oC, +125oC, 55oC -1.0 - mA Standby Positive Supply Current +ISBY VA = 0V, VEN = 0V 1, 2, 3 +25oC,+ 125oC, 55oC - 3.0 mA Standby Negative Supply Current -ISBY VA = 0V, VEN = 0V 1, 2, 3 +25oC,+125oC, 55oC -1.0 - mA 1 +25oC - 300 Ω - 400 Ω - 300 Ω - 400 Ω 0.8 V - V Switch “ON” Resistance +RDS1 VS = +10V, ID = -1mA 2, 3 -RDS1 VS = -10V, ID = +1mA 1 2, 3 Logic Level Voltage +125oC, MIN +25oC, 55oC +125 oC, - -55oC +25oC o o +125 C, -55 C VAL Note 1 1, 2, 3 +25oC, +125oC, VAH Note 1 1, 2, 3 +25oC, +125oC, 55oC 55oC 2.4 NOTE: 1. Use for forcing conditions for all DC tests unless otherwise specified. TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS Device tested at +VSUPPLY = +15V. -VSUPPLY = -15V, VEN = 2.4V, Unless Otherwise Specified PARAMETERS SYMBOL CONDITIONS LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS Break-Before-Make Time Delay tD RL = 200Ω 9 +25oC 25 - ns Propogation Delay Times: Address Inputs to I/O Channel Times tA RL = 10MΩ 9 +25oC - 500 ns 10, 11 +125oC, -55oC - 1000 ns 9 +25oC - 500 ns 10, 11 +125oC, -55oC - 1000 ns 9 +25oC - 500 ns 10, 11 +125oC, -55oC - 1000 ns Enable to I/O tON(EN) tOFF(EN) RL = 200Ω RL = 200Ω Spec Number 4 518860 Specifications HS-0506RH, HS-0507RH TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS Device tested at +VSUPPLY = +15V, -VSUPPLY = -15V, VEN = 2.4V, Unless Otherwise Specified LIMITS PARAMETERS SYMBOL CONDITIONS NOTE TEMPERATURE MIN MAX UNITS 1 +25oC - 12 pF HS-0506RH 1 +25oC - 90 pF HS-0507RH 1 +25oC - 50 pF V+ = V- = 0V f = 1MHz 1 +25oC - 12 pF 1 +25oC - 10 mV 1, 2 +25oC -50 - dB Capacitance: Address Input CA V+ = V- = 0V f = 1MHz Capacitance: Output Switch COS V+ = V- = 0V f = 1MHz Capacitance: Input Switch CIS Charge Transfer Error VCTE VS = GND VGEN = 0V to 5V Off Isolation VISO VEN = 0.8V,RL = 1kΩ , CL = 15pF,VS = 7 VRMS f = 100kHz NOTES: 1. The parameters listed in this table are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics. 2. Worst case isolation occurs on channel 8B due to proximity of the output pins. TABLE 4A. POST 10K RAD DC ELECTRICAL PERFORMANCE CHARACTERISTICS Device tested at +VSUPPLY = +15V. -VSUPPLY = -15V, VEN = 2.4V, Unless Otherwise Specified. LIMITS PARAMETERS SYMBOL Input Leakage Current IIH CONDITIONS Measure Inputs Sequentially GND All Unused Inputs IIL Leakage Current into the Source Terminal of an ‘‘OFF’’ Switch Leakage Current into the Drain Terminal of an “OFF” Switch MAX UNITS +25oC -1.0 1.0 µA +25oC -1.0 1.0 µA VS = +10V, VD = -10V, VEN = 0.8V All Unused Inputs = -10V +25oC -50 +50 nA -IS(OFF) VS = -10V, VD = +10V, VEN = 0.8V All Unused Inputs = +10V +25oC -50 +50 nA +ID(OFF) VD = +10V, VEN = 0.8V All Unused Inputs = -10V HS-0506RH +25oC -300 +300 nA HS-0507RH +25oC -200 +200 nA HS-0506RH +25oC -300 +300 nA HS-0507RH +25oC -200 +200 nA HS-0506RH +25oC -300 +300 nA HS-0507RH +25oC -200 +200 nA HS-0506RH +25oC -300 +300 nA HS-0507RH +25oC -200 +200 nA +25oC - 3.0 mA +ID(ON) -ID(ON) Positive Supply Current MIN +IS(OFF) -ID(OFF) Leakage Current from an “ON” Driver into the Switch (Drain) TEMPERATURE I(+) VD = -10V, VEN = 0.8V All Unused Inputs = +10V VS = VD = +10V All Unused Inputs = -10V VS = VD = -10V All Unused Inputs = +10V VA = 0V, VEN = 2.4V Spec Number 5 518860 Specifications HS-0506RH, HS-0507RH TABLE 4A. POST 10K RAD DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device tested at +VSUPPLY = +15V. -VSUPPLY = -15V, VEN = 2.4V, Unless Otherwise Specified. LIMITS PARAMETERS SYMBOL Negative Supply Current I(-) CONDITIONS TEMPERATURE MIN MAX UNITS VA = 0V, VEN = 2.4V +25oC -1.0 - mA Standby Positive Supply Current +ISBY VA = 0V, VEN = 0V +25oC - 3.0 mA Standby Negative Supply Current -ISBY VA = 0V, VEN = 0V +25oC -1.0 - mA +RDS1 VS = +10V, ID = +1mA +25oC - 400 Ω -RDS1 VS = -10V, ID = -1mA +25oC - 400 Ω VAL Note 1 +25oC - 0.8 V VAH Note 1 +25oC 2.4 - V Switch “ON” Resistance Logic Level Voltage NOTE: 1. Use for forcing conditions for all DC tests unless otherwise specified. TABLE 4B. POST 10K RAD AC ELECTRICAL PERFORMANCE CHARACTERISTICS Device tested at +VSUPPLY = +15V. -VSUPPLY = -15V, VEN = 2.4V, Unless Otherwise Specified. LIMITS PARAMETERS Propagation Delay Times: Address Inputs to I/O Channel Times Enable to I/O SYMBOL CONDITIONS TEMPERATURE MIN MAX UNITS tA RL = 10MΩ +25oC - 1000 ns tON(EN) RL = 200Ω +25oC - 1000 ns tOFF(EN) RL = 200Ω +25oC - 1000 ns Spec Number 6 518860 Specifications HS-0506RH, HS-0507RH TABLE 5. BURN-IN DELTA PARAMETERS (TA = +25oC) Device tested Per Table 1. PARAMETERS SYMBOL DELTA LIMITS IIH, IIL ±100nA +IS(OFF) ±10nA -IS(OFF) ±10nA +ID(OFF) ±10nA -ID(OFF) ±10nA +ID(ON) ±10nA -ID(ON) ±10nA R(DS) ±50Ω R(DS) ±50Ω Positive Supply Current I(+) ± 300µA Negative Supply Current I(-) ±100µA Positive Standby Supply Current +ISBY ± 300µA Negative Standby Supply Current -ISBY ±100µA Input Leakage Current Leakage Current into the Source Terminal of an ‘‘OFF’’ Switch Leakage Current into the Drain Terminal of an ‘‘OFF’’ Switch Leakage Current from an ‘‘ON’’ Driver into the Switch (Drain) Switch On Resistance TABLE 6. APPLICABLE SUBGROUPS GROUP A SUBGROUPS CONFORMANCE GROUPS MIL-STD-883 METHOD TESTED FOR -Q RECORDED FOR -Q Initial Test 100% 5004 1, 9 1 (Note 2) Interim Test 100% 5004 1, 9, ∆ 1, ∆ (Note 2) PDA 100% 5004 1, ∆ − Final Test 100% 5004 2, 3, 10, 11 - Group A (Note 1) Sample 5005 1, 2, 3, 9, 10, 11 - Subgroup B5 Sample 5005 1, 2, 3, ∆ 1, 2, 3, ∆ (Note 2) Subgroup B6 Sample 5005 1 - Group D Sample 5005 1 - Group E, Subgroup 2 Sample 5005 1 - NOTES: 1. Alternate Group A testing in accordance with MIL-STD-883 Method 5005 may be exercised. 2. Table 5 parameters only. Spec Number 7 518860 HS-0506RH, HS-0507RH Intersil Space Level Product Flow -Q Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) (Note 1) 100% Interim Electrical Test 1 (T1) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% PDA 1, Method 5004 (Note 2) 100% Delta Calculation (T0-T1) 100% Nondestructive Bond Pull, Method 2023 100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or Equivalent, Method 1015 Sample - Wire Bond Pull Monitor, Method 2011 100% Interim Electrical Test 2 (T2) Sample - Die Shear Monitor, Method 2019 or 2027 100% Delta Calculation (T0-T2) 100% Internal Visual Inspection, Method 2010, Condition A 100% PDA 2, Method 5004 (Note 2) 100% Temperature Cycle, Method 1010, Condition C, 10 Cycles 100% Final Electrical Test 100% Constant Acceleration, Method 2001, Condition per Method 5004 100% Radiographic (X-Ray), Method 2012 (Note 3) 100% Fine/Gross Leak, Method 1014 100% External Visual, Method 2009 100% PIND, Method 2020, Condition A Sample - Group A, Method 5005 (Note 4) 100% External Visual Sample - Group B, Method 5005 (Note 5) 100% Serialization Sample - Group D, Method 5005 (Notes 5 and 6) 100% Initial Electrical Test (T0) 100% Data Package Generation (Note 7) 100% Static Burn-In, Condition A or B, 72 hrs. min., +125oC min., Method 1015 NOTES: 1. Modified SEM Inspection, not compliant to MIL-STD-883, Method 2018. This device does not meet the Class S minimum metal step coverage of 50%. The metal does meet the current density requirement of <2 E5 A/cm2. Data provided upon request. 2. Failures from subgroup 1 and deltas are used for calculating PDA. The maximum allowable PDA = 5%. 3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. 4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 5. Group B and D inspections are optional and will not be performed unless required by the P.O. When required, the P.O. should include separate line items for Group B test, Group B samples, Group D test and Group D samples. 6. Group D Generic Data, as defined by MIL-I-38535, is optional and will not be supplied unless required by the P.O. When required, the P.O. should include a separate line item for Group D generic data. Generic data is not guaranteed to be available and is therefore not available in all cases. 7. Data Package Contents: • Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity). • Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage. • GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil. • X-Ray report and film. Includes penetrometer measurements. • Screening, Electrical, and Group A attributes (Screening attributes begin after package seal). • Lot Serial Number Sheet (Good units serial number and lot number). • Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. • Group B and D attributes and/or Generic data is included when required by the P.O. • The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. Spec Number 8 518860 HS-0506RH, HS-0507RH Test Circuits INPUT LEAKAGE CURRENT V+ GND ID(OFF) V- V+ OUT CH 1 CH 2 CH 3 GND IS(OFF) V- V+ OUT CH 1 CH 2 CH 3 AN CH n EN A0 AN EN A0 VS IIL IIH IIL IIH VD VA = VEN = 0.8V TRUTH TABLE VAL = 0.8V; VAH = 2.4V SUPPLY CURRENTS V- V+ OUT CH 1 CH 2 CH 3 EN 0.8V IIL IIH ID(ON) GND AN VS VD VAL = 0.8V; VAH = 2.4V UNUSED INPUTS TO GND V+ OUT IS (OFF) CH n A0 V- CH 1 CH 2 CH 3 ID (OFF) CH n GND ID (ON) GND CHARGE TRANSFER ERROR V- V+ I(+) +SBY I(-) -SBY CH 1 CH 2 CH 3 OUT GND V- CH n TEST POINT OUT CH 1 CH 2 CH 3 0.01µF CH n A0 AN EN A0 VS 2.4V A0 TRUTH TABLE VAL = 0.8V VAH = 2.4V AN EN GND VA = 0V VEN = 2.4V VEN = 0V VGEN OFF CHANNEL ISOLATION V- V+ OUT CH 1 CH 2 CH 3 CH n VOUT OUT 1KΩ 15µF(1) CH 4 CH 5 CH 6 CH 7 CH n ID AN GND CH 1 CH 2 CH 3 VM RDN = VM ID A0 EN 5.0V RDS V+ AN CH n VD EN A0 VS AN (1) INCLUDES ALL FACTORS AND SCOPE OR VOLTMETER CAPACITANCE EN VS 2.4V 0.8V TRUTH TABLE VAL = 0.8V; VAH = 2.4V Spec Number 9 518860 HS-0506RH, HS-0507RH Switching Waveforms +15V 3.5V ADDRESS DRIVE (VA) 0V IN 1 A2 IN 2 HS-0506RH † THRU IN 15 A1 IN 16 A0 VA 50% OUTPUT 50% +5V +V A3 +3.5V CH 1 ON GND -V tOPEN CH 16 ON VOUT OUT EN VA INPUT 2V/DIV. OUTPUT 1V/DIV. 200Ω -15V 100ns/DIV † SIMILAR CONNECTION FOR HS-0507RH FIGURE 1. BREAK-BEFORE-MAKE DELAY (tOPEN) +15V 3.5V 50% ADDRESS DRIVE (VA) 90% OUTPUT 5V/DIV. OUT EN +3.5V CH 1 ON ±10V PROBE IN 16 A0 OUTPUT VA INPUT 2V/DIV. ±10V IN 1 A2 IN 2 HS-0506RH † THRU IN 15 A1 0V +10V +V A3 GND 10MΩ -V -10V 14pF tA CH 16 ON -15V 200ns/DIV † SIMILAR CONNECTION FOR HS-0507RH FIGURE 2. ACCESS TIME vs LOGIC LEVEL (HIGH) +15V 3.5V ENABLE DRIVE +V A3 50% A2 0V OUTPUT A 90% 90% tON(EN) tOFF (EN) -VA IN 1 IN 2 THRU IN 16 A1 A0 HS-0506RH † OUT EN GND -V +10V ENABLE DRIVE 2V/DIV. VOUT 200Ω CH 1 ON OUTPUT 2V/DIV. CH 1 OFF -15V † SIMILAR CONNECTION FOR HS-0507RH 100ns/DIV FIGURE 3. ENABLE DELAY tON(EN), tOFF 9EN) Spec Number 10 518860 HS-0506RH, HS-0507RH Burn-Circuits V1 C1 D1 R1 F3 1 28 2 27 3 26 4 5 R2 V2 V2 1 28 2 27 3 26 25 4 25 24 5 24 6 23 6 23 7 22 7 22 8 21 8 21 9 20 9 20 10 19 10 19 11 18 F4 11 18 12 17 F0 12 17 13 16 F1 13 16 14 15 F2 14 15 D2 C1 D1 C2 R1 V1 R2 V3 D2 C2 DYNAMIC STATIC V1 = +15V minimum, +16V maximum V2 = -15V maximum, -16V minimum R1, R2 = 10kΩ, ± 5%, 1/4 or 1/2W (per socket) C1, C2 = 0.01µF minimum (per socket) or 0.1µF minimum (per row) D1, D2 = 1N4002 or equivalent (per board) F0 = 100kHz, 10%; F1 = F0/2; F2 = F1/2; F3 = F2/2; F4 = F3/2 40% - 60% duty cycle; VIL = 0.8V maximum; VIH = 4.0V minimum V1 = +5V minimum, +6V maximum V2 = +15V minimum, +16V maximum V3 = -15V maximum, -16V minimum R1, R2 = 10kΩ, ± 5%, 1/4 or 1/2W (per socket) C1, C2 =0.01µF minimum (per socket) or 0.1µF minimum (per row) D1, D2 = 1N4002 or equivalent (per board) NOTES: 1. The above test circuits are utilized for all package types. 2. The dynamic test circuit is utilized for all life testing. Irradiation Circuit +15V 10kΩ 1 28 2 27 NC 3 26 +1V 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 -15V 10kΩ +5V Spec Number 11 518860 HS-0506RH, HS-0507RH Schematic Diagrams +V P P P P A0 OR A0 A1 OR A1 P P P N N N N N A2 OR A2 TO P-CHANNEL DEVICE OF THE SWITCH TO N-CHANNEL DEVICE OF THE SWITCH N A3 OR A3 (HS-0506RH ONLY) N ENABLE V- FIGURE 4. ADDRESS DECODER +V P3 P5 P1 A +V P4 N1 P6 P7 P8 P9 P10 N6 N7 N8 N9 N10 D1 VL D2 VR P2 200Ω N4 -V AIN A N5 N2 N3 -V ALL N-CHANEL BODIES TO VALL P-CHANNEL BODIES TO V+ UNLESS OTHERWISE INDICATED FIGURE 5. ADDRESS INPUT BUFFER LEVER SHIFTER Spec Number 12 518860 HS-0506RH, HS-0507RH Schematic Diagrams (Continued) V+ P15 Q2P Q3P Q1P Q4P Q5N Q6N Q8N R2 VL N12 Q7P Q11P D3 Q10N VR R3 Q9P P16 N13 N14 Q12N N15 V- GND FIGURE 6. TTL REFERENCE CIRCUIT FROM DECODE N18 V+ N17 N19 IN OUT P17 V- P18 FROM DECODE FIGURE 7. MULTIPLEX SWITCH Spec Number 13 518860 HS-0506RH, HS-0507RH Metallization Topology DIE DIMENSIONS: 82 x 129 x 19 mils METALLIZATION: Type: Al Thickness: 16kÅ ± 2kÅ GLASSIVATION: Type: Nitride Thickness: 7kÅ ± 0.7kÅ WORST CASE CURRENT DENSITY: < 2.0 x 105 A/cm2 TRANSISTOR COUNT: HS-0506RH 421 HS-0507RH 421 PROCESS: CMOS-DI Metallization Mask Layout HS-0506RH HS-0507RH NOTE: Pad numbers correspond to DIP pin numbers only. Spec Number 14 518860