HS-54C138RH T CT DUC PRO PRODU E T E E 8 L T 3 t 1 O U OBS UBSTIT S/HCTS Center a S C port c H s E t , / L 8 om 13 Sheetup SIB Data POS S/ACTS hnical S intersil.c . AC ur Tec www ct o RSIL or a t n E co 8-INT 1-88 ® Radiation Hardened 3-Line to 8-Line Decoder/Demultiplexer August 2000 • Electrically Screened to SMD # 5962-95825 The HS-54C138RH contains a one of eight binary decoder. A three bit binary input is used to select and activate each of the eight outputs, provided the three chip enable inputs are also present (see truth table). The HS-54C138RH has an on-chip enable gate. The active high (G1) and both active low (G2A, G2B) inputs are Anded together to provide a single enable input to the device. The use of both active high and active low inputs minimizes the need for external gates when expanding a system. • QML Qualified per MIL-PRF-38535 Requirements • Radiation Hardened EPI-CMOS - Total Dose . . . . . . . . . . . . . . . . . . . . . . 1 x 105RAD(Si) - Latch-Up Immune . . . . . . . . . . . . . . >1 x 1012RAD(Si)/s • Multiple Input Enable for Easy Expansion • Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . .+5V • Outputs Active Low • Low Standby Power . . . . . . . . . . . . . . .0.5mW Max at +5V • High Noise Immunity • Equivalent to Sandia SA2995 • Bus Compatible with Intersil Rad-Hard 80C85RH • Full Military Temperature Range . . . . . . . -55oC to 125oC Pinouts 16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T16 TOP VIEW Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-95825. A “hot-link” is provided on our homepage for downloading. www.intersil.com/spacedefense/space.asp Ordering Information ORDERING NUMBER TEMP. RANGE (oC) 5962R9582501QEC HS1-54C138RH-8 -55 to 125 5962R9582501QXC HS9-54C138RH-8 -55 to 125 5962R9582501V9A HS0-54C138RH-Q 25 5962R9582501VEC HS1-54C138RH-Q -55 to 125 5962R9582501VXC HS9-54C138RH-Q -55 to 125 1 3037.3 Features The Intersil HS-54C138RH is a radiation hardened 3- to 8-line decoder fabricated using a radiation hardened EPI-CMOS process. It features low power consumption, high noise immunity, and high speed. Also featured are pin and function compatibility with the 54LS138 industry standard part. The HS-54C138RH is ideally suited for high speed memory chip select address decoding. It is intended for use with the Intersil HS-80C85RH radiation hardened microprocessor, but it can also be utilized as a demultiplexer in any low power rad-hard application. INTERNAL MKT. NUMBER File Number A 1 16 VDD B 2 15 Y0 C 3 14 Y1 G2A 4 13 Y2 G2B 5 12 Y3 G1 6 11 Y4 Y7 7 10 Y5 GND 8 9 Y6 16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F16 TOP VIEW A 1 16 VDD B 2 15 Y0 C 3 14 Y1 G2A 4 13 Y2 G2B 5 12 Y3 G1 6 11 Y4 Y7 7 10 Y5 GND 8 9 Y6 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved HS-54C138RH Typical Applications Figure 2 shows a configuration that can be used to enable multiple I/O ports or memory devices. Up to 24 memory devices or I/O ports can be controlled using this circuit. Typical applications include systems which require multiple input/output ports and memories. When the HS-54C138RH is enabled one of the eight outputs will go low. This output can be used to select a particular device or a group of devices. The HS-54C138RH can also be cascaded to provide an enabling scheme for larger systems and allow one decoder to control eight other decoders as in Figure 1. For demultiplexer operation, one of the three enable inputs is used as the data input while the other two inputs are enable. The transmitted data is distributed to the proper output as determined by the 3-line select inputs. See Figure 3. SELECT A ENABLE SELECT B HS-54C138RH Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 TO OTHER DEVICES “1” “0” “1” “0” ENABLE “1” “0” ENABLE HS-54C138RH HS-54C138RH HS-54C138RH Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 FIGURE 1. EN EN G1 G2B G2A C B A Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 EN A4 G1 G2B G2A C B A Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 PORT NUMBERS OR CHIP SELECTS FIGURE 2. 2 A3 G1 G2B G2A A2 A1 A0 C B A Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 ENABLE DATA INPUT EN SELECT HS-54C138RH EN G1 G2B G2A C B A Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 FIGURE 3. 3 HS-54C138RH Die Characteristics DIE DIMENSIONS: Top Metallization: 76 mils x 63 mils x 14 mils ±1 mil Type: AlSi Thickness: 11kÅ ±2kÅ ASSEMBLY RELATED INFORMATION: Substrate: Substrate Potential: Radiation Hardened Silicon Gate, Dielectric Isolation Unbiased (DI) INTERFACE MATERIALS: Backside Finish: Glassivation: Silicon Type: SiO2 Thickness: 8kÅ ±1kÅ Metallization Mask Layout (6) G1 (7) Y7 (8) GND (9) Y6 HS-54C138RH Y5 (10) (5) G2B Y4 (11) (4) G2A Y3 (12) (3) C Y2 (13) 4 B (2) A (1) VDD (16) Y0 (15) Y1 (14)