HT46R64/HT46C64 A/D with LCD Type 8-Bit MCU Features · Operating voltage: · Watchdog Timer fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V · Buzzer output · On-chip crystal, RC and 32768Hz crystal oscillator · 24 bidirectional I/O lines · HALT function and wake-up feature reduce power · Two external interrupt input consumption · One 8-bit and one 16-bit programmable timer/event · 8-level subroutine nesting counter with PFD (programmable frequency divider) function · 8 channels 10-bit resolution A/D converter · 4-channel 8-bit PWM output shared with 4 I/O lines · LCD driver with 33´3 or 32´4 segments · Bit manipulation instruction (logical output option for SEG0~SEG15) · 16-bit table read instruction · 4K´15 program memory · Up to 0.5ms instruction cycle with 8MHz system clock · 192´8 data memory RAM · 63 powerful instructions · Supports PFD for sound generation · All instructions in 1 or 2 machine cycles · Real Time Clock (RTC) · Low voltage reset/detector function · 8-bit prescaler for RTC · 56-pin SSOP, 100-pin QFP package General Description Converter, Pulse Width Modulation function, HALT and wake-up functions, in addition to a flexible and configurable LCD interface enhance the versatility of these devices to control a wide range of applications requiring analog signal processing and LCD interfacing, such as electronic metering, environmental monitoring, handheld measurement tools, motor driving, etc., for both industrial and home appliance application areas. The HT46R64/HT46C64 are 8-bit, high performance, RISC architecture microcontroller devices specifically designed for A/D product applications that interface directly to analog signals and which require LCD Interface. The mask version HT46C64 is fully pin and functionally compatible with the OTP version HT46R64 device. The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, multi-channel A/D Rev. 1.40 HT46C64 under development, available in 4Q, 2004. 1 September 21, 2004 HT46R64/HT46C64 Block Diagram In te rru p t C ir c u it P ro g ra m E P R O M IN T C In s tr u c tio n R e g is te r M M P M T M R 1 C T M R 1 P F D 1 U X P W S T A T U S A L U S P O R T D P D 3 2 7 6 8 H z U Y S /4 R T C X O S C O S C 3 O S C 4 P D P D P D P D P D 0 / 4 / 5 / 6 / 7 / P W IN IN T M T M M 0 ~ P D 3 /P W T 0 T 1 R 0 R 1 M 3 8 -C h a n n e l A /D C o n v e rte r D S P B C A C C C 1 P O R T B P B L C D M e m o ry C 3 P A C P O R T A P A L C D D R IV E R H A L T C O M 0 ~ C O M 2 Rev. 1.40 X W D T O S C S h ifte r B P O S R E V D V S O S Y S P D 7 /T M R 1 fS Y S /4 M M P D C O S C 2 O S C 4 U fS P D 6 /T M R 0 fS W D T M U X T im in g G e n e r a tio n X R T C D A T A M e m o ry T im e B a s e In s tr u c tio n D e c o d e r U P F D 0 S T A C K P ro g ra m C o u n te r P r e s c a le r M T M R 0 C T M R 0 C O M 3 / S E G 3 2 E N /D IS P B 0 /A N 0 ~ P B 7 /A N 7 P A 0 P A 1 P A 2 P A 3 P A 4 /B Z /B Z /P F D ~ P A 7 L V D /L V R S E G 0 ~ S E G 3 1 2 September 21, 2004 HT46R64/HT46C64 Pin Assignment S E G 8 P A 7 8 4 9 S E G 9 P B 0 /A N 0 9 4 8 S E G 1 0 1 0 4 7 S E G 1 1 1 1 4 6 S E G 1 2 P B 3 /A N 3 1 2 4 5 S E G 1 3 P B 4 /A N 4 1 3 4 4 S E G 1 4 P B 5 /A N 5 1 4 4 3 S E G 1 5 V S S 1 5 4 2 S E G 1 6 P D 0 /P W M 0 1 6 4 1 S E G 1 7 P D 1 /P W M 1 1 7 4 0 S E G 1 8 P D 2 /P W M 2 1 8 3 9 S E G 1 9 P D 4 /IN T 0 1 9 3 8 S E G 2 0 P D 5 /IN T 1 2 0 3 7 S E G 2 1 P D 6 /T M R 0 2 1 3 6 S E G 2 2 V L C D 2 2 3 5 S E G 2 3 V M A X 2 3 3 4 S E G 2 4 V 1 2 4 3 3 S E G 2 5 V 2 2 5 3 2 S E G 2 6 C 1 2 6 3 1 C O M 3 /S E G 3 2 C 2 2 7 3 0 C O M 2 C O M 0 2 8 2 9 C O M 1 P P P P P P P A N N N N N P A P A P B 0 /A N P B 1 /A N P B 2 /A N P B 3 /A N P B 4 /A N P B 5 /A N P B 6 /A N P B 7 /A N V S D 0 /P W M D 1 /P W M D 2 /P W M D 3 /P W M P D 4 /IN T P D 5 /IN T D 6 /T M R D 7 /T M R N N N N N 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 1 5 8 0 7 9 C 2 C 3 7 8 C 4 7 7 C 5 7 6 C 6 7 5 7 7 4 6 7 3 8 7 0 1 2 3 4 5 9 7 2 1 0 7 1 1 1 7 0 1 2 6 9 1 3 6 8 1 4 6 7 H T 4 6 R 6 4 /H T 4 6 C 6 4 1 0 0 Q F P -A 1 5 6 1 6 7 1 7 S 6 6 6 5 6 4 6 3 1 8 0 6 2 1 9 1 6 1 2 0 2 2 1 6 0 2 2 5 9 1 2 3 5 8 0 2 4 5 7 1 2 5 5 6 C 2 6 2 7 5 5 C C 2 8 5 3 C 2 9 5 2 C 3 0 3 0 5 4 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 S E S E S E N C N C N C S E S E S E S E S E S E S E S E S E S E S E S E S E S E S E S E S E S E N C N C N C N C N C N C G 1 G 2 G 3 G 4 G 5 G 6 G 7 G 8 G 9 G 1 G 1 G 1 G 1 G 1 G 1 G 1 G 1 G 1 G 1 G 2 G 2 0 1 2 3 4 5 6 7 8 9 0 1 S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G C O M C O M C O M C O M C 2 C 1 V 2 V 1 V M A V L C P B 1 /A N 1 P B 2 /A N 2 0 5 0 C 7 C P A 6 C O S C 4 C 5 1 C 6 C P A 5 C O S C 3 C 5 2 4 5 3 P A 4 D V D D 2 O S C 2 5 3 1 5 4 4 Z 3 S P A 2 P A 3 /P F D Z O S C 1 2 R E S 5 5 4 5 6 2 D 1 S E G N N N N N N N N O S C O S C V D O S C O S C R E P A 0 /B P A 1 /B P A P A 3 /P F P A P A 0 /B Z P A 1 /B Z D 0 3 2 1 Rev. 1.40 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 /S E G 3 2 X H T 4 6 R 6 4 /H T 4 6 C 6 4 5 6 S S O P -A September 21, 2004 HT46R64/HT46C64 Pin Description Pin Name PA0/BZ PA1/BZ PA2 PA3/PFD PA4~PA7 PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7 PD0/PWM0 PD1/PWM1 PD2/PWM2 PD3/PWM3 I/O I/O I/O I/O Options Description Wake-up Pull-high Buzzer PFD Bidirectional 8-bit input/output port. Each bit can be configured as wake-up input by option. Software instructions determine the CMOS output or Schmitt Trigger input with or without pull-high resistor (determined by pull-high options: bit option). The BZ, BZ and PFD are pin-shared with PA0, PA1 and PA3, respectively. Pull-high Bidirectional 8-bit input/output port. Software instructions determine the CMOS output, Schmitt trigger input with or without pull-high resistor (determined by pull-high option: bit option) or A/D input. Once a PB line is selected as an A/D input (by using software control), the I/O function and pull-high resistor are disabled automatically. Pull-high PWM Bidirectional 4-bit input/output port. Software instructions determine the CMOS output, Schmitt trigger input with or without a pull-high resistor (determined by pull-high option: bit option). The PWM0/PWM1/PWM2/PWM3 output function are pin-shared with PD0/PD1/PD2/PD3 (dependent on PWM options). Bidirectional 4-bit input/output port. Software instructions determine the CMOS output, Schmitt trigger input with or without a pull-high resistor (determined by pull-high option: bit option). The INT0, INT1, TMR0 and TMR1 are pin-shared with PD4/PD5/PD6/PD7. PD4/INT0 PD5/INT1 PD6/TMR0 PD7/TMR1 I/O Pull-high VSS ¾ ¾ Negative power supply, ground VLCD I ¾ LCD power supply VMAX I ¾ IC maximum voltage connect to VDD, VLCD or V1 V1, V2, C1, C2 I ¾ Voltage pump COM0~COM2 COM3/SEG32 O 1/3 or 1/4 Duty SEG32 can be set as a segment or as a common output driver for LCD panel by options. COM0~COM2 are outputs for LCD panel plate. SEG0~SEG31 O Logical Output LCD driver outputs for LCD panel segments. SEG0~SEG23 can be optioned as logical outputs. OSC1 OSC2 I O Crystal or RC OSC1 and OSC2 are connected to an RC network or a crystal (by options) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock. The system clock may come from the RTC oscillator. If the system clock comes from RTCOSC, these two pins can be floating. OSC3 OSC4 I O RTC or System Clock Real time clock oscillators. OSC3 and OSC4 are connected to a 32768Hz crystal oscillator for timing purposes or to a system clock source (depending on the options). No built-in capacitor VDD ¾ ¾ Positive power supply RES I ¾ Schmitt trigger reset input, active low Absolute Maximum Ratings Supply Voltage ...........................VSS-0.3V to VSS+6.0V Storage Temperature ............................-50°C to 125°C Input Voltage..............................VSS-0.3V to VDD+0.3V Operating Temperature...........................-40°C to 85°C Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.40 4 September 21, 2004 HT46R64/HT46C64 D.C. Characteristics Ta=25°C Test Conditions Symbol Parameter VDD IDD1 IDD2 ¾ 5.5 V ¾ fSYS=8MHz 3.3 ¾ 5.5 V Operating Current (Crystal OSC) 3V No load, ADC off fSYS=4MHz ¾ 1 2 mA ¾ 3 5 mA Operating Current (RC OSC) 3V No load, ADC off fSYS=4MHz ¾ 1 2 mA ¾ 3 5 mA No load, ADC off fSYS=8MHz ¾ 4 8 mA ¾ 0.3 0.6 mA ¾ 0.6 1 mA ¾ ¾ 1 mA ¾ ¾ 2 mA ¾ 2.5 5 mA ¾ 10 20 mA ¾ 2 5 mA ¾ 6 10 mA ¾ 17 30 mA ¾ 34 60 mA ¾ 13 25 mA ¾ 28 50 mA ¾ 14 25 mA ¾ 26 50 mA ¾ 10 20 mA ¾ 19 40 mA 5V 5V Operating Current (fSYS=32768Hz) 3V Standby Current (*fS=T1) 3V Standby Current (*fS=32.768kHz OSC) 3V ISTB4 ISTB5 ISTB6 ISTB7 Unit 2.2 IDD4 ISTB3 Max. fSYS=4MHz Operating Current (Crystal OSC, RC OSC) ISTB2 Typ. ¾ Operating Voltage IDD3 ISTB1 Min. Conditions VDD Standby Current (*fS=WDT RC OSC) Standby Current (*fS=32.768kHz OSC) Standby Current (*fS=32.768kHz OSC) Standby Current (*fS=WDT RC OSC) Standby Current (*fS=WDT RC OSC) 5V No load, ADC off 5V 5V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V No load, system HALT LCD off at HALT No load, system HALT LCD on at HALT, C type No load, system HALT LCD on at HALT, C type No load, system HALT LCD on at HALT, R type, 1/2 bias, VLCD=VDD (Low bias current option) No load, system HALT LCD on at HALT, R type, 1/3 bias, VLCD=VDD (Low bias current option) No load, system HALT LCD on at HALT, R type, 1/2 bias, VLCD=VDD (Low bias current option) No load, system HALT LCD on at HALT, R type, 1/3 bias, VLCD=VDD (Low bias current option) VIL1 Input Low Voltage for I/O Ports, TMR and INT ¾ ¾ 0 ¾ 0.3VDD V VIH1 Input High Voltage for I/O Ports, TMR and INT ¾ ¾ 0.7VDD ¾ VDD V VIL2 Input Low Voltage (RES) ¾ ¾ 0 ¾ 0.4VDD V VIH2 Input High Voltage (RES) ¾ ¾ 0.9VDD ¾ VDD V VLVR Low Voltage Reset Voltage ¾ ¾ 2.7 3.0 3.3 V VLVD Low Voltage Detector Voltage ¾ ¾ 3.0 3.3 3.6 V IOL I/O Port Segment Logic Output Sink Current 3V 6 12 ¾ mA 10 25 ¾ mA Rev. 1.40 VOL=0.1VDD 5V 5 September 21, 2004 HT46R64/HT46C64 Test Conditions Symbol Parameter I/O Port Segment Logic Output Source Current IOH 3V Min. Typ. Max. Unit -2 -4 ¾ mA -5 -8 ¾ mA Conditions VDD VOH=0.9VDD 5V Pull-high Resistance of I/O Ports and INT0, INT1 3V ¾ 20 60 100 kW 5V ¾ 10 30 50 kW VAD A/D Input Voltage ¾ ¾ 0 ¾ VDD V EAD A/D Conversion Integral Nonlinearity Error ¾ ¾ ¾ ±0.5 ±1 LSB IADC Additional Power Consumption if A/D Converter is Used 3V ¾ 0.5 1 mA ¾ 1.5 3 mA RPH Note: ¾ 5V ²*fS² please refer to clock option of WDT (page 13) A.C. Characteristics Ta=25°C Test Conditions Symbol Parameter fSYS1 System Clock Typ. Max. Unit ¾ 2.2V~5.5V 400 ¾ 4000 kHz ¾ 3.3V~5.5V 400 ¾ 8000 kHz 2.2V~5.5V ¾ 32768 ¾ Hz ¾ 32768 ¾ Hz fSYS2 System Clock (32768Hz Crystal OSC) ¾ fRTCOSC RTC Frequency ¾ fTIMER Timer I/P Frequency (TMR0/TMR1) tWDTOSC Watchdog Oscillator Period Min. Conditions VDD ¾ ¾ 2.2V~5.5V 0 ¾ 4000 kHz ¾ 3.3V~5.5V 0 ¾ 8000 kHz 3V ¾ 45 90 180 ms 5V ¾ 32 65 130 ms tRES External Reset Low Pulse Width ¾ ¾ 1 ¾ ¾ ms tSST System Start-up Timer Period ¾ Power-up or wake-up from HALT ¾ 1024 ¾ tSYS tINT Interrupt Pulse Width ¾ ¾ 1 ¾ ¾ ms tAD A/D Clock Period ¾ ¾ 1 ¾ ¾ ms tADC A/D Conversion Time ¾ ¾ ¾ 76 ¾ tAD tADCS A/D Sampling Time ¾ ¾ ¾ 32 ¾ tAD Note: tSYS= 1/fSYS Rev. 1.40 6 September 21, 2004 HT46R64/HT46C64 Functional Description Execution Flow After accessing a program memory word to fetch an instruction code, the value of the PC is incremented by 1. The PC then points to the memory word containing the next instruction code. The system clock is derived from either a crystal or an RC oscillator or a 32768Hz crystal oscillator. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. When executing a jump instruction, conditional skip execution, loading a PCL register, a subroutine call, an initial reset, an internal interrupt, an external interrupt, or returning from a subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. The pipelining scheme makes it possible for each instruction to be effectively executed in a cycle. If an instruction changes the value of the program counter, two cycles are required to complete the instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get a proper instruction; otherwise proceed to the next instruction. Program Counter - PC The program counter (PC) is 12 bits wide and it controls the sequence in which the instructions stored in the program ROM are executed. The contents of the PC can specify a maximum of 4096 addresses. S y s te m O S C 2 (R C C lo c k T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 o n ly ) P C P C P C + 1 F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 ) P C + 2 F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C ) F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 ) Execution Flow Mode Program Counter *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 Initial Reset 0 0 0 0 0 0 0 0 0 0 0 0 External Interrupt 0 0 0 0 0 0 0 0 0 0 1 0 0 External Interrupt 1 0 0 0 0 0 0 0 0 1 0 0 0 Timer/Event Counter 0 Overflow 0 0 0 0 0 0 0 0 1 1 0 0 Timer/Event Counter 1 Overflow 0 0 0 0 0 0 0 1 0 0 0 0 Time Base Interrupt 0 0 0 0 0 0 0 1 0 1 0 0 RTC Interrupt 0 0 0 0 0 0 0 1 1 0 0 0 A/D Converter Interrupt 0 0 0 0 0 0 0 1 1 1 0 0 Skip PC+2 Loading PCL *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 Jump, Call Branch #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 Return From Subroutine S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Program Counter Note: *11~*0: Program counter bits #11~#0: Instruction code bits Rev. 1.40 S11~S0: Stack register bits @7~@0: PCL bits 7 September 21, 2004 HT46R64/HT46C64 · Location 008H The lower byte of the PC (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination is within 256 locations. Location 008H is reserved for the external interrupt service program also. If the INT1 input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 008H. When a control transfer takes place, an additional dummy cycle is required. · Location 00CH Location 00CH is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00CH. Program Memory - EPROM The program memory (EPROM) is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 4096´15 bits which are addressed by the PC and table pointer. · Location 010H Location 010H is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 010H. Certain locations in the ROM are reserved for special usage: · Location 000H · Location 014H Location 000H is reserved for program initialization. After chip reset, the program always begins execution at this location. Location 014H is reserved for the Time Base interrupt service program. If a Time Base interrupt occurs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 014H. · Location 004H Location 004H is reserved for the external interrupt service program. If the INT0 input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 004H. 0 0 0 H · Location 01CH E x te r n a l in te r r u p t 0 s u b r o u tin e 0 0 8 H 0 1 0 H Location 018H is reserved for the real time clock interrupt service program. If a real time clock interrupt occurs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 018H. D e v ic e in itia liz a tio n p r o g r a m 0 0 4 H 0 0 C H · Location 018H Location 01CH is reserved for the A/D converter interrupt service program. If an A/D converter interrupt results from an end of A/D conversion and the stack is not full, the program begins execution at location 01CH. E x te r n a l in te r r u p t 1 s u b r o u tin e T im e r /e v e n t c o u n te r 0 in te r r u p t s u b r o u tin e T im e r /e v e n t c o u n te r 1 in te r r u p t s u b r o u tin e 0 1 4 H 0 1 8 H · Table location P ro g ra m M e m o ry T im e B a s e In te r r u p t Any location in the ROM can be used as a look-up table. The instructions ²TABRDC [m]² (the current page, 1 page=256 words) and ²TABRDL [m]² (the last page) transfer the contents of the lower-order byte to the specified data memory, and the contents of the higher-order byte to TBLH (Table Higher-order byte register) (08H). Only the destination of the lower-order byte in the table is well-defined; the other bits of the table word are all transferred to the lower portion of TBLH. The TBLH is read only, and the table pointer (TBLP) is a read/write register (07H), indicating the table location. Before accessing the table, the location should be placed in TBLP. All the table related instructions require 2 cycles to complete the operation. R T C In te rru p t 0 1 C H A /D C o n v e rte r In te rru p t n 0 0 H L o o k - u p ta b le ( 2 5 6 w o r d s ) n F F H L o o k - u p ta b le ( 2 5 6 w o r d s ) F F F H 1 5 b its N o te : n ra n g e s fro m 0 to F Program Memory Instruction(s) Table Location *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 TABRDC [m] P11 P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0 TABRDL [m] 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 Table Location Note: *11~*0: Table location bits @7~@0: Table pointer bits Rev. 1.40 P11~P8: Current program counter bits 8 September 21, 2004 HT46R64/HT46C64 These areas may function as a normal ROM depending upon the user¢s requirements. 0 0 H Stack Register - STACK The stack register is a special part of the memory used to save the contents of the PC. The stack is organized into 8 levels and is neither part of the data nor part of the program, and is neither readable nor writeable. Its activated level is indexed by a stack pointer (SP) and is neither readable nor writeable. At the start of a subroutine call or an interrupt acknowledgment, the contents of the PC is pushed onto the stack. At the end of the subroutine or interrupt routine, signaled by a return instruction (RET or RETI), the contents of the PC is restored to its previous value from the stack. After chip reset, the SP will point to the top of the stack. M P 0 0 2 H In d ir e c t A d d r e s s in g R e g is te r 1 0 3 H M P 1 0 4 H B P 0 5 H A C C 0 6 H P C L 0 7 H T B L P 0 8 H T B L H 0 9 H R T C C 0 A H S T A T U S 0 B H IN T C 0 0 C H If the stack is full and a non-masked interrupt takes place, the interrupt request flag is recorded but the acknowledgment is still inhibited. Once the SP is decremented (by RET or RETI), the interrupt is serviced. This feature prevents stack overflow, allowing the programmer to use the structure easily. Likewise, if the stack is full, and a ²CALL² is subsequently executed, a stack overflow occurs and the first entry is lost (only the most recent sixteen return addresses are stored). 0 D H T M R 0 0 E H T M R 0 C 0 F H T M R 1 H 1 0 H T M R 1 L 1 1 H T M R 1 C 1 2 H P A 1 3 H P A C 1 4 H P B 1 5 H P B C S p e c ia l P u r p o s e D a ta M e m o ry 1 6 H 1 7 H Data Memory - RAM The data memory (RAM) is designed with 224´8 bits, and is divided into two functional groups, namely; special function registers 32´8 bit and general purpose data memory, 192´8 bit most of which are readable/writable, although some are read only. The special function register are overlapped in any banks. 1 8 H P D 1 9 H P D C 1 A H P W M 0 1 B H P W M 1 1 C H P W M 2 1 D H P W M 3 1 E H IN T C 1 1 F H 2 0 H 2 1 H 2 2 H 2 3 H Of the two types of functional groups, the special function registers consist of an Indirect addressing register 0 (00H), a Memory pointer register 0 (MP0;01H), an Indirect addressing register 1 (02H), a Memory pointer register 1 (MP1;03H), a Bank pointer (BP;04H), an Ac c u m u l at or ( A C C ; 0 5 H ) , a P r ogr a m co u n t e r lower-order byte register (PCL;06H), a Table pointer (TBLP;07H), a Table higher-order byte register (TBLH;08H), a Real time clock control register (RTCC;09H), a Status register (STATUS;0AH), an Interrupt control register 0 (INTC0;0BH), a Timer/Event Counter 0 (TMR0; 0DH), a Timer/Event Counter 0 control register (TMR0C;0EH), a Timer/Event Counter 1 (TMR1H:0FH;TMR1L:10H), a Timer/Event Counter 1 control register (TMR1C; 11H), Interrupt control register 1 (INTC1;1EH), PWM data register (PWM0;1AH, PWM1;1BH, PWM2;1CH, PWM3;1DH), the A/D result lower-order byte register (ADRL;24H), the A/D result higher-order byte register (ADRH;25H), the A/D control register (ADCR;26H), the A/D clock setting register (ACSR;27H), I/O registers (PA;12H, PB;14H, PD;18H) and I/O control registers (PAC;13H, PBC;15H, PDC;19H). The remaining space before the 40H is reRev. 1.40 In d ir e c t A d d r e s s in g R e g is te r 0 0 1 H 2 4 H A D R L 2 5 H A D R H 2 6 H A D C R 2 7 H A C S R 2 8 H 3 F H 4 0 H F F H : U n u s e d G e n e ra l P u rp o s e D a ta M e m o ry (1 9 2 B y te s ) R e a d a s "0 0 " RAM Mapping served for future expanded usage and reading these locations will get ²00H². The space before 40H is overlapping in each bank. The general purpose data memory, addressed from 40H to FFH, is used for data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by ²SET [m].i² and ²CLR 9 September 21, 2004 HT46R64/HT46C64 The ALU not only saves the results of a data operation but also changes the status register. [m].i². They are also indirectly accessible through memory pointer registers (MP0;01H/MP1;03H). The space before 40H is overlapping in each bank. Status Register - STATUS Indirect Addressing Register The status register (0AH) is 8 bits wide and contains, a carry flag (C), an auxiliary carry flag (AC), a zero flag (Z), an overflow flag (OV), a power down flag (PDF), and a watchdog time-out flag (TO). It also records the status information and controls the operation sequence. Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] accesses the RAM pointed to by MP0 (01H) and MP1(03H) respectively. Reading location 00H or 02H indirectly returns the result 00H. While, writing it indirectly leads to no operation. Except for the TO and PDF flags, bits in the status register can be altered by instructions similar to other registers. Data written into the status register does not alter the TO or PDF flags. Operations related to the status register, however, may yield different results from those intended. The TO and PDF flags can only be changed by a Watchdog Timer overflow, chip power-up, or clearing the Watchdog Timer and executing the ²HALT² instruction. The Z, OV, AC, and C flags reflect the status of the latest operations. The function of data movement between two indirect addressing registers is not supported. The memory pointer registers, MP0 and MP1, are both 8-bit registers used to access the RAM by combining corresponding indirect addressing registers. MP0 can only be applied to data memory, while MP1 can be applied to data memory and LCD display memory. Accumulator - ACC The accumulator (ACC) is related to the ALU operations. It is also mapped to location 05H of the RAM and is capable of operating with immediate data. The data movement between two data memory locations must pass through the ACC. On entering the interrupt sequence or executing the subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly. Arithmetic and Logic Unit - ALU Interrupts This circuit performs 8-bit arithmetic and logic operations and provides the following functions: The device provides two external interrupts, two internal timer/event counter interrupts, an internal time base interrupt, and an internal real time clock interrupt and the A/D converter interrupt (NMI). The interrupt control register 0 (INTC0;0BH) and interrupt control register 1 (INTC1;1EH) both contain the interrupt control bits that are used to set the enable/disable status and interrupt request flags. · Arithmetic operations (ADD, ADC, SUB, SBC, DAA) · Logic operations (AND, OR, XOR, CPL) · Rotation (RL, RR, RLC, RRC) · Increment and Decrement (INC, DEC) · Branch decision (SZ, SNZ, SIZ, SDZ etc.) Labels Bits Function C 0 C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC 1 AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z 2 Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV 3 OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF 4 PDF is cleared by either a system power-up or executing the ²CLR WDT² instruction. PDF is set by executing the ²HALT² instruction. TO 5 TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is set by a WDT time-out. ¾ 6~7 Unused bit, read as ²0² Status Register Rev. 1.40 10 September 21, 2004 HT46R64/HT46C64 The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (T0F; bit 6 of INTC0), which is normally caused by a timer overflow. After the interrupt is enabled, and the stack is not full, and the T0F bit is set, a subroutine call to location 0CH occurs. The related interrupt request flag (T0F) is reset, and the EMI bit is cleared to disable other maskable interrupts. Timer/Event Counter 1 is operated in the same manner but its related interrupt request flag is T1F (bit 4 of INTC1) and its subroutine call location is 10H. Once an interrupt subroutine is serviced, other interrupts except NMI are all blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may take place during this interval, but only the interrupt request flag will be recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC0 or of INTC1 may be set in order to allow interrupt nesting. Once the stack is full, the interrupt request (except NMI) will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack should be prevented from becoming full. The A/D converter Interrupt is a Non-maskable interrupt (NMI) which occurs when an A/D conversion process has been completed and EOCB becomes ²0². The A/D converter interrupt is controlled by an EADI (bit 7 of the INTC0). When EADI=²1², the A/D converter interrupt is enabled. If the EADI=²0², the A/D converter interrupt is disabled. The A/D converter interrupt cannot be masked by disabling the EMI. After the interrupt is enabled, and if the A/D Conversion process has been completed (when EOCB becomes ²0²), a subroutine call to location 1CH occurs. If the stack is and if the A/D converter interrupt subroutine is serviced, the A/D converter interrupt¢s return address will be pushed into the stack, and the first return address in the stack will be flushed. It is important that at least one stack level is left available when using the A/D interrupt. All these interrupts can support a wake-up function. As an interrupt is serviced, a control transfer occurs by pushing the contents of the PC onto the stack followed by a branch to a subroutine at the specified location in the ROM. Only the contents of the PC is pushed onto the stack. If the contents of the register or of the status register (STATUS) is altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. External interrupts are triggered by a an edge transition of INT0 or INT1 (ROM code option: high to low, low to high, low to high or high to low), and the related interrupt request flag (EIF0; bit 4 of INTC0, EIF1; bit 5 of INTC0) is set as well. After the interrupt is enabled, the stack is not full, and the external interrupt is active, a subroutine call to location 04H or 08H occurs. The interrupt request flag (EIF0 or EIF1) and EMI bits are all cleared to disable other maskable interrupts. Register INTC0 (0BH) INTC1 (1EH) The time base interrupt is initialized by setting the time base interrupt request flag (TBF; bit 5 of INTC1), that is caused by a regular time base signal. After the interrupt is enabled, and the stack is not full, and the TBF bit is Bit No. Label Function 0 EMI Control the master (global) interrupt (1=enabled; 0=disabled) 1 EEI0 Control the external interrupt 0 (1=enabled; 0=disabled) 2 EEI1 Control the external interrupt 1 (1=enabled; 0=disabled) 3 ET0I Control the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled) 4 EIF0 External interrupt 0 request flag (1=active; 0=inactive) 5 EIF1 External interrupt 1 request flag (1=active; 0=inactive) 6 T0F Internal Timer/Event Counter 0 request flag (1=active; 0=inactive) 7 EADI Control the A/D converter interrupt (NMI; 1=enable; 0=disable) 0 ET1I Control the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled) 1 ETBI Control the time base interrupt (1=enabled; 0:disabled) 2 ERTI Control the real time clock interrupt (1=enabled; 0:disabled) 3 ¾ 4 T1F Internal Timer/Event Counter 1 request flag (1=active; 0=inactive) Unused bit, read as ²0² 5 TBF Time base request flag (1=active; 0=inactive) 6 RTF Real time clock request flag (1=active; 0=inactive) 7 ¾ Unused bit, read as ²0² INTC Register Rev. 1.40 11 September 21, 2004 HT46R64/HT46C64 converter interrupt (EADI) make up of the Interrupt Control register 0 (INTC0) which is located at 0BH in the RAM. The real time clock interrupt request flag (RTF), time base interrupt request flag (TBF), Timer/Event Counter 1 interrupt request flag (T1F), enable real time clock interrupt bit (ERTI), and enable time base interrupt bit (ETBI), enable Timer/Event Counter 1 interrupt bit (ET1I) on the other hand, constitute the Interrupt Control register 1 (INTC1) which is located at 1EH in the RAM. EMI, EEI0, EEI1, ET0I, ET1I, ETBI, and ERTI are all used to control the enable/disable status of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (RTF, TBF, T0F, T1F, EIF1, EIF0) are all set, they remain in the INTC1 or INTC0 respectively until the interrupts are serviced or cleared by a software instruction. set, a subroutine call to location 14H occurs. The related interrupt request flag (TBF) is reset and the EMI bit is cleared to disable further maskable interrupts. The real time clock interrupt is initialized by setting the real time clock interrupt request flag (RTF; bit 6 of INTC1), that is caused by a regular real time clock signal. After the interrupt is enabled, and the stack is not full, and the RTF bit is set, a subroutine call to location 18H occurs. The related interrupt request flag (RTF) is reset and the EMI bit is cleared to disable further maskable interrupts. During the execution of an interrupt subroutine, other maskable interrupt acknowledgments are all held until the ²RETI² instruction is executed or the EMI bit and the related interrupt control bit are set both to 1 (if the stack is not full). To return from the interrupt subroutine, ²RET² or ²RETI² may be invoked. RETI sets the EMI bit and enables an interrupt service, but RET does not. It is recommended that a program should not use the ²CALL subroutine² within the interrupt subroutine. It¢s because interrupts often occur in an unpredictable manner or require to be serviced immediately in some applications. During that period, if only one stack is left, and enabling the interrupt is not well controlled, operation of the ²call² in the interrupt subroutine may damage the original control sequence. Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses are serviced on the latter of the two T2 pulses if the corresponding interrupts are enabled. In the case of simultaneous requests, the priorities in the following table apply. Except for A/D converter interrupt (NMI). These can be masked by resetting the EMI bit. Interrupt Source Priority Vector External interrupt 0 2 04H External interrupt 1 3 08H Timer/Event Counter 0 overflow 4 0CH Timer/Event Counter 1 overflow 5 10H Time base interrupt 6 14H Real time clock interrupt 7 18H A/D converter interrupt (This is a Non-Maskable Interrupt: NMI) 1 1CH Oscillator Configuration The device provides three oscillator circuits for system clocks, i.e., RC oscillator, crystal oscillator and 32768Hz crystal oscillator, determined by options. No matter what type of oscillator is selected, the signal is used for the system clock. The HALT mode stops the system oscillator (RC and crystal oscillator only) and ignores external signal in order to conserve power. The 32768Hz crystal oscillator still runs at HALT mode. If the 32768Hz crystal oscillator is selected as the system oscillator, the system oscillator is not stopped; but the instruction execution is stopped. Since the 32768Hz oscillator is also designed for timing purposes, the internal timing (RTC, time base, WDT) operation still runs even if the system enters the HALT mode. The Timer/Event Counter 0 interrupt request flag (T0F), external interrupt 1 request flag (EIF1), external interrupt 0 request flag (EIF0), enable Timer/Event Counter 0 interrupt bit (ET0I), enable external interrupt 1 bit (EEI1), enable external interrupt 0 bit (EEI0), enable master interrupt bit (EMI), and enable control the A/D Of the three oscillators, if the RC oscillator is used, an external resistor between OSC1 and VSS is required, and the range of the resistance should be from 30kW to 750kW. The system clock, divided by 4, is available on V O S C 3 O S C 1 O S C 4 O S C 2 3 2 7 6 8 H z C r y s ta l/R T C O s c illa to r C r y s ta l O s c illa to r D D 4 7 0 p F O S C 1 fS Y S /4 O S C 2 R C O s c illa to r System Oscillator Note: *32768Hz crystal enable condition: For WDT clock source or for system clock source. Rev. 1.40 12 September 21, 2004 HT46R64/HT46C64 OSC2 with pull-high resistor, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of the oscillation may vary with VDD, temperature, and the chip itself due to process variations. It is therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired. WDT option, longer time-out periods can be realized. If the WDT time-out is selected 215, the maximum time-out period is divided by 215~216about 2.1s~4.3s. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operate in the same manner except that in the halt state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by external logic. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock. On the other hand, if the crystal oscillator is selected, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. A resonator may be connected between OSC1 and OSC2 to replace the crystal and to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required. The WDT overflow under normal operation initializes a ²chip reset² and sets the status bit ²TO². In the HALT mode, the overflow initializes a ²warm reset², and only the PC and SP are reset to zero. To clear the contents of the WDT, there are three methods to be adopted, i.e., external reset (a low level to RES), software instruction, and a ²HALT² instruction. There are two types of software instructions; ²CLR WDT² and the other set - ²CLR WDT1² and ²CLR WDT2². Of these two types of instruction, only one type of instruction can be active at a time depending on the options - ²CLR WDT² times selection option. If the ²CLR WDT² is selected (i.e., CLR WDT times equal one), any execution of the ²CLR WDT² instruction clears the WDT. In the case that ²CLR WDT1² and ²CLR WDT2² are chosen (i.e., CLR WDT times equal two), these two instructions have to be executed to clear the WDT; otherwise, the WDT may reset the chip due to time-out. There is another oscillator circuit designed for the real time clock. In this case, only the 32.768kHz crystal oscillator can be applied. The crystal should be connected between OSC3 and OSC4. The RTC oscillator circuit can be controlled to oscillate quickly by setting the ²QOSC² bit (bit 4 of RTCC). It is recommended to turn on the quick oscillating function upon power on, and then turn it off after 2 seconds. The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Although the system enters the power down mode, the system clock stops, and the WDT oscillator still works with a period of approximately 65ms at 5V. The WDT oscillator can be disabled by options to conserve power. Watchdog Timer - WDT Multi-function Timer The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator) or an instruction clock (system clock/4) or a real time clock oscillator (RTC oscillator). The timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The WDT can be disabled by options. But if the WDT is disabled, all executions related to the WDT lead to no operation. The HT46R64/HT46C64 provides a multi-function timer for the WDT, time base and RTC but with different time-out periods. The multi-function timer consists of an 8-stage divider and a 7-bit prescaler, with the clock source coming from the WDT OSC or RTC OSC or the instruction clock (i.e., system clock divided by 4). The multi-function timer also provides a selectable frequency signal (ranges from fS/22 to fS/28) for LCD driver circuits, and a selectable frequency signal (ranging from fS/22 to fS/29) for the buzzer output by options. It is recommended to select a nearly 4kHz signal for the LCD driver circuits to have proper display. Once an internal WDT oscillator (RC oscillator with period 65ms at 5V normally) is selected, it is divided by 212~215 (by option to get the WDT time-out period). The minimum period of WDT time-out period is about 300ms~600ms. This time-out period may vary with temperature, VDD and process variations. By selection the S y s te m C lo c k /4 R T C O S C 3 2 7 6 8 H z O p tio n fS D iv id e r fS /2 8 W D T P r e s c a le r O p tio n W D T 1 2 k H z O S C C K T R W D T C le a r C K T R T im e 2 15/fS ~ 2 14/fS ~ 2 13/fS ~ 2 12/fS ~ o u 2 1 2 1 2 1 2 1 t R e s e t 6 / f S 5 / f S 4 / f S 3 / f S Watchdog Timer Rev. 1.40 13 September 21, 2004 HT46R64/HT46C64 fs D iv id e r P r e s c a le r O p tio n O p tio n L C D D r iv e r ( fS /2 2 ~ fS /2 8 ) B u z z e r (fS /2 2~ fS /2 9) T im e B a s e In te r r u p t 2 12/fS ~ 2 15/fS Time Base · The system oscillator turns off but the WDT oscillator Time Base keeps running (if the WDT oscillator or the real time clock is selected). The time base offers a periodic time-out period to generate a regular internal interrupt. Its time-out period ranges from 212/fS to 215/fS selected by options. If time base time-out occurs, the related interrupt request flag (TBF; bit 5 of INTC1) is set. But if the interrupt is enabled, and the stack is not full, a subroutine call to location 14H occurs. · The contents of the on-chip RAM and of the registers remain unchanged. · The WDT is cleared and start recounting (if the WDT clock source is from the WDT oscillator or the real time clock oscillator). · All I/O ports maintain their original status. Real Time Clock - RTC · The PDF flag is set but the TO flag is cleared. The real time clock (RTC) is operated in the same manner as the time base that is used to supply a regular internal interrupt. Its time-out period ranges from fS/28 to fS/215 by software programming . Writing data to RT2, RT1 and RT0 (bit 2, 1, 0 of RTCC;09H) yields various time-out periods. If the RTC time-out occurs, the related interrupt request flag (RTF; bit 6 of INTC1) is set. But if the interrupt is enabled, and the stack is not full, a subroutine call to location 18H occurs. · LCD driver is still running (if the WDT OSC or RTC RT2 RT1 RT0 RTC Clock Divided Factor 0 0 0 2 8* 0 0 1 2 9* 0 1 0 210* 0 1 1 211* 1 0 0 212 1 0 1 213 1 1 0 214 1 1 1 215 OSC is selected). The system quits the HALT mode by an external reset, an interrupt, an external falling edge signal on port A, or a WDT overflow. An external reset causes device initialization, and the WDT overflow performs a ²warm reset². After examining the TO and PDF flags, the reason for chip reset can be determined. The PDF flag is cleared by system power-up or by executing the ²CLR WDT² instruction, and is set by executing the ²HALT² instruction. On the other hand, the TO flag is set if WDT time-out occurs, and causes a wake-up that only resets the PC (Program Counter) and SP, and leaves the others at their original state. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by options. Awakening from an I/O port stimulus, the program resumes execution of the next instruction. On the other hand, awakening from an interrupt, two sequence may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program resumes execution at the next instruction. But if the interrupt is enabled, and the stack is not full, the regular interrupt response takes place. Note: ²*² not recommended to be used Power Down Operation - HALT The HALT mode is initialized by the ²HALT² instruction and results in the following. fS D iv id e r P r e s c a le r R T 2 R T 1 R T 0 8 to 1 M u x . 2 8/fS ~ 2 15/fS R T C In te rru p t Real Time Clock Rev. 1.40 14 September 21, 2004 HT46R64/HT46C64 The functional unit chip reset status is shown below. When an interrupt request flag is set before entering the ²HALT² status, the system cannot be awakened using that interrupt. If wake-up events occur, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period is inserted after the wake-up. If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution is delayed by more than one cycle. However, if the wake-up results in the next instruction execution, the execution will be performed immediately after the dummy period is finished. PC 000H Interrupt Disabled Prescaler, Divider Cleared WDT, RTC, Time Base Cleared. After master reset, WDT starts counting Timer/event Counter Off Input/output Ports Input mode SP Points to the top of the stack To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. V D D 0 .0 1 m F * Reset There are three ways in which reset may occur. 1 0 0 k W · RES is reset during normal operation R E S · RES is reset during HALT 1 0 k W · WDT time-out is reset during normal operation 0 .1 m F * The WDT time-out during HALT differs from other chip reset conditions, for it can perform a ²warm reset² that resets only the PC and SP and leaves the other circuits at their original state. Some registers remain unaffected during any other reset conditions. Most registers are reset to the ²initial condition² once the reset conditions are met. Examining the PDF and TO flags, the program can distinguish between different ²chip resets². TO PDF 0 0 RES reset during power-up u u RES reset during normal operation 0 1 RES Wake-up HALT 1 u WDT time-out during normal operation 1 1 WDT Wake-up HALT Reset Circuit Note: RESET Conditions ²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. V D D R E S tS S T S S T T im e - o u t C h ip R e s e t Reset Timing Chart Note: ²u² stands for unchanged H A L T To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system awakes from the HALT state or during power up. Awaking from the HALT state or system power-up, the SST delay is added. W D T An extra SST delay is added during the power-up period, and any wake-up from HALT may enable only the SST delay. R e s e t T im e - o u t R e s e t E x te rn a l R E S O S C 1 W a rm W D T C o ld R e s e t S S T 1 0 - b it R ip p le C o u n te r P o w e r - o n D e te c tio n Reset Configuration Rev. 1.40 15 September 21, 2004 HT46R64/HT46C64 The register states are summarized below: Register Reset (Power On) WDT Time-out RES Reset (Normal Operation) (Normal Operation) RES Reset (HALT) WDT Time-out (HALT)* TMR0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR0C 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu TMR1H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR1L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR1C 0000 1--- 0000 1--- 0000 1--- 0000 1--- uuuu u--- Program Counter 0000H 0000H 0000H 0000H 0000H MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu BP 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH -xxx xxxx -xxx xxxx -xxx xxxx -xxx xxxx -uuu uuuu STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu INTC0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC1 -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu RTCC --00 0111 --00 0111 --00 0111 --00 0111 --uu uuuu PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PB 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PD 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PDC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PWM0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu PWM1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu PWM2 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu PWM3 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADRL xx-- ---- xx-- ---- xx-- ---- xx-- ---- uu-- ---- ADRH xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADCR 0100 0000 0100 0000 0100 0000 0100 0000 uuuu uuuu ACSR 1--- --00 1--- --00 1--- --00 ---- --00 u--- --uu Note: ²*² stands for warm reset ²u² stands for unchanged ²x² stands for unknown Rev. 1.40 16 September 21, 2004 HT46R64/HT46C64 internal lower-order byte buffer (8-bit) and writing TMR1H will transfer the specified data and the contents of the lower-order byte buffer to TMR1H and TMR1L registers, respectively. Timer/Event Counter Two timer/event counters (TMR0,TMR1) are implemented in the microcontroller. The Timer/Event Counter 0 contains a 8-bit programmable count-up counter and the clock may come from an external source or an internal clock source. An internal clock source comes from fSYS. The Timer/Event Counter 1 contains a 16-bit programmable count-up counter and the clock may come from an external source or an internal clock source. An internal clock source comes from fSYS/4 or 32768Hz selected by option. The external clock input allows the user to count external events, measure time intervals or pulse widths, or to generate an accurate time base. The Timer/Event Counter 1 preload register is changed everytime there is a writing operation to TRM1H. Reading TMR1H will latch the contents of TMR1H and TMR1L counters to the destination and the lower-order byte buffer, respectively. Reading the TMR1L will read the contents of the lower-order byte buffer. The TMR1C is the Timer/Event Counter 1 control register, which defines the operating mode, counting enable or disable and an active edge. The T0M0, T0M1 (TMR0C) and T1M0, T1M1 (TMR1C) bits define the operation mode. The event count mode is used to count external events, which means that the clock source is from an external (TMR0, TMR1) pin. The timer mode functions as a normal timer with the clock source coming from the internal selected clock source. Finally, the pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR0, TMR1), and the counting is based on the internal selected clock source. There are two registers related to the Timer/Event Counter 0; TMR0 ([0DH]) and TMR0C ([0EH]). Two physical registers are mapped to TMR0 location; writing TMR0 puts the starting value in the Timer/Event Counter 0 register and reading TMR0 takes the contents of the Timer/Event Counter 0. The TMR0C is a timer/event counter control register, which defines some options. There are three registers related to the Timer/Event Counter 1; TMR1H (0FH), TMR1L (10H) and TMR1C (11H). Writing TMR1L will only put the written data to an P W M (6 + 2 ) o r (7 + 1 ) C o m p a re fS Y S T o P D 0 /P D 1 /P D 2 /P D 3 C ir c u it 8 - s ta g e P r e s c a le r f IN 8 -1 M U X T 0 P S C 2 ~ T 0 P S C 0 D a ta B u s T T 0 M 1 T 0 M 0 T M R 0 R e lo a d 8 - b it T im e r /E v e n t C o u n te r P r e lo a d R e g is te r T 0 E T 0 M 1 T 0 M 0 T 0 O N P u ls e W id th M e a s u re m e n t M o d e C o n tro l 8 - b it T im e r /E v e n t C o u n te r (T M R 0 ) O v e r flo w to In te rru p t P F D 0 Timer/Event Counter 0 D a ta B u s fS Y S /4 3 2 7 6 8 H z T 1 S M U f IN L o w B y te B u ffe r T X T 1 M 1 T 1 M 0 T M R 1 1 6 - B it P r e lo a d R e g is te r T 1 E T 1 M 1 T 1 M 0 T 1 O N P u ls e W id th M e a s u re m e n t M o d e C o n tro l H ig h B y te R e lo a d O v e r flo w L o w B y te to In te rru p t 1 6 - B it T im e r /E v e n t C o u n te r P F D 1 Timer/Event Counter 1 P F D 0 P F D 1 M U X 1 /2 P F D P A 3 D a ta C T R L P F D S o u r c e O p tio n PFD Source Option Rev. 1.40 17 September 21, 2004 HT46R64/HT46C64 In the event count or timer mode, the timer/event counter 0(1) starts counting at the current contents in the timer/event counter 0(1) and ends at FFH(FFFFH). Once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request flag (T0F; bit 6 of INTC0, T1F; bit 4 of INTC1). In the pulse width measurement mode with the values of the T0ON/T1ON and T0E/T1E bits equal to 1, after the TMR0 (TMR1) has received a transient from low to high (or high to low if the TE bit is ²0²), it will start counting until the TMR0 (TMR1) returns to the original level and resets the T0ON/T1ON. The measured result remains in the timer/event counter even if the activated transient occurs again. In other words, only 1-cycle measurement can be made until the T0ON/T1ON is set. The cycle measurement will Label (TMR0C) re-function as long as it receives further transient pulse. In this operation mode, the timer/event counter begins counting not according to the logic level but to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter register and issues an interrupt request, as in the other two modes, i.e., event and timer modes. To enable the counting operation, the Timer ON bit (T0ON: bit 4 of TMR0C; T1ON: bit 4 of TMR1C) should be set to 1. In the pulse width measurement mode, the T0ON/T1ON is automatically cleared after the measurement cycle is completed. But in the other two modes, the T0ON/T1ON can only be reset by instructions. The overflow of the Timer/Event Counter 0/1 is one of the wake-up sources and can also be applied to a PFD (Programmable Frequency Divider) output at PA3 by op- Bits Function T0PSC0 T0PSC1 T0PSC2 0 1 2 To define the prescaler stages. T0PSC2, T0PSC1, T0PSC0= 000: fINT=fSYS 001: fINT=fSYS/2 010: fINT=fSYS/4 011: fINT=fSYS/8 100: fINT=fSYS/16 101: fINT=fSYS/32 110: fINT=fSYS/64 111: fINT=fSYS/128 T0E 3 Defines the TMR active edge of timer/event counter (0=active on low to high; 1=active on high to low) T0ON 4 Enable/disable timer counting (0=disabled; 1=enabled) ¾ 5 Unused bit, read as ²0² 6 7 Defines the operating mode T0M1, T0M0= 01= Event count mode (External clock) 10= Timer mode (Internal clock) 11= Pulse Width measurement mode (External clock) 00= Unused T0M0 T0M1 TMR0C Register Label (TMR1C) Bits ¾ 0~2 Function Unused bit, read as ²0² T1E 3 Defines the TMR1 active edge of the timer/event counter (0= active on low to high; 1= active on high to low) T1ON 4 Enable/disable timer counting (0= disabled; 1= enabled) T1S 5 Defines the TMR1 internal clock source (0=fSYS/4; 1=32768Hz) 6 7 Defines the operating mode T1M1, T1M0= 01= Event count mode (External clock) 10= Timer mode (Internal clock) 11= Pulse Width measurement mode (External clock) 00= Unused T1M0 T1M1 TMR1C Register Rev. 1.40 18 September 21, 2004 HT46R64/HT46C64 register must write ²1². The input source also depends on the control register. If the control register bit is ²1², the input will read the pad state. If the control register bit is ²0², the contents of the latches will move to the internal bus. The latter is possible in the ²read-modify-write² instruction. tions. Only one PFD (PFD0 or PFD1) can be applied to PA3 by options. If PA3 is set as PFD output, there are two types of selections; One is PFD0 as the PFD output, the other is PFD1 as the PFD output. PFD0, PFD1 are the timer overflow signals of the Timer/Event Counter 0, Timer/Event Counter 1 respectively. No matter what the operation mode is, writing a 0 to ET0I or ET1I disables the related interrupt service. When the PFD function is selected, executing ²SET [PA].3² instruction to enable PFD output and executing ²CLR [PA].3² instruction to disable PFD output. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H and 19H. After a chip reset, these input/output lines remain at high levels or floating state (depending on pull-high options). Each bit of these input/output latches can be set or cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H or 18H) instructions. In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the timer/event counter is turn on, data written to the timer/event counter is kept only in the timer/event counter preload register. The timer/event counter still continues its operation until an overflow occurs. Some instructions first input data and then follow the output operations. For example, ²SET [m].i², ²CLR [m].i², ²CPL [m]², ²CPLA [m]² read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. When the timer/event counter (reading TMR0/TMR1) is read, the clock is blocked to avoid errors, as this may results in a counting error. Blocking of the clock should be taken into account by the programmer. It is strongly recommended to load a desired value into the TMR0/TMR1 register first, before turning on the related timer/event counter, for proper operation since the initial value of TMR0/TMR1 is unknown. Due to the timer/event counter scheme, the programmer should pay special attention on the instruction to enable then disable the timer for the first time, whenever there is a need to use the timer/event counter function, to avoid unpredictable result. After this procedure, the timer/event function can be operated normally. Each line of port A has the capability of waking-up the device. Each I/O port has a pull-high option. Once the pull-high option is selected, the I/O port has a pull-high resistor, otherwise, there¢s none. Take note that a non-pull-high I/O port operating in input mode will cause a floating state. The PA3 is pin-shared with the PFD signal. If the PFD option is selected, the output signal in output mode of PA3 will be the PFD signal generated by timer/event counter overflow signal. The input mode always retain its original functions. Once the PFD option is selected, the PFD output signal is controlled by PA3 data register only. Writing ²1² to PA3 data register will enable the PFD output function and writing 0 will force the PA3 to remain at ²0². The I/O functions of PA3 are shown below. The bit0~bit2 of the TMR0C can be used to define the pre-scaling stages of the internal clock sources of timer/event counter 0. The definitions are as shown. The overflow signal of timer/event counter can be used to generate the PFD signal. The timer prescaler is also used as the PWM counter. I/O I/P Mode (Normal) Input/Output Ports There are 24 bidirectional input/output lines in the microcontroller, labeled as PA, PB and PD, which are mapped to the data memory of [12H], [14H] and [18H] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction ²MOV A,[m]² (m=12H, 14H or 18H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. PA3 Note: I/P (PFD) O/P (PFD) Logical Output Logical Input PFD (Timer on) The PFD frequency is the timer/event counter overflow frequency divided by 2. The PA0, PA1, PA3, PD4, PD5, PD6 and PD7 are pin-shared with BZ, BZ, PFD, INT0, INT1, TMR0 and TMR1 pins respectively. The PA0 and PA1 are pin-shared with BZ and BZ signal, respectively. If the BZ/BZ option is selected, the output signal in output mode of PA0/PA1 will be the buzzer signal generated by multi-function timer. The input mode always remain in its original function. Once the BZ/BZ option is selected, the buzzer output signal are controlled by the PA0, PA1 data register only. Each I/O line has its own control register (PAC, PBC, PDC) to control the input/output configuration. With this control register, CMOS output or Schmitt Trigger input with or without pull-high resistor structures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control Rev. 1.40 Logical Input O/P (Normal) 19 September 21, 2004 HT46R64/HT46C64 V C o n tr o l B it W r ite C o n tr o l R e g is te r P U Q D D a ta B u s C K D D P A 0 P A 1 P A 2 P A 3 P A 4 P B 0 P D 0 P D 1 P D 2 P D 3 P D 4 P D 5 P D 6 P D 7 Q S C h ip R e s e t R e a d C o n tr o l R e g is te r D a ta B it Q D Q C K W r ite D a ta R e g is te r S M P A 0 /P A 1 /P A 3 /P D 0 /P D 1 /P D 2 /P D 3 B Z /B Z /P F D /P W M 0 /P W M 1 /P W M 2 /P W M 3 M R e a d D a ta R e g is te r U T 0 T 1 R 0 R 1 fo fo fo fo r P r P r P r P D 4 D 5 D 6 D 7 o n o n o n o n /P F D ~ P A 7 /A N 0 ~ P B 7 /A N 7 /P W M 0 /P W M 1 /P W M 2 /P W M 3 /IN T 0 /IN T 1 /T M R 0 /T M R 1 X P F D E N (P A 3 ) X S y s te m W a k e -u p ( P A o n ly ) IN IN T M T M U /B Z /B Z O P 0 ~ O P 7 ly ly ly ly Input/Output Ports The I/O function of PA0/PA1 are shown below. PA0 I/O I I O O O O O O O O PA1 I/O I O I PA0 Mode X X C B B C B B B B PA1 Mode X C X X X C C C B B PA0 Data X X D 0 PA1 Data X D X X X D1 D D X X PA0 Pad Status I I D 0 B D0 0 0 B PA1 Pad Status I D I I D1 D D 0 B Note: I I I It is recommended that unused or not bonded out I/O lines should be set as output pins by software instruction to avoid consuming power under input floating state. O O O O O 1 D0 0 1 B 0 The definitions of PFD control signal and PFD output frequency are listed in the following table. Timer PA3 Data PA3 Pad Timer Preload Register State Value 1 ²I² input; ²O² output ²D, D0, D1² Data ²B² buzzer option, BZ or BZ ²X² don¢t care ²C² CMOS output I/O Mode PD0 PD1 PD2 PD3 Rev. 1.40 I/P O/P (Normal) (Normal) Logical Input Logical Output OFF X 0 0 X OFF X 1 U X ON N 0 0 X ON N 1 PFD fTMR/[2´(M-N)] Note: The PB can also be used as A/D converter inputs. The A/D function will be described later. There is a PWM function shared with PD0/PD1/PD2/PD3. If the PWM function is enabled, the PWM0/PWM1/PWM2/PWM3 s ig n a l w i l l appear on P D 0/ P D 1 / P D 2 / P D 3 ( i f PD0/PD1/PD2/PD3 is operating in output mode). Writing ²1² to PD0~PD3 data register will enable the PWM output function and writing ²0² will force the PD0~PD3 to remain at ²0². The I/O functions of PD0/PD1/PD2/PD3 are as shown. I/P (PWM) O/P (PWM) Logical Input PWM0 PWM1 PWM2 PWM3 PFD Frequency ²X² stands for unused ²U² stands for unknown ²M² is ²256² for PFD0 or ²65536² for PFD1 ²N² is preload value for timer/event counter ²fTMR² is input clock frequency for timer/event counter PWM The microcontroller provides 4 channels (6+2)/(7+1) (dependent on options) bits PWM output shared with PD0/PD1/PD2/PD3. The PWM channels have their data registers denoted as PWM0 (1AH), PWM1 (1BH), PWM2 (1CH) and PWM3 (1DH). The frequency source of the PWM counter comes from fSYS. The PWM registers are four 8-bit registers. The waveforms of PWM outputs are as shown. Once the PD0/PD1/PD2/PD3 are selected as the PWM outputs and the output function of PD0/PD1/PD2/PD3 are enabled (PDC.0/PDC.1/ PDC.2/PDC.3=²0²), writing ²1² to PD0/PD1/PD2/PD3 20 September 21, 2004 HT46R64/HT46C64 data register will enable the PWM output function and writing ²0² will force the PD0/PD1/PD2/PD3 to stay at ²0². A (7+1) bits mode PWM cycle is divided into two modulation cycles (modulation cycle0~modulation cycle 1). Each modulation cycle has 128 PWM input clock period. A (6+2) bits mode PWM cycle is divided into four modulation cycles (modulation cycle 0~modulation cycle 3). Each modulation cycle has 64 PWM input clock period. In a (6+2) bit PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM register is denoted by DC which is the value of PWM.7~PWM.2. In a (7+1) bits PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM register is denoted by DC which is the value of PWM.7~PWM.1. The group 2 is denoted by AC which is the value of PWM.0. In a (7+1) bits mode PWM cycle, the duty cycle of each modulation cycle is shown in the table. The group 2 is denoted by AC which is the value of PWM.1~PWM.0. Parameter In a (6+2) bits mode PWM cycle, the duty cycle of each modulation cycle is shown in the table. Parameter AC (0~3) fS i³AC Duty Cycle i<AC DC+1 128 i³AC DC 128 Modulation cycle i (i=0~1) Duty Cycle DC+1 64 DC 64 i<AC Modulation cycle i (i=0~3) AC (0~1) The modulation frequency, cycle frequency and cycle duty of the PWM output signal are summarized in the following table. /2 Y S [P W M ] = 1 0 0 P W M 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4 2 6 /6 4 2 6 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4 2 6 /6 4 2 6 /6 4 2 5 /6 4 2 6 /6 4 [P W M ] = 1 0 1 P W M [P W M ] = 1 0 2 P W M [P W M ] = 1 0 3 P W M 2 6 /6 4 P W M m o d u la tio n p e r io d : 6 4 /fS M o d u la tio n c y c le 0 Y S M o d u la tio n c y c le 1 P W M M o d u la tio n c y c le 2 c y c le : 2 5 6 /fS M o d u la tio n c y c le 3 M o d u la tio n c y c le 0 Y S (6+2) PWM Mode fS Y S /2 [P W M ] = 1 0 0 P W M 5 0 /1 2 8 5 0 /1 2 8 5 0 /1 2 8 5 1 /1 2 8 5 0 /1 2 8 5 1 /1 2 8 5 1 /1 2 8 5 1 /1 2 8 5 1 /1 2 8 5 1 /1 2 8 5 2 /1 2 8 [P W M ] = 1 0 1 P W M [P W M ] = 1 0 2 P W M [P W M ] = 1 0 3 P W M 5 2 /1 2 8 P W M m o d u la tio n p e r io d : 1 2 8 /fS Y S M o d u la tio n c y c le 0 M o d u la tio n c y c le 1 P W M c y c le : 2 5 6 /fS M o d u la tio n c y c le 0 Y S (7+1) PWM Mode Rev. 1.40 21 September 21, 2004 HT46R64/HT46C64 PWM Modulation Frequency The bit 7 of the ACSR is used for testing purposes only. It can not be used by the users. PWM Cycle PWM Cycle Frequency Duty fSYS/64 for (6+2) bits mode fSYS/128 for (7+1) bits mode fSYS/256 The bit1 and bit0 of the ACSR are used to select A/D clock sources. [PWM]/256 Label Bits (ACSR) A/D Converter The 8 channels and 10 bits resolution A/D (9 bits accuracy) converter are implemented in this microcontroller. The reference voltage is VDD. The A/D converter contains 4 special registers which are; ADRL (24H), ADRH (25H), ADCR (26H) and ACSR (27H). The ADRH and ADRL are A/D result register higher-order byte and lower-order byte and are read-only. After the A/D conversion is completed, the ADRH and ADRL should be read to get the conversion result data. The ADCR is an A/D converter control register, which defines the A/D channel number, analog channel select, start A/D conversion control bit and the end of A/D conversion flag. If the users want to start an A/D conversion. Define PB configuration, select the converted analog channel, and give START bit a rising edge and falling edge (0®1®0). At the end of A/D conversion, the EOCB bit is cleared and an A/D converter interrupt occurs. The ACSR is A/D clock setting register, which is used to select the A/D clock source. ADCS0 ADCS1 ¾ 0 1 Function Selects the A/D converter clock source 00= system clock/2 01= system clock/8 10= system clock/32 11= undefined 2~6 Unused bit, read as ²0² TEST 7 For test mode used only ACSR Register Label Bits (ADCR) The A/D converter control register is used to control the A/D converter. The bit2~bit0 of the ADCR are used to select an analog input channel. There are a total of eight channels to select. The bit5~bit3 of the ADCR are used to set PB configurations. PB can be an analog input or as digital I/O line decided by these 3 bits. Once a PB line is selected as an analog input, the I/O functions and pull-high resistor of this I/O line are disabled and the A/D converter circuit is powered-on. The EOCB bit (bit6 of the ADCR) is end of A/D conversion flag. Check this bit to know when A/D conversion is completed. The START bit of the ADCR is used to begin the conversion of the A/D converter. Giving START bit a rising edge and falling edge means that the A/D conversion has started. In order to ensure that the A/D conversion is completed, the START should remain at ²0² until the EOCB is cleared to ²0² (end of A/D conversion). Function ACS0 ACS1 ACS2 0 1 2 Defines the analog channel select. PCR0 PCR1 PCR2 3 4 5 Defines the port B configuration select. If PCR0, PCR1 and PCR2 are all zero, the ADC circuit is power off to reduce power consumption EOCB 6 Provides response at the end of the A/D conversion. (0= end of A/D conversion) START 7 Starts the A/D conversion. (0®1®0= start; 0®1= reset A/D converter) ADCR Register ACS2 ACS1 ACS0 Analog Channel 0 0 0 A0 0 0 1 A1 0 1 0 A2 0 1 1 A3 1 0 0 A4 1 0 1 A5 1 1 0 A6 1 1 1 A7 Analog Input Channel Selection PCR2 PCR1 PCR0 7 6 5 4 3 2 1 0 0 0 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 0 0 1 PB7 PB6 PB5 PB4 PB3 PB2 PB1 A0 0 1 0 PB7 PB6 PB5 PB4 PB3 PB2 A1 A0 0 1 1 PB7 PB6 PB5 PB4 PB3 A2 A1 A0 1 0 0 PB7 PB6 PB5 PB4 A3 A2 A1 A0 1 0 1 PB7 PB6 PB5 A4 A3 A2 A1 A0 1 1 0 PB7 PB6 A5 A4 A3 A2 A1 A0 1 1 1 A7 A6 A5 A4 A3 A2 A1 A0 Port B Configuration Rev. 1.40 22 September 21, 2004 HT46R64/HT46C64 When the A/D conversion is completed, the A/D interrupt request flag is set. The EOCB bit is set to ²1² when the START bit is set from ²0² to ²1². Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADRL D1 D0 ¾ ¾ ¾ ¾ ¾ ¾ ADRH D9 D8 D7 D6 D5 D4 D3 D2 Note: D0~D9 is A/D conversion result data bit LSB~MSB. The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using EOCB Polling Method to detect end of conversion clr INTC0.7 ; disable A/D interrupt in interrupt control register mov a,00100000B mov ADCR,a ; setup ADCR register to configure Port PB0~PB3 as A/D inputs and select ; AN0 to be connected to the A/D converter mov a,00000001B mov ACSR,a ; setup the ACSR register to select fSYS/8 as the A/D clock Start_conversion: clr ADCR.7 set ADCR.7 clr ADCR.7 Polling_EOC: sz ADCR.6 jmp polling_EOC mov a,ADRH mov adrh_buffer,a mov a,ADRL mov adrl_buffer,a : : jmp start_conversion ; reset A/D ; start A/D ; poll the ADCR register EOCB bit to detect end of A/D conversion ; continue polling ; read conversion result from the high byte ADRH register ; save result to user defined register ; read conversion result from the low byte ADRL register ; save result to user defined register ; start next A/D conversion Example: using Interrupt method to detect end of conversion set INTC0.0 ; interrupt global enable set INTC0.7 ; enable A/D interrupt in interrupt control register mov a,00100000B mov ADCR,a ; setup ADCR register to configure Port PB0~PB3 as A/D inputs and select ; AN0 to be connected to the A/D converter mov a,00000001B mov ACSR,a ; setup the ACSR register to select fSYS/8 as the A/D clock start_conversion: clr ADCR.7 set ADCR.7 clr ADCR.7 : : ; interrupt service routine EOC_service routine: mov a_buffer,a mov a,ADRH mov adrh_buffer,a mov a,ADRL mov adrl_buffer,a clr ADCR.7 set ADCR.7 clr ADCR.7 mov a,a_buffer reti Rev. 1.40 ; reset A/D ; start A/D ; save ACC to user defined register ; read conversion result from the high byte ADRH register ; save result to user defined register ; read conversion result from the low byte ADRL register ; save result to user defined register ; reset A/D ; start A/D ; restore ACC from temporary storage 23 September 21, 2004 HT46R64/HT46C64 M in im u m o n e in s tr u c tio n c y c le n e e d e d S T A R T E O C B A /D s a m p lin g tim e 3 2 tA D P C R 2 ~ P C R 0 0 0 0 B A /D s a m p lin g tim e 3 2 tA D 1 0 0 B 1 0 0 B 0 0 0 B 1 . P B p o rt s e tu p a s I/O s 2 . A /D c o n v e r te r is p o w e r e d o ff to r e d u c e p o w e r c o n s u m p tio n A C S 2 ~ A C S 0 0 0 0 B P o w e r-o n R e s e t 0 1 0 B 0 0 0 B S ta rt o f A /D c o n v e r s io n S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n 1 : D e fin e P B c o n fig u r a tio n 2 : S e le c t a n a lo g c h a n n e l 7 6 tA D A /D c o n v e r s io n tim e N o te : A /D c lo c k m u s t b e fS Y S /2 , fS Y S /8 o r fS Y S d o n 't c a r e E n d o f A /D c o n v e r s io n 7 6 tA D A /D c o n v e r s io n tim e /3 2 A/D Conversion Timing LCD Display Memory LCD Driver Output The device provides an area of embedded data memory for LCD display. This area is located from 40H to 60H of the RAM at Bank 1. Bank pointer (BP; located at 04H of the RAM) is the switch between the RAM and the LCD display memory. When the BP is set as ²1², any data written into 40H~60H will effect the LCD display. When the BP is cleared to ²0² or ²1², any data written into 40H~60H means to access the general purpose data memory. The LCD display memory can be read and written to only by indirect addressing mode using MP1. When data is written into the display data area, it is automatically read by the LCD driver which then generates the corresponding LCD driving signals. To turn the display on or off, a ²1² or a ²0² is written to the corresponding bit of the display memory, respectively. The figure illustrates the mapping between the display memory and LCD pattern for the device. The output number of the device LCD driver can be 33´2 or 33´3 or 32´4 by option (i.e., 1/2 duty, 1/3 duty or 1/4 duty). The bias type LCD driver can be ²R² type or ²C² type. If the ²R² bias type is selected, no external capacitor is required. If the ²C² bias type is selected, a capacitor mounted between C1 and C2 pins is needed. The LCD driver bias voltage can be 1/2 bias or 1/3 bias by option. If 1/2 bias is selected, a capacitor mounted between V2 pin and ground is required. If 1/3 bias is selected, two capacitors are needed for V1 and V2 pins. Refer to application diagram. C O M 4 0 H 4 1 H 4 2 H 4 3 H 5 E H 5 F H 6 0 H 0 Option Condition Low Bias Current High Bias Current (Typ.) (Typ.) B it 1/3 Bias (VLCD/4.5)´15mA (VLCD/4.5)´45mA 1/2 Bias (VLCD/3)´15mA (VLCD/3)´45mA 0 1 1 2 2 3 3 S E G M E N T 0 1 2 3 3 0 3 1 3 2 Display Memory Rev. 1.40 24 September 21, 2004 HT46R64/HT46C64 D u r in g a R e s e t P u ls e C O M 0 ,C O M 1 ,C O M 2 A ll L C D d r iv e r o u tp u ts N o r m a l O p e r a tio n M o d e * * C O M 0 C O M 1 C O M 2 * L C D s e g m e n ts O N C O M 0 ,1 , 2 s id e s a r e u n lig h te d O n ly L C D s e g m e n ts O N C O M 0 s id e a r e lig h te d O n ly L C D s e g m e n ts O N C O M 1 s id e a r e lig h te d O n ly L C D s e g m e n ts O N C O M 2 s id e a r e lig h te d L C D s e g m e n ts O N C O M 0 ,1 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 0 , 2 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 1 , 2 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 0 ,1 , 2 s id e s a r e lig h te d H A L T M o d e * V L 1 /2 V S V L 1 /2 V S C D V L 1 /2 V S V L 1 /2 V S V L 1 /2 V S V L 1 /2 V S V L 1 /2 V S V L 1 /2 V S V L 1 /2 V S V L 1 /2 V S V L 1 /2 V S V L 1 /2 V S V L 1 /2 V S C D V L 1 /2 V S V L 1 /2 V S C O M 0 , C O M 1 , C O M 2 A ll lc d d r iv e r o u tp u ts V L C D S C D V L C D S V L C D S C D V L C D S C D V L C D S C D V L S C D V L S C D V L S C D V L S C D V L S C D V L S C D V L S C D V L S C D C D C D C D C D C D C D C D C D V L C D S C D S V L C D N o te : " * " O m it th e C O M 2 s ig n a l, if th e 1 /2 d u ty L C D is u s e d . LCD Driver Output (1/3 Duty, 1/2 Bias, R/C Type) LCD Segments as Logical Output Low Voltage Reset/Detector Functions The SEG0~SEG23 also can be optioned as logical output, once an LCD segment is optioned as a logical output, the content of bit0 of the related segment address in LCD RAM will appear on the segment. There is a low voltage detector (LVD) and a low voltage reset circuit (LVR) implemented in the microcontroller. These two functions can be enabled/disabled by options. Once the LVD options is enabled, the user can use the RTCC.3 to enable/disable (1/0) the LVD circuit and read the LVD detector status (0/1) from RTCC.5; otherwise, the LVD function is disabled. SEG0~SEG7 is together byte optioned as logical output, SEG8~SEG15 are bit individually optioned as logical outputs. LCD Type R Type LCD Bias 1/2 Type bias VMAX Rev. 1.40 1/3 bias The LVR has the same effect or function with the external RES signal which performs chip reset. During HALT state, LVR is disabled both LVR and LVD are disabled. C Type 1/2 bias 1/3 bias The microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~VLVR, such as changing a battery, the LVR will automatically reset the device internally. 3 If V DD >V LCD , then If VDD > VLCD, then 2 VMAX connect to VDD, V connect to VDD, else VMAX connect to MAX else VMAX connect to VLCD V1 25 September 21, 2004 HT46R64/HT46C64 V A V B V C C O M 0 V S S V A V B V C C O M 1 V S S V A V B V C C O M 2 V S S V A V B C O M 3 V C V S S V A V B V C L C D s e g m e n ts O N C O M 2 s id e lig h te d V S S N o te : 1 /4 d u ty , 1 /3 b ia s , C ty p e : " V A " 3 /2 V L C D , " V B " V L C D , " V C " 1 /2 V L C D 1 /4 d u ty , 1 /3 b ia s , R ty p e : "V A " V L C D , "V B " 2 /3 V L C D , "V C " 1 /3 V L C D LCD Driver Output The relationship between VDD and VLVR is shown below. The LVR includes the following specifications: · The low voltage (0.9V~VLVR) has to remain in their V D D 5 .5 V original state to exceed 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and do not perform a reset function. V O P R 5 .5 V · The LVR uses the ²OR² function with the external RES V signal to perform chip reset. L V R 3 .0 V 2 .2 V 0 .9 V Note: VOPR is the voltage range for proper chip operation at 4MHz system clock. Rev. 1.40 26 September 21, 2004 HT46R64/HT46C64 V D D 5 .5 V V L V R L V R D e te c t V o lta g e 0 .9 V 0 V R e s e t S ig n a l N o r m a l O p e r a tio n R e s e t *1 R e s e t *2 Low Voltage Reset Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: Since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay, the device enters the reset mode. The RTCC register definitions are listed below. Register RTCC (09H) Bit No. Label Read/Write Reset Function 0~2 RT0~RT2 R/W 1 8 to 1 multiplexer control inputs to select the real clock prescaler output 3 LVDC R/W 0 LVD enable/disable (1/0) 4 QOSC R/W 0 32768Hz OSC quick start-up oscillating 0/1: quickly/slowly start 5 LVDO R 0 LVD detection output (1/0) 1: low voltage detected 6~7 ¾ ¾ ¾ Unused bit, read as ²0² Options The following shows the options in the device. All these options should be defined in order to ensure proper functioning system. Options OSC type selection. This option is to decide if an RC or crystal or 32768Hz crystal oscillator is chosen as system clock. WDT, RTC and time base clock source selection. There are three types of selections: system clock/4 or RTC OSC or WDT OSC. WDT enable/disable selection. WDT can be enabled or disabled by option. WDT time-out period selection. There are four types of selection: WDT clock source divided by 212/fS~213/fS, 213/fS~214/fS, 214/fS~215/fS or 215/fS~216/fS. CLR WDT times selection. This option defines the method to clear the WDT by instruction. ²One time² means that the ²CLR WDT² can clear the WDT. ²Two times² means only if both of the ²CLR WDT1² and ²CLR WDT2² have been executed, the WDT can be cleared. Rev. 1.40 27 September 21, 2004 HT46R64/HT46C64 Options Time Base time-out period selection. The Time Base time-out period ranges from 212/fS to 215/fS ²fS² means the clock source selected by options. Buzzer output frequency selection. There are eight types of frequency signals for buzzer output: fS/22~fS/29. ²fS² means the clock source selected by options. Wake-up selection. This option defines the wake-up capability. External I/O pins (PA only) all have the capability to wake-up the chip from a HALT by a falling edge (bit option). Pull-high selection. This option is to decide whether the pull-high resistance is visible or not in the input mode of the I/O ports. PA, PB and PD can be independently selected (bit option). I/O pins share with other function selections. PA0/BZ, PA1/BZ: PA0 and PA1 can be set as I/O pins or buzzer outputs. LCD common selection. There are three types of selections: 2 common (1/2 duty) or 3 common (1/3 duty) or 4 common (1/4 duty). If the 4 common is selected, the segment output pin ²SEG40² will be set as a common output. LCD bias power supply selection. There are two types of selections: 1/2 bias or 1/3 bias LCD bias type selection. This option is to determine what kind of bias is selected, R type or C type. LCD driver clock frequency selection. There are seven types of frequency signals for the LCD driver circuits: fS/22~fS/28. ²fS² stands for the clock source selection by options. LCD ON/OFF at HALT selection LCD Segments as logical output selection, (byte, bit, bit, bit, bit, bit, bit, bit, bit option) [SEG0~SEG7], SEG8, SEG9, SEG10, SEG11, SEG12, SEG13, SEG14 or SEG15 LVR selection. LVR has enable or disable options LVD selection. LVD has enable or disable options PFD selection. If PA3 is set as PFD output, there are two types of selections; One is PFD0 as the PFD output, the other is PFD1 as the PFD output. PFD0, PFD1 are the timer overflow signals of the Timer/Event Counter 0, Timer/Event Counter 1 respectively. PWM selection: (7+1) or (6+2) mode PD0: level output or PWM0 output PD1: level output or PWM1 output PD2: level output or PWM2 output PD3: level output or PWM3 output INT0 or INT1 trigger edge selection: disable; high to low; low to high; low to high or high to low LCD bias current selection: low/high driving current (for R type only). Rev. 1.40 28 September 21, 2004 HT46R64/HT46C64 Application Circuits V D D 0 .0 1 m F * C O M 0 ~ C O M 2 C O M 3 /S E G 3 2 S E G 0 ~ S E G 3 1 V D D 1 0 0 k W 0 .1 m F R E S L C D P A N E L V L C D 1 0 k W L C D P o w e r S u p p ly V M A X 0 .1 m F * V S S C 1 0 .1 m F V C 2 O S C C ir c u it O S C 1 D D 4 7 0 p F V 1 O S C 2 0 .1 m F R O S C S e e r ig h t s id e V 2 3 2 7 6 8 H z O S C 1 fS C 1 0 .1 m F Y S /4 O S C 2 O S C 1 O S C 3 1 0 p F O S C 4 P P P D 4 /IN T 0 P ~ P P D 5 /IN T 1 P D 6 /T M R 0 P A 0 /B P A 1 /B P A A 3 /P F A 4 ~ P A B 0 /A N B 7 /A N C 2 Z Z R 1 2 C ry s ta l S y s te m F o r th e v a lu e s , s e e ta b le b e lo w O s c illa to r O S C 2 D 7 O S C 1 0 7 P D 0 /P W M 0 P D 3 /P W M 3 O S C 2 ~ P D 7 /T M R 1 R C S y s te m O s c illa to r 3 0 k W < R O S C < 7 5 0 k W H T 4 6 R 6 4 /H T 4 6 C 6 4 O S C 3 2 O s O S u n 7 6 8 H z C ry s ta l S y s te m c illa to r C 1 a n d O S C 2 le ft c o n n e c te d C ir c u it The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only) C1, C2 R1 4MHz Crystal Crystal or Resonator 0pF 10kW 4MHz Resonator 10pF 12kW 3.58MHz Crystal 0pF 10kW 3.58MHz Resonator 25pF 10kW 2MHz Crystal & Resonator 25pF 10kW 1MHz Crystal 35pF 27kW 480kHz Resonator 300pF 9.1kW 455kHz Resonator 300pF 10kW 429kHz Resonator 300pF 10kW The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed. Note: The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. ²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. ²VMAX² connect to VDD or VLCD or V1 refer to the table. LCD Type LCD bias type VMAX Rev. 1.40 R Type 1/2 bias 1/3 bias C Type 1/2 bias If VDD>VLCD, then VMAX connect to VDD, else VMAX connect to VLCD 29 1/3 bias If VDD > 3/2VLCD, then VMAX connect to VDD, else VMAX connect to V1 September 21, 2004 HT46R64/HT46C64 Instruction Set Summary Description Instruction Cycle Flag Affected Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Rev. 1.40 30 September 21, 2004 HT46R64/HT46C64 Instruction Cycle Flag Affected Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Mnemonic Description Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Ö: Flag is affected -: Flag is not affected (1) : If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). (2) : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. (3) (1) : (4) Rev. 1.40 and (2) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. 31 September 21, 2004 HT46R64/HT46C64 Instruction Definition ADC A,[m] Add data memory and carry to the accumulator Description The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. Operation ACC ¬ ACC+[m]+C Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö ADCM A,[m] Add the accumulator and carry to data memory Description The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. Operation [m] ¬ ACC+[m]+C Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö ADD A,[m] Add data memory to the accumulator Description The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. Operation ACC ¬ ACC+[m] Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö ADD A,x Add immediate data to the accumulator Description The contents of the accumulator and the specified data are added, leaving the result in the accumulator. Operation ACC ¬ ACC+x Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö ADDM A,[m] Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ¬ ACC+[m] Affected flag(s) Rev. 1.40 TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö 32 September 21, 2004 HT46R64/HT46C64 AND A,[m] Logical AND accumulator with data memory Description Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. Operation ACC ¬ ACC ²AND² [m] Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ AND A,x Logical AND immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. Operation ACC ¬ ACC ²AND² x Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ ANDM A,[m] Logical AND data memory with the accumulator Description Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. Operation [m] ¬ ACC ²AND² [m] Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ CALL addr Subroutine call Description The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Operation Stack ¬ PC+1 PC ¬ addr Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] ¬ 00H Affected flag(s) Rev. 1.40 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ 33 September 21, 2004 HT46R64/HT46C64 CLR [m].i Clear bit of data memory Description The bit i of the specified data memory is cleared to 0. Operation [m].i ¬ 0 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ CLR WDT Clear Watchdog Timer Description The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. Operation WDT ¬ 00H PDF and TO ¬ 0 Affected flag(s) TO PDF OV Z AC C 0 0 ¾ ¾ ¾ ¾ CLR WDT1 Preclear Watchdog Timer Description Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. Operation WDT ¬ 00H* PDF and TO ¬ 0* Affected flag(s) TO PDF OV Z AC C 0* 0* ¾ ¾ ¾ ¾ CLR WDT2 Preclear Watchdog Timer Description Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. Operation WDT ¬ 00H* PDF and TO ¬ 0* Affected flag(s) TO PDF OV Z AC C 0* 0* ¾ ¾ ¾ ¾ CPL [m] Complement data memory Description Each bit of the specified data memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] ¬ [m] Affected flag(s) Rev. 1.40 TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ 34 September 21, 2004 HT46R64/HT46C64 CPLA [m] Complement data memory and place result in the accumulator Description Each bit of the specified data memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. Operation ACC ¬ [m] Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ DAA [m] Decimal-Adjust accumulator for addition Description The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. Operation If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö DEC [m] Decrement data memory Description Data in the specified data memory is decremented by 1. Operation [m] ¬ [m]-1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ DECA [m] Decrement data memory and place result in the accumulator Description Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. Operation ACC ¬ [m]-1 Affected flag(s) Rev. 1.40 TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ 35 September 21, 2004 HT46R64/HT46C64 HALT Enter power down mode Description This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. Operation PC ¬ PC+1 PDF ¬ 1 TO ¬ 0 Affected flag(s) TO PDF OV Z AC C 0 1 ¾ ¾ ¾ ¾ INC [m] Increment data memory Description Data in the specified data memory is incremented by 1 Operation [m] ¬ [m]+1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ INCA [m] Increment data memory and place result in the accumulator Description Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. Operation ACC ¬ [m]+1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ JMP addr Directly jump Description The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Operation PC ¬addr Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ MOV A,[m] Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC ¬ [m] Affected flag(s) Rev. 1.40 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ 36 September 21, 2004 HT46R64/HT46C64 MOV A,x Move immediate data to the accumulator Description The 8-bit data specified by the code is loaded into the accumulator. Operation ACC ¬ x Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ MOV [m],A Move the accumulator to data memory Description The contents of the accumulator are copied to the specified data memory (one of the data memories). Operation [m] ¬ACC Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ NOP No operation Description No operation is performed. Execution continues with the next instruction. Operation PC ¬ PC+1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ OR A,[m] Logical OR accumulator with data memory Description Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. Operation ACC ¬ ACC ²OR² [m] Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ OR A,x Logical OR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. Operation ACC ¬ ACC ²OR² x Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ ORM A,[m] Logical OR data memory with the accumulator Description Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ¬ACC ²OR² [m] Affected flag(s) Rev. 1.40 TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ 37 September 21, 2004 HT46R64/HT46C64 RET Return from subroutine Description The program counter is restored from the stack. This is a 2-cycle instruction. Operation PC ¬ Stack Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ RET A,x Return and place immediate data in the accumulator Description The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Operation PC ¬ Stack ACC ¬ x Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ RETI Return from interrupt Description The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. Operation PC ¬ Stack EMI ¬ 1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ RL [m] Rotate data memory left Description The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. Operation [m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 ¬ [m].7 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ RLA [m] Rotate data memory left and place result in the accumulator Description Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 ¬ [m].7 Affected flag(s) Rev. 1.40 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ 38 September 21, 2004 HT46R64/HT46C64 RLC [m] Rotate data memory left through carry Description The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. Operation [m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 ¬ C C ¬ [m].7 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö RLCA [m] Rotate left through carry and place result in the accumulator Description Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. Operation ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 ¬ C C ¬ [m].7 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö RR [m] Rotate data memory right Description The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. Operation [m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 ¬ [m].0 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ RRA [m] Rotate right and place result in the accumulator Description Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 ¬ [m].0 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ RRC [m] Rotate data memory right through carry Description The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 ¬ C C ¬ [m].0 Affected flag(s) Rev. 1.40 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö 39 September 21, 2004 HT46R64/HT46C64 RRCA [m] Rotate right through carry and place result in the accumulator Description Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. Operation ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 ¬ C C ¬ [m].0 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö SBC A,[m] Subtract data memory and carry from the accumulator Description The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. Operation ACC ¬ ACC+[m]+C Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö SBCM A,[m] Subtract data memory and carry from the accumulator Description The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. Operation [m] ¬ ACC+[m]+C Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö SDZ [m] Skip if decrement data memory is 0 Description The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m]-1)=0, [m] ¬ ([m]-1) Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SDZA [m] Decrement data memory and place result in ACC, skip if 0 Description The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m]-1)=0, ACC ¬ ([m]-1) Affected flag(s) Rev. 1.40 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ 40 September 21, 2004 HT46R64/HT46C64 SET [m] Set data memory Description Each bit of the specified data memory is set to 1. Operation [m] ¬ FFH Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SET [m]. i Set bit of data memory Description Bit i of the specified data memory is set to 1. Operation [m].i ¬ 1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SIZ [m] Skip if increment data memory is 0 Description The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m]+1)=0, [m] ¬ ([m]+1) Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SIZA [m] Increment data memory and place result in ACC, skip if 0 Description The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m]+1)=0, ACC ¬ ([m]+1) Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SNZ [m].i Skip if bit i of the data memory is not 0 Description If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if [m].i¹0 Affected flag(s) Rev. 1.40 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ 41 September 21, 2004 HT46R64/HT46C64 SUB A,[m] Subtract data memory from the accumulator Description The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. Operation ACC ¬ ACC+[m]+1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö SUBM A,[m] Subtract data memory from the accumulator Description The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. Operation [m] ¬ ACC+[m]+1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö SUB A,x Subtract immediate data from the accumulator Description The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. Operation ACC ¬ ACC+x+1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö SWAP [m] Swap nibbles within the data memory Description The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. Operation [m].3~[m].0 « [m].7~[m].4 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SWAPA [m] Swap data memory and place result in the accumulator Description The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ¬ [m].7~[m].4 ACC.7~ACC.4 ¬ [m].3~[m].0 Affected flag(s) Rev. 1.40 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ 42 September 21, 2004 HT46R64/HT46C64 SZ [m] Skip if data memory is 0 Description If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if [m]=0 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SZA [m] Move data memory to ACC, skip if 0 Description The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if [m]=0 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SZ [m].i Skip if bit i of the data memory is 0 Description If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if [m].i=0 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ TABRDC [m] Move the ROM code (current page) to TBLH and data memory Description The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. Operation [m] ¬ ROM code (low byte) TBLH ¬ ROM code (high byte) Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ TABRDL [m] Move the ROM code (last page) to TBLH and data memory Description The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Operation [m] ¬ ROM code (low byte) TBLH ¬ ROM code (high byte) Affected flag(s) Rev. 1.40 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ 43 September 21, 2004 HT46R64/HT46C64 XOR A,[m] Logical XOR accumulator with data memory Description Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. Operation ACC ¬ ACC ²XOR² [m] Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ XORM A,[m] Logical XOR data memory with the accumulator Description Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. Operation [m] ¬ ACC ²XOR² [m] Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ XOR A,x Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ¬ ACC ²XOR² x Affected flag(s) Rev. 1.40 TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ 44 September 21, 2004 HT46R64/HT46C64 Package Information 56-pin SSOP (300mil) Outline Dimensions 2 9 5 6 B A 2 8 1 C C ' G H D Symbol Rev. 1.40 a F E Dimensions in mil Min. Nom. Max. A 395 ¾ 420 B 291 ¾ 299 C 8 ¾ 12 C¢ 720 ¾ 730 D 89 ¾ 99 E ¾ 25 ¾ F 4 ¾ 10 G 25 ¾ 35 H 4 ¾ 12 a 0° ¾ 8° 45 September 21, 2004 HT46R64/HT46C64 100-pin QFP (14´20) Outline Dimensions C H D 8 0 G 5 1 I 5 0 8 1 F A B E 3 1 1 0 0 K a J 1 Symbol Rev. 1.40 3 0 Dimensions in mm Min. Nom. Max. A 18.50 ¾ 19.20 B 13.90 ¾ 14.10 C 24.50 ¾ 25.20 D 19.90 ¾ 20.10 E ¾ 0.65 ¾ F ¾ 0.30 ¾ G 2.50 ¾ 3.10 H ¾ ¾ 3.40 I ¾ 0.10 ¾ J 1 ¾ 1.40 K 0.10 ¾ 0.20 a 0° ¾ 7° 46 September 21, 2004 HT46R64/HT46C64 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031 Tel: 0755-8346-5589 Fax: 0755-8346-5590 ISDN: 0755-8346-5591 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holmate Semiconductor, Inc. (North America Sales Office) 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright Ó 2004 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.40 47 September 21, 2004