SUTEX HV21816X Low charge injection 8-channel high voltage analog switch Datasheet

–
E
T
E
L
O
S
B
O
–
HV21716
HV21816
Low Charge Injection
8-Channel High Voltage Analog Switch
Ordering Information
Package Options
Operating
VPP
VPP – VNN
28-lead plastic
chip carrier
Die
40V to 80V
160V
HV21716PJ
HV21716X
80V to 150V
160V
HV21816PJ
HV21816X
Features
General Description
■ HVCMOS® technology for high performance
Not recommended for new designs. Please use HV20220 for
all new designs.
■ Low charge injection
This device is a low charge injection 8-channel high-voltage analog switch integrated circuit (IC) intended for use in applications
requiring high voltage switching controlled by low voltage control
signals, such as ultrasound imaging and printers. Input data is
shifted into an 8-bit shift register which can then be retained in an
8-bit latch. To reduce any possible clock feedthrough noise, Latch
Enable (LE) should be left high until all bits are clocked in. Using
HVCMOS technology, this switch combines high voltage bilateral
DMOS switches and low power CMOS logic to provide efficient
control of high voltage analog signals.
■ Very low quiescent power dissipation – 10µA
■ Output On-resistance typically 22 ohms
■ Low parasitic capacitances
■ DC to 10MHz analog signal frequency
■ -50dB typical output off isolation at 5MHz
■ CMOS logic circuitry for low power
■ Excellent noise immunity
■ On-chip shift register and latch logic circuitry
■ Flexible high voltage supplies
■ Surface mount package available
Absolute Maximum Ratings*
VDD logic power supply voltage
VPP - VNN supply voltage
-0.5V to +18V
174V
VPP positive high voltage supply
-0.5V to +160V
VNN negative high voltage supply
+0.5V to -160V
Logic input voltages
-0.5V to VDD +0.3V
Analog signal range
VNN to VPP
Peak analog signal current/channel
Storage temperature
Power dissipation
3.0A
-65°C to +150°C
1.2W
* Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability.
13-66
HV21716/HV21816
Electrical Characteristics
(over operating conditions, VPP = +80V, VNN = -80V, and VDD= 15V unless otherwise noted)
DC Characteristics
Characteristics
Sym
0°C
min
max
min
+25°C
typ
max
22
25
+70°C
min max
Units
Test Conditions
28
ohms
ISIG = 5mA
ISIG = 200mA
Small Signal Switch (ON)
RONS
24
Resistance
RONS
18
18
20
23
ohms
Small Signal Switch (ON)
Resistance Matching
∆RONS
20
5.0
20
20
%
Large Signal Switch (ON)
Resistance
RONL
13
22
Switch Off Leakage
Per Switch
ISOL
5.0
1.0
10
300
100
500
DC Offset Switch Off
DC Offset Switch On
ohms
VSIG = VPP -10V,
ISIG = 1.0A
15
µA
VSIG = VPP -10V
and VNN +10V
300
300
mV
RL = 100KΩ
500
mV
RL = 100KΩ
100
500
Pos. HV Supply Current
IPPQ
10
50
µA
Neg. HV Supply Current
INNQ
-10
-50
µA
Pos. HV Supply Current
IPPQ
10
50
µA
Neg. HV Supply Current
INNQ
-10
-50
3.0
2.0
Switch Output
Peak Current
Output Switch Frequency
3.0
2.0
50
fSW
ISW = 5mA
ALL SWS OFF
µA
ALL SWS ON
ISW = 5mA
A
VSIG ≤ 0.1% Duty Cycle
KHz
Duty Cycle = 50%
IPP Supply Current
IPP
4.0
3.5
5.0
5.5
mA
INN Supply Current
INN
4.0
3.5
5.0
5.5
mA
HV output switching
frequency = 50KHz
Logic Supply
Average Current
IDD
6.0
4.0
6.0
6.0
mA
fCLK = 3MHz
Logic Supply
Quiescent Current
IDDQ
10
10
10
µA
Data Out Source Current
ISOR
0.45
0.45
0.70
0.40
mA
VOUT = VDD - 0.7V
Data Out Sink Current
ISINK
0.45
0.45
0.70
0.40
mA
VOUT = 0.7V
–
E
T
E
L
O
S
B
O
–
13-67
13
13
HV21716/HV21816
AC Characteristics
Characteristics
0°C
Sym
min
Time to Turn Off VSIG*
+25°C
max
min
tSIG (OFF)
+70°C
typ
max
min
Units
Test Conditions
max
0
ns
Set Up Time Before LE Rises
tSD
150
150
150
ns
Time Width of LE
tWLE
150
150
150
ns
Clock Delay Time to Data Out
tDO
175
175
190
ns
Turn On Time
tON
3.0
3.0
3.0
µs
RL = 10KΩ
Turn Off Time
tOFF
Off Isolation
KO
Clock Freq
fCLK
Set Up Time Data to Clock
tSU
µs
RL = 10KΩ
-30
5.0
-30
-33
5.0
-30
dB
f = 5MHz,
1KΩ// 15pF load
-45
-45
-50
-45
dB
f = 5MHz,
50Ω load
5.0
15
5.0
5.0
15
5.0
MHz
8.0
20
ns
35
ns
-60
dB
f = 5MHz,
50Ω load
0V, 1MHz
tH
35
35
KCR
-60
-60
-70
Off Capacitance SW to GND
CSG(OFF)
5.0
17
5.0
12
17
5.0
17
pF
On Capacitance SW to GND
CSG(ON)
25
50
25
38
50
25
50
pF
Hold Time Data from Clock
Switch Crosstalk
Output Voltage Spike
50% duty cycle
fDATA = fCLK/2
+VSPK
150
–VSPK
150
0V, 1MHz
VPP = +80V,
mV
VNN = -80V,
RL = 50Ω
–
E
T
E
L
O
S
B
O
–
* Time required for analog signal to turn off before output switch turns off (critical timing).
Operating Conditions*
Device
Symbol
HV21716
VPP1, 3
HV21816
Value
X
X
80V to 150V
VNN1, 3
X
X
-10V to VPP -160V
VDD1, 3
X
X
10V to 15.5V
VIH
X
X
VDD -2.0V to VDD
40V to 80V
VIL
X
X
0V to 2.0V
VSIG2
X
X
VNN +10V to VPP -10
TA
X
X
0°C to 70°C
Notes:
1. Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last.
2. VSIG must be VNN ≤ VSIG ≤ VPP or floating during power up/down transistion.
3. Rise and fall times of power supplies, VDD, VPP, and VNN should not be less than 1.0msec.
13-68
HV21716/HV21816
Test Circuits
VPP –10
VPP –10V
VIN = 10 VP–P
@5MHz
ISOL
RL
10KΩ
VOUT
50Ω
NC
50Ω
VNN +10
+80V
VPP
VDD
–80V
VNN
GND
15V
+80V
VPP
VDD
–80V
VNN
GND
KCR = 20Log
15V
+80V
VPP
VDD
–80V
VNN
GND
VOUT
VIN
TON /TOFF
Crosstalk
Switch OFF Leakage
15V
+VSPK
VIN = 10 VP–P
@5MHz
VOUT
VOUT
–VSPK
50Ω
VOUT
RL
100KΩ
RL
1KΩ
+80V
VPP
VDD
–80V
VNN
GND
KO = 20Log
15V
+80V
VPP
VDD
–80V
VNN
GND
15V
RL
+80V
VPP
VDD
-80V
VNN
GND
15V
VOUT
VIN
DC Offset ON/OFF
OFF Isolation
Output Voltage Spike
–
E
T
E
L
O
S
Logic Timing Waveforms
B
O
–
DN–1
DN
DATA
IN
50%
LE
50%
DN+1
50%
13
50%
t WLE
t SD
50%
CLOCK
50%
t SU
th
t DO
DATA
OUT
50%
t OFF
V
OUT
(TYP)
OFF
t ON
90%
10%
ON
13-69
13
HV21716/HV21816
Logic Diagram
LEVEL
SHIFTERS
LATCHES
OUTPUT
SWITCHES
DIN
D
LE
SW0
CLK
D
LE
SW1
D
LE
SW2
D
LE
SW3
D
LE
SW4
D
LE
SW5
D
LE
SW6
D
LE
SW7
8 BIT
SHIFT
REGISTER
DOUT
VNN VPP
VDD
–
E
T
E
L
O
S
B
O
–
LE
Truth Table
D0
D1
D2
D3
D4
D5
D6
D7
LE SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7
L
L
OFF
H
L
ON
X
L
L
OFF
H
L
ON
X
L
L
OFF
H
L
ON
X
L
L
OFF
H
L
ON
X
L
L
OFF
H
L
ON
X
L
L
OFF
H
L
ON
X
L
L
OFF
H
L
ON
X
L
L
OFF
H
L
ON
X
H
HOLD PREVIOUS STATE
13-70
Notes:
1. The eight switches operate
independently.
2. Serial data is clocked in on the L→ H
transition CLK.
3. The switches go to a state retaining
their present condition at the rising
edge of LE. When LE is low the shift
register data flows through the latch.
4. DOUT is high when switch 7 is on.
5. Shift register clockng has no effect on
the switch states if LE is H.
–
E
T
E
L
– OBSO
HV21716/HV21816
Typical Performance Curves
RON vs. Ambient Temp TA
VDD = 15V & VPP/VNN = ±80V
40
RON vs. VPP/VNN
VDD = 15V
50
35
RON (ohms) @ 5mA
RON (ohms)
30
25
ISW = 5mA
20
15
10
40
30
TA = 125°C
TA = 85°C
20
TA = 25°C
TA = 0°C
TA = -45°C
5
0
-55 -25
10
VPP 0 20 40 60 80 100 120 140 160
VNN -160 -140 -120 -100 -80 -60 -40 -20 0
0
25 50 75 100 125 150
Ambient Temp TA (°C)
Switch Current vs. Switch Voltage Drop
VDD = 15V & VPP/VNN = ±80V
400
IPP/INN vs. Output Switching Frequency
VDD = 15V & VPP/VNN = ±80V
40
TA = 0°C
TA = 25°C
200
ISWITCH (mA)
IPP/INN Average Current (mA)
300
100
TA = 70°C
0
-100
-200
-300
-4000
200
-4
-3
-2
-1
0
1
VSWITCH (volts)
2
3
TA = 70°C
TA = 25°C
20
TA = -55°C
10
0
4
Junction Temp Tj vs. Switch Peak Current
VSIG Freq = 10KHz & Duty Cycle = 0.1%
VDD = 15V & VPP/VNN = ±80V
275
175
0
100
200
300
HV Output Switching Freq (KHz)
400
TDO vs. Ambient Temp TA
VPP/VNN = ±80V
250
TA = 75°C
150
225
VDD = 10V
125
200
TDO (ns)
Junction Temp Tj (°C)
TA = 125°C
30
100
75
TA = 25°C
50
175
150
125
25
VDD = 15V
100
0
75
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Switch Peak Current (A)
-50 -25 0 25 50 75
Ambient Temp TA (°C)
13-71
100 125
13
13
HV21716/HV21816
–
E
T
E
L
O
S
B
O
–
Typical Performance Curves
40
TWLE vs. Ambient Temp
VPP/VNN = ±80V
110
36
100
32
90
28
TSD (ns)
TWLE (ns)
VDD = 10V
24
20
16
80
70
50
40
8
TH vs. Ambient Temp
VPP/VNN = ±80V
16
14
16
12
VDD = 10V
TSU (ns)
TH (ns)
-50 -25 0
25 50 75 100 125
Ambient Temp TA (°C)
17
14
13
12
TSU vs. Ambient Temp
VPP/VNN = ±80V
VDD = 10V
10
8
VDD = 15V
6
VDD = 15V
4
11
2
10
0
-50 -25 0
25 50 75 100 125
Ambient Temp TA (°C)
800
VDD = 15V
30
-50 -25 0
25 50 75 100 125
Ambient Temp TA (°C)
15
VDD = 10V
60
VDD = 15V
12
18
TSD vs. Ambient Temp
VPP/VNN = ±80V
-50 -25 0
25 50 75 100 125
Ambient Temp TA (°C)
TON vs. Ambient Temp
VPP/VNN = ±80V
2.5
TOFF vs. Ambient Temp
VPP/VNN = ±80V
700
VDD = 10V
2.0
500
400
TOFF (ns)
TON (ns)
600
VDD = 15V
300
200
VDD = 10V
VDD = 15V
1.5
1
100
0
0
-50 -25 0
25 50 75 100 125
Ambient Temp TA (°C)
-50 -25 0
25 50 75 100 125
Ambient Temp TA (°C)
13-72
HV21716/HV21816
Typical Performance Curves
Off Isolation vs Signal Voltage Frequency
VDD = 15V, VPP/VNN = ±80V
-120
5
-100
Off Isolation (db)
6
4
3
-80
-60
2
-40
1
-20
10K
100K
1M
10K
10M
100K
1M
10M
Signal Voltage Frequency (Hz)
CLK Frequency (Hz)
Crosstalk vs Analog Signal Frequency
VDD = 15V, VPP/VNN = ±80V
-100
-90
Crosstalk (db)
I DD Current (mA)
I DD vs CLK Frequency
VDD = 15V, VPP/VNN = ±80V, TA = 0°C to 70°C
-80
70 ° C
-70
0° C
-60
-50
100K
1M
10M
100M
Analog Signal Frequency (Hz)
–
E
T
E
L
O
S
B
O
–
13
13
13-73
HV21716/HV21816
Pin Configurations
Package Outlines
28-Pin J-Lead
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Function
SW3
SW3
SW2
SW2
N/C
N/C
SW1
SW1
SW0
SW0
VPP
VNN
GND
VDD
25
Pin
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Function
N/C
DIN
CLK
LE
DOUT
SW7
SW7
SW6
SW6
N/C
SW5
SW5
SW4
SW4
24
23
22
21
20
26
18
27
17
28
16
1
15
2
14
3
13
4
12
5
6
7
8
9
10
top view
28-pin J-Lead Package
–
E
T
E
L
O
S
B
O
–
13-74
19
11
HV2216
8-Channel High Voltage Analog Switch
Ordering Information
Package Options
VPP – VNN
28-pin
plastic DIP
28-lead plastic
chip carrier
Die
160V
HV2216P
HV2216PJ
HV2216X
Features
General Description
®
HVCMOS technology for high performance
Not recommended for new designs. Please use HV20220 for
all new designs.
Very low quiescent power dissipation – 10µA
This device is an 8-channel high-voltage analog switch integrated circuit (IC) intended for use in applications requiring high
voltage switching controlled by low voltage control signals, such
as ultrasound imaging and printers. Input data is shifted into an
8-bit shift register which can then be retained in an 8-bit latch. To
reduce any possible clock feedthrough noise, Latch Enable (LE)
should be left high until all bits are clocked in. Using HVCMOS
technology, this switch combines high voltage bilateral DMOS
switches and low power CMOS logic to provide efficient control
of high voltage analog signals.
Output On-resistance typically 22 ohms
Low parasitic capacitances
DC to 10MHz analog signal frequency
-50dB typical output off isolation at 5MHz
CMOS logic circuitry for low power
Excellent noise immunity
On-chip shift register, latch and clear logic circuitry
This IC is suitable for various combinations of high voltage
supplies, e.g., for HV2216 +40V/-120V, or +80V/-80V or +150V/
-10V.
Flexible high voltage supplies
Surface mount package available
13
13
Absolute Maximum Ratings*
VDD Logic power supply voltage
VPP - VNN Supply voltage
-0.5V to +18V
174V
VPP Positive high voltage supply
-0.5V to +160V
VNN Negative high voltage supply
+0.5V to -160V
Logic input voltages
Analog Signal Range
Peak analog signal current/channel
Storage temperature
Power dissipation
-0.5V to VDD +0.3V
VNN to VPP
3.0A
-65°C to +150°C
1.2W
* Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability.
13-75
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