HV461 Initial Release HV461FG Ring Generator Controller IC Features 3.3V operation, logic inputs 3.3V & 5V compatible Digital control of ring frequency, amplitude, and offset Control via 8-bit bus or via individual inputs 8 built-in ring frequencies: 162/3, 20, 25, 331/3, 40, 50, 60Hz External ring frequency input Low distortion sine wave synthesizer AC-only, AC+DC, or DC-only ringer output Adjustable over-current protection Internal precision voltage references Power-on reset and undervoltage lockout for hotswap capability Sync output with adjustable lead time for synchronizing ringing relays Fault output for problem detection Open or closed loop operation Efficient 4-quadrant operation Zero-cross turn-on with zero-cross turn-off option Applications ❑ ❑ ❑ ❑ ❑ PBX DLC Key Systems Remote Terminal Wireless Loop Systems Description The HV461FG is a highly integrated Ring Generator controller IC designed to work with a patented four-quadrant inverter topology, with Synchronous Rectifiers on the secondary side to achieve higher efficiencies. The inverter delivers the desired ring voltage from a standard -48V Telecom power supply. HV461 consists of a sine wave synthesizer that can provide eight different ring frequencies for universal applications. Any other frequency in the 12 to 63 Hz range can be obtained by applying an external logic signal to the IC. A transparent latch permits control of the ringer output through the 8-bit bus or individually. The output amplitude and DC offset can be digitally controlled providing high flexibility to the designers. The patented inverter topology using the HV461 controller IC is capable of achieving higher efficiencies, typically over 80%, and drive up to a 40 REN load. The controller allows ring generators to provide a floating 94VAC (rms) waveform that can be referenced to either the –48V or any other offset level by using the programmable offset pins of the IC. Output offset may be achieved by directly generating the offset within the power stage, or by floating the output stage on a DC source, or both. HV461 also has an internal Boost Converter that can be used to provide the gate drive voltages for the two MOSFETS on the primary side and the two secondary rectifiers on the secondary side. Typical Application Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. HV461 Absolute Maximum Ratings VDD Ordering Information +4.0V Digital Inputs -0.5V to +7.0V Analog Inputs -0.5V to +7.0V Storage Temperature Order Number 48 lead TQFP HV461FG -65°C to +150°C Operating Temperature Specifications Package Option -40°C to +85°C (unless otherwise specified: VDD = +3.3V, TA = -40ºC to +85ºC) External Supply Symbol Parameter Min Typ Max Unit VDD Supply Voltage 3.0 3.3 3.6 V IDD Supply Current (AVDD + DVDD) 7 30 mA Conditions fPWM=100kHz fosc=19.6608MHz SW outputs NC Open loop config External VGD Gate Drive Supply Symbol Parameter Min Typ Max Unit VGD Boost circuit voltage 9.0 9.6 10.2 V IGD Gate drive supply current 5 10 mA mA VDR(lo) Drive voltage, low 0.2 V IOUT=-10µA VDR(hi) Drive voltage, hi V IOUT=10µA VDD-0.4 Conditions VDD=2.97-3.63V, SW outputs unloaded VDD=2.50-2.93V, SW outputs unloaded tRISE Rise time 100 ns CL=200pF tFALL Fall time 100 ns CL=200pF fGD Converter frequency DGD Duty cycle same as PWM 45 50 55 % Voltage Reference Symbol VREF1 TCREF1 Parameter Reference voltage 1 Min Typ Max Unit 1.237 1.250 1.263 V Temperature coefficient 200 ∆Vref1 Output regulation -6.25 VREF2 Reference voltage 2 2.475 TCREF2 ∆Vref2 2.500 Temperature coefficient Output regulation +6.25 mV 2.525 V Iout=±100µA Ta=25ºC µV/ºC 0 2 Ta=25ºC µV/ºC 500 -12.5 Conditions mV Iout=0–100µA source HV461 Logic Inputs Symbol Parameter VIN(lo) Min Typ Input voltage low Max Unit 0.3·VDD V 0.7·VDD Conditions VIN(hi) Input voltage high IIN(lo) Input current low -1 V µA VIN=0V IIN(hi) Input current high 1 µA VIN=5.0V CIN Input capacitance 10 pF tS Set-up time 100 ns tH Hold time 100 ns RESET Symbol Parameter Min Typ Max Unit VRESET(ON) RESET on voltage 1.200 1.325 1.450 V VRESET(OFF) RESET off voltage 1.000 1.125 1.250 V VRESET (HYS) RESET hysteresis 0.150 0.200 0.250 V 7.0 10.0 13.0 µA IP-UP RESET pull-up current Conditions Undervoltage Lockout Symbol Parameter Min Typ Max Unit VDD(ON) VDD on voltage 2.75 2.85 2.95 V 2.60 VDD(OFF) VDD off voltage VDD(HYS) VDD hysteresis 0.10 V VGD(ON) VGD on voltage same as VGD regulation point V VGD(OFF) VGD off voltage 7.0 V VGD(HYS) VGD hysteresis 0.20 V Parameter Min Typ Conditions V Fault Output Symbol VOUT(lo) Output voltage low Max Unit Conditions 0.2 V KFAULT(on) FAULT on threshold 6 8 10 %* CFAULT=10µF IOUT=1mA KFAULT(off) FAULT off threshold 1 2 3 %* CFAULT=10µF tFAULT(hold) FAULT hold time 50 mS CFAULT=10µF * Percent of time PWM overrange or overcurrent is active. Amplifiers Symbol Parameter Min Typ Max Unit VIN Input Range 0.25 2.50 V IIN Input Bias Current -500 500 nA -5 5 mV 0.2 V VOFFSET Input Offset Voltage VOUT(min) Min output VOUT(max) AVOL CMRR Max output 0.1 VDD -0.2 VDD -0.1 Open Loop Gain 60 80 dB Common mode rejection ratio -40 -60 dB 3 Conditions VIN=0.5V to VDD-0.5 IOUT=±100uA IOUT=±100uA HV461 GBW SL PSRR Gain-Bandwidth Product 1 MHz Slew Rate 0.1 V/µs Power supply rejection ratio -30 dB f<10kHz Sinewave Synthesizer Symbol VDC Parameter Min Typ Max Unit Conditions DC level 1.237 1.250 1.263 V A Amplitude 1.940 2.000 2.060 0 VP-P VP-P AMP≠00 AMP=00 f0 Frequency 16 2/3 Hz FREQ=000, fOSC=19.6608MHz f1 Frequency 20 Hz FREQ=001, fOSC=19.6608MHz f2 Frequency 25 Hz FREQ=010, fOSC=19.6608MHz f3 Frequency 30 Hz FREQ=011, fOSC=19.6608MHz f4 Frequency 1 33 /3 Hz FREQ=100, fOSC=19.6608MHz f5 Frequency 40 Hz FREQ=101, fOSC=19.6608MHz f6 Frequency 50 Hz FREQ=110, fOSC=19.6608MHz f7 Frequency 60 Hz FREQ=111, fOSC=19.6608MHz ∆f Frequency accuracy 0.1 % fosc=19.6608MHz THD Harmonic distortion 3 % CSINE=33nF fring=16 2/3 to 60Hz ROUT Output resistance 17.6 88.0 kΩ kΩ AMP≠00 AMP=00 14.4 72.0 16.0 80.0 External Ring Frequency Symbol Parameter Min Typ Max Unit Conditions fCAP(lo) Capture frequency low* 12 Hz loop filter=(33µF+10kΩ)||4.7µF fCAP(hi) Capture frequency high* 63 Hz loop filter=(33µF+10kΩ)||4.7µF VIN(lo) Input low VIN(hi) Input high Phase jitter, sine ref out ∆θRING * Lock range is the same as capture range 0.3·VDD 0.7·VDD V V -5 +5 deg loop filter=(33µF+10kΩ)||4.7µF Sine Reference Attenuator Symbol Parameter VDC DC level AOFF Attenuation Min Typ Max Unit Conditions 1.237 1.250 1.263 V 0.010 V/V AMP=00 VIN(DC)=1.250V ALO Attenuation 0.495 0.500 0.505 V/V AMP=01 AMED Attenuation 0.742 0.750 0.758 V/V AMP=10 AHI Attenuation 0.990 1.000 1.010 V/V AMP=11 VIN Input range 0.2 VDD-0.2V V DC REF Multiplexer Symbol Parameter VIN Input range IIN Input bias current IOFF Min Typ Max Unit 0.0 VDD V -500 +500 nA 1.0 µA Off leakage current 4 Conditions VIN = 0.5 to VDD-0.5V HV461 ENABLE and SYNC Symbol Parameter VOUT(lo) SYNC output voltage low VOUT(hi) SYNC output voltage high tON ENABLE delay, on tOFF ENABLE delay, off τSYNC(ON) SYNC on lead time τSYNC(OFF) SYNC off delay tSYNC(rise) tSYNC(fall) Min Typ Max Unit 0.2 V IOUT = 1mA sink V IOUT = 1mA source VDD - 0.2 0 5 µs 60 1 µs ring cycle Conditions SYNCMODE=0 SYNCMODE=1 4.5 5 5.5 ms CSINE=0 RSYNC=154kΩ CSYNC=47nF -250 0 +250 µs CSINE=10nF SYNC rise time 300 ns CL=50pF SYNC fall time 300 ns CL=50pF PWM Controller Symbol Parameter Min Typ Max Unit Conditions 21.25 127.5 25.00 150.0 28.75 172.5 kHz kHz RPWM=500kΩ RPWM=83kΩ 30 50 70 ns 150 kHz 0.2 V PWM Frequency fPWM tPWMSYNC(OUT) PWM frequency PWM sync output pulse width tPWMSYNC(IN) PWM sync input pulse width 25 fPWMSYNC(IN) PWM sync input frequency range 25 VPWMSYNC(lo) PWM sync output low voltage IPWMSYNC PWM sync pull-up current ns IOUT=1mA sink µA 100 Switch Driver Outputs VOUT(lo) Output voltage, low VOUT(hi) Output voltage, high 0.2 VGD-0.2 V IOUT=20mA sink V IOUT=20mA source tRISE Rise time 50 ns CL=4nF tFALL Fall time 50 ns CL=4nF Timing Duty cycle 23 48 73 25 50 75 27 52 77 % % % PWMin=0.625V PWMin=1.250V PWMin=1.875V VDCL=0V Dlimit Duty cycle limit 12 72 22 62 20 80 30 70 28 88 38 78 % % % % VDCL = 0.50V, PWMIN=0V VDCL = 0.50V, PWMIN=2.5V VDCL = 0.75V, PWMIN=0V VDCL = 0.75V, PWMIN=2.5V IDCL VDCL input current 1 µA VDCL=0-1V tDB Primary switch deadband 0 0.95 100 1.00 150 1.05 ns µs CDB=0pF RDB=14kΩ, CDB=100pF tDLY Secondary switch delay 0 0.95 100 1.00 150 1.05 ns µs CDLY=0pF RDLY=14kΩ, CDLY=100pF D 5 HV461 Switch Outputs ENABLE AMP OFF SW1 SW2 SW3 SW4 0 00 XX Off Off Off Off 0 ≠00 XX Off Off Switching Switching 1 XX XX Switching Switching Switching Switching X = don’t care, ≠00 = 01,10, or 11 Switch Timing tDB tDB tDLY SW1 On Off SW2 Off On On Off Off On SW3 SW4 tDLY Figure 1: Switch Timing Diagram 6 HV461 ENABLE and SYNC Timing: SYNCMODE=0 ENABLE SYNC tON tOFF SYNC(ON) SINE REF Decay time dependent on value of cap connected to SINEREF. ErrAmp Siezed Siezed Free Figure 2: ENABLE and SYNC Timing – SYNCMODE=0 ENABLE and SYNC Timing: SYNCMODE=1 ENABLE SYNC tON(delay) SYNC(ON) SYNC(OFF) sync at 0º or 180º Filtered SINE REF ErrAmp Siezed Free Figure 3: ENABLE and SYNC Timing – SYNCMODE=1 7 Siezed HV461 AMP Timing AMP AMP 00 AMP 00 AMP 00 SYNC tSYNC(delay) amplitude changes sync'd to zero crossings SYNC(ON) SINE REF Figure 4: AMP Timing Typical Application Figures 5 and 6 on pages 9 and 10 show the schematic of a typical 15 REN ring generator application. The basic design equations for elements connected to different pins are given in the Pin Descriptions Table beginning on page 11. 8 AMP 00 HV461 Block Diagram and Typical Application RDC1 - RDC4 selected for the desired DC Offsets. RTSYNC and CTSYNC selected for desired ring sync lead time RTSYNC 3.3k CSINE 47nF VREF2 CDC 100nF RCOMP 2.7k RDC1 RDC2 RDC3 RDC4 VREF1 TSYNC XTAL SYNC SINEREF DCREF1–3 +1 VREF1 FRING PLL reset SW1 switch drivers 2 PWMin FREQ0 FREQ1 FREQ2 AMP0 AMP1 OFF0 OFF1 ENABLE HV461FG Latch freq 2 current limit SW3 referto power stage schematic CL+ CLCLCOMP amp VREF1 enable offset osc enable Enable Control dutycyclelimit LE overrange overcurrent pri deadband sec delay VDD SW2 SW4 VREF1 Transparent Latch to host controller 10k 40k CPLL1 4.7µF PWM Controller +1 20k PWMSYNC ROSC VDCL ROSC 267k RDCL1 100 kΩ RDCL2 33 kΩ VDD VDD RDLY 4.7 kΩ VREF1 1.25V VREF2 2.50V CREF2 100nF VDD TDB TDLY SYNCMODE CREF1 100nF refer to power stage schematic VREF1 3 PLLFLT RPLL PLL filter only required for 10k external ring frequency C PLL2 33µF RFB4 4.02M RFB3 30.1k 10k Amplitude Mux 20k Differential Amplifier Error Amplifier 20k 2 Synthesizer freq ringer output output reference DIFFAMPDIFFAMP+ VREF1 20k RFB2 4.02M DIFFAMPO COMP2 Offset Mux OSC clk Sine Wave VGD COMP1 Sync sync external ring frequency RFB1 30.1k CCOMP1 47nF CTSYNC 100nF Y1 19.6608MHz CCOMP2 1nF Precision Reference Deglitcher undervoltage VDD CFAULT CFAULT 10µF Undervoltage Detector FAULT 10 A RESET Boost Converter CRESET 4.7µF AVDD VDR DVDD LGD 330µH VGD AGND DGND PGND DGD 4148 VDD CDD1 10µF CDD2 100nF CGD 6.8µF QGD TN2504 Figure 5: Block Diagram and Typical Application 9 CDLY selected for desired Fault response time CDLY 120pF VDD RFAULT 100 kΩ to host controller RDB 4.7 kΩ CDB 120pF HV461 Typical Power Stage for 15 REN Ring Generator RCL4 6.8k CCL2 68nF PWR GND RCL1 10k CLCOMP CSW3a 100nF CL+ CCL1 10nF TSW3 1:1 SW3 VREF1 RSENSE 0.18 RCL3 39k CL- CSW3b 100nF RCL2 10k CSW2 100nF ZSW2a,b 12V SW2 RSW2a 220 DSW2 MMBD4148 RSW2b 100k CIN1 470µF RSW3a 220 QSW2 IRF9540 CIN2 470nF SW 1 CSW1 100nF ZSWa,b 12V RSW1a 220 RSW1b 100k QSW1 IRF530 DSW2 MMBD4148 CPRI4 470nF CPRI3 100µF T MAIN 1:6.5:6.5 RPR1 100k QSW3 IRFR320 52 H RPRI2 100k QSW4 IRFR320 CPRI1 100µF CPRI2 470nF LIN Ferrite bead COUT1 1µF ROUT1 1.0M COUT2 1µF ROUT2 1.0M RSW4b 220 CSW4b 100nF CSW4a 100nF SW4 TSW4 1:1 Figure 6: Typical Power Stage for 15 REN Ring Generator 10 RSW3b 10k RSW4a 10k DSW4 MMBD4148 -48V DSW3 MMBD4148 Output Reference Ringer Output HV461 DCREF2 DCREF1 VDCL AGND SINEREF COMP1 COMP2 DIFFAMPO DIFFAMPDIFFAMP+ CLCOMP CL- Pin Descriptions DCREF3 VREF1 VREF2 AVDD TSYNC XTAL FRING PLLFLT ROSC RESET PWMSYNC CFAULT SYNCMODE SYNC FAULT ENABLE OFF0 OFF1 AMP0 AMP1 FREQ0 FREQ1 FREQ2 LE HV461 CL+ DVDD VDR VGD PGND SW1 SW2 SW3 SW4 DGND TDB TDLY Pin Name Description 1 DCREF3 See DCREF1 and DCREF2 (pins 47 & 48). 2 VREF1 Outputs a 1.25V nominal reference voltage. Bypass with a 100nF capacitor to ground. 3 VREF2 Outputs a 2.50V nominal reference voltage. Bypass with a 100nF capacitor to ground. 4 AVDD Supply for the analog section. 3.0 to 3.6V Must be from the same source as DVDD. Bypass with a 100nF capacitor to ground as close as possible to the IC. 5 TSYNC An RC network connected to this pin determines the SYNC pulse lead time (see SYNC pin 14). tLEAD = 0.48RC If unused, this pin should be left unconnected. 6 XTAL A crystal from this pin to ground provides the frequency reference for the internal sine wave synthesizer. A 19.6608MHz baud rate crystal provides the 8 most common ring frequencies. The crystal is operated in the series mode. A loading capacitor is not necessary. See also FREQ0–2 (pins 21–23) and FRING (pin 7). 7 FRING Ring frequency is normally selected from the 8 built-in frequencies using control inputs FREQ0–2. Other arbitrary frequencies in the range of 12 to 70Hz may be obtained by applying an external signal to FRING. This external signal sets the ring frequency at a 1:1 ratio. The ring signal remains a sine wave, with amplitude and offset still controlled via AMPx and OFFx. The ring signal, while frequency locked to the FRING signal, is not phase–synchronized to it. This allows the ring signal to immediately start at 0º when enabled via ENABLE or AMP≠00. When unused, this input must be connected to VGD. 8 PLLFLT Phase locked loop filter. An RC network connected to this pin stabilizes the PLL that locks on to the optional external ring frequency signal. (See FRING, pin 7) The RC network determines the lock time of the PLL. Due to the low frequencies involved, it may take a couple seconds to lock to the external signal. See the typical application schematic for typical values. When unused, this pin should be left unconnected. 9 ROSC A resistor from this pin to VDD sets the PWM frequency. fPWM ≈ 12.5GHzΩ / ROSC (valid for 20-150kHz) 10 RESET 11 PWMSYNC A capacitor from this pin to ground provides a power–on reset interval. It has an internal 10µA pull–up to charge the external reset capacitor. Alternatively, an external logic–level or open–drain signal may be applied to implement the reset function. During the reset interval when VRESET<1.325V, the ringer output is disabled regardless of the state of the ENABLE input, allowing time for the host controller to assume control. Use a low leakage tantalum or ceramic capacitor. tRESET = 1.325V · CRESET / 10µA This pin functions as both an input and an output. It is open–drain with an internal 100µA pull–up. As an output, it provides a short, low–going pulse at the internal PWM frequency. As an input, it synchronizes internal PWM frequency to the externally applied signal, provided the external signal is at a higher frequency. The lowgoing applied sync pulse should be between 25ns and less than the PWM period in duration. The external source should be open drain. If the PWMSYNC pins of multiple HV461s are tied together, their PWM frequencies will be phase–locked to the HV461 with the highest free-running frequency. A maximum of 10 HV461s may be tied together. If unused, this pin should be left unconnected. 11 HV461 12 CFAULT A capacitor from this pin to ground sets the integration time of the FAULT detection circuitry. A larger capacitor provides less suseptability to transient problems, while a smaller capacitor provides quicker response. Values in the range of 1µF to 100µF are appropriate. If the FAULT output is not used, this pin should be grounded. See also FAULT (pin 15). 13 SYNCMODE With SYNCMODE low, ringer output ceases the instant ENABLE goes low. When high, ringer output ceases at the next ring signal phase crossing (0º/180º) after ENABLE goes low. 14 SYNC Outputs a pulse indicating sine reference 0º and 180º phase crossing (not to be confused with zero–voltage crossing). The rising edge precedes phase crossing by a user–adjustable time period (see TSYNC pin 44). Falling edge coincides with sine reference phase crossing. SYNC is digitally derived, therefore phase shifts caused by the external filter capacitor at SINEREF will not be reflected at the SYNC output. Indicates abnormal operating conditions of output overcurrent, supply undervoltage (VDD & VGD), or PWM overrange (duty cycle limit – see VDCL, pin 3). Together, these 3 conditions catch most any problem. When an overcurrent or overrange condition exists for more than 8% of the time, this output becomes active. It is cleared when the problem occurs less than 2% of the time. Undervoltage conditions immediately activate the FAULT output. It is active low and open drain to allow wire-ORing. See CFAULT (pin 15) for additional information. Ringer output enable. Active high. When enabled, the ring signal always starts immediately at 0 degrees. If AMP≠00, SW1 and SW2 are held off when ENABLE=0 but SW3 and SW4 continue switching. If AMP=00, SW3 and SW4 are held off as well. When disabled, the error amplifier is set at unity gain to prevent saturation, reducing turn-on glitches when re-enabled. See SYNCMODE (pin 13) for additional information. 15 FAULT 16 ENABLE 17 OFF0 18 OFF1 19 AMP0 20 AMP1 21 FREQ0 22 FREQ1 000 = 16.7Hz 001 = 20Hz 010 = 25Hz 011 = 30Hz 23 FREQ2 100 = 33.3Hz 101 = 40Hz 110 = 50Hz 111 = 60Hz Sets ring DC offset. Offset changes are effected at the next phase crossing (0º/180º) of the ring signal. Except for 00, offsets are set by the voltages at DCREF1–3. (OFF0 is LSB) Offset = ½ x Gain x (VDCREFx - VREF1) 00 = 0V 01 = DCREF1 10 = DCREF2 11 = DCREF3 Sets ring amplitude. Amplitude changes are effected at the next phase crossing (0º/180º) of the ring signal. Amplitudes, as a percentage of full scale, are: (AMP0 is LSB) Full scale amplitude = 0.707VRMS x Gain 00 = 0% 01 = 50% 10 = 75% 11 = 100% Sets ring frequency. Frequency changes are effected at the next phase crossing (0º/180º) of the ring signal. Frequencies when using a 19.6608MHz crystal are: (FREQ0 is LSB) Latch enable. The latch gates control inputs FREQ0–2, AMP0–1, OFF0–1, and ENABLE. When LE is high, latch outputs follow inputs. On a low–going transition, outputs are latched. 24 LE 25 TDLY An RC network on this pin sets the primary to secondary switch delay. This prevents the secondary–side switches (SW3&4) from turning on prematurely. tDLY=0.48RC 26 TDB An RC network on this pin sets the deadband (break–before–make time) on the primary–side switches (SW1&2). Deadband prevents both switches from conducting simultaneously. tDB=0.48RC 27 DGND Digital ground. Connect to AGND and PGND close to the IC. 28 SW4 Secondary–side switch driver output. 29 SW3 Secondary–side switch driver output. 30 SW2 Primary–side N-channel switch driver output. 31 SW1 Primary–side P-channel switch driver output. 32 PGND Power ground. Connect to AGND and DGND close to the IC. 33 VGD Supply for the SW1–4 drivers. An external boost converter controlled by VDR provides 9.6V for driving the power stage MOSFETs. An undervoltage condition on this supply pin disables ringer output and activates the FAULT output. 34 VDR Gate drive for the external boost converter circuit. Outputs a fixed 50% duty cycle at the ringer PWM frequency (see ROSC, pin 9). Output voltage regulation is via burp-mode operation. This output is boostrapped to VGD, thus during startup VDR amplitude is VDD and after startup is VGD. (See VGD, pin 33) 35 DVDD Supply for the digital section. 3.0V to 3.6V input. Undervoltage disables ringer output. Must be from the same source as AVDD. Bypass with a 100nF capacitor to ground as close as possible to the IC. An undervoltage condition on this supply pin disables ringer output and activates the FAULT output. 36 CL+ Current limit amplifier non-inverting input. 12 HV461 37 CL- Current limit amplifier inverting input. 38 CLCOMP Current limit compensation. An RC network connected between this pin and CL- establishes current limit reaction time and stability. 39 DIFFAMP+ Differential amplifier non-inverting input. The differential amplifier sets gain, establishing output 40 DIFFAMP- Differential amplifier inverting input. amplitude and DC offset in conjunction with AMPx and OFFx. 41 DIFFAMPO Differential amplifier output. Gain = RFB2/RFB1 (RFB3=RFB1 and RFB4=RFB2, see schematic) 42 COMP2 Error amplifier compensation. An RC network connected between these pins establishes loop stability. 43 COMP1 COMP1 is the error amp inverting input. COMP2 is the error amp output. 44 SINEREF Sine wave reference. Amplitude is 2VP-P nominal. Output impedance is approximately 16kΩ. An external 33nF capacitor from this pin to ground should be employed to remove high frequency synthesizer ripple. Synthesizer ripple is at a frequency of 215 · fRING 45 AGND Analog ground. Connect to AGND and DGND close to the IC. 46 VDCL Voltage applied to this pin sets the min/max duty cycle limits. If the PWM controller hits these limits, clipping of the ringer output will occur and the FAULT output will be activated. DMIN=0.4VDCL DMAX=1–0.4VDCL 47 DCREF1 In conjunction with the OFFx control inputs, voltages applied to these inputs set the output DC offset. 48 DCREF2 Output offset is the selected DCREFx voltage multiplied by gain. See also OFF0 & OFF1 (pins 17 & 18) 10/3/03 13 2003 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited. 1235 Bordeaux Drive, Sunnyvale, CA 94809 TEL: (408) 222-8888 / FAX: (408) 222-4895 www.supertex.com Package Outlines 48-Lead TQFP Package (FG) D, E 0.024 ± 0.008 (0.610 ± 0.2032) 0.354 ± 0.010 (8.992 ± 0.254) L 0.354 ± 0.010 (8.992 ± 0.254) 0.275 ± 0.004 (6.985 ± 0.102) 0.008 ± 0.003 (0.2032 ± 0.0762) Pin #1 B D1, E1 0° - 7° 0.275 ± 0.004 (6.985 ± 0.1016) A A2 0.055 ± 0.004 (1.397 ± 0.102) 0.020 BSC (0.508) Note: Circle (e.g. B ) indicates JEDEC Reference. 0.059 ± 0.004 (1.4986 ± 0.102) 0.039 TYP. (0.991) Measurement Legend = Dimensions in Inches (Dimensions in Millimeters) 03/18/02 ©2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 • FAX: (408) 222-4895 www.supertex.com