HV4937 64-Channel Serial To Parallel Converter With P-Channel Open Drain Outputs Ordering Information Package Options Device 80-Lead Quad Plastic Gullwing Die HV4937 HV4937PG HV4937X Features General Description ■ HVCMOS® Technology Not recommended for new designs. ■ Output voltages up to -375V The HV49 is a low voltage serial to high voltage parallel converter with open drain outputs. It has been designed especially for use as a driver for electrostatic printers. ■ Source current minimum 0.25mA ■ Shift register speed 6 MHz This device consists of a 64-bit shift register, 64 latches, a latch enable (LE), and an output enable (OE). Data is shifted through the shift register on the high to low transition of the clock. When the DIR pin is set high, the HV49 shifts in the counterclockwise direction when viewed from the top of the package. When the DIR pin is set low, the HV49 shifts in the clockwise direction. A serial data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register. Operation of the shift register is not affected by the LE or the OE inputs. Transfer of data from the shift register to the latch occurs when the LE input is high. The data in the latch is stored when LE is low. ■ Latched outputs ■ CMOS compatible inputs ■ Forward and reverse shifting options Absolute Maximum Ratings1 Supply voltage, VDD +0.5V to -9V Supply voltage, VPP +0.5V to -400V Logic input levels Ground current Continuous total power dissipation2 Operating temperature range Storage temperature range +0.5V to VDD -0.5V 0.75A 1200mW -40°C to +85°C -65°C to +150°C Notes: 1. All voltages are referenced to VSS. 2. For operation above 25°C ambient derate linearly by 20mW/°C up to 85°C. 12-29 12 HV4937 Electrical Characteristics (over recommended operating conditions unless noted) DC Characteristics Symbol Parameter Min Typ VDD Supply Current IDD Max Units -15 mA Conditions fCLK = 6MHz, fDATA = 3MHz LE = LOW IDDQ Quiescent VDD Supply Current -250 µA All VIN = 0V IO(OFF) Off State Output Current at 25°C, per Switch -100 nA Output high, and at -375V IIH High-Level Logic Input Current -10 µA VIH = VDD IIL Low-Level Logic Input Current +10 µA VI = 0V VOH High-Level Data Out VDD +1 V IDOUT = -100µA VOL Low-Level Output VOC HVOUT Clamp Voltage CHVO Output Capacitance per Channel AC Characteristics HVOUT -10 V IHVOUT = -0.25mA Data Out -1 V IDOUT = 100µA -3.0 V IOL = 1mA 3 pF VDS = 100V (For VDD = -5V, TA = 25°C) Symbol Parameter Min Typ Max Units 6 MHz fCLK Clock Frequency tW Clock Width High or Low 83 ns tSU Data Setup Time Before Clock Falls 35 ns tH Data Hold Time After Clock Falls 15 ns tWLE Width of Latch Enable Pulse 83 ns tDLE LE Delay Time After Falling Edge of Clock 35 ns tSLE LE Setup Time Before Falling Edge of Clock 40 tDHL Clock Delay Time Data High to Low 160 ns tDLH Clock Delay Time Data Low to High 160 ns Conditions ns Recommended Operating Conditions Symbol Parameter Min Typ Max Units -5.0 -5.5 V VDD Logic supply voltage -4.5 HVOUT High voltage output +0.3 -375 V VIH High-level input voltage -3.5 VDD V VIL Low-level input voltage 0 -0.8 V TA Operating free-air temperature -40 +85 °C Notes: All voltages are referenced to VSS. Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply VPP. Power-down sequence should be the reverse of the above. 12-30 HV4937 Input and Output Equivalent Circuit VSS VSS VSS Data Out Input HVIN HVOUT VDD VDD Logic Data Output Logic Inputs High Voltage Output Switching Waveforms VIH Data In Data Valid 1 Data Valid 2 VIL tSU tH VIH Clock VIL Data Out tWH tWL VOL tDHL VOH Data Out tDLH VIH Latch Enable VIL tDLE tWLE 12-31 tSLE HV4937 Functional Block Diagram VSS Output Enable Latch Enable Data Input HVOUT1 Clock HVOUT2 DIR 64 bit Static Shift Register • • • 60 Additional Outputs • • • HVOUT63 64 Latches HVOUT64 Data Out Function Table Inputs Outputs Function Data CLK LE OE DIR Shift Reg 1 2 … 64 All off X X X L X *…* Load S/R H or L ↓ L L H H or L ↓ L L L H or L ↓ H L X X H or L H H H ↓ H L ↓ H Load Latch Output Enable Transparent Latch Mode Latch HVOUT 1 2 … 64 1 2 … 64 DOUT *…* H…H * H or L…Qn → Qn+1 *…* H…H * H or L…Qn → Qn-1 *…* H…H * H or L…* H or L…* H…H * X H or L…* H or L…* L or H…* * H X H…* H…* L …* * H X L …* L…* H…* * Notes: X = Don’t care * = Dependent on previous stage’s state before the last CLK : High to low transition. ↓ = -5V to VSS transition H = VDD L = VSS 12-32 HV4937 Pin Configurations Package Outline PG Package HV49 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 64 Function VSS N/C HVOUT 59/6 HVOUT 60/5 HVOUT 61/4 HVOUT 62/3 HVOUT 63/2 HVOUT 64/1 DIR Data Out CLK VSS VDD LE Data In OE HVOUT 1/64 HVOUT 2/63 HVOUT 3/62 HVOUT 4/61 HVOUT 5/60 HVOUT 6/59 N/C VSS HVOUT 7/58 HVOUT 8/57 HVOUT 9/56 HVOUT 10/55 HVOUT 11/54 HVOUT 12/53 HVOUT 13/52 HVOUT 14/51 HVOUT 15/50 HVOUT 16/49 HVOUT 17/48 HVOUT 18/47 HVOUT 19/46 HVOUT 20/45 HVOUT 21/44 HVOUT 22/43 Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Function N/C N/C HVOUT 23/42 HVOUT 24/41 HVOUT 25/40 HVOUT 26/39 HVOUT 27/38 HVOUT 28/37 HVOUT 29/36 HVOUT 30/35 HVOUT 31/34 HVOUT 32/33 HVOUT 33/32 HVOUT 34/31 HVOUT 35/30 HVOUT 36/29 HVOUT 37/28 HVOUT 38/27 HVOUT 39/26 HVOUT 40/25 HVOUT 41/24 HVOUT 42/23 N/C N/C HVOUT 43/22 HVOUT 44/21 HVOUT 45/20 HVOUT 46/19 HVOUT 47/18 HVOUT 48/17 HVOUT 49/16 HVOUT 50/15 HVOUT 51/14 HVOUT 52/13 HVOUT 53/12 HVOUT 54/11 HVOUT 55/10 HVOUT 56/9 HVOUT 57/8 HVOUT 58/7 40 65 Index 25 80 24 1 top view 80-pin Gullwing Package Note: Pin designation DIR = H or L Example: For DIR = H, Pin 3 is HVOUT 59 For DIR = L, Pin 3 is HVOUT 6 12-33