HV518 32-Channel Vacuum-Fluorescent Display Driver Features General Description ► ► ► ► ► ► The HV518 is designed for vacuum fluorescent or DC plasma applications, where it can serve as a segment, digit or matrix display driver. Each device has 32 outputs, 32 latches and a 32-bit cascadable shift register. 32 output lines 90V output swing Active pull-down Latches on all outputs Up to 6MHz @ VDD = 5.0V -40°C to +85°C operation Serial data enters the shift register on the LOW-to-HIGH transition of the clock input. With latch enable (LE) HIGH, parallel data is transferred to the output buffers through a 32-bit latch. When LE is low the data is stored in the latch. When STROBE is LOW, all outputs are enabled; if STROBE is HIGH, all outputs are LOW. Applications ► Vacuum flourescent displays ► DC plasma displays Block Diagram LE STB VPP HVOUT1 DIN CLK 32-Bit Shift Register Latches DOUT HVOUT32 1 HV518 Pin Configurations Ordering Information Device Package Options 40-Lead PDIP 44-Lead PLCC HV518P-G HV518PJ-G HV518 21 40 -G indicates package is RoHS compliant (‘Green’) 20 1 40-Lead PDIP (P) (top view) 39 38 37 36 35 34 33 32 31 30 29 Absolute Maximum Ratings Parameter 28 41 27 42 26 43 25 44 24 1 23 2 22 3 21 Value Supply voltage, VDD -0.5V to +6.0V Supply voltage, VPP -0.5V to +90V Logic input levels 4 20 5 19 6 18 -0.5V to VDD+0.5V Continuous total power dissipation Operating temperature Storage temperature Soldering temperature 40 (1,2) 7 8 9 10 11 12 13 14 15 16 17 44-Lead PLCC (PJ) 1200mW (top view) -40°C to +85°C -65°C to +150°C (3) Product Markings 260°C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to GND. Top Marking YYWW HV518P LLLLLLLLLL Notes: (1) Duty cycle is limited by the total power dissipated in the package. (2) For operation above 25OC ambient, derate linearly to 85OC at 20mW/OC. (3) Distance of 1.6mm from case for 10 seconds. Bottom Marking CCCCCCCCCCC AAA Y = Last Digit of Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking 40-Lead PDIP (P) Top Marking Y Y WW HV518PJ LLLLLLLLLL Bottom Marking CCCCCCCCCCC AAA YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking 44-Lead PLCC (PJ) 2 HV518 Recommended Operating Conditions (T A = 25°C, unless otherwise noted) Sym Parameter Min Max Unit Conditions VDD Logic supply voltage 4.5 5.5 V --- VPP High voltage supply 8.0 80 V --- VIH High-level input voltage 3.5 - V VDD = 4.5V, See Figure 3 VIL Low-level input voltage - 1.0 V VDD = 4.5V, See Figure 3 IOH High-level output current -25 - mA --- IOL Low-level output current - 2.0 mA --- fCLK Clock frequency - 6.0 MHz tw(CKH) Pulse duration, clock high 83 - ns VDD = 4.5V tw(CKL) Pulse duration, clock low 83 - ns VDD = 4.5V tsu Setup time, data before clock 75 - ns VDD = 4.5V th Hold time, data after clock 75 - ns VDD = 4.5V TA Operating free-air temperature -40 85 °C --- VDD = 4.5V, See Figure 3 Electrical Characteristics (over recommended ranges of operating free-air temperature and VDD. Unless otherwise noted, VPP = 80V) Sym Parameter Min Typ Max Units Conditions IDD Supply current - - 10 mA VDD = 5.0V, fCH = 6.0 MHz IDDQ Quiescent supply current - - 0.5 mA VDD = 5.5V, VIN = 0V IPPQ Quiescent supply current - - 100 µA --- VOH HVIN operating current HV output 70 - - Serial output 4.5 4.9 5.0 VOL LVIN operating current HV output - - 5.0 Serial output - 0.06 0.8 IIH Logic input current high - 0.1 1.0 µA VIH = VDD IIL Logic input current low - -0.1 -1.0 µA VIL = 0V V V IOH = -25mA VDD = 5.0V, IOH = -20µA IOL = 1.0mA IOL = 20µA Note: The total number of ON outputs times the duty cycle must not exceed the allowable package power disspation. Switching Characteristics (V PP = 80V, CL = 50pF, TA = 25°C, unless otherwise noted) Sym Parameter Max Unit td Delay time, clock to data output 600 ns Turn-on time when high voltage is enabled from latch enable 1.5 tDHL from strobe 1.0 Delay time, high-to-low-level, HV output from latch enable 1.5 tDLH from strobe 1.0 tTHL Transition time, high-to-low-level, HV output 3.0 µs VDD = 4.5V, See Figure 3 tTLH Transition time, low-to-high-level, HV output 2.5 µs VDD = 4.5V, See Figure 3 µs VDD = 4.5V, CL = 15pF, See Figure 1 VDD = 4.5V, See Figure 2 VDD = 4.5V, See Figure 3 µs 3 Conditions VDD = 4.5V, See Figure 2 VDD = 4.5V, See Figure 3 HV518 Power-Up/ Power-Down Sequences Power-up sequence should be the following: 1. 2. 3. 4. 5. Connect ground. Apply VDD. Set all inputs (Data, CLK, Enable, etc.) to a known state. Apply VPP. The VPP should not drop below VDD or float during operation. Power-down sequence should be the reverse of the above. Input and Output Equivalent Circuits VDD VDD VPP DATA OUT INPUT GND HVOUT GND GND Parameter Measurement Information t w(CKH) t w(CKH) V IH Clock 50% V IH Clock 50% V IL V IL t w(CKL) t su td th V IH V OH Data Output Data In 50% V OL V IL Figure 1 Input Timing Voltage Waveforms V IH Latch Enable V IH 50% Strobe 50% V IL V IL t DLH t DHL t DLH or t DHL 90% V OH 90% HV Output 10% HV Output 10% V OL t TLH V OH V OL t THL Figure 3: Input Timing Voltage Waveforms Figure 2 Note: For testing purposes, all input pulses have maximum rise and fall times of 30 nsec. 4 HV518 Truth Tables Output Input Data Out Data In LE STB HV Outputs H H X X H All Low L L H H L High * L H L Low X L L * Data In X CLK No Change * Previous state. * Previous state. Typical Operating Sequence Clock ● ● ● Data In SR Contents VALID IRRELEVANT INVALID VALID Latch Enable Latch Contents PREVIOUSLY STORED DATA NEW DATA VALID Strobe HV Output VALID 5 HV518 Pin Descriptions 40-Lead PDIP (P) Pin Function Pin Function Pin Function 1 VPP 15 HVOUT20 29 HVOUT10 2 Serial Out 16 HVOUT19 30 HVOUT9 3 HVOUT32 17 HVOUT18 31 HVOUT8 4 HVOUT31 18 HVOUT17 32 HVOUT7 5 HVOUT30 19 Strobe 33 HVOUT6 6 HVOUT29 20 GND 34 HVOUT5 7 HVOUT28 21 Clock 35 HVOUT4 8 HVOUT27 22 LE 36 HVOUT3 9 HVOUT26 23 HVOUT16 37 HVOUT2 10 HVOUT25 24 HVOUT15 38 HVOUT1 11 HVOUT24 25 HVOUT14 39 Data In 12 HVOUT23 26 HVOUT13 40 VDD 13 HVOUT22 27 HVOUT12 14 HVOUT21 28 HVOUT11 Function Pin Function Pin Function 1 VPP 16 HVOUT20 31 HVOUT12 2 Serial Out 17 HVOUT19 32 HVOUT11 3 HVOUT32 18 N/C 33 HVOUT10 4 HVOUT31 19 HVOUT18 34 HVOUT9 5 HVOUT30 20 HVOUT17 35 HVOUT8 6 NC 21 Strobe 36 HVOUT7 7 HVOUT29 22 GND 37 HVOUT6 8 HVOUT28 23 Clock 38 HVOUT5 9 HVOUT27 24 LE 39 HVOUT4 10 HVOUT26 25 HVOUT16 40 HVOUT3 11 HVOUT25 26 HVOUT15 41 HVOUT2 12 HVOUT24 27 HVOUT14 42 HVOUT1 13 HVOUT23 28 N/C 43 Data In 14 HVOUT22 29 N/C 44 VDD 15 HVOUT21 30 HVOUT13 44-Lead PLCC (PJ) Pin 6 HV518 40-Lead PDIP (.600in Row Spacing) Package Outline (P) D 40 E1 Note 1 (Index Area) E B1 1 D1 D1 B Top View View B View B A Seating Plane A A2 A1 L eA eB e A Front View View AA Note 1: A Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. Symbol Dimension (inches) A A1 A2 MIN .140 .015 .125 NOM - - - MAX .250 .125 .195 eA .600 BSC B B1 eB D D1 E E1 .014 .030 .600 1.980 .005 .600 0.485 - - - - - - - .022 .070 .700 2.095 .625 .625 0.580 JEDEC Registration MS-011, Variation AC, Issue B, June, 1988. Drawings not to scale. 7 e L .115 .100 BSC .200 HV518 44-Lead PLCC Package Outline (PJ) .653x.653in body, .180in height (max.), .050in pitch D D1 1 44 .048/.042 x 45O 6 .056/.042 x 45O 40 .150 MAX Note 1 (Index Area) .075 MAX E1 E Note 2 (3 places) 0.20max 3 Places Top View Side View View B b1 A Base Plane A2 .020 MIN Seating Plane e A1 b Side View View B Note: 1. A Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. 2. Exact shape of this feature is optional. Symbol Dimension (inches) A A1 A2 b b1 D D1 E E1 MIN .165 .090 .062 .013 .026 .685 .650 .685 .650 NOM .172 .105 - - - .690 .653 .690 .653 MAX .180 .120 .083 .021 .036 .695 .656 .695 .656 e .050 BSC JEDEC Registration MS-018, Variation AC, Issue A, June, 1993. Drawings are not to scale. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV518 A091007 8