HV57708 32MHz, 64-Channel Serial to Parallel Converter with Push-Pull Outputs General Description Features ► ► ► ► ► ► ► ► ► HVCMOS® technology 5.0V CMS Logic Output voltage up to +80V Low power level shifting 32MHz equivalent data rate Latched data outputs Foreward and reverse shifting options (DIR pin) Diode to VPP allows efficient power recovery Outputs may be hot switched General Description The HV57708 is a low voltage serial to high voltage parallel converter with push-pull outputs. The device has been designed for use as a driver for EL displays. It can also be used in any application requiring multiple output high voltage current sourcing and sinking capability such as driving plasma panels, vacuum fluorescent displays, or large matrix LCD displays. The device has 4 parallel 16-bit registers, permitting data rates 4x the speed of one (they are clocked together). There are also 64 latches and control logic to perform the polarity select and blanking of the outputs. HVOUT1 is connected to the first stage of the first shift register through the polarity and blanking logic. Data is shifted through the shift registers on the logic low to high transition of the clock. The DIR pin causes CCW shifting when connected to GND, and CW shifting when connected to VDD. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register (HVOUT64). Operation of the shift register is not affected by the LE (latch enable), BL (blanking), or the POL (polarity) inputs. Transfer of data from the shift registers to the latches occurs when the LE input is high. The data in the latches is stored when the LE is low. Functional Block Diagram DO 1 DO 2 D I4 D I3 DO 3 D O4 D I2 D I1 V DD LE BL POL V PP HVOUT 1 5 9 • • • HVOUT61 DIR SR1 HVOUT 2 6 10 • • • HVOUT62 SR2 CLK HVOUT 3 7 11 • • • HVOUT63 SR3 HVOUT 4 8 12 • • • HVOUT64 SR4 D O4 D O3 DI 1 DI 2 D O2 DI 3 D O1 DI 4 GND Note: Each SR (shift register) provides 16 outputs. SR1 supplies every fourth output starting with 1; SR2 supplies every fourth output with 2, etc. HV57708 Ordering Information Package Options Device 80-Lead PQFP HV57708 HV57708PG-G -G indicates package is RoHS compliant (‘Green’) Pin Configuration Absolute Maximum Ratings Parameter Value Supply voltage, VDD -0.5V to +7.5V Output voltage , VPP -0.5V to +90V Logic input levels -0.3V to VDD + 0.3V Ground current(1) 1.5A Continuous total power dissipation(2) Operating temperature range Storage temperature range 1200mW -40°C to +85°C -65°C to +150°C Lead temperature 1.6mm from case for 10 seconds 80 260°C 1 80-Lead PQFP (PG) (top view) Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Product Marking Top Marking Notes: 1. Limited by the total dissipated in the package. 2. For operation above 25°C ambient derate linearly to maximum operating temperature at 20mW/°C. YYWW HV57708PG LLLLLLLLLL Bottom Marking CCCCCCCC AAA YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking 80-Lead PQFP (PG) Recommended Operating Conditions Symbol Parameter Min Max Units VDD Logic supply voltage 4.5 5.5 V VPP Output voltage 8.0 80 V VIH High-level input voltage VDD - 0.5V - V VIL Low-level input voltage 0 0.5 V fCLK Clock frequency per register - 8.0 MHz TA Operating free-air temperature -40 +85 °C Notes: Power-up sequence should be the following*: 1. Apply ground 2. Apply VDD 3. Set all inputs (DIN, CLK, LE , POL, etc.) to a known state 4. Apply VPP 5. The VPP should not drop below VDD or float during operation Power-down sequence should be the reverse of the above 2 HV57708 DC Electrical Characteristics (Over operating supply voltages and temperature, unless otherwise noted) Symbol Parameter Min Max Units Conditions - 15 mA VDD = VDD max, fCLK = 8MHz - 100 µA Outputs high - 100 µA Outputs low - 100 µA All VIN = VDD 65 - V IO = -15mA, VPP = +80V VDD - 0.5V - V IO = -100µA HVOUT - 7.0 V IO = 12mA, VPP = +80V DOUT - 0.5 V IO = 100µA IDD VDD supply current IPP High voltage supply current IDDQ Quiescent VDD supply current VOH High level output VOL Low level output IIH High-level logic input current - 1.0 µA VIH = VDD IIL Low-level logic input current - -1.0 µA VIL = 0V High voltage clamp diode - 1.0 V IOC = 1.0mA VOC HVOUT DOUT AC Electrical Characteristics (T A Symbol Min Max Units Conditions - 8 MHz Per register Clock width high or low 62 - ns --- tSU Data set-up time before clock rises 10 - ns --- tH Data hold time after clock rises 15 - ns --- tON, tOFF Time from latch enable to HVOUT - 500 ns CL = 15pF tDHL Delay time clock to data high to low - 70 ns CL = 15pF tDLH Delay time clock to data low to high - 70 ns CL = 15pF tDLE* Delay time clock to LE low to high 25 - ns --- tWLE LE pulse width 25 - ns --- tSLE LE set-up time before clock rises 0 - ns --- fCLK tWL, tWH Parameter = 85°C max. Logic signal inputs and Data inputs have tr, tf ≤ 5ns [10% and 90% points]) Clock frequency * tDLE is not required but is recommended to produce stable HV outputs and thus minimize power dissipation and current spikes (allows internal SR output to stabilize). 3 HV57708 Input and Output Equivalent Circuits V DD V DD V PP Data Out Input HVOUT GND GND GND Logic Data Output Logic Inputs High Voltage Outputs Switching Waveforms VIH Data Input 50% Data Valid 50% VIL tSU Clock 50% tf tH 90% 50% 50% tWL tr VIH 10% 10% 90% 50% VIL tWH VOH 50% VOL tDLH Data Out VOH 50% VOL tDHL VIH 50% 50% Latch Enable VOL tDLE tWLE tSLE 90% 10% HVOUT w/ S/R LOW VOH VOL tOFF HVOUT w/ S/R HIGH 10% tON 4 90% VOH VOL HV57708 Function Table Inputs Function Outputs Data CLK LE BL POL DIR Shift Reg HV Outputs Data Out All O/P high X X X L L X - H - All O/P low X X X L H X - L - O/P normal X X X H H X - No inversion - O/P inverted X X H L X - Inversion - H H H X L L - H H H X H H - H H L X L H - H X _ _↑ _ _↑ _ _↑ _ _↑ H H L X H L - X X L H H X * Stored Data - X X _ _↑ _ _↑ _ _↑ _ _↑ L H L X * Inversion of stored data - H H H H Qn→Qn+1 New H or L DI/O1-4B L H H H Qn→Qn+1 Previous H or L DI/O1-4B L H H L Qn→Qn-1 Previous H or L DI/O1-4A H H H L Qn→Qn-1 New H or L DI/O1-4A Data falls through (latches transparent) Data stored/ latches loaded L H L DI/O1-4A I/O relation DI/O1-4A DI/O1-4B DI/O1-4B Note: * = data at the last CLK ↑ Shift Register Operation HV OUT 32 DIR = H; CW (HVOUT1 → HVOUT64) HOUT 33 DIR = L; CCW (HVOUT64 → HVOUT1) • • DIR = H DIR = L • • 1 SR1 4 2 SR2 3 3 SR3 2 4 SR4 1 • • • • • • HV OUT 2 HOUT 63 HV OUT 1 HOUT 64 Pin 25 26 27 28 36 37 38 39 5 HV57708 Pin Function HVOUT24/41 Pin # 21 HVOUT4/61 Pin # 41 HVOUT64/1 Pin # 61 HVOUT44/21 2 HVOUT23/42 22 HVOUT3/62 42 HVOUT63/2 62 HVOUT43/22 3 HVOUT22/43 23 HVOUT2/63 43 HVOUT62/3 63 HVOUT42/23 4 HVOUT21/44 24 HVOUT1/64 44 HVOUT61/4 64 HVOUT41/24 5 HVOUT20/45 25 DIN1/DOUT4(A) 45 HVOUT60/5 65 HVOUT40/25 6 HVOUT29/46 26 DIN2/DOUT3(A) 46 HVOUT59/6 66 HVOUT39/26 7 HVOUT18/47 27 DIN3/DOUT2(A) 47 HVOUT58/7 67 HVOUT38/27 8 HVOUT17/48 28 DIN4/DOUT1(A) 48 HVOUT57/8 68 HVOUT37/28 9 HVOUT16/49 29 LE 49 HVOUT56/9 69 HVOUT36/29 10 HVOUT15/50 30 CLK 50 HVOUT55/10 70 HVOUT35/30 11 HVOUT14/51 31 BL 51 HVOUT54/11 71 HVOUT34/31 12 HVOUT13/52 32 VDD 52 HVOUT53/12 72 HVOUT33/32 13 HVOUT12/53 33 DIR 53 HVOUT52/13 73 HVOUT32/33 14 HVOUT11/54 34 GND 54 HVOUT51/14 74 HVOUT31/34 15 HVOUT10/55 35 POL 55 HVOUT50/15 75 HVOUT30/35 16 HVOUT9/56 36 DOUT4/DIN1(B) 56 HVOUT49/16 76 HVOUT29/36 17 HVOUT8/57 37 DOUT3/DIN2(B) 57 HVOUT48/17 77 HVOUT28/37 18 HVOUT7/58 37 DOUT2/DIN3(B) 58 HVOUT47/18 78 HVOUT27/38 19 HVOUT6/59 39 DOUT1/DIN4(B) 59 HVOUT46/19 79 HVOUT26/39 20 HVOUT5/60 40 VPP 60 HVOUT45/20 80 HVOUT25/40 Pin # 1 Function Function Note: Pin designation for DIR = H/L. Example: For DIR = H, pin 41 is HVOUT64. For DIR = L, pin 41 is HVOUT1. For CW/CCW Shift see function table QN → QN+1. 6 Function Function HV57708 80-Lead PQFP Package Outline (PG) 20x14mm body, 0.80mm pitch D D1 θ1 E Note 1 (Index Area D1/4 x E1/4) E1 Gauge Plane L2 80 1 e L L1 b Seating Plane θ Top View View B View B A A2 Seating Plane A1 Side View Note 1: A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. Symbol MIN Dimension (mm) A A1 A2 b D D1 E E1 2.80 0.25 2.55 0.30 23.65 19.80 17.65 13.80 NOM MAX 3.40 - 2.80 3.05 0.45 23.90 24.15 20.00 20.20 17.90 18.15 14.00 14.20 e L L1 L2 0.80 BSC 0.88 1.03 θ θ1 0O 0.73 1.95 REF 0.25 BSC O 3.5 O 7 5O 16O JEDEC Registration MO-112, Variation CB-1, Issue B, Sept.1995. Drawings not to scale. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV57708 A083107 7