SUTEX HV9113 High-voltage current-mode pwm controller Datasheet

HV9110
HV9112
HV9113
High-Voltage Current-Mode PWM Controller
Ordering Information
+VIN
Min
Max
Feedback
Accuracy
Max
Duty Cycle
20 Pin
Plastic PLCC
HV9110PJ
Package Options
14 Pin
Narrow Body SOIC
HV9110NG
HV9110X
10V
120V
< ± 1%
49%
14 Pin
Plastic DIP
HV9110P
9.0V
80V
± 2%
49%
HV9112P
HV9112PJ
HV9112NG
HV9112X
10V
120V
< ± 1%
99%
HV9113P
HV9113PJ
HV9113NG
HV9113X
Die
Standard temperature range for all parts is industrial (-40° to +85°C).
Features
General Description
❏
10 to 120V input range
❏
Current-mode control
❏
High efficiency
❏
Up to 1.0MHz internal oscillator
The Supertex HV9110 through HV9113 are a series of BiCMOS/
DMOS single-output, pulse width modulator ICs intended for use
in high-speed high-efficiency switchmode power supplies. They
provide all the functions necessary to implement a single-switch
current-mode PWM, in any topology, with a minimum of external
parts.
❏
Internal start-up circuit
❏
Low internal noise
Because they utilize Supertex’s proprietary BiCMOS/DMOS technology, they require less than one tenth of the operating power of
conventional bipolar PWM ICs, and can operate at more than
twice their switching frequency. Dynamic range for regulation is
also increased, to approximately 8 times that of similar bipolar
parts. They start directly from any DC input voltages between 10
and 120VDC, requiring no external power resistor. The output
stage is push-pull CMOS and thus requires no clamping diodes
for protection, even when significant lead length exists between
the output and the external MOSFET. The clock frequency is set
with a single external resistor.
Applications
❏
DC/DC converters
❏
Distributed power systems
❏
ISDN equipment
❏
PBX systems
❏
Modems
Accessory functions are included to permit fast remote shutdown
(latching or nonlatching) and undervoltage shutdown.
For similar ICs intended to operate directly from up to 450VDC
input, please consult the data sheet for the HV9120/9123.
Absolute Maximum Ratings
+VIN, Input Voltage
HV9110/9113
HV9112
VDD, Logic Voltage
Logic Linear Input, FB and
Sense Input Voltage
Storage Temperature
Power Dissipation, SOIC
120V
80V
15.5V
-0.3V to VDD+0.3V
-65°C to 150°C
750mW
Power Dissipation, Plastic DIP
1000mW
Power Dissipation PLCC
1400mW
For detailed circuit and application information, please refer
to application notes AN-H13 and AN-H21 to AN-H24.
11/12/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
1
HV9110/HV9112/HV9113
Electrical Characteristics
(Unless otherwise specified, VDD = 10V, +VIN = 48V, Discharge = -VIN = 0V, RBIAS = 390KΩ, ROSC = 330KΩ,TA = 25°C.)
Symbol Parameters
Min
Typ
Max
Unit
Conditions
HV9110/13
3.92
4.00
4.08
V
RL = 10MΩ
HV9112
3.88
4.00
4.12
HV9110/13
3.82
4.00
4.16
Reference
VREF
Output Voltage
RL = 10MΩ,
TA = -55°C to 125°C
Impedance1
ZOUT
Output
ISHORT
Short Circuit Current
∆VREF
15
Change in VREF with
Temperature1
30
45
KΩ
125
250
µA
VREF = -VIN
0.25
mV/°C
TA = -55°C to 125°C
MHz
ROSC = 0Ω
KHz
ROSC = 330KΩ
Oscillator
fMAX
Oscillator Frequency
1.0
3.0
fOSC
Accuracy2
80
100
120
160
200
240
Initial
Voltage Stability
Temperature
15
Coefficient1
170
ROSC = 150KΩ
%
ppm/°C
9.5V < VDD <13.5V
TA = -55°C to 125°C
PWM
DMAX
Maximum Duty Cycle1
HV9110/12
HV9113
Deadtime1
DMIN
49.0
49.4
49.6
95
97
99
HV9113
225
nsec
Minimum Duty Cycle
Minimum Pulse Width
Before Pulse Drops Out1
%
0
%
80
125
nsec
1.2
1.4
V
VFB = 0V
80
120
ns
VSENSE = 1.5V, VCOMP ≤ 2.0V
V
VFB Shorted to Comp
nA
VFB = 4.0V
Current Limit
Maximum Input Signal
td
Delay to
1.0
Output1
Error Amplifier
VFB
Feedback Voltage
IIN
Input Bias Current
VOS
Input Offset Voltage
AVOL
GB
Open Loop Voltage
Unity Gain
HV9110/13
3.96
4.00
4.04
HV9112
3.92
4.00
4.08
25
500
nulled during trim
Gain1
Bandwidth1
except HV9111
60
80
dB
1.0
1.3
MHz
see Fig. 1
Ω
Impedance1
ZOUT
Output
ISOURCE
Output Source Current
-1.4
-2.0
mA
VFB = 3.4V
ISINK
Output Sink Current
0.12
0.15
mA
VFB = 4.5V
see Fig. 2
dB
PSRR
Power Supply
Rejection1
Notes:
1. Guaranteed by design. Not subject to production test.
2. Stray capacitance on OSC In pin must be ≤5pF.
2
HV9110/HV9112/HV9113
Electrical Characteristics
(continued)
(Unless otherwise specified, VDD = 10V, +VIN = 48V, Discharge = -VIN = 0V, RBIAS = 390KΩ, ROSC = 330KΩ,TA = 25°C.)
Symbol Parameters
Min
Typ
Max
Unit
Conditions
HV9110/13
120
V
IIN < 10µA; VCC > 9.4V
HV9112
80
10
µA
VDD > 9.4V
IPREREG = 10µA
Pre-regulator/Startup
+VIN
Input Voltage
+IIN
Input Leakage Current
VTH
VDD Pre-regulator Turn-off Threshold Voltage
8.0
8.7
9.4
V
VLOCK
Undervoltage Lockout
7.0
8.1
8.9
V
1.0
mA
CL < 75pF
Shutdown = -VIN
Supply
IDD
Supply Current
0.75
IQ
Quiescent Supply Current
0.55
mA
IBIAS
Nominal Bias Current
20
µA
VDD
Operating Range
9.0
13.5
V
100
ns
Shutdown Logic
tSD
Shutdown Delay1
tSW
Shutdown Pulse Width1
50
ns
tRW
RESET Pulse Width1
50
ns
tLW
Latching Pulse Width1
25
ns
VIL
Input Low Voltage
VIH
Input High Voltage
IIH
Input Current, Input Voltage High
1.0
5.0
µA
VIN = VDD
IIL
Input Current, Input Voltage Low
-25
-35
µA
VIN = 0V
V
IOUT = 10mA
50
2.0
7.0
CL = 500pF, VSENSE = -VIN
Shutdown and reset low
V
V
Output
VOH
VOL
ROUT
tR
tF
Output High Voltage
Output Low Voltage
Output Resistance
Rise
Fall
HV9110/13
VDD -0.25
HV9112
VDD -0.3
HV9110/13
VDD -0.3
IOUT = 10mA,
TA = -55°C to 125°C
All
0.2
HV9110/13
0.3
V
IOUT = -10mA
IOUT = -10mA,
TA = -55°C to 125°C
Ω
IOUT = ±10mA
Ω
IOUT = ±10mA,
Pull Up
15
25
Pull Down
8.0
20
Pull Up
20
30
Pull Down
10
30
30
75
ns
CL = 500pF
20
75
ns
CL = 500pF
Time1
Time1
Note:
1. Guaranteed by design. Not subject to production test.
3
TA = -55°C to 125°C
HV9110/HV9112/HV9113
Truth Table
Shutdown
Reset
Output
H
H
H
H→L
L
H
Off, Not Latched
L
L
Off, Latched
L→H
L
Off, Latched, No Change
Normal Operation
Normal Operation, No Change
Shutdown Timing Waveforms
1.5V
tF ≤ 10ns
VDD
tR ≤ 10ns
50%
Sense
50%
Shutdown
0
0
td
t SD
VDD
Output
VDD
90%
Output
0
90%
0
t SW
VDD
50%
Shutdown
tR, tF ≤ 10ns
50%
0
t LW
VDD
Reset
50%
50%
50%
0
t RW
Functional Block Diagram
FB
COMP
14
(19)
Discharge
13
(18)
9
(12)
OSC
In
OSC
Out
8 (11)
7 (10)
Error
Amplifier
OSC
–
10 (14)
+
VREF
2V
Modulator
Comparator
–
4V
9113
+
Current
Sources
Output
9110
9112
5 (8)
Current Limit
Comparator
–
1 (20)
4 (6)
Q
S
To
Internal
Circuits
To V DD
Q
R
+
REF
GEN
BIAS
T
-V IN
1.2V
3 (5)
Current Sense
V DD
6 (9)
VDD
2 (3)
–
+V IN
11 (16)
Undervoltage
Comparator
Shutdown
S
Q
8.1V
–
+
+
Reset
R
12 (17)
8.6V
Pre-regulator/Startup
Pin numbers in parentheses are for PLCC package
4
HV9110/HV9112/HV9113
Typical Performance Curves
Fig. 1
Fig. 4
Error Amplifier Output Impedance (Z0)
1M
6
10
Output Switching Frequency
vs. Oscillator Resistance
105
104
fOUT (Hz)
HV9113
ZO (Ω)
3
10
2
10
100k
HV9110, 9111, 9112
10
1
.1
1KHz
100KHz
10KHz
1MHz
10k
10k
10MHz
100 k
Frequency
ROSC (Ω)
PSRR — Error Amplifier and Reference
Fig. 2
Fig. 5
0
80
-10
70
-20
Gain (dB)
-30
PSSR (dB)
1M
-40
-50
-60
-70
Error Amplifier
Open Loop Gain/Phase
60
180
50
120
40
60
30
0
20
-60
10
-120
0
-180
-10
-80
10
100
1K
10K
100K
1M
100
1K
100K
10K
1M
Frequency (Hz)
Frequency (Hz)
RDISCHARGE vs. tOFF (9113 only)
100
Fig. 6
104
ROSC = 100K
VDD = 12V
VDD = 10V
tOFF (nsec)
Bias Current (µA)
Fig. 3
10
103
ROSC = 10K
ROSC = 1K
1
105
106
102
10-1
107
100
101
102
103
RDISCHARGE (Ω)
Bias Resistance (Ω)
5
104
105
106
Phase (°C)
100Hz
HV9110/HV9112/HV9113
Test Circuits
PSRR
Error Amp ZOUT
0.1V swept 10Hz – 1MHz
+10V
(VDD)
1.0V swept 100Hz – 2.2MHz
100K1%
60.4K
–
(FB)
Reference
GND
(–VIN)
100K1%
10.0V
+
V1
Tektronix
P6021
(1 turn
secondary)
4.00V
V2
Reference
40.2K
0.1µF
V1
–
+
V2
0.1µF
NOTE: Set Feedback Voltage so that
VCOMP = VDIVIDE ± 1mV before connecting transformer
Detailed Description
Preregulator
the 50% maximum duty cycle versions, a frequency dividing flipflop. A single external resistor between the OSC In and OSC Out
pins is required to set oscillator frequency (see graph). For the
50% maximum duty cycle versions the Discharge pin is internally
connected to GND. For the 99% duty cycle version, the discharge
pin can either be connected to VSS directly or connected to VSS
through a resistor used to set a deadtime.
The preregulator/startup circuit for the HV911X consists of a highvoltage n-channel depletion-mode DMOS transistor driven by an
error amplifier to form a variable current path between the VIN
terminal and the VDD terminal. Maximum current (about 20 mA)
occurs when VDD = 0, with current reducing as VDD rises. This path
shuts off altogether when VDD rises to somewhere between 7.8
and 9.4V, so that if VDD is held at 10 or 12V by an external source
(generally the supply the chip is controlling). No current other than
leakage is drawn through the high voltage transistor. This minimizes dissipation.
One difference exists between the Supertex HV911X and competitive 911X’s: On the Supertex part the oscillator is shut off
when a shutoff command is received. This saves about 150µA of
quiescent current, which aids in the construction of power supplies to meet CCITT specification I-430, and in other situations
where an absolute minimum of quiescent power dissipation is
required.
An external capacitor between VDD and VSS is generally required
to store energy used by the chip in the time between shutoff of the
high voltage path and the VDD supply’s output rising enough to
take over powering the chip. This capacitor should have a value
of 100X or more the effective gate capacitance of the MOSFET
being driven, i.e.,
Reference
Cstorage ≥ 100 x (gate charge of FET at 10V ÷ 10V)
The Reference of the HV911X consists of a stable bandgap
reference followed by a buffer amplifier which scales the voltage
up to approximately 4.0V. The scaling resistors of the reference
buffer amplifier are trimmed during manufacture so that the output
of the error amplifier when connected in a gain of –1 configuration
is as close to 4.000V as possible. This nulls out any input offset
of the error amplifier. As a consequence, even though the observed reference voltage of a specific part may not be exactly
4.0V, the feedback voltage required for proper regulation will be.
as well as very good high frequency characteristics. Stacked
polyester or ceramic caps work well. Electrolytic capacitors are
generally not suitable.
A common resistor divider string is used to monitor VDD for both
the undervoltage lockout circuit and the shutoff circuit of the high
voltage FET. Setting the undervoltage sense point about 0.6V
lower on the string than the FET shutoff point guarantees that the
undervoltage lockout always releases before the FET shuts off.
A ≈50KΩ resistor is placed internally between the output of the
reference buffer amplifier and the circuitry it feeds (reference
output pin and non-inverting input to the error amplifier). This
allows overriding the internal reference with a low-impedance
voltage source ≤6.0V. Using an external reference reinstates the
input offset voltage of the error amplifier, and its effect of the exact
value of feedback voltage required.
Bias Circuit
An external bias resistor, connected between the bias pin and VSS
is required by the HV911X to set currents in a series of current
mirrors used by the analog sections of the chip. Nominal external
bias current requirement is 15 to 20µA, which can be set by a
390KΩ to 510KΩ resistor if a 10V VDD is used, or a 510kΩ to
680KΩ resistor if VDD will be 12V. A precision resistor is not
required; ± 5% is fine.
Because the reference of the 911X is a high impedance node, and
usually there will be significant electrical noise near it, a bypass
capacitor between the reference pin and VSS is strongly recommended. The reference buffer amplifier is intentionally compensated to be stable with a capacitive load of 0.01 to 0.1µF.
Clock Oscillator
The clock oscillator of the HV911X consists of a ring of CMOS
inverters, timing capacitors, a capacitor discharge FET, and, in
6
HV9110/HV9112/HV9113
Detailed Description (continued)
Error Amplifier
Remote Shutdown
The error amplifier in the HV911X is a true low-power differential
input operational amplifier intended for around-the-amplifier compensation. It is of mixed CMOS-bipolar construction: A PMOS
input stage is used so the common-mode range includes ground
and the input impedance is very high. This is followed by bipolar
gain stages which provide high gain without the electrical noise of
all-MOS amplifiers. The amplifier is unity-gain stable.
The shutdown and reset pins of the 911X can be used to perform
either latching or non-latching shutdown of a converter as required. These pins have internal current source pull-ups so they
can be driven from open-drain logic. When not used they should
be left open, or connected to VDD.
Current Sense Comparators
The output buffer of the HV911X is of standard CMOS construction (P-channel pull-up, N-channel pull-down). Thus the bodydrain diodes of the output stage can be used for spike clipping if
necessary, and external Schottky diode clamping of the output is
not required.
Output Buffer
The HV911X uses a true dual comparator system with independent comparators for modulation and current limiting. This allows
the designer greater latitude in compensation design, as there are
no clamps (except ESD protection) on the compensation pin. Like
the error amplifier, the comparators are of low-noise BiCMOS
construction.
Sense
3
12
Reset
Output
4
11
Shutdown
–VIN
5
10
VREF
VDD
6
9
Discharge
OSC Out
7
8
OSC In
14 Pin SOIC/DIP Package
VREF
COMP
18
17
16
15
14
FB
19
13
NC
BIAS
20
12
Discharge
NC
1
11
OSC In
NC
2
10
OSC Out
+VIN
3
9
VDD
•
NC
4
5
6
7
8
–VIN
13
NC
2
NC
+VIN
Shutdown
FB
Output
14
Reset
1
Sense
BIAS
COMP
Pinout
20-pin PJ Package
top view
11/12/01
©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
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