ETC1 HX6356XSFT 32k x 8 static ram-soi Datasheet

Aerospace Electronics
32K x 8 STATIC RAM—SOI
HX6356
FEATURES
RADIATION
OTHER
• Fabricated with RICMOS™ IV Silicon on Insulator (SOI)
0.75 µm Process (Leff = 0.6 µm)
• Listed On SMD# 5962-95845
• Total Dose Hardness through 1x106 rad(SiO2)
• Fast Read/Write Cycle Times
≤ 17 ns (Typical)
≤ 25 ns (-55 to 125°C)
• Neutron Hardness through 1x1014 cm-2
• Typical Operating power < 15 mW/MHz
• Dynamic and Static Transient Upset Hardness
through 1x1011 rad(Si)/s
• Asynchronous Operation
• Dose Rate Survivability through 1x1012 rad(Si)/s
• CMOS or TTL Compatible I/O
• Soft Error Rate of <1x10-10 upsets/bit-day
in Geosynchronous Orbit
• Single 5 V ± 10% Power Supply
• Latchup Free
GENERAL DESCRIPTION
The 32K x 8 Radiation Hardened Static RAM is a high
performance 32,768 word x 8-bit static random access
memory with industry-standard functionality. It is fabricated
with Honeywell’s radiation hardened technology, and is
designed for use in systems operating in harsh, transient
radiation environments. The RAM operates over the full
military temperature range and requires only a single 5 V ±
10% power supply. The RAM is available with either TTL or
CMOS compatible I/O. Power consumption is typically less
than 15 mW/MHz in operation, and less than 5 mW when
de-selected. The RAM read operation is fully asynchronous, with an associated typical access time of 14 ns at 5V.
Honeywell’s enhanced SOI RICMOS™ IV (Radiation Insensitive CMOS) technology is radiation hardened through the
use of advanced and proprietary design, layout and process hardening techniques. The RICMOS™ IV process is a
5-volt, SIMOX CMOS technology with a 150 Å gate oxide
and a minimum drawn feature size of 0.75 µm (0.6 µm
effective gate length—Leff). Additional features include
tungsten via plugs, Honeywell’s proprietary SHARP planarization process, and a lightly doped drain (LDD) structure for improved short channel reliability. A 7 transistor
(7T) memory cell is used for superior single event upset
hardening, while three layer metal power bussing and the
low collection volume SIMOX substrate provide improved
dose rate hardening.
• Packaging Options
- 36-Lead CFP—Bottom Braze (0.630 in. x 0.650 in.)
- 36-Lead CFP—Top Braze (0.630 in. x 0.650 in.)
HX6356
FUNCTIONAL DIAGRAM
A:0-8,12-13
32,768 x 8
Memory
Array
•
•
•
Row
Decoder
11
CE
NCS
•
•
•
8
Column Decoder
Data Input/Output
NWE
8
DQ:0-7
WE • CS • CE
NOE
NWE • CS • CE • OE
(0 = high Z)
A:9-11, 14
Signal
1 = enabled
#
Signal
All controls must be
enabled for a signal to
pass. (#: number of
buffers, default = 1)
4
SIGNAL DEFINITIONS
A: 0-14
Address input pins which select a particular eight-bit word within the memory array.
DQ: 0-7
Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write
operation.
NCS
Negative chip select, when at a low level allows normal read or write operation. When at a high level NCS
forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and
disables all input buffers except CE. If this signal is not used it must be connected to VSS.
NWE
Negative write enable, when at a low level activates a write operation and holds the data output drivers in a
high impedance state. When at a high level NWE allows normal read operation.
NOE
Negative output enable, when at a high level holds the data output drivers in a high impedance state. When
at a low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must
be connected to VSS.
CE
Chip enable, when at a high level allows normal operation. When at a low level CE forces the SRAM to a
precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers
except the NCS input buffer. If this signal is not used it must be connected to VDD.
TRUTH TABLE
NCS
CE
NWE
NOE
MODE
DQ
L
H
H
L
Read
Data Out
L
H
L
X
Write
Data In
H
X
XX
XX
Deselected
High Z
X
L
XX
XX
Disabled
High Z
2
Notes:
X: VI=VIH or VIL
XX: VSS≤VI≤VDD
NOE=H: High Z output state maintained for
NCS=X, CE=X, NWE=X
HX6356
RADIATION CHARACTERISTICS
The SRAM will meet any functional or electrical specification after exposure to a radiation pulse up to the transient
dose rate survivability specification, when applied under
recommended operating conditions. Note that the current
conducted during the pulse by the RAM inputs, outputs,
and power supply may significantly exceed the normal
operating levels. The application design must accommodate these effects.
Total Ionizing Radiation Dose
The SRAM will meet all stated functional and electrical
specifications over the entire operating temperature range
after the specified total ionizing radiation dose. All electrical
and timing performance parameters will remain within
specifications after rebound at VDD = 5.5 V and T =125°C
extrapolated to ten years of operation. Total dose hardness
is assured by wafer level testing of process monitor transistors and RAM product using 10 keV X-ray and Co60
radiation sources. Transistor gate threshold shift correlations have been made between 10 keV X-rays applied at a
dose rate of 1x105 rad(SiO2)/min at T = 25°C and gamma
rays (Cobalt 60 source) to ensure that wafer level X-ray
testing is consistent with standard military radiation test
environments.
Neutron Radiation
The SRAM will meet any functional or timing specification
after exposure to the specified neutron fluence under
recommended operating or storage conditions. This assumes an equivalent neutron energy of 1 MeV.
Soft Error Rate
Transient Pulse Ionizing Radiation
The SRAM has an extremely low Soft Error Rate (SER) as
specified in the table below. This hardness level is defined
by the Adams 90% worst case cosmic ray environment.
The low SER is achieved by the use of a unique 7-transistor
memory cell and the oxide isolation of the SOI substrate.
The SRAM is capable of writing, reading, and retaining
stored data during and after exposure to a transient
ionizing radiation pulse up to the transient dose rate upset
specification, when applied under recommended operating conditions. To ensure validity of all specified performance parameters before, during, and after radiation
(timing degradation during transient pulse radiation (timing degradation during transient pulse radiation is ≤10%),
it is suggested that stiffening capacitance be placed on or
near the package VDD and VSS, with a maximum inductance between the package (chip) and stiffening capacitance of 0.7 nH per part. If there are no operate-through
or valid stored data requirements, typical circuit board
mounted de-coupling capacitors are recommended.
Latchup
The SRAM will not latch up due to any of the above radiation
exposure conditions when applied under recommended
operating conditions. Fabrication with the SIMOX substrate
material provides oxide isolation between adjacent PMOS
and NMOS transistors and eliminates any potential SCR
latchup structures. Sufficient transistor body tie connections to the p- and n-channel substrates are made to ensure
no source/drain snapback occurs.
RADIATION HARDNESS RATINGS (1)
Parameter
Limits (2)
Units
Test Conditions
Total Dose
≥1x106
rad(SiO2)
TA=25°C
Transient Dose Rate Upset
≥1x1011
rad(Si)/s
Pulse width ≤1 µs
Transient Dose Rate Survivability
≥1x1012
rad(Si)/s
Soft Error Rate
<1x10-10
upsets/bit-day
Neutron Fluence
≥1x10
14
N/cm2
(1) Device will not latch up due to any of the specified radiation exposure conditions.
(2) Operating conditions (unless otherwise specified): VDD=4.5 V to 5.5 V, -55°C to 125°C.
3
Pulse width ≤50 ns, X-ray,
VDD=6.0 V, TA=25°C
TA=125°C, Adams 90%
worst case environment
1 MeV equivalent energy,
Unbiased, TA=25°C
HX6356
ABSOLUTE MAXIMUM RATINGS (1)
Rating
Symbol
Parameter
Min
Max
Units
VDD
Positive Supply Voltage (2)
-0.5
6.5
V
VPIN
Voltage on Any Pin (2)
-0.5
VDD+0.5
V
TSTORE
Storage Temperature (Zero Bias)
-65
150
°C
TSOLDER
Soldering Temperature (5 Seconds)
270
°C
PD
Total Package Power Dissipation (3)
2.0
W
IOUT
DC or Average Output Current
25
mA
VPROT
ESD Input Protection Voltage (4)
ΘJC
Thermal Resistance (Jct-to-Case)
TJ
Junction Temperature
2000
V
2
°C/W
175
°C
– 36 FP
(1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is not
implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.
(2) Voltage referenced to VSS.
(3) RAM power dissipation (IDDSB + IDDOP) plus RAM output driver power dissipation due to external loading must not exceed this specification.
(4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab.
RECOMMENDED OPERATING CONDITIONS
Description
Parameter
Symbol
Min
Typ
Max
Units
VDD
Supply Voltage (referenced to VSS)
4.5
5.0
5.5
V
TA
Ambient Temperature
-55
25
125
°C
VPIN
Voltage on Any Pin (referenced to VSS)
-0.3
VDD+0.3
V
CAPACITANCE (1)
Symbol
Parameter
Worst Case
Typical
(1)
Min
Max
Units
Test Conditions
CI
Input Capacitance
7
pF
VI=VDD or VSS, f=1 MHz
CO
Output Capacitance
9
pF
VIO=VDD or VSS, f=1 MHz
(1) This parameter is tested during initial design characterization only.
DATA RETENTION CHARACTERISTICS
Symbol
Parameter
VDR
Data Retention Voltage
IDR
Data Retention Current
Typical
Worst Case (2)
(1)
Min
Max
2.5
V
500
330
(1) Typical operating conditions: TA= 25°C, pre-radiation.
(2) Worst case operating conditions: -55°C to +125°C, post total dose at 25°C.
4
Units
µA
µA
Test Conditions
NCS=VDR
VI=VDR or VSS
NCS=VDD=2.5V, VI=VDD or VSS
NCS=VDD=3.0V, VI=VDD or VSS
HX6356
DC ELECTRICAL CHARACTERISTICS
Symbol
Typical Worst Case (2)
Units
(1)
Min
Max
Parameter
Test Conditions
0.2
1.5
mA
VIH=VDD, IO=0
VIL=VSS, f=0MHz
IDDSBMF Standby Supply Current - Deselected
0.2
1.5
mA
IDDOPW
Dynamic Supply Current, Selected (Write)
3.4
4.0
mA
IDDOPR
Dynamic Supply Current, Selected (Read)
2.8
4.0
mA
NCS=VDD, IO=0,
f=40 MHz
f=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS (3)
f=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS (3)
II
Input Leakage Current
-1
+1
µA
VSS≤VI≤VDD
IOZ
Output Leakage Current
-1
+1
µA
VSS≤VIO≤VDD
Output=high Z
VIL
Low-Level Input Voltage
V
V
March Pattern
VDD = 4.5V
V
V
March Pattern
VDD = 5.5V
IDDSB1
VIH
VOL
VOH
Static Supply Current
High-Level Input Voltage
CMOS
TTL
1.7
CMOS
TTL
3.2
0.3xVDD
0.8
0.7xVDD
2.2
Low-Level Output Voltage
0.3
0.4
V
0.005
0.1
V
VDD = 4.5V, IOL = 10 mA (CMOS)
= 8 mA (TTL)
VDD = 4.5V, IOL = 200 µA
V
V
VDD = 4.5V, IOH = -5 mA
VDD = 4.5V, IOH = -200 µA
4.3
4.5
High-Level Output Voltage
4.2
VDD-0.1
(1) Typical operating conditions: VDD= 5.0 V,TA=25°C, pre-radiation.
(2) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55°C to +125°C, post total dose at 25°C.
(3) All inputs switching. DC average current.
2.9 V
Vref1
+
-
Valid high
output
249Ω
DUT
output
Vref2
+
-
Valid low
output
CL >50 pF*
*CL = 5 pF for TWLQZ, TSHQZ, TELQZ, and TGHQZ
Tester Equivalent Load Circuit
5
HX6356
READ CYCLE AC TIMING CHARACTERISTICS (1)
Worst Case (3)
Symbol
Parameter
Typical (2)
Units
Min
Max
TAVAVR
Address Read Cycle Time
17
25
ns
TAVQV
Address Access Time
14
TAXQX
Address Change to Output Invalid Time
9
TSLQV
Chip Select Access Time
17
TSLQX
Chip Select Output Enable Time
10
TSHQZ
Chip Select Output Disable Time
4
10
ns
TEHQV
Chip Enable Access Time (4)
17
25
ns
TEHQX
Chip Enable Output Enable Time (4)
10
TELQZ
Chip Enable Output Disable Time (4)
4
10
ns
TGLQV
Output Enable Access Time
4
9
ns
TGLQX
Output Enable Output Enable Time
4
TGHQZ
Output Enable Output Disable Time
2
25
3
ns
ns
25
5
ns
ns
5
ns
0
ns
9
ns
(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V, input and
output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading CL >50 pF, or equivalent
capacitive output loading CL=5 pF for TSHQZ, TELQZ TGHQZ. For CL >50 pF, derate access times by 0.02 ns/pF (typical).
(2) Typical operating conditions: VDD=5.0 V, TA=25°C, pre-radiation.
(3) Worst case operating conditions: VDD=4.5 V to 5.5 V, post total dose at 25°C.
TAVAVR
ADDRESS
TAVQV
TSLQV
TAXQX
NCS
TSLQX
DATA OUT
TSHQZ
HIGH
IMPEDANCE
DATA VALID
TEHQX
TEHQV
CE
TELQZ
TGLQX
TGLQV
TGHQZ
NOE
(NWE = high)
6
HX6356
WRITE CYCLE AC TIMING CHARACTERISTICS (1)
Worst Case (3)
Symbol
Parameter
Typical (2)
Min
Max
Units
TAVAVW
Write Cycle Time (4)
13
25
ns
TWLWH
Write Enable Write Pulse Width
9
20
ns
TSLWH
Chip Select to End of Write Time
10
20
ns
TDVWH
Data Valid to End of Write Time
5
15
ns
TAVWH
Address Valid to End of Write Time
9
20
ns
TWHDX
Data Hold Time after End of Write Time
0
0
ns
TAVWL
Address Valid Setup to Start of Write Time
0
0
ns
TWHAX
Address Valid Hold after End of Write Time
0
0
ns
TWLQZ
Write Enable to Output Disable Time
3
0
TWHQX
Write Disable to Output Enable Time
9
5
ns
TWHWL
Write Disable to Write Enable Pulse Width(5)
4
5
ns
TEHWH
Chip Enable to End of Write Time
12
20
ns
9
ns
(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V, input and
output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading >50 pF, or equivalent capacitive
load of 5 pF for TWLQZ.
(2) Typical operating conditions: VDD=5.0 V, TA=25°C, pre-radiation.
(3) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55 to 125°C, post total dose at 25°C.
(4) TAVAVW = TWLWH + TWHWL
(5) Guaranteed but not tested.
TAVAVW
ADDRESS
TAVWH
TWHAX
TAVWL
TWHWL
TWLWH
NWE
TWLQZ
DATA OUT
TWHQX
HIGH
IMPEDANCE
TDVWH
DATA IN
DATA VALID
TSLWH
NCS
TEHWH
CE
7
TWHDX
HX6356
DYNAMIC ELECTRICAL CHARACTERISTICS
Read Cycle
Write Cycle
The RAM is asynchronous in operation, allowing the read
cycle to be controlled by address, chip select (NCS), or chip
enable (CE) (refer to Read Cycle timing diagram). To
perform a valid read operation, both chip select and output
enable (NOE) must be low and chip enable and write enable
(NWE) must be high. The output drivers can be controlled
independently by the NOE signal. Consecutive read cycles
can be executed with NCS held continuously low, and with
CE held continuously high, and toggling the addresses.
The write operation is synchronous with respect to the
address bits, and control is governed by write enable
(NWE), chip select (NCS), or chip enable (CE) edge
transitions (refer to Write Cycle timing diagrams). To perform a write operation, both NWE and NCS must be low,
and CE must be high. Consecutive write cycles can be
performed with NWE or NCS held continuously low, or CE
held continuously high. At least one of the control signals
must transition to the opposite state between consecutive
write operations.
For an address activated read cycle, NCS and CE must be
valid prior to or coincident with the activating address edge
transition(s). Any amount of toggling or skew between address edge transitions is permissible; however, data outputs
will become valid TAVQV time following the latest occurring
address edge transition. The minimum address activated
read cycle time is TAVAV. When the RAM is operated at the
minimum address activated read cycle time, the data outputs
will remain valid on the RAM I/O until TAXQX time following
the next sequential address transition.
The write mode can be controlled via three different control
signals: NWE, NCS, and CE. All three modes of control are
similar except the NCS and CE controlled modes actually
disable the RAM during the write recovery pulse. Both CE
and NCS fully disable the RAM decode logic and input
buffers for power savings. Only the NWE controlled mode
is shown in the table and diagram on the previous page for
simplicity. However, each mode of control provides the
same write cycle timing characteristics. Thus, some of the
parameter names referenced below are not shown in the
write cycle table or diagram, but indicate which control pin
is in control as it switches high or low.
To control a read cycle with NCS, all addresses and CE
must be valid prior to or coincident with the enabling NCS
edge transition. Address or CE edge transitions can occur
later than the specified setup times to NCS, however, the
valid data access time will be delayed. Any address edge
transition, which occurs during the time when NCS is low,
will initiate a new read access, and data outputs will not
become valid until TAVQV time following the address edge
transition. Data outputs will enter a high impedance state
TSHQZ time following a disabling NCS edge transition.
To write data into the RAM, NWE and NCS must be held low
and CE must be held high for at least TWLWH/TSLSH/
TEHEL time. Any amount of edge skew between the
signals can be tolerated, and any one of the control signals
can initiate or terminate the write operation. For consecutive write operations, write pulses must be separated by the
minimum specified TWHWL/TSHSL/TELEH time. Address
inputs must be valid at least TAVWL/TAVSL/TAVEH time
before the enabling NWE/NCS/CE edge transition, and
must remain valid during the entire write time. A valid data
overlap of write pulse width time of TDVWH/TDVSH/TDVEL,
and an address valid to end of write time of TAVWH/
TAVSH/TAVEL also must be provided for during the write
operation. Hold times for address inputs and data inputs
with respect to the disabling NWE/NCS/CE edge transition
must be a minimum of TWHAX/TSHAX/TELAX time and
TWHDX/TSHDX/TELDX time, respectively. The minimum
write cycle time is TAVAV.
To control a read cycle with CE, all addresses and NCS
must be valid prior to or coincident with the enabling CE
edge transition. Address or NCS edge transitions can
occur later than the specified setup times to CE; however,
the valid data access time will be delayed. Any address
edge transition which occurs during the time when CE is
high will initiate a new read access, and data outputs will
not become valid until TAVQV time following the address
edge transition. Data outputs will enter a high impedance
state TELQZ time following a disabling CE edge transition.
8
HX6356
TESTER AC TIMING CHARACTERISTICS
TTL I/O Configuration
3V
Input
Levels*
0V
VDD-0.4V
0.4 V
2.4 V
High Z = 2.9V
VDD/2
0.5 V
High Z
3.4 V
High Z
VDD-0.5 V
1.5 V
1.5 V
Output
Sense
Levels
CMOS I/O Configuration
VDD/2
VDD-0.4V
0.4 V
High Z
3.4 V
High Z
2.4 V
High Z = 2.9V
* Input rise and fall times <1 ns/V
QUALITY AND RADIATION HARDNESS
ASSURANCE
Honeywell maintains a high level of product integrity through
process control, utilizing statistical process control, a complete “Total Quality Assurance System,” a computer data
base process performance tracking system, and a radiation-hardness assurance strategy.
need to create detailed specifications and offer benefits of
improved quality and cost savings through standardization.
RELIABILITY
The radiation hardness assurance strategy starts with a
technology that is resistant to the effects of radiation.
Radiation hardness is assured on every wafer by irradiating
test structures as well as SRAM product, and then monitoring key parameters which are sensitive to ionizing radiation.
Conventional MIL-STD-883 TM 5005 Group E testing,
which includes total dose exposure with Cobalt 60, may
also be performed as required. This Total Quality approach
ensures our customers of a reliable product by engineering
in reliability, starting with process development and continuing through product qualification and screening.
Honeywell understands the stringent reliability requirements for space and defense systems and has extensive
experience in reliability testing on programs of this nature.
This experience is derived from comprehensive testing of
VLSI processes. Reliability attributes of the RICMOSTM
process were characterized by testing specially designed
irradiated and non-irradiated test structures from which
specific failure mechanisms were evaluated. These specific
mechanisms included, but were not limited to, hot carriers,
electromigration and time dependent dielectric breakdown.
This data was then used to make changes to the design
models and process to ensure more reliable products.
SCREENING LEVELS
In addition, the reliability of the RICMOSTM process and
product in a military environment was monitored by testing
irradiated and non-irradiated circuits in accelerated dynamic life test conditions. Packages are qualified for product use after undergoing Groups B & D testing as outlined
in MIL-STD-883, TM 5005, Class S. The product is qualified
by following a screening and testing flow to meet the
customer’s requirements. Quality conformance testing is
performed as an option on all production lots to ensure the
ongoing reliability of the product.
Honeywell offers several levels of device screening to meet
your system needs. “Engineering Devices” are available
with limited performance and screening for breadboarding
and/or evaluation testing. Hi-Rel Level B and S devices
undergo additional screening per the requirements of MILSTD-883. As a QML supplier, Honeywell also offers QML
Class Q and V devices per MIL-PRF-38535 and are available per the applicable Standard Microcircuit Drawing (SMD).
QML devices offer ease of procurement by eliminating the
9
HX6356
PACKAGING
The 32K x 8 SRAM is offered in two custom 36-lead flat
packs (FP). The packages are constructed of multilayer
ceramic (Al2O3) and feature internal power and ground
planes. The 36-lead flat packs also feature a non-conductive ceramic tie bar on the lead frame. The tie bar allows
electrical testing of the device, while preserving the lead
integrity during shipping and handling, up to the point of
lead forming and insertion.
36-LEAD FP PINOUT
VSS
VDD
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
NC
VDD
VSS
On the bottom braze 36-lead FP, ceramic chip capacitors
can be mounted to the package by the user to maximize
supply noise decoupling and increase board packing density. These capacitors attach directly to the internal package power and ground planes. This design minimizes
resistance and inductance of the bond wire and package.
All NC (no connect) pins should be connected to VSS to
prevent charge build up in the radiation environment.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
Top
View
36-LEAD FLAT PACK—Bottom Braze (22018131-001)
E
22018131-001
1
b
(width)
D
G
Top
View
e
(pitch)
H
L
L
Ceramic
Body
A
J
I
0.004
C
X
VSS
Optional
Capacitors
N
VDD
VDD
Y
1
O
V
W
T
P
R
M
All dimensions are in inches [1]
VSS
1
F
NonConductive
Tie-Bar
Kovar
Lid [3]
U
10
S
A
b
C
D
E
e
F
G
H
I
J
L
0.095 ± 0.014
0.008 ± 0.002
0.005 to 0.0075
0.650 ± 0.010
0.630 ± 0.007
0.025 ± 0.002 [2]
0.425 ± 0.005 [2]
0.525 ± 0.005
0.135 ± 0.005
0.030 ± 0.005
0.080 typ.
0.285 ± 0.015
M
N
O
P
R
S
T
U
V
W
X
Y
0.008 ± 0.003
0.050 ± 0.010
0.090 ref
0.015 ref
0.075 ref
0.113 ± 0.010
0.050 ref
0.030 ref
0.080 ref
0.005 ref
0.450 ref
0.400 ref
[1] Parts delivered with leads unformed
[2] At tie bar
[3] Lid tied to VSS
VSS
VDD
NWE
CE
A13
A8
A9
A11
NOE
A10
NCS
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
VSS
HX6356
36-LEAD FLAT PACK—Top Braze (22019627-001)
E
1
22019627-001
b
(width)
D
G
Top
View
e
(pitch)
All dimensions are in inches
H
L
C
J
Ceramic
Body
A
Kovar
Lid [3]
Kovar Lead [1]
M
I
Non-Conductive
Tie-Bar
S
1
22019627-001
A
b
C
D
E
e
F
G
H
I
J
L
M
S
0.085 ± 0.010
0.008 ± 0.002
0.005 to 0.0075
0.650 ± 0.010
0.630 ± 0.007
0.025 ± 0.002 [2]
0.425 ± 0.005 [2]
0.525 ± 0.005
0.135 ± 0.005
0.030 ± 0.005
0.080 typ.
0.285 ± 0.015
0.009 ± 0.003
0.113 ± 0.010
[1] Parts delivered with leads unformed
[2] At tie bar
[3] Lid tied to VSS
F
Bottom
View
Pin 1 Index Bar
F16
F7
F6
F5
F4
F3
F2
F8
F13
F14
F1
F1
F1
R
R
R
R
R
R
R
R
R
R
R
R
R
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
VSS
VDD
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQO
DQ1
DQ2
VDD
VSS
32K x 8 SRAM
VSS
VSS
VDD
NWE
CE
A13
A8
A9
A11
NOE
A10
NCS
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
VSS
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
VDD
R
R
R
R
R
R
R
R
R
R
R
R
R
R
VSS
R
F0
F17
F15
F12
F11
F10
F17
F9
F17
F1
F1
F1
F1
F1
R
R
R
R
R
R
R
R
R
R
R
R
NC
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
VSS
VDD
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQO
DQ1
DQ2
VDD
VSS
32K x 8 SRAM
STATIC BURN-IN DIAGRAM
DYNAMIC BURN-IN DIAGRAM
VSS
VDD
NWE
CE
A13
A8
A9
A11
NOE
A10
NCS
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
VSS
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
VSS
VDD = 5.5V, R ≤ 10 KΩ
Ambient Temperature ≥ 125 °C
VDD = 5.6V, R ≤ 10 KΩ, VIH = VDD, VIL = VSS
Ambient Temperature ≥ 125 °C, F0 ≥ 100 KHz Sq Wave
Frequency of F1 = F0/2, F2 = F0/4, F3 = F0/8, etc.
11
VDD
R
R
R
R
R
R
R
R
R
R
R
R
R
R
HX6356
ORDERING INFORMATION (1)
H
6356
X
S
X
PART NUMBER
PROCESS
X=SOI
SOURCE
H=HONEYWELL
PACKAGE DESIGNATION
X=36-Lead FP (Bottom Braze)
P=36-Lead FP (Top Braze)
K=Known Good Die
- = Bare Die (No Package)
H
C
INPUT
BUFFER TYPE
C=CMOS Level
T=TTL Level
SCREEN LEVEL
V=QML Class V
Q=QML Class Q
S=Class S
B=Class B
E=Engr Device (2)
TOTAL DOSE
HARDNESS
R=1x105 rad(SiO2)
F=3x105 rad(SiO2)
H=1x106 rad(SiO2)
N=No Level Guaranteed
(1) Orders may be faxed to 612-954-2051. Please contact our Customer Logistics Department at 612-954-2888 for further information.
(2) Engineering Device description: Parameters are tested from -55 to 125°C, 24 hr burn-in, no radiation guaranteed.
Contact Factory with other needs.
To learn more about Honeywell Solid State Electronics Center,
visit our web site at http://www.ssec.honeywell.com
Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any liability
arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Helping You Control Your World
900155 Rev. A
6-97
12