D a t a S h e e t , Rev. 1.13, M a i 2 00 4 HYB18T512[400/800/160]AC–[3.7/5] HYB18T512[400/800/160]AF–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM M e m or y P r o du c t s N e v e r s t o p t h i n k i n g . The information in this document is subject to change without notice. Edition 2004-05 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany © Infineon Technologies AG 2004. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. D a t a S h e e t , Rev. 1.13, M a i 2 00 4 HYB18T512[400/800/160]AC–[3.7/5] HYB18T512[400/800/160]AF–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM M e m or y P r o du c t s N e v e r s t o p t h i n k i n g . HYB18T512[400/800/160]A[C/F]–[3.7/5] Revision History: Rev. 1.13 Page Subjects (major changes since last revision) all initial release 2004-05 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] Template: mp_a4_v2.3_2004-01-14.fm HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Page Table of Contents 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 512Mbit DDR2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input/Output Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2 2.1 2.2 2.2.1 2.2.2 2.2.2.1 2.2.3 2.2.4 2.2.5 2.3 2.4 2.5 2.6 2.6.1 2.6.2 2.6.3 2.6.4 2.6.5 2.6.6 2.7 2.7.1 2.7.2 2.8 2.8.1 2.8.2 2.8.3 2.8.4 2.9 2.9.1 2.9.2 2.10 2.11 2.11.1 2.11.2 2.12 2.13 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power On and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming the Mode Register and Extended Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . DDR2 SDRAM Mode Register Set (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DDR2 SDRAM Extended Mode Register Set (EMRS(1)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMRS(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMRS(3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Off-Chip Driver (OCD) Impedance Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Die Termination (ODT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bank Activate Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read and Write Commands and Access Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Posted CAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Data Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Interruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Precharge Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Operation Followed by a Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write followed by Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto-Precharge Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read with Auto-Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write with Auto-Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read or Write to Precharge Command Spacing Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Concurrent Auto-Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto-Refresh Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self-Refresh Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Other Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . No Operation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Deselect Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Clock Frequency Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous CKE Low Reset Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5 5.1 5.2 5.3 5.4 5.4.1 5.5 5.6 AC & DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC & AC Logic Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Default Output V-I Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Calibrated Output Driver V-I Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input / Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power & Ground Clamp V-I Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet 5 21 21 22 22 23 23 25 27 27 28 31 35 36 37 38 39 42 45 46 48 48 51 52 52 55 56 57 57 57 58 59 63 63 63 63 64 68 68 69 71 72 74 75 76 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Page Table of Contents 6 6.1 6.2 IDD Specifications and Conditions 7 Electrical Characteristics & AC Timing - Absolute Specification . . . . . . . . . . . . . . . . . . . . . . . . 80 8 8.1 8.2 8.2.1 8.2.2 8.2.3 8.3 8.3.1 8.3.2 8.3.3 8.4 Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating . . . . . . . . . . . . . . . . Reference Load for Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slewrate Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Slewrate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Slewrate - Differential signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Slewrate - Single ended signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input and Data Setup and Hold Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Definition for Input Setup (tIS) and Hold Time (tIH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Definition for Data Setup (tDS) and Hold Time (tDH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slew Rate Definition for Input and Data Setup and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . . . Overshoot and Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 10 DDR2 Component Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 IDD Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 On Die Termination (ODT) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Data Sheet 6 83 83 83 83 83 83 84 84 84 85 91 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Overview 1 Overview This chapter gives an overview of the 512-Mbit Double-Data-Rate-Two SDRAM product family and describes its main characteristics. 1.1 Features The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features: • • • • • • • • • 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O DRAM organisations with 4, 8 and 16 data in/outputs Double Data Rate architecture: two data transfers per clock cycle, four internal banks for concurrent operation CAS Latency: 3, 4 and 5 Burst Length: 4 and 8 Differential clock inputs (CK and CK) Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data. Edge aligned with read data and center-aligned with write data. DLL aligns DQ and DQS transitions with clock DQS can be disabled for single-ended data strobe operation Table 1 • • Commands entered on each positive clock edge, data and data mask are referenced to both edges of DQS Data masks (DM) for write data Posted CAS by programmable additive latency for better command and data bus efficiency Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality. Auto-Precharge operation for read and write bursts Auto-Refresh, Self-Refresh and power saving Power-Down modes Average Refresh Period 7.8 µs at a TCASE lower than 85 °C, 3.9 µs between 85 °C and 95 °C Normal and Weak Strength Data-Output Drivers • 1K page size for ×4 & ×8, 2K page size for ×16 • Packages: P-TFBGA-60-6 for ×4 & ×8 components P-TFBGA-84-1 for ×16 components • • • • • • High Performance Product Type Speed Code –3.7 –5 Units Speed Grade DDR2–533 4–4–4 DDR2–400 3–3–3 — 266 200 MHz 266 200 MHz 200 200 MHz 15 15 ns 15 15 ns 45 40 ns 60 55 ns max. Clock Frequency @CL5 @CL4 @CL3 min. RAS-CAS-Delay min. Row Precharge Time min. Row Active Time min. Row Cycle Time 1.2 fCK5 fCK4 fCK3 tRCD tRP tRAS tRC Description 1. 2. 3. 4. 5. The 512-Mb DDR2 DRAM is a high-speed DoubleData-Rate-2 CMOS Synchronous DRAM device containing 536,870,912 bits and internally configured as a quad-bank DRAM. The 512-Mb device is organized as either 32 Mbit × 4 I/O × 4 bank, 16 Mbit × 8 I/O × 4 bank or 8 Mbit × 16 I/O × 4 bank chip. These synchronous devices achieve high speed transfer rates starting at 400 Mb/sec/pin for general applications. See Table 1 for performance figures. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchronous fashion. The device is designed to comply with all DDR2 DRAM key features: Data Sheet posted CAS with additive latency, write latency = read latency - 1, normal and weak strength data-output driver, Off-Chip Driver (OCD) impedance adjustment and an On-Die Termination (ODT) function. 7 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Overview A 16-bit address bus for ×4 and ×8 organised components and a 15-bit address bus for ×16 components is used to convey row, column and bank address information in a RAS-CAS multiplexing style. provided along with various power-saving power-down modes. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation. The DDR2 device operates with a 1.8 V ± 0.1 V power supply. An Auto-Refresh and Self-Refresh mode is 1.3 Ordering Information Table 2 Ordering information Part Number Org. Speed HYB18T512400AC–5 x4 HYB18T512800AC–5 x8 HYB18T512160AC–5 x16 HYB18T512400AC–3.7 x4 HYB18T512800AC–3.7 x8 HYB18T512160AC–3.7 x16 HYB18T512400AF–5 x4 HYB18T512800AF–5 x8 HYB18T512160AF–5 x16 HYB18T512400AF–3.7 x4 HYB18T512800AF–3.7 x8 HYB18T512160AF–3.7 x16 The DDR2 SDRAM is available in P-TFBGA package. CAS-RCD-RP Clock (MHz) Latencies DDR2–400 3–3–3 200 CAS-RCD-RP Clock (MHz) Latencies Package — P-TFBGA-60-6 — P-TFBGA-84-1 DDR2–533 4–4–4 266 3–3–3 200 P-TFBGA-60-6 P-TFBGA-84-1 DDR2–400 3–3–3 200 — — P-TFBGA-60-6 P-TFBGA-84-1 DDR2–533 4–4–4 266 3–3–3 200 P-TFBGA-60-6 P-TFBGA-84-1 Note: For product nomenclature see Chapter 10 of this data sheet Data Sheet 8 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Overview 1.4 Pin Configuration The pin configuration of a DDR2 SDRAM is listed by function in Table 3. The abbreviations used in the Pin#/Buffer Type columns are explained in Table 4 and Table 5 respectively. The pin numbering for the FBGA package is depicted in Figure 1 for ×4, Figure 2 for ×8 and Figure 3 for ×16. Table 3 Ball#/Pin# Pin Configuration of DDR SDRAM Name Pin Type Buffer Type Function Clock Signals ×4/×8 organizations E8 CK F8 CK F2 CKE I SSTL Clock Signal I SSTL Complementary Clock Signal I SSTL Clock Enable Rank Clock Signals ×16 organization J8 CK I SSTL Clock Signal K8 CK I SSTL Complementary Clock Signal K2 CKE I SSTL Clock Enable Rank Control Signals ×4/×8 organizations F7 RAS I SSTL Row Address Strobe G7 CAS I SSTL Column Address Strobe F3 WE I SSTL Write Enable G8 CS I SSTL Chip Select Control Signals ×16 organization K7 RAS I SSTL Row Address Strobe L7 CAS I SSTL Column Address Strobe K3 WE I SSTL Write Enable L8 CS I SSTL Chip Select Address Signals ×4/×8 organizations G2 BA0 I SSTL G3 BA1 I SSTL H8 A0 I SSTL H3 A1 I SSTL H7 A2 I SSTL J2 A3 I SSTL J8 A4 I SSTL J3 A5 I SSTL J7 A6 I SSTL K2 A7 I SSTL K8 A8 I SSTL K3 A9 I SSTL H2 A10 I SSTL AP I SSTL K7 A11 I SSTL L2 A12 I SSTL L8 A13 I SSTL Data Sheet Bank Address Bus 1:0 Address Signal 12:0 Address Signal 13 9 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Overview Table 3 Ball#/Pin# Pin Configuration of DDR SDRAM Name Pin Type Buffer Type Function Address Signals ×16 organization L2 BA0 I SSTL L3 BA1 I SSTL L1 NC – – M8 A0 I SSTL M3 A1 I SSTL M7 A2 I SSTL N2 A3 I SSTL N8 A4 I SSTL N3 A5 I SSTL N7 A6 I SSTL P2 A7 I SSTL P8 A8 I SSTL P3 A9 I SSTL M2 A10 I SSTL AP I SSTL P7 A11 I SSTL R2 A12 I SSTL Bank Address Bus 1:0 Address Signal 12:0 Data Signals ×4/×8 organizations C8 DQ0 I/O SSTL Data Signal 0 C2 DQ1 I/O SSTL Data Signal 1 D7 DQ2 I/O SSTL Data Signal 2 D3 DQ3 I/O SSTL Data Signal 3 Data Signals ×8 organization D1 DQ4 I/O SSTL Data Signal 4 D9 DQ5 I/O SSTL Data Signal 5 B1 DQ6 I/O SSTL Data Signal 6 B9 DQ7 I/O SSTL Data Signal 7 Data Signals ×16 organization G8 DQ0 I/O SSTL Data Signal 0 G2 DQ1 I/O SSTL Data Signal 1 H7 DQ2 I/O SSTL Data Signal 2 H3 DQ3 I/O SSTL Data Signal 3 H1 DQ4 I/O SSTL Data Signal 4 H9 DQ5 I/O SSTL Data Signal 5 F1 DQ6 I/O SSTL Data Signal 6 F9 DQ7 I/O SSTL Data Signal 7 C8 DQ8 I/O SSTL Data Signal 8 C2 DQ9 I/O SSTL Data Signal 9 D7 DQ10 I/O SSTL Data Signal 10 Data Sheet 10 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Overview Table 3 Pin Configuration of DDR SDRAM Ball#/Pin# Name Pin Type Buffer Type Function D3 DQ11 I/O SSTL Data Signal 11 D1 DQ12 I/O SSTL Data Signal 12 D9 DQ13 I/O SSTL Data Signal 13 B1 DQ14 I/O SSTL Data Signal 14 B9 DQ15 I/O SSTL Data Signal 15 Data Strobe ×4/×8 organisations B7 DQS I/O SSTL Data Strobe A8 DQS I/O SSTL Data Strobe Data Strobe ×8 organisations B3 RDQS I/O SSTL Mode Register Select A2 RDQS I/O SSTL Data Strobe Data Strobe ×16 organization B7 UDQS I/O SSTL Data Strobe Upper Byte A8 UDQS I/O SSTL Data Strobe Upper Byte F7 LDQS I/O SSTL Data Strobe Lower Byte E8 LDQS I/O SSTL Data Strobe Lower Byte SSTL Data Mask Data Mask ×4/×8 organizations B3 DM I Data Mask ×16 organization B3 UDM I SSTL Data Mask Upper Byte F3 LDM I SSTL Data Mask Lower Byte Power Supplies ×4/×8/×16 organizations A9,C1,C3,C7, C9 VDDQ PWR – I/O Driver Power Supply A1 VDD VSSQ PWR – Power Supply PWR – Power Supply VSS PWR – Power Supply A7,B2,B8,D2, D8 A3,E3 Power Supplies ×4/×8 organizations E2 E1 E9,H9,L1 E7 J1,K9 VREF VDDL VDD VSSDL VSS AI – I/O Reference Voltage PWR – Power Supply PWR – Power Supply PWR – Power Supply PWR – Power Supply Power Supplies ×16 organization J2 E9, G1, G3, G7, G9 J1 Data Sheet VREF VDDQ AI – I/O Reference Voltage PWR – I/O Driver Power Supply VDDL PWR – Power Supply 11 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Overview Table 3 Ball#/Pin# Pin Configuration of DDR SDRAM Pin Type Buffer Type Function E1, J9, M9, R1 VDD PWR – Power Supply E7, F2, F8, H2, VSSQ H8 PWR – Power Supply PWR – Power Supply PWR – Power Supply J7 J3,N1,P9 Name VSSDL VSS Not Connected ×4/×8 organizations L3,L7, G1 NC NC – Not Connected – Not Connected – Not Connected – On-Die Termination Control – On-Die Termination Control Not Connected ×4 organization A2, B1, B9, D1, D9 NC NC Not Connected ×16 organization A2, E2, L1, R3, NC R7, R8 NC Other Pins ×4/×8 organizations F9 ODT – Other Pins ×16 organization K9 Table 4 ODT – Abbreviations for Pin Type Abbreviation Description I Standard input-only pin. Digital levels. O Output. Digital levels. I/O I/O is a bidirectional input/output signal. AI Input. Analog levels. PWR Power GND Ground NC Not Connected Table 5 Abbreviations for Buffer Type Abbreviation Description SSTL Serial Stub Terminated Logic (SSTL_18) LV-CMOS CMOS OD Data Sheet Low Voltage CMOS CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR. 12 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Overview 7 8 9 A VSSQ DQS VDDQ DM B DQS VSSQ NC DQ1 VDDQ C V DDQ DQ0 VDDQ NC VSSQ DQ3 D DQ2 VSSQ NC V DDL V REF VSS E V SSDL CK V DD CKE WE F RAS CK ODT BA0 BA1 G CAS CS A10/AP A1 H A2 A0 A3 A5 J A6 A4 A7 A9 K A11 A8 A12 NC L NC NC/A13 1 2 3 VDD NC VSS NC VSSQ VDDQ NC/BA2 V SS VDD 4 5 6 V DD VSS MPPT0010 Figure 1 Pin Configuration P-TFBGA-60 (×4) Top View, see the balls throught the package Notes 1. VDDL and VSSDL are power and ground for the DLL.They are isolated on the device from VDD, VDDQ, VSS and VSSQ. Data Sheet 2. Ball position G1 is Not Connected and will be used for BA2 on 1-Gbit memory densities and higher 3. Ball position L8 is A13 for 512-Mbit and higher and is Not Connected on 256-Mbit 13 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Overview 7 8 9 A VSSQ DQS VDDQ DM/ RDQS B DQS VSSQ DQ7 DQ1 VDDQ C V DDQ DQ0 VDDQ DQ4 VSSQ DQ3 D DQ2 VSSQ DQ5 V DDL V REF VSS E V SSDL CK V DD CKE WE F RAS CK ODT BA0 BA1 G CAS CS A10/AP A1 H A2 A0 A3 A5 J A6 A4 A7 A9 K A11 A8 A12 NC L NC NC/A13 1 2 3 VDD NU/ RDQS VSS DQ6 VSSQ VDDQ NC/BA2 V SS VDD 4 5 6 V DD VSS MPPT0080 Figure 2 Pin Configuration P-TFBGA-60 (×8) Top View, see the balls throught the package Notes 4. VDDL and VSSDL are power and ground for the DLL. They are isolated on thedevice from VDD, VDDQ, VSS and VSSQ. 5. Ball position G1 is Not Connected and will be used for BA2 on 1-Gbit memory densities and higher 6. Ball position L8 is A13 for 512-Mbit and higher and is Not Connected on 256-Mbit 1. RDQS / RDQS are enabled by EMRS(1) command. 2. If RDQS / RDQS is enabled, the DM function is disabled 3. When enabled, RDQS & RDQS are used as strobe signals during reads. Data Sheet 14 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Overview 7 8 9 A VSSQ UDQS VDDQ UDM B UDQS VSSQ DQ15 DQ9 VDDQ C V DDQ DQ8 VDDQ DQ12 VSSQ DQ11 D UDQ2 VSSQ DQ13 VDD NC VSS E VSSQ LDQS VDDQ DQ6 VSSQ LDM F LDQS VSSQ DQ7 VDDQ DQ1 VDDQ G V DDQ DQ0 VDDQ DQ4 VSSQ DQ3 H DQ2 VSSQ DQ5 V DDL V REF VSS J V SSDL CK V DD CKE WE K RAS CK ODT BA0 BA1 L CAS CS A10/AP A1 M A2 A0 A3 A5 N A6 A4 A7 A9 P A11 A8 A12 NC R NC NC/A13 1 2 3 VDD NC VSS DQ14 VSSQ VDDQ NC/BA2 V SS VDD 4 5 6 V DD VSS MPPT0110 Figure 3 Pin Configuration P-TFBGA-84 (×16) Top View, see the balls throught the package Notes 3. Ball position L1 will be used for BA2 on 1-Gbit memory densities and higher 1. UDQS/UDQS is data strobe for upper byte, LDQS/LDQS is data strobe for lower byte 2. UDM is the data mask signal for the upper byte UDQ[7:0], LDM is the data mask signal for the lower byte LDQ[7:0] Data Sheet 15 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Overview 1.5 512Mbit DDR2 Addressing Table 6 512 Mbit DDR2 Addressing Configuration 128 Mb x 4 64 Mb x 8 32 Mb x 16 Number of Banks 4 4 4 Note Bank Address BA[1:0] BA[1:0] BA[1:0] Auto-Precharge A10 / AP A10 / AP A10 / AP Row Address A[13:0] A[13:0] A[12:0] Column Address A11, A[9:0] A[9:0] A[9:0] Number of Column Address Bits 11 10 10 1) Number of I/Os 4 8 16 2) Page Size [Bytes] 1024 (1K) 1024 (1K) 2048 (2K) 3) 1) Refered to as ’colbits’ 2) Refered to as ’org’ 3) org PageSize = 2 colbits × -------8 [ Bytes ] 1.6 Input/Output Functional Description Table 7 Input/Output Functional Description Symbol Type Function CK, CK Input Clock: CK and CK are differential clock inputs. All address and control inputs are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossing of CK and CK (both directions of crossing). CKE Input Clock Enable: CKE high activates and CKE low deactivates internal clock signals and device input buffers and output drivers. Taking CKE low provides Precharge PowerDown and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit and for self-refresh entry. Input buffers excluding CKE are disabled during self-refresh. CKE is used asynchronously to detect self-refresh exit condition. Self-refresh termination itself is synchronous. After VREF has become stable during power-on and initialisation sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during power-down. CS Input Chip Select: All commands are masked when CS is registered high. CS provides for external rank selection on systems with multiple ranks. CS is considered part of the command code. ODT Input On Die Termination: ODT (registered high) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM signal for ×4 and DQ, DQS, DQS, RDQS, RDQS and DM for ×8 configurations. For ×16 configuration ODT is applied to each DQ, UDQS, UDQS, LDQS, LDQS, UDM and LDM signal. The ODT pin will be ignored if the EMRS(1) is programmed to disable ODT. RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered Data Sheet 16 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Overview Table 7 Input/Output Functional Description Symbol Type Function DM, LDM, UDM Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled high coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. LDM and UDM are the input mask signals for ×16 components and control the lower or upper bytes. For ×8 components the data mask function is disabled, when RDQS / RQDS are enabled by EMRS(1) command. BA[1:0] Input Bank Address Inputs: BA[1:0] define to which bank an Activate, Read, Write or Precharge command is being applied. BA[1:0] also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS(1) cycle. A[13:0] Input Address Inputs: Provides the row address for Activate commands and the column address and Auto-Precharge bit A10 (=AP) for Read/Write commands to select one location out of the memory array in the respective bank. A10 (=AP) is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10=low) or all banks (A10=high). If only one bank is to be precharged, the bank is selected by BA[1:0]. The address inputs also provide the op-code during Mode Register Set commands. Row address A13 is used on ×4 and ×8 components only. DQx Input/ Output Data Inputs/Output: Bi-directional data bus. DQ[0:3] for ×4 components, DQ[0:7] for ×8 components, DQ[0:15] for ×16 components. DQS, (DQS) LDQS, (LDQS), UDQS,(UDQS) Input/ Output Data Strobe: output with read data, input with write data. Edge aligned with read data, centered with write data. For the ×16, LDQS corresponds to the data on LDQ[7:0]; UDQS corresponds to the data on UDQ[7:0]. The data strobes DQS, LDQS, UDQS may be used in single ended mode or paired with the optional complementary signals DQS, LDQS, UDQS to provide differential pair signaling to the system during both reads and writes. An EMRS(1) control bit enables or disables the complementary data strobe signals. RDQS, (RDQS) Input/ Output Read Data Strobe: For the ×8 components a RDQS, RDQS pair can be enabled via the EMRS(1) for read timing. RDQS, RDQS is not supported on ×4 and ×16 components. RDQS, RDQS are edge-aligned with read data. If RDQS, RDQS is enabled, the DM function is disabled on ×8 components. NC — No Connect: no internal electrical connection is present VDDQ VSSQ VDDL VSSDL VDD VSS VREF Supply DQ Power Supply: 1.8 V ± 0.1 V (BA2), A[15:14] — Data Sheet Supply DQ Ground Supply DLL Power Supply: 1.8 V ± 0.1 V Supply DLL Ground Supply Power Supply: 1.8 V ± 0.1 V Supply Ground Supply Reference Voltage BA2, A[15:14] are additional address pins for future generation DRAMs and are not connected on this component. 17 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Overview DQS, DQS Block Diagrams COL0,1 CK, CK 16 4 4 4 COL 0, 1 2 9 A0 -A13, BA0, BA1 16 11 Column-Address Counter/Latch Address Register CS WE CAS RAS CKE CK CK 2 16 Refresh Counter 16 Command Decode Mode Registers Row-Address MUX Control Logic 2 Bank Control Logic 14 16 Bank0 Row-Address Latch & Decoder MPBT0040 Block Diagram 32 Mbit × 4 I/O × 4 Internal Memory Banks device; it does not represent an actual circuit implementation. 3. DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals. Notes 1. 64Mbit x 4 Organisation with 14 Row, 2 Bank and 11 Column External Addresses 2. This Functional Block Diagram is intended to facilitate user understanding of the operation of the Data Sheet 4 512 (x16) Column lumn Co Decoder CDecoder olu mn Colum n Decoder Decoder I/OGating DM MaskLogic 8192 Sense Amplifier 16384 Bank1 Bank2 Bank0 Memory Array (16384x 512x 16) Bank3 16 16 16 Read Latch Figure 4 4 4 4 Write FIFO & Drivers 4 Data 4 1 1 4 1 1 1 1 Mask COL0,1 4 4 1 2 DQS Generator Data 4 MUX 4 4 Receivers DQS Drivers Input Register 1 1 DLL CK, CK DQ0DQ3, DM 1.7 18 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM COL0,1 8 8 CK, CK 32 8 8 COL0,1 10 Column-Address Counter/Latch 2 16 Refresh Counter 16 CS WE CAS RAS A0 - A13, BA0, BA1 Address Register 16 Mode Registers Command Decode Control Logic Row-Address MUX CKE CK CK 2 8 2 Bank Control Logic 14 16 Bank0 Row-Address Latch & Decoder MPBT0050 Block Diagram 16 Mbit × 8 I/O × 4 Internal Memory Banks device; it does not represent an actual circuit implementation. 3. DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals. Notes 1. 64Mb x 8 Organisation with 14 Row, 2 Bank and 10 Column External Addresses 2. This Functional Block Diagram is intended to facilitate user understanding of the operation of the Data Sheet 8 Data Write FIFO & Drivers 4 256 (x32) Column Column Decoder Column Decoder Column Decoder Decoder I/O Gating DM Mask Logic 8192 Sense Amplifier 16384 Bank1 Bank2 Bank0 Memory Array (16384x 256 x 32) Bank3 32 32 32 Read Latch Figure 5 8 8 1 1 8 1 1 8 1 1 8 8 Mask COL0,1 1 1 DQS Generator Data 8 MUX 8 8 Receivers DQS Drivers Input Register 1 1 DLL CK, CK DQ0DQ7, DM DQS, DQS Overview 19 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM COL0,1 16 16 CK, CK 64 COL 0, 1 A0 - A12, BA0, BA1 15 2 Address Register CS WE CAS RAS CKE CK CK 16 16 Write FIFO & Drivers 8 2 15 Refresh Counter 15 Mode Registers Command Decode Control Logic Row-Address MUX 10 Column-Address Counter/Latch 2 Bank Control Logic 13 15 Bank0 Row-Address Latch & Decoder MPBT0060 Block Diagram 8 Mbit × 16 I/O × 4 Internal Memory Banks Notes device; it does not represent an actual circuit implementation. 3. LDM, UDM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional LDQS and UDQS signals. 1. 32 Mb × 16 Organisation with 13 Row, 2 Bank and 10 Column External Adresses 2. This Functional Block Diagram is intended to facilitate user understanding of the operation of the Data Sheet 16 16 16 Data 16 2 2 16 2 2 8 256 (x64) Column Column Decoder Column Decoder Column Decoder Decoder I/O Gating DMMask Logic 16384 Sense Amplifier 8192 Bank1 Bank2 Bank0 Memory Array (16384x256 x64) Bank3 64 64 64 Read Latch Figure 6 UDQS, UDQS LDQS, LDQS UDQ0UDQ7, UDQM 2 Mask 2 2 DQS 16 16 MUX 16 16 Receivers COL0,1 16 Data 1 DQS Generator Drivers Input Register 2 2 DLL CK, CK LDQ0LDQ7, LDM Overview 20 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description 2 Functional Description 2.1 Simplified State Diagram Auto Refreshing Initialization Sequence REF tRFC RE PD_entry MRS Idle CKEH FS tMRD Setting MRS or EMRS PRE AC T Precharge PD CKEL Self Refresh REFA CKEL SX Activating tRCD Writing_AP _A P PRE P Writing Active PD Reading Wr CKEL Read Re _A ad it e Write Reading_AP Precharging Wr Write_AP RL + BL/2 + tRTP tRP Read_AP WL + BL/2 + WR i te PD_entry CKEH Re Bank Active ad Automatic Sequence Command Sequence MPFT0010 Figure 7 Simplified State Diagram bank, enabling / disabling on-die termination, Power-Down entry / exit - among other things are not captured in full detail. Note: This Simplified State Diagram is intended to provide a floorplan of the possible state transitions and thecommands to control them. In particular situations involving more than one Data Sheet 21 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description 2.2 Basic Functionality select the row for ×4 and ×8 components, A[12:0] select the row for ×16 components. Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for the burst length of four or eight in a programmed sequence. The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access and to determine if the Auto-Precharge command is to be issued. Accesses begin with the registration of an Activate command, which is followed by a Read or Write command. The address bits registered coincident with the activate command are used to select the bank and row to be accessed. BA[1:0] select the bank, A[13:0] 2.2.1 Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command description and device operation. Power On and Initialization DDR2 SDRAM’s must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power-up and Initialization Sequence The following sequence is required for POWER UP and Initialization. 6. Issue EMRS(3) command. To issue EMRS(3) command, provide “high” to BA[1:0]. 7. Issue EMRS(1) to enable DLL. To issue “DLL Enable” command, provide “low” to A0 and “high” to BA0 and “low” to BA1 and A13. 8. Issue a MRS command for “DLL reset”. To issue DLL reset command, provide “high” to A8 and “low” to BA[1:0] and A13. 9. Issue Precharge-all command. 10. Issue 2 or more Auto-refresh commands. 11. Issue a MRS command with low on A8 to initialize device operation (i.e. to program operating parameters without resetting the DLL.) 12. At least 200 clocks after step 8, execute Off Chip Driver impedance adjustment ( OCD Calibration). If OCD calibration is not used, EMRS OCD Default command (A9 = A8 = A7 = 1) followed by EMRS OCD Calibration Mode Exit command (A9 = A8 = A7 = 0) must be issued with other operating parameters of EMRS(1). 13. The DDR2 SDRAM is now ready for normal operation. 1. Apply power and attempt to maintain CKE below 0.2 × VDDQ and ODT at a low state (all other inputs may be undefined). To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin. Maximum power up interval for VDD / VDDQ is specified as 10.0 ms. The power interval is defined as the amount of time it takes for VDD / VDDQ to power-up from 0 V to 1.8 V ± 100 mV. At least one of these two sets of conditions must be met: – VDD, VDDL and VDDQ are driven from a single power converter output, AND – VTT is limited to 0.95 V max, AND – Vref tracks VDDQ/2 or 2. 3. 4. 5. – Apply VDD before or at the same time as VDDL. – Apply VDDL before or at the same time as VDDQ. – Apply VDDQ before or at the same time as VTT & Vref. Start clock (CK, CK) and maintain stable power and clock condition for a minimum of 200 µs.. Apply NOP or Deselect commands and take CKE high. Wait minimum of 400 ns, then issue a Precharge-all command. Issue EMRS(2) command. To issue EMRS(2) command, provide “low” to BA0 and “high” to BA1. Data Sheet 22 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description CK, CK CKE ODT "low" tRP 400 ns NOP PRE ALL EMRS(2) tMRS tMRS EMRS(3) tMRS EMRS(1) tMRS MRS tRP PRE ALL tRFC 1st Auto refresh 2nd Auto refresh tRFC tMRS MRS Follow OCD flowchart EMRS(1) OCD tMRS EMRS(1) OCD Any Command min. 200 cycles to lock the DLL Extended Mode Register(1) Set with DLL enable Mode Register Set with DLL reset Mode Register Set w/o DLL reset OCD Drive(1) or OCD default OCD calibration mode exit Figure 8 Initialization Sequence after Power Up 2.2.2 Programming the Mode Register and Extended Mode Registers For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time (tWR) are user defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable function, additive CAS latency, driver impedance, On Die Termination (ODT), single-ended strobe and Off Chip Driver impedance adjustment (OCD) are also user defined variables and must be programmed with an Extended Mode Register Set (EMRS) command. must be issued before read or write cycles may begin. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. Either MRS or EMRS Commands are activated by the low signals of CS, RAS, CAS and WE at the positive edge of the clock. Contents of the Mode Register (MRS) or Extended Mode Registers (EMRS(#)) can be altered by reexecuting the MRS and EMRS Commands. If the user chooses to modify only a subset of the MRS or EMRS variables, all variables must be redefined when the MRS or EMRS commands are issued. The address input data during this cycle defines the parameters to be set as shown in the MRS and EMRS table. A new command may be issued after the mode register set command cycle time (tMRD). When both bank addresses BA[1:0] are low, the DDR2 SDRAM enables the MRS command. When the bank addresses BA0 is high and BA1 is low, the DDR2 SDRAM enables the EMRS(1) command. MRS, EMRS and DLL Reset do not affect array contents, which means reinitialization including those can be executed any time after power-up without affecting array contents. Also any programming of EMRS(2) or EMRS(3) must be followed by programming of MRS and EMRS(1). After initial power up, all MRS and EMRS Commands 2.2.2.1 DDR2 SDRAM Mode Register Set (MRS) and clock cycle requirements during normal operation as long as all banks are in the precharged state. The mode register is divided into various fields depending on functionality. The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It programs CAS latency, burst length, burst sequence, test mode, DLL reset, Write Recovery (WR) and various vendor specific options to make DDR2 SDRAM useful for various applications. Burst length is defined by A[2:0] with options of 4 and 8 bit burst length. Burst address sequence type is defined by A3 and CAS latency is defined by A[6:4]. A7 is used for test mode and must be set to low for normal MRS operation. A8 is used for DLL reset. A[11:9] are used for write recovery time (tWR) definition for Auto-Precharge mode. With address bit A12 two Power-Down modes can be selected, a “standard mode” and a “low-power” Power-Down mode, where the DLL is disabled. Address bit A13 and all “higher” address bits have to be set to “low” for compatibility with other DDR2 memory products with higher memory densities. The default value of the mode register is not defined, therefore the mode register must be written after power-up for proper operation. The mode register is written by asserting low on CS, RAS, CAS, WE, BA[1:0], while controlling the state of address pins A[13:0]. The DDR2 SDRAM should be in all bank precharged (idle) mode with CKE already high prior to writing into the mode register. The mode register set command cycle time (tMRD) is required to complete the write operation to the mode register. The mode register contents can be changed using the same command Data Sheet 23 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description MR Mode Register Definition BA1 BA0 A13 A12 0 0 01) PD w reg. addr (BA[1:0] = 00B) A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 WR DLL TM CL BT BL w w w w w w A0 1) A13 is only available for ×4 and ×8 configuration. Field Bits Type1) Description BL [2:0] w Burst Length Number of sequential bits per DQ related to one read/write command. 010 4 011 8 BT 3 w Burst Type See Table 12 for internal address sequence of low order address bits; see Chapter 2.6.2. 0 Sequential 1 Interleaved CL [6:4] w CAS Latency Number of clock cycles from read command to first data valid window; see Chapter 2.6.1. Note: All other bit combinations are RESERVED. 010 011 100 101 2 2) 3 4 5 TM 7 w Test Mode 0 Normal mode 1 Vendor specific test mode DLL 8 w DLL Reset Reset of DLL is required after application of a stable clock; see . 0 No 1 Yes WR [11:9] w Write Recovery Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer: WR[cycles] ≥ tWR(ns) / tCK(ns) The mode register must be programmed to fulfill the minimum requirement for the analogue tWR timing. WRmin is determined by tCK,max and WRmax is determined by tCK,min. Note: All other bit combinations are RESERVED. 001 010 011 100 101 PD 12 w 2 3 4 5 6 Active Power-Down Mode Select 0 Fast exit (use tXARD) 1 Slow exit (use tXARDs) 1) w = write only register bits 2) CAS Latency 2 is optional for Jedec compliant devices. This option is implemented in this device but is neither tested nor guaranteed. Data Sheet 24 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description 2.2.3 DDR2 SDRAM Extended Mode Register Set (EMRS(1)) BAO, while controlling the state of the address pins. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register. The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the EMRS(1). Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in precharge state. The Extended Mode Register EMRS(1) stores the data for enabling or disabling the DLL, output driver strength, additive latency, OCD program, ODT, DQS and output buffers disable, RQDS and RDQS enable. The default value of the extended mode register EMRS(1) is not defined, therefore the extended mode register must be written after power-up for proper operation. The extended mode register is written by asserting low on CS, RAS, CAS, WE, BA1 and high on EMR(1) Extended Mode Register Definition BA1 BA0 A13 A12 0 1 01) Q reg. addr A11 (BA[1:0] = 01B) A10 RDQS DQS OFF w A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 OCD Program Rtt AL Rtt DIC DLL w w w w w w w 1) A13 is only available for ×4 and ×8 configuration. Field Bits Type1) Description DLL 0 w DLL Enable The DLL must be enabled for normal operation. See . 0 Enable 1 Disable DIC 1 w Off-chip Driver Impedance Control 0 Normal (Driver Size = 100%) 1 Weak (Driver Size = 60%) RTT 2,6 w Nominal Termination Resistance of ODT Note: All other bit combinations are RESERVED. 00 10 01 AL [5:3] w ∞ (ODT disabled) 75 Ohm 150 Ohm Additive Latency The additive latency must be programmed into the device to delay all read and write commands; see Chapter 2.5. Note: All other bit combinations are RESERVED. 000 001 010 011 100 Data Sheet 0 1 2 3 4 25 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description Field Bits OCD [9:7] Program Type1) Description (cont’d) w Off-Chip Driver Calibration Program Every calibration mode command should be followed by “OCD calibration mode exit” before any other command will be issued; see Chapter 2.3. 000 OCD calibration mode exit, maintain setting 001 Drive 1 010 Drive 0 100 Adjust mode Note: When Adjust Mode is issued, AL from previously set value must be applied. 111 OCD calibration default Note: After setting to default, OCD mode needs to be exited by setting A[9:7] to 000. DQS 10 w Complement Query Strobe (DQS, RDQS Output) If enabled the complement query strobe (DQS output) is driven high one clock cycle before valid query data (DQ) is driven onto the data bus; see Chapter 2.6.3. 0 Enable 1 Disable RDQS 11 w Read Data Strobe Output (RDQS, RDQS) 0 Disable 1 Enable Qoff 12 w Output Disable Disabling the DRAM outputs (DQ, DQS, DQS, RDQS, RDQS) allows users to measure IDD during Read operations without including the output buffer current. 0 Output buffers enabled 1 Output buffers disabled 1) w = write only register bits operation. With A12 set to “high” the SDRAM outputs are disabled and in Hi-Z. “High” on BA0 and “low” for BA1 have to be set to access the EMRS(1). A13 and all “higher” address bits have to be set to “low” for compatibility with other DDR2 memory products with higher memory densities. Refer to Mode Register Definition (BA[1:0] = 00B). A0 is used for DLL enable or disable. A1 is used for enabling half-strength data-output driver. A2 and A6 enables ODT (On-Die termination) and sets the Rtt value. A[5:3] are used for additive latency settings and A[9:7] enables the OCD impedance adjustment mode. A10 enables or disables the differential DQS and RDQS signals, A11 disables or enables RDQS. Address bit A12 have to be set to “low” for normal Single-ended and Differential Data Strobe Signals If RDQS is enabled in ×8 components, the DM function is disabled. RDQS is active for reads and don’t care for writes. Table 8 lists all possible combinations for DQS, DQS, RDQS, RQDS which can be programmed by A[11:10] address bits in EMRS. RDQS and RDQS are available in ×8 components only. Table 8 Single-ended and Differential Data Strobe Signals EMRS(1) Strobe Function Matrix Signaling A11 A10 RDQS/DM (RDQS Enable) (DQS Enable) RDQS DQS DQS 0 (Disable) 0 (Enable) DM Hi-Z DQS DQS differential DQS signals 0 (Disable) 1 (Disable) DM Hi-Z DQS Hi-Z single-ended DQS signals 1 (Enable) 0 (Enable) RDQS RDQS DQS DQS differential DQS signals 1 (Enable) 1 (Disable) RDQS Hi-Z DQS Hi-Z single-ended DQS signals DLL Enable/Disable Data Sheet 26 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a Read command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters. The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering Self-Refresh operation and is automatically reenabled upon exit of Self-Refresh operation. Any time Output Disable (Qoff) DRAM outputs allows users to measure IDD currents during Read operations, without including the output buffer current. Under normal operation, the DRAM outputs are enabled during Read operation for driving data (Qoff bit in the EMRS(1) is set to 0). When the Qoff bit is set to 1, the DRAM outputs will be disabled. Disabling the 2.2.4 EMRS(2) BA1,while controlling the states of the address pins. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register(2). The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register(2). Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in precharge state. The Extended Mode Registers EMRS(2) and EMRS(3) are reserved for future use and must be programmed when setting the mode register during initialization. The extended mode register(2) controls refresh related features. The default value of the extended mode register(2) is not defined, therefore the extended mode register(2) must be written after Power-up for proper operation. The extended mode register EMRS(2) is written by asserting low on CS, RAS, CAS, WE, BA0 and high on EMRS(2) Programming Extended Mode Register Definition BA1 BA0 1 0 A13 A12 A11 A10 (BA[1:0] = 01B) A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 01)2) reg.addr 1) A13 is only available for ×4 and ×8 configuration. 2) Must be programmed to “0” 2.2.5 EMRS(3) The Extended Mode Register EMRS(3) is reserved for future use and all bits except BA0 and BA1 must be EMRS(3) Programming Extended Mode Register Definition BA1 BA0 1 1 A13 A12 A11 A10 programmed to 0 when setting the mode register during initialization. (BA[1:0] = 01B) A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 01)2) reg. addr 1) A13 is only available for ×4 and ×8 configuration. 2) Must be programmed to “0” Data Sheet 27 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description 2.3 Off-Chip Driver (OCD) Impedance Adjustment command being issued. MRS should be set before entering OCD impedance adjustment and On Die Termination (ODT) should be carefully controlled depending on system environment. DDR2 SDRAM supports driver calibration feature and the flow chart below is an example of the sequence. Every calibration mode command should be followed by “OCD calibration mode exit” before any other Start EMRS: OCD calibration mode exit EMRS: Drive (1) DQ & DQS High; DQS Low Test EMRS: Drive (0) DQ & DQS Low; DQS High ALL OK ALL OK Need Calibration Test Need Calibration EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit EMRS: Enter Adjust Mode EMRS: Enter Adjust Mode BL = 4 code input to all DQs Inc, Dec or NOP BL = 4 code input to all DQs Inc, Dec or NOP EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit End MPFT0020 Figure 9 OCD Impedance Adjustment Flow Chart Note 1. MRS should be set before entering OCD impedance adjustment and ODT should be carefully controlled depending on system environment Data Sheet 28 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description Extended Mode Register Set for OCD impedance adjustment voltage conditions. Output driver characteristics for OCD calibration default are specified in Table 10. OCD applies only to normal full strength output drive setting defined by EMRS(1) and if half strength is set, OCD default output driver characteristics are not applicable. When OCD calibration adjust mode is used, OCD default output driver characteristics are not applicable. After OCD calibration is completed or driver strength is set to default, subsequent EMRS(1) commands not intended to adjust OCD characteristics must specify A[9:7] as ’000’ in order to maintain the default or calibrated value. OCD impedance adjustment can be done using the following EMRS(1) mode. In drive mode all outputs are driven out by DDR2 SDRAM and drive of RDQS is dependent on EMRS(1) bit enabling RDQS operation. In Drive(1) mode, all DQ, DQS (and RDQS) signals are driven high and all DQS (and RDQS) signals are driven low. In Drive(0) mode, all DQ, DQS (and RDQS) signals are driven low and all DQS (and RDQS) signals are driven high. In adjust mode, BL = 4 of operation code data must be used. In case of OCD calibration default, output driver characteristics have a nominal impedance value of 18 Ohms during nominal temperature and Table 9 Output driver characteristics for OCD calibration A9 A8 A7 Operation 0 0 0 OCD calibration mode exit 0 0 1 Drive(1) DQ, DQS, (RDQS) high and DQS (RDQS) low 0 1 0 Drive(0) DQ, DQS, (RDQS) low and DQS (RDQS) high 1 0 0 Adjust mode 1 1 1 OCD calibration default OCD impedance adjust after OCD calibration, all DQs of a given DDR2 SDRAM will be adjusted to the same driver strength setting. The maximum step count for adjustment is 16 and when the limit is reached, further increment or decrement code has no effect. The default setting may be any step within the maximum step count range. When Adjust mode command is issued, AL from previously set value must be applied. To adjust output driver impedance, controllers must issue the ADJUST EMRS(1) command along with a 4 bit burst code to DDR2 SDRAM as in Table 10. For this operation, Burst Length has to be set to BL = 4 via MRS command before activating OCD and controllers must drive the burst code to all DQs at the same time. DT0 in Table 10 means all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted for all DDR2 SDRAM DQs simultaneously and Table 10 Off- Chip-Driver Adjust Program 4 bit burst code inputs to all DQs Operation DT0 DT1 DT2 DT3 Pull-up driver strength Pull-down driver strength 0 0 0 0 NOP (no operation) NOP (no operation) 0 0 0 1 Increase by 1 step NOP 0 0 1 0 Decrease by 1 step NOP 0 1 0 0 NOP Increase by 1 step 1 0 0 0 NOP Decrease by 1 step 0 1 0 1 Increase by 1 step Increase by 1 step 0 1 1 0 Decrease by 1 step Increase by 1 step 1 0 0 1 Increase by 1 step Decrease by 1 step 1 0 1 0 Decrease by 1 step Decrease by 1 step Other Combinations Data Sheet Reserved 29 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description For proper operation of adjust mode, WL = RL - 1 = AL + CL - 1 clocks and tDS / tDH should be met as Figure 10. Input data pattern for adjustment, DT[0:3] is fixed and not affected by MRS addressing mode (i.e. sequential or interleave). Burst length of 4 have to be programmed in the MRS for OCD impedance adjustment. CK, CK CMD NOP EMRS(1) NOP NOP NOP NOP WL NOP EMRS(1) NOP tWR DQS DQS_in tDS tDH DQ_in DT0 DT1 DT2 DT3 DM Figure 10 OCD1 OCD calibration mode exit OCD adjust mode Timing Diagram Adjust Mode Drive Mode mode” command and all output drivers are turned-off Drive mode, both Drive(1) and Drive(0), is used for controllers to measure DDR2 SDRAM Driver impedance before OCD impedance adjustment. In this mode, all outputs are driven out tOIT after “enter drive tOIT after “OCD calibration mode exit” command. See Figure 11. CK, CK CMD EMRS(1) NOP NOP NOP NOP tOIT DQS_in EMRS(1) NOP NOP NOP tOIT DQS high & DQS low for Drive(1), DQS low & DQS high for Drive 0 DQS high for Drive(1) DQS high for Drive(0) DQ_in OCD calibration mode exit Enter Drive Mode Figure 11 Data Sheet OCD2 Timing Diagram Drive Mode 30 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description 2.4 On-Die Termination (ODT) the ODT control pin. UDQS and LDQS are terminated only when enabled in the EMRS(1) by address bit A10 = 0. On-Die Termination (ODT) is a new feature on DDR2 components that allows a DRAM to turn on/off termination resistance for each DQ, DQS, DQS, DM for ×4 and DQ, DQS, DQS, DM, RDQS (DM/RDQS share the same pin), RDQS for ×8 configuration via the ODT control pin. DQS is terminated only when enabled in the EMRS(1) by address bit A10 = 0. For ×8 configuration RDQS is only terminated, when enabled in the EMRS(1) by address bits A10 = 0 and A11 = 1. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices. The ODT function can be used for all active and standby modes. ODT is turned off and not supported in Self-Refresh mode. For ×16 configuration ODT is applied to each DQ, UDQS, UDQS, LDQS, LDQS, UDM and LDM signal via VDDQ VDDQ sw1 sw2 Rval1 Rval2 DRAM Input Buffer Input Pin Rval1 Rval2 sw1 sw2 VSSQ VSSQ Figure 12 Functional Representation of ODT Target Rtt = 0.5 × Rval1 or 0.5 × Rval2. Switch sw1 or sw2 is enabled by the ODT pin. Selection between sw1 or sw2 is determined by “Rtt (nominal)” in EMRS(1) address bits A6 & A2. Data Sheet The ODT pin will be ignored if the Extended Mode Register (EMRS(1)) is programmed to disable ODT. 31 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description ODT Truth Tables organisations (×4, ×8 and ×16). To activate termination of any of these pins, the ODT function has to be enabled in the EMRS(1) by address bits A6 and A2. The ODT Truth Table shows which of the input pins are terminated depending on the state of address bit A10 and A11 in the EMRS(1) for all three device Table 11 ODT Truth Table Input Pin EMRS(1) Address Bit A10 EMRS(1) Address Bit A11 X X ×4 components DQ[3:0] DQS X X DQS 0 X DM X X DQ[7:0] X X DQS X X DQS 0 X RDQS X 1 RDQS 0 1 DM X 0 DQ[15:0] X X LDQS X X LDQS 0 X UDQS X X UDQS 0 X LDM X X UDM X X ×8 components ×16 components Note: X = don’t care; 0 = bit set to low; 1 = bit set to high ODT timing modes Depending on the operating mode synchronous or asynchronous ODT timings apply. Synchronous timings (tAOND, tAOFD, tAON and tAOF) apply for all modes, when the on-die DLL is enabled. These modes are: Asynchronous ODT timings (tAOFPD, tAONPD) apply when the on-die DLL is disabled. • • • • These modes are: • Active Mode Standby Mode Fast Exit Active Power Down Mode (with MRS bit A12 is set to “0”) Data Sheet 32 Slow Exit Active Power Down Mode (with MRS bit A12 is set to “1”) Precharge Power Down Mode Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description T T T T T T T T 0 1 2 3 4 5 6 7 T 8 CK, CK CKE see note 1 t IS t ODT IS tAOFD (2.5 tCK) tAOND (2 tck) Rtt DQ tAON(min) tAOF(min) tAOF(max) tAON(max) ODT01 Figure 13 ODT Timing for Active and Standby (Idle) Modes Note: to turn on. ODT turn on time max. (tAON max) is when the ODT resistance is fully on. Both are measured from tAOND. 3. ODT turn off time min. (tAOF min) is when the device starts to turn off the ODT resistance.ODT turn off time max. (tAOF max) is when the bus is in high impedance. Both are measured from tAOFD. 1. Synchronous ODT timings apply for Active Mode and Standby Mode with CKE “high” and for the “Fast Exit” Active Power Down Mode (MRS bit A12 set to “0”). In all these modes the on-die DLL is enabled. 2. ODT turn-on time (tAON,min) is when the device leaves high impedance and ODT resistance begins T 1 T 0 T 3 T 2 T 4 T 5 T 6 T 7 T 8 CK, CK CKE "low" tIS ODT tIS tAOFPD,min tAOFPD,max DQ Rtt tAONPD,min tAONPD,max ODT02 Figure 14 ODT Timing for Precharge Power-Down and Active Power-Down Mode (with slow exit) (Asynchronous ODT timings) Note: Asynchronous ODT timings apply for Precharge Power-Down Mode and “Slow Exit” Active Power Down Mode (MRS bit A12 set to “1”), where the on-die DLL is disabled in this mode of operation. Data Sheet 33 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description Mode entry: As long as the timing parameter tANPD, min is satisfied when ODT is turned on or off before entering these power-down modes, synchronous timing parameters can be applied. If tANPD, min is not satisfied, asynchronous timing parameters apply. T- T- T- T- T- T 5 4 3 2 1 0 T 1 T 2 CK, CK tANPD (3 tCK) t CKE IS ODT turn-off, tANPD >= 3 tCK : t IS ODT Synchronou timings apply RTT tAOFD ODT turn-off, tANPD <3 tCK : ODT Asynchronou timings apply RTT tAOFPDmax ODT turn-on, tANPD >= 3 tCK : t IS ODT tAOND Synchronou timings apply RTT t IS ODT turn-on, tANPD < 3 tCK : tAONPDmax ODT RTT ODT0 3 Figure 15 Data Sheet Asynchronou timings apply ODT Mode entry Timing Diagram 34 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description Mode exit: As long as the timing parameter tAXPD, min is satisfied when ODT is turned on or off after exiting these powerdown modes, synchronous timing parameters can be T 1 T 0 T 5 applied. If tAXPD, min is not satisfied, asynchronous timing parameters apply. T 6 T 7 T 8 T 9 T10 CK, CK t IS tAXPD CKE t IS ODT turn-off, tAXPD >= tAXPDmin: Synchronous ODT timings apply Rtt tAOFD ODT turn-off, tAXPD < tAXPDmin: Asynchronous t IS ODT timings apply Rtt tAOFPDmax ODT turn-on, tAXPD >= tAXPDmin: Synchronou s t IS timings apply ODT Rtt tAOND t IS ODT turn-on, tAXPD < tAXPDmin: Asynchronous ODT Rtt timings apply tAONPDmax ODT04 Figure 16 ODT Mode exit Timing Diagram 2.5 Bank Activate Command (with or without Auto-Precharge) on the following clock cycle. If a R/W command is issued to a bank that has not satisfied the tRCD, min specification, then additive latency must be programmed into the device to delay the R/W command which is internally issued to the device. The additive latency value must be chosen to assure tRCD, min is satisfied. Additive latencies of 0, 1, 2, 3 and 4 are supported. Once a bank has been activated it must be precharged before another Bank Activate command can be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP, The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The bank addresses BA[1:0] are used to select the desired bank. The row addresses A0 through A13 are used to determine which row to activate in the selected bank for ×4 and ×8 organised components. For ×16 components row addresses A0 through A12 have to be applied. The Bank Activate command must be applied before any Read or Write operation can be executed. Immediately after the bank active command, the DDR2 SDRAM can accept a read or write command Data Sheet 35 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description more time for RAS precharge for a Precharge-All command. The rules are as follows: respectively. The minimum time interval between successive Bank Activate commands to the same bank is determined (tRC). The minimum time interval between Bank Active commands, to any other bank, is the Bank A to Bank B delay time (tRRD). 1. Sequential Bank Activation Restriction (JEDEC ballot item 1293.15): No more than 4 banks may be activated in a rolling tFAW window. Converting to clocks is done by deviding tFAW(ns) by tCK(ns) and rounding up to next integer value. As an example of the rolling window, if (tFAW/tCK) rounds up to 10 clocks, and an activate command is issued in clock N, no more than three further activate commands may be issued in clocks N + 1 through N + 9. 2. Precharge All Allowance: tRP for a Precharge-All command will equal to tRP + 1 tCK, where tRP is the value for a single bank precharge. In order to ensure that components with 8 internal memory banks do not exceed the instantaneous current supplying capability, certain restrictions on operation of the 8 banks must be observed. There are two rules. One for restricting the number of sequential Active commands that can be issued and another for allowing T 0 T 1 T 2 T 3 T 4 T n Tn+1 Tn+2 Tn+3 CK, CK Internal RAS-CAS delay tRCDmin. Address Bank A Row Addr. Bank A Col. Addr. Bank B Row Addr. Bank B Col. Addr. Bank A Addr. NOP Bank B Addr. Bank A Precharge NOP Bank B Precharge Bank A Row Addr. Bank A to Bank B delay tRRD. additive latency AL=2 Command Bank A Activate Posted CAS Read A Bank B Activate Read A Begins Posted CAS Read B tRAS Row Active Time (Bank A) Bank A Activate tRP Row Precharge Time (Bank A) tCCD tRC Row Cycle Time (Bank A) ACT Figure 17 Bank Activate Command Cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2 2.6 Read and Write Commands and Access Modes In case of a 4-bit burst operation (burst length = 4) the page length of 2048 is divided into 512 uniquely addressable segments (4-bits × 4 I/O each). The 4-bit burst operation will occur entirely within one of the 512 segments (defined by CA[8:0] beginning with the column address supplied to the device during the Read or Write Command (CA[9:0] & A11). The second, third and fourth access will also occur within this segment, however, the burst order is a function of the starting address, and the burst sequence. After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high, CS and CAS low at the clock’s rising edge. WE must also be defined at this time to determine whether the access cycle is a read operation (WE high) or a write operation (WE low). The DDR2 SDRAM provides a wide variety of fast access modes. A single Read or Write Command will initiate a serial read or write operation on successive clock cycles at data rates of up to 667 Mb/sec/pin for main memory. The boundary of the burst cycle is restricted to specific segments of the page length. In case of a 8-bit burst operation (burst length = 8) the page length of 2048 is divided into 256 uniquely addressable double segments (8-bits × 4 I/O each). The 8-bit burst operation will occur entirely within one of the 256 double segments (defined by CA[7:0]) For example, the 32Mbit × 4 I/O × 4 Bank chip has a page length of 2048 bits (defined by CA[9:0] & CA11). Data Sheet 36 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description minimum CAS to CAS delay (tCCD) is a minimum of 2 clocks for read or write cycles. beginning with the column address supplied to the device during the Read or Write Command (CA[9:0] & CA11). For 8 bit burst operation (BL = 8) the minimum CAS to CAS delay (tCCD) is 4 clocks for read or write cycles. A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. Therefore the T 0 T 1 T 2 T 3 Burst interruption is allowed with 8 bit burst operation. For details see Chapter 2.6.6. T 4 T 5 T 6 T 7 T12 CK, CK CMD NOP READ A NOP READ B tCCD NOP READ C NOP NOP NOP NOP tCCD DQS, DQS DQ Dout A0 Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 Dout B2 Dout B3 Dout C0 Dout C1 Dout C2 Dout C3 RB Figure 18 Read Burst Timing Example: (CL = 3, AL = 0, RL = 3, BL = 4) 2.6.1 Posted CAS the CAS latency (CL). Therefore if a user chooses to issue a Read/Write command before the tRCD, min, then AL greater than 0 must be written into the EMRS(1). The Write Latency (WL) is always defined as RL - 1 (Read Latency -1) where Read Latency is defined as the sum of Additive Latency plus CAS latency (RL=AL+CL). If a user chooses to issue a Read command after the tRCD, min period, the Read Latency is also defined as RL = AL + CL. Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. In this operation, the DDR2 SDRAM allows a Read or Write command to be issued immediately after the RAS bank activate command (or any time during the RAS to CAS delay time, tRCD period). The command is held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is the sum of AL and 0 1 2 3 4 5 6 7 8 9 10 11 CK, CK WL = RL -1 = 4 CMD Activate Bank A Write Bank A Read Bank A AL = 2 DQS, DQS CL = 3 tRCD RL = AL + CL = 5 DQ Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3 PostCAS1 Figure 19 Data Sheet Activate to Read Timing Example : Read followed by a write to the same bank, Activate to Read delay < tRCDmin: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 4 37 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description 0 1 2 3 4 5 6 7 8 9 10 11 12 CK, CK WL = RL -1 = 4 Activate Bank A CMD Write Bank A Read Bank A AL = 2 DQS, DQS CL = 3 tRCD RL = AL + CL = 5 DQ Dout0 Dout1 Dout2 Dout3 Dout4 Dout5 Dout6 Dout7 Din0 Din1 Din2 Din3 PostCAS3 Figure 20 Read to Write Timing Example : Read followed by a write to the same bank, Activate to Read delay < tRCDmin: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 8 0 1 2 3 4 5 6 7 8 9 10 11 CK, CK AL = 0 Activate Bank A CMD Read Bank A Write Bank A CL = 3 DQS, DQS WL = RL -1 = 2 tRCD RL = AL + CL = 3 DQ Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3 PostCAS2 Figure 21 Read to Write Timing Example : Read followed by a write to the same bank, Activate to Read delay = tRCDmin: AL = 0, CL = 3, RL = (AL + CL) = 3, WL = (RL -1) = 2, BL = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 CK, CK WL = 3 CMD Activate Bank A Write Bank A Read Bank A tRCD > tRCDmin. DQS, DQS RL = 4 DQ Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3 PostCAS5 Figure 22 Read to Write Timing Example : Read followed by a write to the same bank, Activate to Read delay > tRCDmin: AL = 1, CL = 3, RL = 4, WL = 3, BL = 4 2.6.2 Burst Mode Operation mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. The burst length is programmable and defined by the addresses A[2:0] of the MRS. The burst type, either sequential or interleaved, is programmable and defined by the Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8 bit burst Data Sheet 38 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description write burst when burst length = 8 is used, see the Chapter 2.6.6. A Burst Stop command is not supported on DDR2 SDRAM devices. address bit 3 (A3) of the MRS. Seamless burst read or write operations are supported. Interruption of a burst read or write operation is prohibited, when burst length = 4 is programmed. For burst interruption of a read or Table 12 Burst Length and Sequence Burst Length Starting Address (A2 A1 A0) Sequential Addressing (decimal) Interleave Addressing (decimal) 4 000 0, 1, 2, 3 0, 1, 2, 3 001 1, 2, 3, 0 1, 0, 3, 2 010 2, 3, 0, 1 2, 3, 0, 1 011 3, 0, 1, 2 3, 2, 1, 0 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 011 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 111 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 8 Note: 1. Page length is a function of I/O organization: 128Mb X 4 organization (CA[9:0], CA11); Page Length = 1 kByte; 64Mb X 8 organization (CA[9:0]); Page Length = 1 kByte; 32Mb X 16 organization (CA[9:0]); Page Length = 2 kByte 2. Order of burst access for sequential addressing is “nibble-based” and therefore different from SDR or DDR components 2.6.3 Read Command data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus CAS latency (CL). The CL is defined by the Mode Register Set (MRS). The AL is defined by the Extended Mode Register Set (EMRS(1)). The Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command until the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output (DQS) is driven low one clock cycle before valid data (DQ) is driven onto the Data Sheet 39 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description t CH t CL t CK CLK CLK, CLK CLK t DQSCK t AC DQS DQS, DQS DQS t RPRE t RPST t LZ DQ Dout Dout t DQSQmax Dout Dout t DQSQmax t QH t HZ t QH DO-Read Figure 23 Basic Read Timing Diagram T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 CK, CK CMD Post CAS READ A NOP NOP NOP NOP NOP NOP NOP NOP <= tDQSCK DQS, DQS AL = 2 CL = 3 RL = 5 DQ Dout A0 Dout A1 Dout A2 Dout A3 BRead523 Figure 24 Burst Operation Example 1: RL = 5 (AL = 2, CL = 3, BL = 4) The seamless read operation is supported by enabling a read command at every BL / 2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks are activated. Data Sheet 40 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 CK, CK CM D NOP READ A NOP NOP NOP NOP NOP NOP NOP <= tDQSCK DQS, DQS CL = 3 DQ' s RL = 3 Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7 BRead303 Figure 25 Read Operation Example 2: RL = 3 (AL = 0, CL = 3, BL = 8) T 0 T 1 T 3 T 4 T 5 T 6 T 7 T 8 T 9 CK, CK CMD Posted CAS READ A NOP NOP Posted CAS WRITE A NOP NOP NOP NOP NOP BL/2 + 2 DQS, DQS WL = RL - 1 = 4 RL = 5 DQ Dout A0 Dout A1 Dout A2 Dout A3 Din A0 Din A1 Din A2 Din A3 BRBW514 Figure 26 Read followed by Write Example: RL = 5, WL = (RL-1) = 4, BL = 4 The minimum time from the read command to the write command is defined by a read-to-write turn-around time, which is BL/2 + 2 clocks. Data Sheet 41 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 CK, CK CMD Post CAS READ A Post CAS READ B NOP NOP NOP NOP NOP NOP NOP DQS, DQS AL = 2 CL = 3 RL = 5 DQ Dout A0 Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 Dout B2 Dout B3 SBR523 Figure 27 Seamless Read Operation Example: RL = 5, AL = 2, CL = 3, BL = 4 The seamless read operation is supported by enabling a read command at every BL / 2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks are activated. T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T10 CK, CK CMD Post CAS READ A NOP NOP NOP Post CAS READ B NOP NOP NOP NOP NOP NOP NOP DQS, DQS CL = 3 DQ RL = 3 Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A4 Dout A7 Dout B0 Dout B1 Dout B2 Dout B3 Dout B4 Dout B5 Dout B6 Dout B7 SBR_BL8 Figure 28 Seamless Read Operation Example: RL = 3, AL = 0, CL = 3, BL = 8 (non interrupting) The seamless, non interrupting 8-bit read operation is supported by enabling a read command at every BL/2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks are activated. 2.6.4 Write Command successive edges of the DQS until the burst length is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ signal is ignored after the burst write operation is complete. The time from the completion of the burst write to bank precharge is named “write recovery time” (tWR) and is the time needed to store the write data into the memory array. tWR is an analog timing parameter (see AC & DC Operating Conditions) and is not the programmed value for WR in the MRS. The Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL) minus one and is equal to (AL + CL 1). A data strobe signal (DQS) has to be driven low (preamble) a time tWPRE prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The tDQSS specification must be satisfied for write cycles. The subsequent burst bit data are issued on Data Sheet 42 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description t DQSH t DQSL DQS DQS, DQS DQS t WPST t WPRE Din Din Din t DS Figure 29 Din t DH Basic Write Timing T0 T1 T2 T3 T4 T5 T6 T7 T9 CK, CK CMD P o st C A S W R IT E A NOP NOP NOP NOP NOP NOP <= tDQSS NOP P re c h a rg e C o m p le tio n o f th e B u rs t W rite DQS, DQS tW R WL = RL-1 = 4 DQ DIN A0 DIN A1 DIN A2 DIN A3 BW543 Figure 30 Example Timing Diagram : Write Operation: RL = 5 (AL = 2, CL = 3), WL = 4, BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 T9 CK, CK CMD P ost C A S W R IT E A NOP NOP NOP NOP <= tDQSS NOP P recha rge B ank A A ctiva te C om pletion of the B urst W rite DQS, DQS tW R WL = RL-1 = 2 DQ NOP tR P DIN A0 DIN A1 DIN A2 DIN A3 BW322 Figure 31 Data Sheet Write Operation Example: RL = 3 (AL = 0, CL = 3), WL = 2, BL = 4 43 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description T0 T1 T2 T3 T4 T5 T6 T7 T9 T8 CK, CK W rite to R ea d = (C L - 1)+ B L/2 + tW T R (2) = 6 CMD NOP NOP P o st C A S READ A NOP NOP NOP NOP NOP NOP DQS, DQS DQ C L= 3 A L= 2 tW T R W L = RL - 1 = 4 DIN A0 DIN A1 DIN A2 DIN A3 R L= 5 BWBR Write followed by Burst Read Example: RL = 5 (AL = 2, CL = 3), WL = 4, tWTR = 2, BL = 4 Figure 32 The minimum number of clocks from the write command to the read command is (CL - 1) +BL/2 + tWTR, where tWTR is the write-to-read turn-around time tWTR expressed in clock cycles. The tWTR is not a write recovery time (tWR) but the time required to transfer 4 bit write data from the input buffer into sense amplifiers in the array. T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD P ost C A S W R IT E A NOP P o st C A S W R IT E B NOP NOP NOP NOP NOP NOP DQS, DQS W L = RL - 1 = 4 DQ DIN A0 DIN A1 DIN A2 DIN A3 DIN B0 DIN B1 DIN B2 DIN B3 SBR Figure 33 Seamless Write Operation Example 1: RL = 5, WL = 4, BL = 4 The seamless write operation is supported by enabling a write command every BL/2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks are activated. Data Sheet 44 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD W R IT E A NOP NOP NOP NOP W R IT E B NOP NOP NOP DQS, DQS W L = RL - 1 = 2 DQ DIN A0 DIN A1 DIN A2 DIN A3 DIN A4 DIN A5 DIN A5 DIN A7 DIN B0 DIN B1 DIN B2 DIN B3 DIN B4 DIN B5 DIN B6 DIN B7 SBW_BL8 Figure 34 Seamless Write Operation Example 2: RL = 3, WL = 2, BL = 8, non interrupting The seamless, non interrupting 8-bit burst write operation is supported by enabling a write command at every BL/2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks are activated. 2.6.5 Write Data Mask One write data mask input (DM) for ×4 and ×8 components and two write data mask inputs (LDM, UDM) for ×16 components are supported on DDR2 SDRAM’s, consistent with the implementation on DDR SDRAM’s. It has identical timings on write operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. Data mask is not used during read cycles. If DM is high during a write burst coincident with the write data, the write data bit is not written to the memory. For ×8 components the DM function is disabled, when RDQS / RDQS are enabled by EMRS(1). t DQSH t DQSL DQS DQS, DQS DQS t WPST t WPRE DQ D D t DS DM D D Mask Mask t DH Mask Mask don't care Figure 35 Data Sheet Write Data Mask Timing 45 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description T0 T1 T2 T3 T4 T5 T6 T7 T9 CK, CK CMD W R IT E A NOP NOP NOP NOP NOP NOP P re ch a rg e B ank A A ctiva te <= tDQSS DQS, DQS WL = RL-1 = 2 DQ tW R tR P DIN A0 DIN A1 DIN A2 DIN A3 DM DM Figure 36 Write Operation with Data Mask Example: RL = 3 (AL = 0, CL = 3), WL = 2, tWR = 3, BL = 4 2.6.6 Burst Interruption 6. Read or Write burst with Auto-Precharge enabled is not allowed to be interrupted. 7. Read burst interruption is allowed by a Read with Auto-Precharge command. 8. Write burst interruption is allowed by a Write with Auto-Precharge command. 9. All command timings are referenced to burst length set in the mode register. They are not referenced to the actual burst. For example, Minimum Read to Precharge timing is AL + BL/2 where BL is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt). Minimum Write to Precharge timing is WL + BL/ 2 + tWR, where tWR starts with the rising clock after the un-interrupted burst end and not form the end of the actual burst end. Interruption of a read or write burst is prohibited for burst length of 4 and only allowed for burst length of 8 under the following conditions: 1. A Read Burst of 8 can only be interrupted by another Read command. Read burst interruption by a Write or Precharge Command is prohibited. 2. A Write Burst of 8 can only be interrupted by another Write command. Write burst interruption by a Read or Precharge Command is prohibited. 3. Read burst interrupt must occur exactly two clocks after the previous Read command. Any other Read burst interrupt timings are prohibited. 4. Write burst interrupt must occur exactly two clocks after the previous Write command. Any other Read burst interrupt timings are prohibited. 5. Read or Write burst interruption is allowed to any bank inside the DDR2 SDRAM. Data Sheet 46 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD READ A NOP READ B NOP NOP NOP NOP NOP NOP NOP DQS, DQS DQ Dout A0 Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 Dout B2 Dout B3 Dout B4 Dout B5 Dout B6 Dout B7 RBI Figure 37 Read Interrupt Timing Example 1: (CL = 3, AL = 0, RL = 3, BL = 8) T0 T1 T2 T3 T4 T5 T6 T7 T8 C K, C K CMD NOP W R IT E A NOP W R IT E B NOP NOP NOP NOP NOP NOP DQS, DQS DQ Din A0 Din A1 Din A2 Din A3 Din B0 Din B1 Din B2 Din B3 Dout B4 Din B5 Din B6 Din B7 WBI Figure 38 Data Sheet Write Interrupt Timing Example 2: (CL = 3, AL = 0, WL = 2, BL = 8) 47 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description 2.7 Precharge Command charge Command can be used to precharge each bank independently or all banks simultaneously. Three address bits A10, BA0 and BA1 are used to define which bank to precharge when the command is issued. The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The PreTable 13 Bank Selection for Precharge by Address Bits A10 BA0 BA1 Precharge Bank(s) LOW LOW LOW Bank 0 only LOW LOW HIGH Bank 1 only LOW HIGH LOW Bank 2 only LOW HIGH HIGH Bank 3 only HIGH Don’t Care Don’t Care all banks Note: The bank address assignment is the same for activating and precharging a specific bank. 2.7.1 Read Operation Followed by a Precharge The following rules apply as long as the tRTP timing parameter - Internal Read to Precharge Command delay time - is less or equal two clocks, which is the case for operating frequencies less or equal 266 Mhz (DDR2 400 and 533 speed sorts): A new bank active command may be issued to the same bank if the following two conditions are satisfied simultaneously: 1. The RAS precharge time (tRP) has been satisfied from the clock at which the precharge begins. 2. The RAS cycle time (tRC, min) from the previous bank activation has been satisfied. Minimum Read to Precharge command spacing to the same bank = AL + BL/2 clocks. For the earliest possible precharge, the Precharge command may be issued on the rising edge which is “Additive Latency (AL) + BL/2 clocks” after a Read Command, as long as the minimum tRAS timing is satisfied. T0 T1 T2 T3 For operating frequencies higher than 266 MHz, tRTP becomes > 2 clocks and one additional clock cycle has to be added for the minimum Read to Precharge command spacing, which now becomes AL + BL/2 + 1 clocks. T4 T5 T6 T7 T8 CK, CK CMD P ost C A S READ A NOP NOP P re ch a rg e NOP NOP B ank A A ctiva te NOP NOP tR P A L + B L /2 clks DQS, DQS AL = 1 CL = 3 RL = 4 DQ Dout A0 > = tR A S Dout A1 Dout A2 Dout A3 CL = 3 > = tR C > = tR T P BR-P413 Figure 39 Data Sheet Read Operation Followed by Precharge Example 1: RL = 4 (AL = 1, CL = 3), BL = 4, tRTP ≤ 2 clocks 48 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD P ost C A S READ A NOP NOP NOP NOP P re ch a rg e NOP NOP A L + B L /2 clks B ank A A ctiva te tR P DQS, DQS AL = 1 CL = 3 RL = 4 DQ Dout A0 > = tR A S Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7 CL = 3 > = tR C > = tR T P Figure 40 BR-P413(8) second 4-bit prefetch first 4-bit prefetch Read Operation Followed by Precharge Example 2: RL = 4 (AL = 1, CL = 3), BL = 8, tRTP ≤ 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD P o st C A S READ A NOP NOP NOP NOP P re ch a rg e A L + B L /2 clks NOP B ank A A ctiva te NOP tR P DQS, DQS CL = 3 AL = 2 RL = 5 DQ Dout A0 > = tR A S Dout A1 Dout A2 Dout A3 CL = 3 > = tR C > = tR T P Figure 41 Data Sheet BR-P523 Read Operation Followed by Precharge Example 3: RL = 5 (AL = 2, CL = 3), BL = 4, tRTP ≤ 2 clocks 49 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD P ost C A S READ A NOP NOP NOP P re ch a rg e A NOP NOP A L + B L /2 clo cks NOP B ank A A ctiva te tR P DQS, DQS AL = 2 CL = 4 RL = 6 DQ Dout A0 > = tR A S Dout A1 Dout A2 Dout A3 CL = 4 > = tR C > = tR T P Figure 42 BR-P624 Read Operation Followed by Precharge Example 4: RL = 6, (AL = 2, CL = 4), BL = 4, tRTP ≤ 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD READ A NOP NOP NOP NOP P re ch a rg e NOP NOP A L + B L /2 clks + 1 B ank A A ctiva te tR P DQS, DQS CL = 4 RL = 4 DQ Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7 > = tR A S > = tR T P first 4-bit prefetch Figure 43 Data Sheet BR-P404(8) second 4-bit prefetch Read Operation Followed by Precharge Example 5: RL = 4, (AL = 0, CL = 4), BL = 8, tRTP > 2 clocks 50 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description 2.7.2 Write followed by Precharge to the Precharge command. No Precharge command should be issued prior to the tWR delay, as DDR2 SDRAM does not support any burst interrupt by a Precharge command. tWR is an analog timing parameter (see Chapter 7) and is not the programmed value for tWR in the MRS. Minimum Write to Precharge command spacing to the same bank = WL + BL/2 + tWR. For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the Precharge command can be issued. This delay is known as a write recovery time (tWR) referenced from the completion of the burst write T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD P ost C A S W R IT E A NOP NOP NOP NOP NOP NOP NOP P re ch a rg e A C o m p le tio n o f th e B u rst W rite DQS, DQS tW R WL = 3 DQ DIN A0 DIN A1 DIN A2 DIN A3 BW-P3 Figure 44 Write followed by Precharge Example 1: WL = (RL - 1) = 3, BL = 4, tWR = 3 T0 T1 T2 T3 T4 T5 T6 T7 T9 CK, CK CMD P o st C A S W R IT E A NOP NOP NOP NOP NOP NOP P re ch a rg e A C o m p le tio n o f th e B u rst W rite DQS, DQS tW R WL = 4 DQ NOP DIN A0 DIN A1 DIN A2 DIN A3 BW-P4 Figure 45 Data Sheet Write followed by Precharge Example 2: WL = (RL - 1) = 4, BL = 4, tWR = 3 51 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description 2.8 Auto-Precharge Operation Auto-Precharge is also implemented for Write Commands.The precharge operation engaged by the Auto-Precharge command will not begin until the last data of the write burst sequence is properly stored in the memory array. This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon CAS Latency) thus improving system performance for random data access. Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge Command or the Auto-Precharge function. When a Read or a Write Command is given to the DDR2 SDRAM, the CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the Read or Write Command is issued, then the Auto-Precharge function is enabled. The RAS lockout circuit internally delays the precharge operation until the array restore operation has been completed so that the Auto-Precharge command may be issued with any read or write command. During Auto-Precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge internally on the rising edge which is CAS Latency (CL) clock cycles before the end of the read burst. 2.8.1 Read with Auto-Precharge becomes AL + tRTP + tRP. For BL = 8 the time from Read with Auto-Precharge to the next Activate command is AL + 2 + tRTP + tRP. Note that (tRTP + tRP) has to be rounded up to the next integer value. In any event internal precharge does not start earlier than two clocks after the last 4-bit prefetch. If A10 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The DDR2 SDRAM starts an Auto-Precharge operation on the rising edge which is (AL + BL/2) cycles later from the Read with AP command if tRAS(min) and tRTP are satisfied. If tRAS(min) is not satisfied at the edge, the start point of Auto-Precharge operation will be delayed until tRAS(min) is satisfied. If tRTPmin is not satisfied at the edge, the start point of Auto-Precharge operation will be delayed until tRTPmin is satisfied. A new bank active (command) may be issued to the same bank if the following two conditions are satisfied simultaneously: 1. The RAS precharge time (tRP) has been satisfied from the clock at which the Auto-Precharge begins. 2. The RAS cycle time (tRC) from the previous bank activation has been satisfied. In case the internal precharge is pushed out by tRTP, tRP starts at the point where the internal precharge happens (not at the next rising clock edge after this event). So for BL = 4 the minimum time from Read with Auto-Precharge to the next Activate command Data Sheet 52 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD P o ste d C A S R E A D w /A P NOP NOP NOP NOP NOP NOP NOP B ank A ctiva te A10 ="high" AL + BL/2 A u to -P re ch a rg e B e g in s DQS, DQS AL = 2 CL = 3 tRP RL = 5 DQ Dout A0 Dout A1 Dout A2 Dout A3 tRAS tRCmin. BR-AP5231 Figure 46 Read with Auto-Precharge Example 1, followed by an Activation to the Same Bank (tRC Limit): RL = 5 (AL = 2, CL = 3), BL = 4, tRTP ≤ 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD P o ste d C A S R E A D w /A P NOP NOP NOP NOP NOP B ank A ctiva te NOP NOP A10 ="high" tRAS(min) A u to -P re ch a rg e B e g in s DQS, DQS AL = 2 CL = 3 tRP RL = 5 DQ Dout A0 Dout A1 Dout A2 Dout A3 tRC BR-AP5232 Figure 47 Data Sheet Read with Auto-Precharge Example 2, followed by an Activation to the Same Bank (tRAS Limit): RL = 5 (AL = 2, CL = 3), BL = 4, tRTP ≤ 2 clocks 53 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD P o ste d C A S R E A D w /A P NOP NOP NOP A10 ="high" NOP NOP NOP AL + BL/2 NOP B ank A ctiva te tRP A u to -P re ch a rg e B e g in s DQS, DQS AL = 1 CL = 3 RL = 4 DQ Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7 >= tRTP BR-AP413(8)2 second 4-bit prefetch first 4-bit prefetch Figure 48 Read with Auto-Precharge Example 3, followed by an Activation to the Same Bank: RL = 4 (AL = 1, CL = 3), BL = 8, tRTP ≤ 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD P o ste d C A S R E A D w /A P A10 ="high" NOP NOP NOP NOP NOP NOP B ank A ctiva te NOP AL + tRTP + tRP A u to -P re ch a rg e B e g in s DQS, DQS AL = 1 CL = 3 RL = 4 DQ Dout A0 Dout A1 Dout A2 Dout A3 tRP tRTP BR-AP4133 first 4-bit prefetch Figure 49 Data Sheet Read with Auto-Precharge Example 4, followed by an Activation to the Same Bank: RL = 4 (AL = 1, CL = 3), BL = 4, tRTP > 2 clocks 54 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description 2.8.2 Write with Auto-Precharge 1. The last data-in to bank activate delay time (tDAL = WR + tRP) has been satisfied. 2. The RAS cycle time (tRC) from the previous bank activation has been satisfied. If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The DDR2 SDRAM automatically begins precharge operation after the completion of the write burst plus the write recovery time delay (tWR), programmed in the MRS register, as long as tRAS is satisfied. The bank undergoing Auto-Precharge from the completion of the write burst may be reactivated if the following two conditions are satisfied. T0 T1 T2 In DDR2 SDRAM’s the write recovery time delay (tWR) has to be programmed into the MRS mode register. As long as the analog tWR timing parameter is not violated, WR can be programmed between 2 and 6 clock cycles. Minimum Write to Activate command spacing to the same bank = WL + BL/2 + tDAL. T3 T4 T5 T6 T7 CK, CK W R IT E w /A P CMD NOP NOP A10 ="high" NOP NOP NOP NOP Completion of the Burst Write B ank A A ctiva te A u to -P re ch a rg e B e g in s DQS, DQS WR WL = RL-1 = 2 DQ NOP tRP tDAL DIN A0 DIN A1 DIN A2 DIN A3 tRCmin. >=tRASmin. BW-AP223 Write with Auto-Precharge Example 1 (tRC Limit): WL = 2, tDAL = 6 (WR = 3, tRP = 3), BL = 4 Figure 50 T0 T3 T4 T5 T6 NOP NOP NOP T8 T7 T9 T12 CK, CK P o s te d C A S W R IT E w /A P CMD A10 ="high" NOP NOP NOP NOP B ank A A ctiva te Completion of the Burst Write A u to -P re ch a rg e B e g in s DQS, DQS WR WL = RL-1 = 4 tRP tDAL DQ DIN A0 DIN A1 DIN A2 DIN A3 >=tRC >=tRAS BW-AP423 Figure 51 Data Sheet Write with Auto-Precharge Example 2 (WR + tRP Limit): WL = 4, tDAL = 6 (WR = 3, tRP = 3), BL = 4 55 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description 2.8.3 Read or Write to Precharge Command Spacing Summary The following table summarizes the minimum command delays between Read, Read w/AP, Write, Table 14 Write w/AP to the Precharge commands to the same banks and Precharge-All commands. Minimum Command Delays From Command To Command Minimum Delay between “From Command” to “To Command” Units Notes READ PRECHARGE (to same banks as READ) AL + BL/2 + max(tRTP, 2) - 2 tCK 1)2) PRECHARGE-ALL AL + BL/2 + max(tRTP, 2) - 2 1)2) PRECHARGE (to same banks as READ w/AP) AL + BL/2 + max(tRTP, 2) - 2 tCK tCK PRECHARGE-ALL AL + BL/2 + max(tRTP, 2) - 2 1)2) PRECHARGE (to same banks as WRITE) WL + BL/2 + tWR tCK tCK PRECHARGE-ALL WL + BL/2 + tWR 2)3) PRECHARGE (to same banks as WRITE w/AP) WL + BL/2 + WR tCK tCK PRECHARGE-ALL WL + BL/2 + WR 2) PRECHARGE (to same banks as PRECHARGE) 1 tCK tCK PRECHARGE-ALL 1 tCK tCK tCK 2) READ w/AP WRITE WRITE w/AP PRECHARGE PRECHARGE-ALL PRECHARGE 1 PRECHARGE-ALL 1 1)2) 2)3) 2) 2) 2) 2) 1) RU{tRTP(ns) / tCK(ns)} must be used, where RU stands for “Round Up” 2) For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or prechargeall, issued to that bank. The precharge period is satisfied after tRP or tRP, all depending on the latest precharge command issued to that bank 3) RU{tWR(ns) / tCK(ns)} must be used, where RU stands for “Round Up” Data Sheet 56 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description 2.8.4 Concurrent Auto-Precharge The minimum delay from a Read or Write command with Auto-Precharge enabled, to a command to a different bank, is summarized in Table 15. As defined, the WL = RL - 1 for DDR2 devices which allows the command gap and corresponding data gaps to be minimized. DDR2 devices support the “Concurrent AutoPrecharge” feature. A Read with Auto-Precharge enabled, or a Write with Auto-Precharge enabled, may be followed by any command to the other bank, as long as that command does not interrupt the read or write data transfer, and all other related limitations (e.g. contention between Read data and Write data must be avoided externally and on the internal data bus. Table 15 Command Delay Table From Command To Command (different bank, non-interrupting command) Minimum Delay with Concurrent Auto- Units Precharge Support Note WRITE w/AP Read or Read w/AP (CL -1) + (BL/2) + tWTR 1) Write or Write w/AP BL/2 Precharge or Activate 1 Read or Read w/AP BL/2 Write or Write w/AP BL/2 + 2 Precharge or Activate 1 Read w/AP tCK tCK tCK tCK tCK tCK 2) 2) 1) RU{tWTR(ns)/tCK(ns)} must be used where RU stands for “Round Up” 2) This rule only applies to a selective Precharge command to another banks, a Precharge-All command is illegal 2.9 Refresh DDR2 SDRAM requires a refresh of all rows in any rolling 64 ms interval. The necessary refresh can be generated in one of two ways: by explicit Auto-Refresh commands or by an internally timed Self-Refresh mode. 2.9.1 Auto-Refresh Command external address bus is required once this cycle has started. Auto-Refresh is used during normal operation of the DDR2 SDRAM’s. This command is non persistent, so it must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller. This makes the address bits ”don’t care” during an Auto-Refresh command. The DDR2 SDRAM requires Auto-Refresh cycles at an average periodic interval of tREF(maximum). When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Auto-Refresh Command and the next Activate Command or subsequent Auto-Refresh Command must be greater than or equal to the AutoRefresh cycle time (tRFC). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between any Auto-Refresh command and the next Auto-Refresh command is 9 × tREFI. When CS, RAS and CAS are held low and WE high at the rising edge of the clock, the chip enters the AutoRefresh mode. All banks of the SDRAM must be precharged and idle for a minimum of the precharge time (tRP) before the Auto-Refresh Command can be applied. An internal address counter supplies the addresses during the refresh cycle. No control of the Data Sheet 57 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description T0 T1 T2 T3 CK, CK "high" CKE CMD P re ch a rg e NOP > = t RFC > = t RFC > = tRP NOP AUTO REFRESH NOP AUTO REFRESH NOP NOP ANY AR Figure 52 Auto Refresh Timing 2.9.2 Self-Refresh Command The Self-Refresh command can be used to retain data, even if the rest of the system is powered down. When in the Self-Refresh mode, the DDR2 SDRAM retains data without external clocking. The DDR2 SDRAM device has a built-in timer to accommodate SelfRefresh operation. The Self-Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. ODT must be turned off before issuing Self Refresh command, by either driving ODT pin low or using EMRS(1) command. Once the command is registered, CKE must be held low to keep the device in Self-Refresh mode. The DLL is automatically disabled upon entering Self Refresh and is automatically enabled upon exiting Self Refresh. When the DDR2 SDRAM has entered SelfRefresh mode all of the external control signals, except CKE, are “don’t care”. The DRAM initiates a minimum of one Auto Refresh command internally within tCKE period once it enters Self Refresh mode. The clock is internally disabled during Self-Refresh Operation to save power. The minimum time that the DDR2 SDRAM must remain in Self Refresh mode is tCKE. The user may change the external clock frequency or halt the external Data Sheet clock one clock after Self-Refresh entry is registered, however, the clock must be restarted and stable before the device can exit Self-Refresh operation. The procedure for exiting Self Refresh requires a sequence of commands. First, the clock must be stable prior to CKE going back HIGH. Once Self-Refresh Exit command is registered, a delay of at least tXSNR must be satisfied before a valid command can be issued to the device to allow for any internal refresh in progress. CKE must remain high for the entire Self-Refresh exit period tXSRD for proper operation. Upon exit from Self Refresh, the DDR2 SDRAM can be put back into Self Refresh mode after tXSNR expires. NOP or deselect commands must be registered on each positive clock edge during the Self-Refresh exit interval tXSNR. ODT should be turned off during tXSNR. The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be missed when CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh, the DDR2 SDRAM requires a minimum of one extra auto refresh command before it is put back into Self Refresh Mode. 58 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description T0 T1 T2 T4 T3 T5 Tm Tn Tr CK/CK tRP tis tis tCKE CKE tis tAOFD >=tXSRD >= tXSNR ODT Self Refresh Entry CMD NOP CK/CK may be halted Figure 53 Non-Read Command Read Command CK/CK must be stable Self Refresh Timing Note: 1. Device must be in the “All banks idle” state before entering Self Refresh mode. 2. tXSRD (≥ 200 tCK) has to be satisfied for a Read or a Read 3. tXSNR has to be satisfied for any command except a Read or a Read with Auto-Precharge command 4. Since CKE is an SSTL input, VREF must be maintained during Self Refresh. with Auto-Precharge command. 2.10 Power-Down referred as “standard active power-down mode” and a fast power-down exit timing defined by the tXARD timing parameter can be used. When A12 is set to “high” this mode is referred as a power saving “low power active power-down mode”. This mode takes longer to exit from the power-down mode and the tXARDS timing parameter has to be satisfied. Power-down is synchronously entered when CKE is registered low, along with NOP or Deselect command. CKE is not allowed to go low while mode register or extended mode register command time, or read or write operation is in progress. CKE is allowed to go low while any other operation such as row activation, Precharge, Auto-Precharge or Auto-Refresh is in progress, but power-down IDD specification will not be applied until finishing those operations. Entering power-down deactivates the input and output buffers, excluding CK, CK, ODT and CKE. Also the DLL is disabled upon entering Precharge Power-down or slow exit active power-down, but the DLL is kept enabled during fast exit active power-down. In powerdown mode, CKE low and a stable clock signal must be maintained at the inputs of the DDR2 SDRAM, and all other input signals are “Don’t Care”. Power-down duration is limited by 9 times tREFI of the device. The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting power-down mode for proper read operation. DRAM design guarantees it’s DLL in a locked state with any CKE intensive operations as long as DRAM controller complies with DRAM specifications. If power-down occurs when all banks are precharged, this mode is referred to as Precharge Power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as Active Power-down. For Active Power-down two different power saving modes can be selected within the MRS register, address bit A12. When A12 is set to “low” this mode is Data Sheet The power-down state is synchronously exited when CKE is registered high (along with a NOP or Deselect command). A valid, executable command can be applied with power-down exit latency, tXP, tXARD or tXARDS, after CKE goes high. Power-down exit latencies are defined in Table 40. 59 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description Power-Down Entry Active Power-down mode entry is prohibited as long as a Write Burst and the internal write recovery is in progress. In case of a write command, active powerdown mode entry is allowed when WL + BL/2 + tWTR is satisfied. Active Power-down mode can be entered after an Activate command. Precharge Power-down mode can be entered after a Precharge, Precharge-All or internal precharge command. It is also allowed to enter powermode after an Auto-Refresh command or MRS / EMRS(1) command when tMRD is satisfied. In case of a write command with Auto-Precharge, Power-down mode entry is allowed after the internal precharge command has been executed, which is WL + BL/2 + WR starting from the write with AutoPrecharge command. In this case the DDR2 SDRAM enters the Precharge Power-down mode. Active Power-down mode entry is prohibited as long as a Read Burst is in progress, meaning CKE should be kept high until the burst operation is finished. Therefore Active Power-Down mode entry after a Read or Read with Auto-Precharge command is allowed after RL + BL/2 is satisfied. T0 T1 T2 Tn Tn+1 Tn+2 CK, CK CM D NOP A ctivate NOP V alid C om m and NOP NOP NOP tIS CKE tIS tXARD or tXARDS *) Act.PD 0 Active Power-Down Exit Active Power-Down Entry Figure 54 Active Power-Down Mode Entry and Exit after an Activate Command Note: Active Power-Down mode exit timing tXARD (“fast exit”) or tXARDS (“slow exit”) depends on the programmed state in the MRS, address bit A12. T0 T1 T2 T3 T4 T5 T6 T7 T8 Tn Tn+1 Tn+2 CK, CK CMD READ R E A D w /A P NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP V a lid C om m a nd tIS CKE RL + BL/2 tIS DQ S, DQS AL = 1 DQ tXARD or tXARDS *) CL = 3 RL = 4 Dout A0 Dout A1 Dout A2 Dout A3 Active Power-Down Entry Figure 55 Active Power-Down Exit Act.PD 1 Active Power-Down Mode Entry and Exit Example after a Read Command: RL = 4 (AL = 1, CL =3), BL = 4 Note: Active Power-Down mode exit timing tXARD (“fast exit”) or tXARDS (“slow exit”) depends on the programmed state in the MRS, address bit A12. Data Sheet 60 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description T0 T1 T2 T3 T4 T5 T6 Tn T7 Tn+1 Tn+2 CK, CK CMD W R IT E NOP NOP NOP NOP CKE NOP NOP NOP NOP NOP V alid C o m m and NOP tIS WL + BL/2 + tWTR tIS DQS, DQS WL = RL - 1 = 2 DQ tWTR tXARD or tXARDS *) DIN A0 DIN A1 DIN A2 DIN A3 Active Power-Down Entry Figure 56 Active Power-Down Exit Act.PD 2 Active Power-Down Mode Entry and Exit Example after a Write Command: WL = 2, tWTR = 2, BL = 4 Note: Active Power-Down mode exit timing tXARD (“fast exit”) or tXARDS (“slow exit”) depends on the programmed state in the MRS, address bit A12. T0 T1 T2 T3 T4 T5 T6 Tn T7 Tn+1 Tn+2 CK, CK CM D W R IT E w /A P NOP CKE NOP NOP NOP NOP NOP WL + BL/2 + WR NOP tIS NOP NOP V a lid Com m and NOP tIS DQS, DQS WL = RL - 1 = 2 DQ WR tXARD or tXARDS *) DIN A0 DIN A1 DIN A2 DIN A3 Active Power-Down Entry Figure 57 Active Power-Down Exit Act.PD 3 Active Power-Down Mode Entry and Exit Example after a Write Command with AP: WL = 2, WR = 3, BL = 4 Note: Active Power-Down mode exit timing tXARD (“fast exit”) or tXARDS (“slow exit”) depends on the programmed state in the MRS, address bit A12. WR is the programmed value in the MRS mode register. Data Sheet 61 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description T0 T1 T2 T3 Tn Tn+1 Tn+2 CK, CK CMD NOP Precharge NOP NOP NOP NOP NOP Valid Command NOP tIS CKE tIS tXP tRP Precharge Power-Down Entry Figure 58 Precharge Power-Down Exit Precharge Power Down Mode Entry and Exit Note: "Precharge" may be an external command or an internal precharge following Write with AP. T0 T1 T2 T3 T4 Tn CK, CK tRFC Auto Refresh CMD tXP Valid Command CKE tis CKE can go low one clock after an Auto-Refresh command When tRFC expires the DRAM is in Precharge Power-Down Mode Figure 59 T0 ARPD Auto-Refresh command to Power-Down entry T1 T2 T3 T4 T5 T6 T7 CK, CK CMD MRS or EMRS t MRD CKE Enters Precharge Power-Down Mode Figure 60 Data Sheet MRS_PD MRS, EMRS command to Power-Down entry 62 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description 2.11 Other Commands 2.11.1 No Operation Command registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle. The No Operation Command (NOP) should be used in cases when the SDRAM is in a idle or a wait state. The purpose of the No Operation Command is to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is 2.11.2 Deselect Command The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs 2.12 when CS is brought high, the RAS, CAS, and WE signals become don’t care. Input Clock Frequency Change satisfied the input clock frequency can be changed. A stable new clock frequency has to be provided, before CKE can be changed to a “high” logic level again. After tXP has been satisfied a DLL RESET command via EMRS(1) has to be issued. During the following DLL relock period of 200 clock cycles, ODT must remain off. After the DLL-re-lock period the DRAM is ready to operate with the new clock frequency. During operation the DRAM input clock frequency can be changed under the following conditions: • • During Self-Refresh operation DRAM is in Precharge Power-down mode and ODT is completely turned off. The DDR2-SDRAM has to be in Precharged Powerdown mode and idle. ODT must be already turned off and CKE must be at a logic “low” state. After a minimum of two clock cycles after tRP and tAOFD have been T0 T1 T2 T3 T4 Tx Tx+1 Ty Ty+1 Ty+2 Tz Ty+3 CK, CK CMD NOP NOP NO P NOP NOP NOP NOP NOP NO P D LL RESET NO P V alid C o m m a nd CKE tRP tAOFD tXP Minimum 2 clocks required before changing the frequency Frequency Change occurs here 200 clocks Stable new clock before power-down exit ODT is off during DLL RESET Frequ.Ch. Figure 61 Data Sheet Input Frequency Change Example during Precharge Power-Down mode 63 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Functional Description 2.13 Asynchronous CKE Low Reset Event contents of the memory array. If this event occurs, the memory controller must satisfy a time delay (tdelay) before turning off the clocks. Stable clocks must exist at the input of DRAM before CKE is raised “high” again. The DRAM must be fully re-initialized as described the initialization sequence (section 2.2.1, step 4 thru 13). DRAM is ready for normal operation after the initialization sequence. See Chapter 7. In a given system, Asynchronous Reset event can occur at any time without prior knowledge. In this situation, memory controller is forced to drop CKE asynchronously low, immediately interrupting any valid operation. DRAM requires CKE to be maintained “high” for all valid operations as defined in this data sheet. If CKE asynchronously drops “low” during any valid operation, the DRAM is not guaranteed to preserve the stable clocks CK, CK tdelay CKE CKE drops low due to an asynchronous reset event Figure 62 Data Sheet Clocks can be turned off after this point Asynchronous Low Reset Event 64 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Truth Tables 3 Truth Tables Table 16 Command Truth Table Function CS RAS CAS WE BA0 A[13:11] A10 A[9:0] BA1 Previous Current Cycle Cycle CKE Notes 1)2)3)4) 5) (Extended) Mode Register Set H H L L L L BA OP Code Auto-Refresh H H L L L H X X X X Self-Refresh Entry H L L L L H X X X X 6) Self-Refresh Exit L H H X X X X X X X 6) Single Bank Precharge H H L L H L BA X L X 5) Precharge all Banks H H L L H L X X H X Bank Activate H H L L H H BA Row Address Write H H L H L L BA Column L Column 5)7) Write with AutoPrecharge H H L H L L BA Column H Column 5)7) Read H H L H L H BA Column L Column 5)7) Read with AutoPrecharge H H L H L H BA Column H Column 5)7) No Operation H X L H H H X X X X Device Deselect H X H X X X X X X X Power Down Entry H L H X X X X X X X 8) L H H H H X X X X X X X 4)8) L H H H Power Down Exit L H 5) 1) All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock. 2) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. 3) “X” means “H or L (but a defined logic level)”. 4) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 5) Bank addresses (BAx) determine which bank is to be operated upon. For (E)MRS BAx selects an (Extended) Mode Register. 6) VREF must be maintained during Self refresh Operation 7) Burst reads or writes at BL = 4 cannot be terminated. 8) The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh requirements outlined in Chapter 2.9. Data Sheet 65 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Truth Tables Table 17 Clock Enable (CKE) Truth Table for Synchronous Transitions Current State1) CKE Command (N)2) 3) Action (N)2) Notes4)5) Maintain Power-Down 7)8)11) Previous Cycle6) Current Cycle6) RAS, CAS, WE, CS (N-1) (N) Power-Down L L X L H DESELECT or NOP Power-Down Exit 9)10)11)7) L L X 11)8)12) L H DESELECT or NOP Self Refresh Exit 9)13)14)12) Bank(s) Active H L DESELECT or NOP Active Power-Down Entry 9)10)15)11)7) All Banks Idle H L DESELECT or NOP Precharge Power-Down Entry 9)10)15)11) H L AUTOREFRESH 16)14)11)7) Any State other H than listed above H Refer to the Command Truth Table Self Refresh Maintain Self Refresh Self Refresh Entry 17) 1) Current state is the state of the DDR2 SDRAM immediately prior to clock edge N. 2) Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N) 3) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. 4) CKE must be maintained high while the device is in OCD calibration mode. 5) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 6) CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge. 7) The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by the refresh requirements 8) “X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven high or low in Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMRS(1)). 9) All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 10) Valid commands for Power-Down Entry and Exit are NOP and DESELECT only. 11) Minimum CKE high time is 3 clocks, minimum CKE low time is 3 clocks. 12) VREF must be maintained during Self Refreh Operation 13) On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read commands may be issued only after tXSRD (200 clocks) is satisfied. 14) Valid commands for Self Refresh Exit are NOP and DESELCT only. 15) Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations, Precharge or Refresh operations are in progress. See Chapter 2.10 and Chapter 2.9.2 for a detailed list of restrictions. 16) Self Refresh mode can only be entered from the All Banks Idle state. 17) Must be a legal command as defined in the Command Truth Table. Table 18 Data Mask (DM) Truth Table Name (Function) DM DQs Notes Write Enable L Valid 1) Write Inhibit H X 1) 1) Used to mask write data; provided coincident with the corresponding data. Data Sheet 66 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Operating Conditions 4 Operating Conditions Table 19 Absolute Maximum Ratings Symbol Parameter VDD VDDQ VDDL VIN, VOUT TSTG Rating Units Notes Voltage on VDD pin relative to VSS -1.0 to +2.3 V 1) Voltage on VDDQ pin relative to VSS -0.5 to +2.3 V 1) Voltage on VDDL pin relative to VSS -0.5 to +2.3 V 1) Voltage on any pin relative to VSS -0.5 to +2.3 V 1) Storage Temperature -55 to +100 °C 1) 1) Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 20 DRAM Component Operating Temperature Range Symbol Parameter TOPER Operating Temperature Rating Units Notes 0 to 95 o 1)2)3)4) C 1) Operating Temperature is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case temperature must be maintained between 0 - 95 oC under all other specification parameters. 3) Above 85 oC case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs. 4) Self-Refresh period is hard-coded in the chip and therefore it is imperative that the system ensures the DRAM is below 85oC case temperature before initiating self-refresh operation. Data Sheet 67 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM AC & DC Operating Conditions 5 AC & DC Operating Conditions 5.1 DC Operating Conditions Table 21 Recommended DC Operating Conditions (SSTL_18) Symbol Parameter Rating Units Notes Min. Typ. Max. VDD VDDDL VDDQ VREF VTT Supply Voltage 1.7 1.8 1.9 V 1) Supply Voltage for DLL 1.7 1.8 1.9 V 1) Supply Voltage for Output 1.7 1.8 1.9 V 1) Input Reference Voltage 0.49 × VDDQ 0.5 × VDDQ 0.51 × VDDQ V 2)3) Termination Voltage VREF – 0.04 VREF VREF + 0.04 V 4) VDDQ tracks with VDD, VDDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together. 2) The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 × VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 3) Peak to peak ac noise on VREF may not exceed ± 2% VREF (dc) 4) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in die dc level of VREF. 1) Table 22 ODT DC Electrical Characteristics Parameter / Condition Symbol Min. Nom. Max. Units Notes Termination resistor impedance value for EMRS(1)(A6,A2)= 0,1 Rtt1(eff) 60 75 90 Ω 1) Termination resistor impedance value for EMRS(1)(A6,A2)=1,0 Rtt2(eff) 120 150 180 Ω 1) Deviation of VM with respect to VDDQ / 2 delta VM –6.00 — + 6.00 % 2) 1) Measurement Definition for Rtt(eff): Apply VIH(ac) and VIL(ac) to test pin separately, then measure current I(VIHac) and I(VILac) respectively. Rtt(eff) = (VIH(ac) – VIL(ac)) /(I(VIHac) – I(VILac)). 2) Measurement Definition for VM: Measure voltage (VM) at test pin (midpoint) with no load: delta VM =((2 x VM / VDDQ) – 1) x 100% Table 23 Input and Output Leakage Currents Symbol Parameter / Condition Min. Max. Units Notes IIL Input Leakage Current; any input 0 V < VIN < VDD –2 +2 µA 1) IOL Output Leakage Current; 0 V < VOUT < VDDQ –5 +5 µA 2) 1) all other pins not under test = 0 V 2) DQ’s, DQS, DQS and ODT are disabled Data Sheet 68 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM AC & DC Operating Conditions 5.2 DC & AC Logic Input Levels relative to the rising or falling edges of DQS crossing at DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the EMRS(1) “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timing are measured is mode dependent. In single ended mode, timing relationships are measured Table 24 VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is verified by design and characterization but not subject to production test. In single ended mode, the DQS (and RDQS) signals are internally disabled and don’t care. Single-ended DC & AC Logic Input Levels Symbol Parameter Min. Max. Units VIH(dc) VIL(dc) VIH(ac) VIL(ac) DC input logic high VREF + 0.125 V DC input low –0.3 VDDQ + 0.3 VREF – 0.125 AC input logic high VREF + 0.250 — V AC input low — VREF – 0.250 V Table 25 Symbol V Single-ended AC Input Test Conditions Condition Value Units Notes VREF VSWING(max) Input reference voltage 0.5 x VDDQ V 1)2) Input signal maximum peak to peak swing 1.0 V 1)2) SLEW Input signal minimum slew rate 1.0 V / ns 3)4) 1. 1) This timing and slew rate definition is valid for all single-ended signals except tIS, tIH, tDS, tDH. 2) Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 3) The input signal minimum slew rate is to be maintained over the range from VIL(dc)max to VIH(ac)min for rising edges and the range from VIH(dc)min to VIL(ac)max for falling edges as shown in Figure 63 4) AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac on the negative transitions. Start of Falling Edge Input Timing Start of Rising Edge Input Timing VDDQ VIH(ac) min VIH(dc) min VSWING(MAX) VREF VIL(dc) max VIL(ac) max delta TF Falling Slew = Figure 63 Data Sheet delta TR VIH (dc) min - V IL(ac) max Rising Slew = delta TF VSS VIH(ac) min - VIL(dc) max delta TR Single-ended AC Input Test Conditions Diagram 69 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM AC & DC Operating Conditions Table 26 Differential DC and AC Input and Output Logic Levels Symbol Parameter Min. Max. Units VIN(dc) VID(dc) VID(ac) VIX(ac) DC input signal voltage –0.3 DC differential input voltage 0.25 AC differential input voltage 0.5 AC differential cross point input voltage 0.5 × VDDQ – 0.175 VDDQ + 0.3 VDDQ + 0.6 VDDQ + 0.6 0.5 × VDDQ + 0.175 VOX(ac) AC differential cross point output voltage 0.5 × VDDQ – 0.125 0.5 × VDDQ + 0.125 1) 2) 3) 4) 5) Notes 1) 2) V 3) V 4) V 5) VIN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc. VID(dc) specifies the input differential voltage VTR– VCP required for switching. The minimum value is equal to VIH(dc) – VIL(dc). VID(ac) specifies the input differential voltage VTR – VCP required for switching. The minimum value is equal to VIH(ac) – VIL(ac). The value of VIX(ac) is expected to equal 0.5 × VDDQ of the transmitting device and VIX(ac) is expected to track variations in VDDQ. VIX(ac) indicates the voltage at which differential input signals must cross. The value of VOX(ac) is expected to equal 0.5 × VDDQ of the transmitting device and VOX(ac) is expected to track variations in VDDQ. VOX(ac) indicates the voltage at which differential input signals must cross. VDDQ VTR Crossing Point VID VCP VIX or VOX VSSQ SSTL18_3 Figure 64 Data Sheet Differential DC and AC Input and Output Logic Levels Diagram 70 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM AC & DC Operating Conditions 5.3 Output Buffer Table 27 SSTL_18 Output AC Test Conditions Symbol Parameter SSTL_18 Class II Units Notes VOH VOL VOTR Minimum Required Output Pull-up VTT + 0.603 VTT – 0.603 0.5 × VDDQ V 1) V 1) V 2) Maximum Required Output Pull-down Output Timing Measurement Reference Level 1) SSTL_18 test load for VOH and VOL is different from the referenced load described in Chapter 8.1. The SSTL_18 test load has a 20 Ohm series resistor additionally to the 25 Ohm termination resistor into VTT. The SSTL_18 definition assumes that ± 335 mV must be developed across the effectively 25 Ohm termination resistor (13.4 mA × 25 Ohm = 335 mV). With an additional series resistor of 20 Ohm this translates into a minimum requirement of 603 mV swing relative to VTT, at the ouput device (13.4 mA × 45 Ohm = 603 mV). 2) The VDDQ of the device under test is referenced. Table 28 Symbol IOH IOL 1) SSTL_18 Output DC Current Drive Parameter SSTL_18 Class II Units Notes Output Minimum Source DC Currentl –13.4 mA 1)2)3) Output Minimum Sink DC Current 13.4 mA 2)3)4) VDDQ = 1.7 V; VOUT = 1.42 V. (VOUT–VDDQ) / IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ – 280 mV. 2) The dc value of VREF applied to the receiving device is set to VTT 3) The values of IOH(dc) and IOL(dc) are based on the conditions given in 1) and 4). They are used to test drive current capability to ensure VIHmin. plus a noise margin and VILmax minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating points along 21 Ohm load line to define a convenient current for measurement. 4) VDDQ = 1.7 V; VOUT = 280 mV. VOUT / IOL must be less than 21 Ohm for values of VOUT between 0 V and 280 mV. Table 29 OCD Default Characteristics Symbol Description Min. Nominal Max. Units Notes — Output Impedance 12.6 18 23.4 Ohms 1)2) — Pull-up / Pull down mismatch 0 — 4 Ohms 1)2)3) — Output Impedance step size for OCD calibration 0 — 1.5 Ohms 4) SOUT Output Slew Rate 1.5 — 5.0 V / ns 1)5)6)7)8) 1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V 2) Impedance measurement condition for output source dc current: VDDQ = 1.7 V, VOUT = 1420 mV; (VOUT–VDDQ) / IOH must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ – 280 mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7 V; VOUT = –280 mV; VOUT / IOL must be less than 23.4 Ohms for values of VOUT between 0 V and 280 mV. Mismatch is absolute value between pull-up and pull-down, both are measured at same temperature and voltage. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and represents only the DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18 ± 0.75 Ohms under nominal conditions. Slew rates measured from VIL(ac) to VIH(ac) with the load specified in Chapter 8.2. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is verified by design and characterisation but not subject to production test. 3) 4) 5) 6) Data Sheet 71 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM AC & DC Operating Conditions 7) Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQ’s is included in tDQSQ and tQHS specification. 8) DRAM output slew rate specification applies to 400, 533 and 667 MT/s speed bins. 5.4 Default Output V-I Characteristics DDR2 SDRAM output driver characteristics are defined for full strength default operation as selected by the EMRS(1) bits A[9:7] =’111’. Figure 65 and Figure 66 Table 30 show the driver characteristics graphically and the tables show the same data suitable for input into simulation tools. Full Strength Default Pull-up Driver Characteristics Voltage (V) Pull-up Driver Current [mA] Min. Nominal Default low Nominal Default high Max. 0.2 –8.5 –11.1 –11.8 –15.9 0.3 –12.1 –16.0 –17.0 –23.8 0.4 –14.7 –20.3 –22.2 –31.8 0.5 –16.4 –24.0 –27.5 –39.7 0.6 –17.8 –27.2 –32.4 –47.7 0.7 –18.6 –29.8 –36.9 –55.0 0.8 –19.0 –31.9 –40.8 –62.3 0.9 –19.3 –33.4 –44.5 –69.4 1.0 –19.7 –34.6 –47.7 –75.3 1.1 –19.9 –35.5 –50.4 –80.5 1.2 –20.0 –36.2 –52.5 –84.6 1.3 –20.1 –36.8 –54.2 –87.7 1.4 –20.2 –37.2 –55.9 –90.8 1.5 –20.3 –37.7 –57.1 –92.9 1.6 –20.4 –38.0 –58.4 –94.9 1.7 –20.6 –38.4 –59.6 –97.0 1.8 — –38.6 –60.8 –99.1 1.9 — — — –101.1 Note: The driver characteristics evaluation conditions are: 1. Nominal Default 25oC (Tcase), VDDQ = 1.8 V, typical process 2. Minimum 95 oC (Tcase), VDDQ = 1.7V, slow–slow process 3. Maximum 0 oC (Tcase). VDDQ = 1.9 V, fast–fast process Data Sheet 72 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM AC & DC Operating Conditions 0 Pullup current (mA) -20 -40 Minimum Nominal Default Low Nominal Default High Maximum -60 -80 -100 -120 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 VDDQ to VOUT (V) Figure 65 Full Strength Default Pull-up Driver Diagram Table 31 Full Strength Default Pull–down Driver Characteristics Voltage (V) Pull-down Driver Current [mA] Minimum Nominal Default low Nominal Default high Maximum 0.2 8.5 11.3 11.8 15.9 0.3 12.1 16.5 16.8 23.8 0.4 14.7 21.2 22.1 31.8 0.5 16.4 25.0 27.6 39.7 0.6 17.8 28.3 32.4 47.7 0.7 18.6 30.9 36.9 55.0 0.8 19.0 33.0 40.9 62.3 0.9 19.3 34.5 44.6 69.4 1.0 19.7 35.5 47.7 75.3 1.1 19.9 36.1 50.4 80.5 1.2 20.0 36.6 52.6 84.6 1.3 20.1 36.9 54.2 87.7 1.4 20.2 37.1 55.9 90.8 1.5 20.3 37.4 57.1 92.9 1.6 20.4 37.6 58.4 94.9 1.7 20.6 37.7 59.6 97.0 1.8 — 37.9 60.9 99.1 1.9 — — — 101.1 Note: The driver characteristics evaluation conditions are: 1. Nominal Default 25 oC (Tcase), VDDQ = 1.8 V, typical process, 2. Minimum 95 oC (Tcase), VDDQ = 1.7V, slow-slow process, 3. Maximum 0 oC (Tcase). VDDQ = 1.9 V, fast-fast process Data Sheet 73 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM AC & DC Operating Conditions Pulldown current (mA) 120 100 80 Minimum Nominal Default Low Nominal Default High Maximum 60 40 20 0 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 VOUT to VSSQ (V) Figure 66 Full Strength Default Pull–down Driver Diagram 5.4.1 Calibrated Output Driver V-I Characteristics looking at one DQ only. If the calibration procedure is used, it is possible to cause the device to operate outside the bounds of the default device characteristics tables and figure. In such a situation, the timing parameters in the specification cannot be guaranteed. It is solely up to the system application to ensure that the device is calibrated between the minimum and maximum default values at all times. If this can’t be guaranteed by the system calibration procedure, recalibration policy and uncertainty with DQ to DQ variation, it is recommended that only the default values to be used. The nominal maximum ad minimum values represent the change in impedance from nominal low and high as a result of voltage and temperature change from the nominal condition to the maximum and minimum conditions. If calibrated at an extreme condition, the amount of variation could be as much as from the nominal minimum to the nominal maximum or vice versa. DDR2 SDRAM output driver characteristics are defined for full strength calibrated operation as selected by the procedure outlined in the Off-Chip Driver (OCD) Impedance Adjustment. The Table 32 and Table 33 show the data in tabular format suitable for input into simulation tools. The nominal points represent a device at exactly 18 ohms. The nominal low and nominal high values represent the range that can be achieved with a maximum 1.5 ohms step size with no calibration error at the exact nominal conditions only (i.e. perfect calibration procedure, 1.5 ohm maximum step size guaranteed by specification). Real system calibration error needs to be added to these values. It must be understood that these V-I curves are represented here or in supplier IBIS models need to be adjusted to a wider range as a result of any system calibration error. Since this is a system specific phenomena, it cannot be quantified here. The values in the calibrated tables represent just the DRAM portion of uncertainty while Data Sheet 74 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM AC & DC Operating Conditions Table 32 Voltage (V) Full Strength Calibrated Pull-down Driver Characteristics Calibrated Pull-down Driver Current [mA] Nominal Minimum (21 Ohms) Normal Low (18.75 Ohms) Nominal (18 ohms) Normal High (17.25 Ohms) Nominal Maximum (15 Ohms) 0.2 9.5 10.7 11.5 11.8 13.3 0.3 14.3 16.0 16.6 17.4 20.0 0.4 18.7 21.0 21.6 23.0 27.0 Note: The driver characteristics evaluation conditions are: 1. 2. 3. 4. Nominal 25 oC (Tcase), VDDQ = 1.8 V, typical process Nominal Low and Nominal High 25 oC (Tcase), VDDQ = 1.8V, any process Nominal Minimum 95 oC (Tcase). VDDQ = 1.7 V, any process Nominal Maximum 0 oC (Tcase), VDDQ = 1.9 V, any process Table 33 Voltage (V) Full Strength Calibrated Pull-up Driver Characteristics Calibrated Pull-up Driver Current [mA] Nominal Minimum (21 Ohms) Normal Low (18.75 Ohms) Nominal (18 ohms) Normal High (17.25 Ohms) Nominal Maximum (15 Ohms) 0.2 –9.5 –10.7 –11.4 –11.8 –13.3 0.3 –14.3 –16.0 –16.5 –17.4 –20.0 0.4 –18.3 –21.0 –21.2 –23.0 –27.0 Note: The driver characteristics evaluation conditions are: 1. 2. 3. 4. Nominal 25 oC (Tcase), VDDQ = 1.8 V, typical process Nominal Low and Nominal High 25 oC (Tcase), VDDQ = 1.8V, any process Nominal Minimum 95 oC (Tcase). VDDQ = 1.7 V, any process Nominal Maximum 0 oC (Tcase), VDDQ = 1.9 V, any process 5.5 Input / Output Capacitance Table 34 Input / Output Capacitance Symbol Parameter min. max. Units CCK Input capacitance, CK and CK 1.0 2.0 pF CDCK Input capacitance delta, CK and CK — 0.25 pF CI Input capacitance, all other input-only pins 1.0 2.0 pF CDI Input capacitance delta, all other input-only pins — 0.25 pF CIO Input/output capacitance, DQ, DM, DQS, DQS, RDQS, RDQS 3.0 4.0 pF CDIO Input/output capacitance delta, DQ, DM, DQS, DQS, RDQS, RDQS — 0.5 pF Data Sheet 75 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM AC & DC Operating Conditions 5.6 Power & Ground Clamp V-I Characteristics Power and Ground clamps are provided on address (A[13:0], BA[1:0]), RAS, CAS, CS, WE, CKE and ODT Table 35 pins. The V-I characteristics for pins with clamps is shown in Table 35. Power & Ground Clamp V-I Characteristics Voltage across clamp (V) Minimum Power Clamp Current (mA) Minimum Ground Clamp Current (mA) 0.0 0 0 0.1 0 0 0.2 0 0 0.3 0 0 0.4 0 0 0.5 0 0 0.6 0 0 0.7 0 0 0.8 0.1 0.1 0.9 1.0 1.0 1.0 2.5 2.5 1.1 4.7 4.7 1.2 6.8 6.8 1.3 9.1 9.1 1.4 11.0 11.0 1.5 13.5 13.5 1.6 16.0 16.0 1.7 18.2 18.2 1.8 21.0 21.0 Data Sheet 76 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM IDD Specifications and Conditions 6 IDD Specifications and Conditions Table 36 IDD Measurement Conditions Parameter Symbol Notes 1)2)3)4)5)6) Operating Current 0 IDD0 One bank Active - Precharge; tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin., CKE is HIGH, CS is high between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Operating Current 1 IDD1 One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin., tRCD = tRCDmin.,AL = 0, CL = CLmin.; CKE is HIGH, CS is high between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Precharge Power-Down Current IDD2P All banks idle; CKE is LOW; tCK = tCKmin;Other control and address inputs are STABLE, Data bus inputs are FLOATING. Precharge Standby Current All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. IDD2N Precharge Quiet Standby Current All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address inputs are STABLE, Data bus inputs are FLOATING. IDD2Q Active Power-Down Current IDD3P(0) All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to “0” (Fast Power-down Exit); Active Power-Down Current IDD3P(1) All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to “1” (Slow Power-down Exit); Active Standby Current IDD3N Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.; tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA. Operating Current IDD4R Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.; tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA. Operating Current IDD4W Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.; tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; Burst Refresh Current tCK = tCKmin., Refresh command every tRFC = tRFCmin. interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. IDD5B Distributed Refresh Current tCK = tCKmin., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. IDD5D Data Sheet 77 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM IDD Specifications and Conditions Table 36 IDD Measurement Conditions Parameter Symbol Notes 1)2)3)4)5)6) Self-Refresh Current CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data bus inputs are FLOATING. RESET = Low. IDD6 current values are guaranteed up to TCASE of 85 °C max. IDD6 All Bank Interleave Read Current All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address bus inputs are STABLE during DESELECTS. Iout = 0 mA. IDD7 VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V 2) IDD specifications are tested after the device is properly initialized. 3) IDD parameter are specified with ODT disabled. 1) 4) Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS. 5) Definitions for IDD: LOW is defined as VIN ≤ VIL(ac)max; HIGH is defined as VIN ≥ VIH(ac)min; STABLE is defined as inputs are stable at a HIGH or LOW level; FLOATING is defined as inputs are VREF = VDDQ / 2; SWITCHING is defined as: Inputs are changing between HIGH and LOW every other clock (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other clock (once per clock) for DQ signals not including mask or strobes. 6) Timing parameter minimum and maximum values for IDD current measurements are defined in Table 38. Table 37 IDD Specification Product Type Speed Code –3.7 –5 Speed Grade DDR2 – 533 DDR2 – 400 Unit Notes Symbol Max. Max. IDD0 65 55 mA ×4/×8 80 70 mA ×16 75 60 mA ×4/×8 90 75 mA ×16 4 4 mA ×16/×4/×8 40 32 mA ×16/×4/×8 30 25 mA ×16/×4/×8 16 13 mA ×16/×4/×8 MRS(12)=0 5 5 mA ×16/×4/×8 MRS(12)=1 40 35 mA ×16/×4/×8 90 70 mA ×4/×8 100 85 mA ×16 IDD4W 95 75 mA ×4/×8 110 90 mA ×16 IDD5B IDD5D IDD6 130 120 mA ×16/×4/×8 6 6 mA IDD1 IDD2P IDD2N IDD2Q IDD3P IDD3N IDD4R IDD7 1) ×16/×4/×8 4 4 mA 1) 2 2 mA 1) 140 130 mA ×4/×8 220 210 mA ×16 , standard products , low power products IDD6: 0 ≤ TCASE ≤ 85 oC Data Sheet 78 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM IDD Specifications and Conditions 6.1 IDD Test Conditions For testing the IDD parameters, the following timing parameters are used: Table 38 IDD Measurement Test Condition Parameter Symbol -3.7 -5 Units Notes DDR2–533 4–4–4 DDR2–400 3–3–3 CAS Latency CLmin 4 3 tCK Clock Cycle Time tCKmin tRCDmin tRCmin 3.75 5 ns 15 15 ns 60 55 ns Active bank A to Active bank B command delay tRRDmin 7.5 7.5 ns 1) 10 10 ns 2) Active to Precharge Command tRASmin tRPmin tRFCmin 45 40 ns 15 15 ns 105 105 ns Active to Read or Write delay Active to Active / Auto-Refresh command period Precharge Command Period Auto-Refresh to Active / Auto-Refresh command period 1) ×4 & ×8 (1 kB page size) 2) ×16 (2 kB page size) 6.2 On Die Termination (ODT) Current current consumption for any terminated input pin, depends on the input pin is in tri-state or driving “0” or “1”, as long a ODT is enabled during a given period of time. The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1). Depending on address bits A6 & A2 in the EMRS(1) a “week” or “strong” termination can be selected. The . Table 39 ODT current per terminated input pin: ODT Current EMRS(1) State min. typ. max. Unit Enabled ODT current per DQ IODTO added IDDQ current for ODT enabled; ODT is HIGH; Data Bus inputs are FLOATING A6 = 0, A2 = 1 5 6 7.5 mA/DQ A6 = 1, A2 = 0 2.5 3 3.75 mA/DQ Active ODT current per DQ IODTT added IDDQ current for ODT enabled; ODT is HIGH; worst case of Data Bus inputs are STABLE or SWITCHING. A6 = 0, A2 = 1 10 12 15 mA/DQ A6 = 1, A2 = 0 5 6 7.5 mA/DQ Note: For power consumption calculations the ODT duty cycle has to be taken into account Data Sheet 79 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Electrical Characteristics & AC Timing - Absolute Specification 7 Electrical Characteristics & AC Timing - Absolute Specification Table 40 Timing Parameter by Speed Grade - DDR2-400 & DDR2-5331)2)3)4)5)6) Symbol Parameter tAC tDQSCK tCH tCL tHP tCK –5 DDR2–400 3–3–3 –3.7 DDR2–533 4–4–4 Unit Notes Min. Max. Min. Max. DQ output access time from CK / CK –600 + 600 –500 +500 ps DQS output access time from CK / CK –500 + 500 –450 +450 ps CK, CK high-level width 0.45 0.55 0.45 0.55 CK, CK low-level width 0.45 0.55 0.45 0.55 tCK tCK Clock half period min. (tCL, tCH) min. (tCL, tCH) Clock cycle time 5000 8000 5000 8000 ps 8)9) 5000 8000 3750 8000 ps 8)10) 7) tIS tIH tDS tDH tIPW Address and control input setup time 350 — 250 — ps 11) Address and control input hold time 475 — 375 — ps 11) DQ and DM input setup time 150 — 100 — ps 12) DQ and DM input hold time 275 — 225 — ps 12) Address and control input pulse width (each input) 0.6 — 0.6 — tCK tDIPW tHZ DQ and DM input pulse width (each input) 0.35 — 0.35 — tCK Data-out high-impedance time from CK / CK — tACmax — tACmax ps 13) tLZ(DQ) tLZ(DQS) tDQSQ DQ low-impedance time from CK / CK 2×tACmin 2×tACmin 13) tACmin tACmin tACmax tACmax ps DQS low-impedance from CK / CK tACmax tACmax ps 13) DQS-DQ skew (for DQS & associated DQ — signals) 350 — 300 ps 14) tQHS tQH tDQSS Data hold skew factor — 450 — 400 ps Data output hold time from DQS tHP-tQHS — tHP-tQHS — Write command to 1st DQS latching transition WL –0.25 WL +0.25 WL –0.25 WL +0.25 tCK tDQSL,H DQS input low (high) pulse width (write cycle) 0.35 — 0.35 — tCK tDSS DQS falling edge to CK setup time (write cycle) 0.2 — 0.2 — tCK tDSH DQS falling edge hold time from CK (write 0.2 cycle) — 0.2 — tCK tMRD tWPRE tWPST tRPRE tRPST tRAS tRC Mode register set command cycle time 2 — 2 — Write preamble 0.25 — 0.25 — Write postamble 0.40 0.60 0.40 0.60 Read preamble 0.9 1.1 0.9 1.1 Read postamble 0.40 0.60 0.40 0.60 tCK tCK tCK tCK tCK Active to Precharge command 40 70000 45 70000 ns Active to Active/Auto-Refresh command period 55 — 60 — ns Data Sheet 80 15) 13) 13) 16) Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Electrical Characteristics & AC Timing - Absolute Specification Timing Parameter by Speed Grade - DDR2-400 & DDR2-5331)2)3)4)5)6) Table 40 Symbol Parameter –5 DDR2–400 3–3–3 –3.7 DDR2–533 4–4–4 Min. Max. Min. Max. Unit Notes tRFC Auto-Refresh to Active/Auto-Refresh command period 105 — 105 — ns 17) tRCD Active to Read or Write delay (with and without Auto-Precharge) 15 — 15 — ns 18) tRP tRRD Precharge command period 15 — 15 — ns Active bank A to Active bank B command period 7.5 — 7.5 — ns 19) 10 — 10 — ns 20) tCCD tWR tDAL CAS A to CAS B command period 2 Write recovery time 15 Auto-Precharge write recovery + precharge time tWTR tRTP tCK 2 — ns WR + tRP — WR + tRP — tCK 21) Internal Write to Read command delay 10 — 7.5 — ns 22) Internal Read to Precharge command delay 7.5 — 7.5 — ns tXARD Exit power down to any valid command (other than NOP or Deselect) 2 — 2 — tCK 23) tXARDS Exit active power-down mode to Read command (slow exit, lower power) 6 - AL — 6 - AL — tCK 23) tXP Exit precharge power-down to any valid command (other than NOP or Deselect) 2 — 2 — tCK tXSRD tXSNR tCKE tREFI Exit Self-Refresh to Read command 200 — 200 — tCK Exit Self-Refresh to non-Read command tRFC+10 — tRFC+10 CKE minimum high and low pulse width 3 — 3 — Average periodic refresh Interval — 7.8 — 7.8 — 3.9 — 3.9 tCK µs µs 0 12 0 12 ns tIS+tCK+tIH –– ns tOIT tDELAY OCD drive mode output delay — Minimum time clocks remain ON after CKE tIS+tCK+tIH — asynchronously drops LOW 15 ns 24)25) 26) 27) 1) VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V) See notes 3)4)5)6) 2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 3) Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1 V/ns in single ended mode. For other slew rates see Chapter 8 of this datasheet. 4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS, RDQS / RDQS, tIS, tiH, tDS, tDH is VREF. For tIS, tiH, tDS, tDH input reference levels see Chapter 8.3 of this datasheet. 5) Inputs are not recognized as valid until recognized as LOW. VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is 6) The output timing reference voltage level is VTT. See Chapter 8 for the reference load for timing measurements. 7) Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). 8) For input frequency change during DRAM operation, see Chapter 2.12 of this datasheet. Data Sheet 81 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Electrical Characteristics & AC Timing - Absolute Specification 9) CL = 3 10) CL = 4 & 5 11) For timing definition, slew rate and slew rate derating see Chapter 8.3 12) For timing definition, slew rate and slew rate derating see Chapter 8.3 13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These parameters are verified by design and characterisation, but not subject to production test. 14) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mis-match between DQS / DQS and associated DQ in any given cycle. 15) The maximum limit for this parameter is not a device limit. The device operate with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 16) tRAS(max) is calculated from the maximum amount of time a DDR2 device can operate without a Refresh command which is equal to 9 x tREFI. 17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 18) The tRCD timing parameter is valid for both activate command to read or write command with and without Auto-Precharge. Therefore a separate parameter tRAP for activate command to read or write command with Auto-Precharge is not necessary anymore. 19) ×4 & ×8 (1k page size) 20) ×16 (2k page size) 21) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MRS. 22) tWTR is at least two clocks independent of operation frequency. 23) User can choose two different active power-down modes for additional power saving via MRS address bit A12. 24) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85oC and 95oC. 25) 0 oC - 85 oC 26) 85 oC - 95 oC 27) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock frequency change during power-down, a specific procedure is required as describes in Chapter 2.12. Table 41 ODT AC Electrical Characteristics and Operating Conditions (all speed bins) Symbol Parameter / Condition tAOND tAON tAONPD ODT turn-on delay ODT turn-on Max. Units 2 2 tCK tAC(min) tAC(min) + 2 ns tAC(max) + 1 ns 2 tCK + tAC(max) + 1 ns ns tAOFD tAOF tAOFPD ODT turn-off delay 2.5 2.5 tCK ODT turn-off tAC(min) tAC(min) + 2 ns tAC(max) + 0.6 ns 2.5 tCK + tAC(max) + 1 ns ns tANPD ODT to Power Down Mode Entry Latency 3 — tCK tAXPD ODT Power Down Exit Latency 8 — tCK ODT turn-on (Power-Down Modes) ODT turn-off (Power-Down Modes) Min. Notes 1) ns 2) ns 1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measure from tAOND. 2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. Data Sheet 82 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating 8 Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating 8.1 Reference Load for Timing Measurements transmission line terminated at the tester electronics. This reference load is also used for output slew rate characterisation. The output timing reference voltage level for single ended signals is the crosspoint with VTT. The figure represents the timing reference load used in defining the relevant timing parameters of the device. It is not intended to either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally a coaxial The output timing reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal. VDDQ CK, CK DUT DQ DQS DQS RDQS RDQS 25 Ohm VTT = VDDQ / 2 Timing Reference Points Figure 67 Reference Load for Timing Measurements 8.2 Slewrate Measurements 8.2.1 Output Slewrate For differential signals (e.g. DQS / DQS) output slew rate is measured between DQS - DQS = 500 mV and DQS – DQS = + 500 mV. Output slew rate is verified by design and characterisiation, but not subject to production test. With the reference load for timing measurements output slew rate for falling and rising edges is measured between VTT – 250 mV and VTT + 250 mV for single ended signals. 8.2.2 Input Slewrate - Differential signals Input slewrate for differential signals (CK / CK, DQS / DQS, RDQS / RDQS) for rising edges are measured from f.e. CK - CK = –250 mV to CK – CK = +500 mV 8.2.3 and from CK – CK = +250 mV to CK – CK = –500mV for falling edges. Input Slewrate - Single ended signals Input slew rate for single ended signals (other than tIS, tIH, tDS and tDH) are measured from dc-level to ac-level: VREF –125 mV to VREF + 250 mV for rising edges and Data Sheet from VREF + 125 mV to VREF – 250 mV for falling edges. For slew rate definition of the input and data setup and hold parameters see Chapter 8.3 of this datasheet. 83 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating 8.3 Input and Data Setup and Hold Time 8.3.1 Timing Definition for Input Setup (tIS) and Hold Time (tIH) Address and control input setup time (tIS) is referenced from the input signal crossing at the VIH(ac) level for a rising signal and VIL(ac) for a falling signal applied to the device under test. Address and control input hold time (tIH) is referenced from the input signal crossing at the VIL(dc) level for a rising signal and VIH(dc) for a falling signal applied to the device under test. . CK CK t IS t t IH IS t IH V DDQ V IH(ac) min V IH(dc) min V REF V IL(dc) max V IL(ac) max V SS Figure 68 Input, setup and Hold Time Diagram 8.3.2 Timing Definition for Data Setup (tDS) and Hold Time (tDH) 2. Data input hold time with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIL(dc) level to the differential data strobe crosspoint for a rising signal and VIH(dc) to the differential data strobe crosspoint for a falling signal applied to the device under test. Input waveform timing with single-ended data strobe enabled MR[bit10]=1, is referenced from the input signal crossing at the VIL(dc) level to the singleended data strobe crossing VREF for a rising signal and VIH(dc) to the single-ended data strobe crossing VREF for a falling signal applied to the device under test. 1. Data input setup time with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL(ac) level to the differential data strobe crosspoint for a falling signal applied to the device under test. Input waveform timing with single-ended data strobe enabled MR[bit10]=1, is referenced from the input signal crossing at the VIH(ac) level to the data strobe crossing VREF for a rising signal, and from the input signal crossing at the VIL(ac) level to the singleended data strobe crossing VREF for a falling signal applied to the device under test. Data Sheet 84 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating DQS Differential Input Waveform DQS Single-ended Input Waveform DQS V REF t DS t DH t t DS DH V DDQ V IH(ac) min V IH(dc) min V REF V IL(dc) max V IL(ac) max V SS Figure 69 Data, Setup and Hold Time Diagram 8.3.3 Slew Rate Definition for Input and Data Setup and Hold Times Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIH(ac)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line between shaded ‘VREF(dc) to ac region’, use nominal slew rate for derating value.(Figure 70) Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line between shaded ‘dc level to VREF(dc) region’, use nominal slew rate for derating value. (Figure 72) If the actual signal is later than the nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value. (Figure 71) If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value.(Figure 73) Data Sheet 85 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating CK,DQS CK,DQS t t IS ,t DS IH ,t DH t IS ,t DS t ,t IH DH V DDQ V IH (ac) min V min IH (dc) Nominal slew rate V REF(dc) Nominal slew rate V V IL (dc) IL (ac) max V REF to ac region max V SS Delta TF Figure 70 Delta TR Setup Slew Rate = Falling Signal Vref(dc) - VIL(ac)max Setup Slew Rate = Rising Signal VIH(ac)min - VREF(dc) Delta TF Delta TR Slew Rate Definition Nominal Diagram for tIS(tDS) Note: DQS, DQS signals must be monotonic between VIL(dc)max and VIH(dc)min. Data Sheet 86 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating CK,DQS CK,DQS V IH (ac) min V min IH (dc) t t IS ,t DS V DDQ VREF to ac region IH ,t DH t ,t t ,t IS DS IH DH Nominal line Tangent line V REF Tangent line V IL (dc) max V IL (ac) max VREF to ac region Nominal line Delta TR V SS Delta TF Figure 71 Setup Slew Rate = Falling Signal tangent line [VREF(dc) - VIL(ac)max] Setup Slew Rate = Rising Signal tangent line [VIH(ac)min - VREF(dc)] Delta TF Delta TR Slew Rate Definition Tangent Diagram for tIS(tDS) Note: DQS, DQS signals must be monotonic between VIL(dc)max and VIH(dc)min. Data Sheet 87 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating CK ,DQS CK ,DQS V t t IS ,t DS IH ,t DH t IS ,t t ,t DS IH DH DDQ V IH (ac) min V min IH (dc) Dc to VREF region V REF(dc) Dc to VREF region V IL (dc) max V IL (ac) max Nominal slew rate Nominal slew rate V SS Delta TR Hold Slew Rate Falling Signal VIH(dc)min - VREF(dc) = Hold Slew Rate = Rising Signal Figure 72 Delta TF Delta TF VREF(dc) - VIL(dc)max Delta TR Slew Rate Definition Nominal Diagram for tIH(tDH) Note: DQS, DQS signals must be monotonic between VIL(dc)max and VIH(dc)min. Data Sheet 88 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating CK,DQS CK,DQS V t t IS ,t DS DDQ IH ,t DH t ,t t ,t IS DS IH DH Nominal V IH (ac) min V min IH (dc) slew rate Dc to VREF region Tangent line V REF(dc) Dc to VREF region V IL (dc) max V IL (ac) max Tangent line Nominal slew rate V SS Delta TR Hold Slew Rate Falling Signal Tangent line [VIH(dc)min - VREF(dc)] = Hold Slew Rate = Rising Signal Figure 73 Delta TF Delta TF Tangent line [VREF(dc) - VIL(dc)max] Delta TR Slew Rate Definition Tangent Diagram for tIH(tDH) Note: DQS, DQS signals must be monotonic between VIL(dc)max and VIH(dc)min. Data Sheet 89 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating Table 42 Input Setup (tIS) and Hold (tIH) Time Derating Table Command / Address Slew rate (V/ns) Units 2.0 V/ns 1.5 V/ns 1.0 V/ns ∆ tIS ∆ tIH ∆ tIS ∆ tIH ∆ tIS ∆ tIH 4.0 187 94 217 124 247 154 ps 3.5 179 89 209 119 239 149 ps 3.0 167 83 197 113 227 143 ps 2.5 150 75 180 105 210 135 ps 2.0 125 45 155 75 185 105 ps 1.5 83 21 113 51 143 81 ps 1.0 0 0 30 30 60 60 ps 0.9 –11 –14 19 16 49 46 ps 0.8 –25 –31 5 –1 35 29 ps 0.7 –43 –54 –13 –24 17 6 ps 0.6 –67 –83 –37 –53 –7 –23 ps 0.5 –110 –125 –80 –95 –50 –65 ps 0.4 –175 –188 –145 –158 –115 –128 ps 0.3 –285 –292 –255 –262 –225 –232 ps 0.25 –350 –375 –320 –345 –290 –315 ps 0.2 –525 –500 –495 –470 –465 –440 ps 0.15 –800 –708 –770 –678 –740 –648 ps 0.1 –1450 –1125 –1420 –1095 –1390 –1065 ps 1) For all input signals the total tIS (input setup time) and value to the derating value listed in this table. Data Sheet Notes 1) CK, CK Differential Slew Rate tIH (input hold time) required is calculated by adding the individual 90 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating DQ Slewrate (V/ns) Table 43 Data Setup (tDS) and Hold Time (tDH) Derating Table1)2) DQS, DQS Differential Slew Rate 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH ∆ 2.0 125 45 125 45 125 45 — — — — — — — — — — — — 1.5 83 21 83 21 83 21 95 33 — — — — — — — — — — 1.0 0 0 0 0 0 0 12 12 24 24 — — — — — — — — 0.9 — — –11 –14 –11 –14 1 –2 13 10 25 22 — — — — — — 0.8 — — — — –25 –31 –13 –19 –1 –7 11 5 23 17 — — — — 0.7 — — — — — — –31 –42 –19 –30 –7 –6 17 6 — — 0.6 — — — — — — — — –43 –49 –31 –47 –19 –35 –7 –23 5 –11 0.5 — — — — — — — — — — –74 –89 –62 –77 –50 –65 –38 –53 0.4 — — — — — — — — — — — –18 5 — –127 –140 –115 –128 –103 –116 1) All units in ps. 2) For all input signals the total tDS (setup time) and value to the derating value listed in this table. tDH (hold time) required is calculated by adding the individual datasheet 8.4 Overshoot and Undershoot Specification Table 44 AC Overshoot / Undershoot Specification for Address and Control Pins Parameter DDR2–400 DDR2–533 Units Maximum peak amplitude allowed for overshoot area 0.9 0.9 V Maximum peak amplitude allowed for undershoot area 0.9 0.9 V Maximum overshoot area above VDD 0.75 0.56 V.ns Maximum undershoot area below VSS 0.75 0.56 V.ns Volts (V) Maximum Amplitude Overshoot Area VDD VSS Maximum Amplitude Undershoot Area Time (ns) Figure 74 Data Sheet AC Overshoot / Undershoot Diagram for Address and Control Pins 91 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating Table 45 AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins Parameter DDR2–400 DDR2–533 Units Maximum peak amplitude allowed for overshoot area 0.9 0.9 V Maximum peak amplitude allowed for undershoot area 0.9 0.9 V Maximum overshoot area above VDDQ 0.38 0.28 V.ns Maximum undershoot area below VSSQ 0.38 0.28 V.ns Volts (V) Maximum Amplitude Overshoot Area VDDQ VSSQ Maximum Amplitude Undershoot Area Time (ns) Figure 75 Data Sheet AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins 92 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Package Dimensions 9 Package Dimensions 10.5 11 x 0.8 = 8.8 0.8 5) A 2) 2) 10 8 x 0.8 = 6.4 0.8 2.2 MAX. B 1) 0.18 MAX. 0.2 4) 3) 0.1 C 1.2 MAX. 0.31 MIN. 0.1 C ø0.46 ±0.05 60x A B ø0.15 M C ø0.08 M C SEATING PLANE 1) Dummy pads without ball 2) Middle of packages edges 3) Package orientation mark A1 4) Bad unit marking (BUM) 5) Die sort fiducial Figure 76 Data Sheet Package Pinout P-TFBGA-60-6 (top view) 93 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Package Dimensions 12.5 14 x 0.8 = 11.2 0.8 5) A 2) 4) 2) 10 8 x 0.8 = 6.4 0.8 2.2 MAX. B 1) 0.18 MAX. 0.2 3) 0.1 C 0.31 MIN. 1.2 MAX. 0.1 C ø0.46 ±0.05 84x ø0.15 M A B C ø0.08 M C SEATING PLANE 1) Dummy pads without ball 2) Middle of packages edges 3) Package orientation mark A1 4) Bad unit marking (BUM) 5) Die sort fiducial Figure 77 Data Sheet Package Pinout P-TFBGA-84-1 (top view) 94 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM DDR2 Component Nomenclature 10 DDR2 Component Nomenclature Table 46 Nomenclature Fields and Examples Example for Field Number DDR2 DRAM 1 2 3 4 5 HYB 18 T 512 16 6 7 8 9 10 0 A C –5 Table 47 DDR2 DRAM Nomenclature Field Description Values Coding 1 INFINEON Component Prefix HYB Constant 2 Interface Voltage [V] 18 SSTL1.8 3 DRAM Technology T DDR2 4 Component Density [Mbit] 256 256 Mbit 512 512 Mbit 1G 1 Gbit 2G 2 Gbit 40 ×4 80 ×8 16 ×16 5+6 Number of I/Os 7 Product Variations 0 .. 9 look up table 8 Die Revision A First B Second C FBGA, lead-containing F FBGA, lead-free –3.7 DDR2-533 –5 DDR2-400 9 10 11 Data Sheet Package, Lead-Free Status Speed Grade 11 N/A for Components 95 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P www.infineon.com Published by Infineon Technologies AG