Siemens HYB3117405BJ-60 4m x 4-bit dynamic ram 2k & 4k refresh Datasheet

4M × 4-Bit Dynamic RAM
2k & 4k Refresh
(Hyper Page Mode - EDO)
HYB 5116405BJ-50/-60
HYB 5117405BJ-50/-60
HYB 3116405BJ/BT(L)-50/-60
HYB 3117405BJ/BT-50/-60
Advanced Information
• 4 194 304 words by 4-bit organization
• 0 to 70 °C operating temperature
• Hyper Page Mode - EDO - operation
• Performance:
-50
-60
tRAC RAS access time
50
60
ns
tCAC CAS access time
13
15
ns
tAA
Access time from address
25
30
ns
tRC
Read/Write cycle time
84
104 ns
20
25
tHPC Hyper page mode (EDO) cycle time
ns
• Power dissipation, refresh & addressing:
HYB 5116405 HYB 3116405 HYB 5117405 HYB 3117405
-50
Power supply
Addressing
-60
-50
-60
-50
-60
-50
-60
5 V ± 10%
3.3 V ± 0.3 V
5 V ± 10%
3.3 V ± 0.3 V
12/10
12/10
11/11
11/11
Refresh
4096 cylces / 64 ms
2048 cycles / 32 ms
L-version
4096 cycles / 128 ms
–
Active
275
220
180
144
440
385
288
252
mW
TTL Standby
11
7.2
11
7.2
mW
CMOS Standby
5.5
3.6
5.5
3.6
mW
CMOS Standby
(L-version)
–
0.72
–
–
mW
• Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh,
test mode and Self Refresh (on L-versions only)
• All inputs, outputs and clocks fully TTL (5 V versions) and LV-TTL (3.3 V version)-compatible
• Plastic Package:
Semiconductor Group
P-SOJ-26/24-1
300 mil
P-TSOPII-26/24-1 300 mil
1
1998-10-01
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
The HYB 5(3)116(7)405 are 16 MBit dynamic RAMs based on die revisions “G” & “F” and organized
as 4 194 304 words by 4-bits. The HYB 5(3)116(7)405BJ/BT(L) utilizes a submicron CMOS silicon
gate process technology, as well as advanced circuit techniques to provide wide operating margins,
both internally and for the system user. Multiplexed address inputs permit the HYB 5(3)116(7)405
to be packaged in a standard SOJ-26/24 and TSOPII-26/24 plastic package with 300 mil width.
These packages provide high system bit densities and are compatible with commonly used
automatic testing and insertion equipment. The HYB 3116(7)405BTL have a very low power “sleep
mode” supported by Self Refresh.
Ordering Information
Type
Ordering Code Package
Descriptions
HYB 5117405BJ-50
Q67100-Q1101 P-SOJ-26/24-1 300 mil
5 V 50 ns EDO-DRAM
HYB 5117405BJ-60
Q67100-Q1102 P-SOJ-26/24-1 300 mil
5 V 60 ns EDO-DRAM
HYB 3117405BJ-50
on request
P-SOJ-26/24-1 300 mil
3.3 V 50 ns EDO-DRAM
HYB 3117405BJ-60
on request
P-SOJ-26/24-1 300 mil
3.3 V 60 ns EDO-DRAM
HYB 3117405BT-50
on request
P-TSOPII-26/24-1 300 mil 3.3 V 50 ns EDO-DRAM
HYB 3117405BT-60
on request
P-TSOPII-26/24-1 300 mil 3.3 V 60 ns EDO-DRAM
2k-Refresh Versions:
4k-Refresh Versions:
HYB 5116405BJ-50
Q67100-Q1098 P-SOJ-26/24-1 300 mil
5 V 50 ns EDO-DRAM
HYB 5116405BJ-60
Q67100-Q1099 P-SOJ-26/24-1 300 mil
5 V 60 ns EDO-DRAM
HYB 3116405BJ-50
on request
P-SOJ-26/24-1 300 mil
3.3 V 50 ns EDO-DRAM
HYB 3116405BJ-60
on request
P-SOJ-26/24-1 300 mil
3.3 V 60 ns EDO-DRAM
HYB 3116405BT-50
on request
P-TSOPII-26/24-1 300 mil 3.3 V 50 ns EDO-DRAM
HYB 3116405BT-60
on request
P-TSOPII-26/24-1 300 mil 3.3 V 60 ns EDO-DRAM
HYB 3116405BTL-50 on request
P-TSOPII-26/24-1 300 mil 3.3 V 50 ns LP-EDO-DRAM
HYB 3116405BTL-60 on request
P-TSOPII-26/24-1 300 mil 3.3 V 60 ns LP-EDO-DRAM
Semiconductor Group
2
1998-10-01
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Pin Names
HYB 5(3)16405
4k-Refresh
HYB 5(3)17405
2k-Refresh
Row Address Inputs
A0 - A11
A0 - A10
Column Address Inputs
A0 - A9
A0 - A10
Row Address Strobe
RAS
Column Address Strobe
CAS
Output Enable
OE
Data Input/Output
I/O1 - I/O4
Read/Write Input
WE
Power Supply
VCC
Ground (0 V)
VSS
Not Connected
–
N.C.
P-SOJ-26/24-1 300 mil
P-TSOPII-26/24-1 300 mil
VCC
I/O1
I/O2
WE
RAS
A11 / N.C.
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
26
25
24
23
22
21
VSS
I/O4
I/O3
CAS
OE
A9
8
9
10
11
12
13
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
SPP03454
Pin Configuration
(top view)
Semiconductor Group
3
1998-10-01
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
I/O1 I/O2 I/O3 I/O4
Data IN
Buffer
Data OUT
Buffer
OE
&
WE
4
CAS
4
No.2 Clock
Generator
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
Column
Address
Buffers (10)
10
Column
Decoder
Refresh
Controller
Sense Amplifier
I/O Gating
Refresh
Counter (12)
4
1024
x4
12
12
RAS
Row
Address
Buffers (12)
12
Row
Decoder
4096
Memory Array
4096 x 1024 x 4
No.1 Clock
Generator
Voltage Down
Generator
VCC
VCC
(internal)
SPB03455
Block Diagram for HYB 5(3)116405 (4k-refresh)
Semiconductor Group
4
1998-10-01
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
I/O1 I/O2 I/O3 I/O4
Data In
Buffer
OE
4
&
WE
Data Out
Buffer
4
CAS
No.2 Clock
Generator
11
A0
Column
Address
Buffers (11)
11
Column
Decoder
A1
A2
Refresh
Controller
A3
Sense Amplifier
I/O Gating
A4
4
A5
A6
11
A9
A10
.
..
A8
2048
x4
.
..
Refresh
Counter (11)
A7
11
RAS
Row
Address
Buffers (11)
11
Row
Decoder
..
.
2048
..
.
Memory Array
2048 x 2048 x 4
No.1 Clock
Generator
Voltage Down
Generator
V CC
V CC (internal)
SPB02823
Block Diagram for HYB 5(3)117405 (2k-refresh)
Semiconductor Group
5
1998-10-01
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Absolute Maximum Ratings
Operating temperature range ........................................................................................... 0 to 70 ˚C
Storage temperature range........................................................................................ – 55 to 150 ˚C
Input/output voltage (5 V versions) ................................................... – 0.5 to min (VCC + 0.5, 7.0) V
Input/output voltage (3.3 V versions) ................................................ – 0.5 to min (VCC + 0.5, 4.6) V
Power supply voltage (5 V versions) ....................................................................... – 1.0 V to 7.0 V
Power supply voltage (3.3 V versions) .................................................................... – 1.0 V to 4.6 V
Power dissipation (5 V versions) ............................................................................................ 1.0 W
Power dissipation (3.3 V versions) ......................................................................................... 0.5 W
Data out current (short circuit) ............................................................................................... 50 mA
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics
TA = 0 to 70 °C, VSS = 0 V, tT = 2 ns
Parameter
Symbol
Limit Values
min.
max.
Unit Test
Condition
V
5 V Versions
Power supply voltage
VCC
4.5
5.5
Input high voltage
VIH
2.4
VCC + 0.5 V
1
Input low voltage
VIL
– 0.5
0.8
V
1
Output high voltage (IOUT = – 5 mA)
VOH
2.4
–
V
1
Output low voltage (IOUT = 4.2 mA)
VOL
–
0.4
V
1
Power supply voltage
VCC
3.0
3.6
V
Input high voltage
VIH
2.0
VCC + 0.5 V
1
Input low voltage
VIL
– 0.5
0.8
V
1
TTL Output high voltage (IOUT = – 2 mA)
VOH
2.4
–
V
1
TTL Output low voltage (IOUT = 2 mA)
VOL
–
0.4
V
1
3.3 V Versions
CMOS Output high voltage (IOUT = – 100 µA) VOH
VCC – 0.2 –
V
CMOS Output low voltage (IOUT = 100 µA)
–
V
Semiconductor Group
VOL
6
0.2
1998-10-01
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
DC Characteristics (cont’d)
TA = 0 to 70 °C, VSS = 0 V, tT = 2 ns
Parameter
Symbol
Limit Values
min.
Unit Notes
max.
2k
4k
Common Parameters
Input leakage current
(0 V ≤ VIH ≤ VCC + 0.3 V, all other pins = 0 V)
II(L)
– 10
10
µA
1
Output leakage current
(DO is disabled, 0 V ≤ VOUT ≤ VCC + 0.3 V)
IO(L)
– 10
10
µA
1
Average VCC supply current
ICC1
mA
mA
2, 3, 4
mA
–
mA
mA
2, 4
-50 version
-60 version
(RAS, CAS, address cycling: tRC = tRC MIN.)
–
–
Standby VCC supply current
(RAS = CAS = VIH)
ICC2
Average VCC supply current, during RAS-only
refresh cycles
-50 version
-60 version
(RAS cycling, CAS = VIH, tRC = tRC MIN.)
ICC3
Standby VCC supply current
(RAS = CAS = VCC – 0.2 V)
ICC5
Average VCC supply current, during CASbefore-RAS refresh mode
-50 version
-60 version
(RAS, CAS cycling: tRC = tRC MIN.)
ICC6
Average Self Refresh current
(CBR cycle with tRAS > tRASS MIN., CAS held
low, WE = VCC – 0.2 V, Address and
Din = VCC – 0.2 V or 0.2 V)
ICC7
Semiconductor Group
–
–
–
Average VCC supply current,during hyper page ICC4
mode (EDO)
-50 version
-60 version
(RAS = VIL, CAS, address cycling:
tPC = tPC MIN.)
50
40
2
80
70
50
40
2, 3, 4
2, 4
–
–
35
30
mA
mA
2, 3, 4
–
1
200
mA
µA
1
mA
mA
2, 4
µA
Lversion
only
–
–
7
80
70
–
80
70
50
40
250
2, 3, 4
L-version
2, 4
1998-10-01
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Capacitance
TA = 0 to 70 °C, f = 1 MHz
Parameter
Symbol
Limit Values
min.
max.
Unit
Input capacitance (A0 to A11)
CI1
–
5
pF
Input capacitance (RAS, CAS, WE, OE)
CI2
–
7
pF
I/O capacitance (I/O1 to I/O4)
CIO
–
7
pF
AC Characteristics 5, 6
TA = 0 to 70 °C, VCC = 5 V ± 10 % / VCC = 3.3 V ± 0.3 V, tT = 2 ns
Parameter
Symbol
Limit Values
-50
Unit Note
-60
min.
max. min.
max.
Common Parameters
Random read or write cycle time
tRC
84
–
104
–
ns
RAS precharge time
tRP
30
–
40
–
ns
RAS pulse width
tRAS
50
10k
60
10k
ns
CAS pulse width
tCAS
8
10k
10
10k
ns
Row address setup time
tASR
0
–
0
–
ns
Row address hold time
tRAH
8
–
10
–
ns
Column address setup time
tASC
0
–
0
–
ns
Column address hold time
tCAH
8
–
10
–
ns
RAS to CAS delay time
tRCD
12
37
14
45
ns
RAS to column address delay
tRAD
10
25
12
30
ns
RAS hold time
tRSH
13
–
15
–
ns
CAS hold time
tCSH
40
–
50
–
ns
CAS to RAS precharge time
tCRP
5
–
5
–
ns
Transition time (rise and fall)
tT
1
50
1
50
ns
Refresh period for 2k-refresh version
tREF
–
32
–
32
ms
Refresh period for 4k-refresh version
tREF
–
64
–
64
ms
Refresh period for Low Power Version
tREF
–
128
–
128
ms
Access time from RAS
tRAC
–
50
–
60
ns
8, 9
Access time from CAS
tCAC
–
13
–
15
ns
8, 9
Semiconductor Group
8
7
Read Cycle
1998-10-01
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
AC Characteristics (cont’d) 5, 6
TA = 0 to 70 °C, VCC = 5 V ± 10 % / VCC = 3.3 V ± 0.3 V, tT = 2 ns
Parameter
Symbol
Limit Values
-50
Unit Note
-60
min.
max. min.
max.
8, 10
Access time from column address
tAA
–
25
–
30
ns
OE access time
tOEA
–
13
–
15
ns
Column address to RAS lead time
tRAL
25
–
30
–
ns
Read command setup time
tRCS
0
–
0
–
ns
Read command hold time
tRCH
0
–
0
–
ns
11
Read command hold time referenced to RAS tRRH
0
–
0
–
ns
11
CAS to output in low-Z
tCLZ
0
–
0
–
ns
8
Output buffer turn-off delay
tOFF
0
13
0
15
ns
12
Output turn-off delay from OE
tOEZ
0
13
0
15
ns
12
Data to CAS low delay
tDZC
0
–
0
–
ns
13
Data to OE low delay
tDZO
0
–
0
–
ns
13
CAS high to data delay
tCDD
10
–
13
–
ns
14
OE high to data delay
tODD
10
–
13
–
ns
14
Write command hold time
tWCH
8
–
10
–
ns
Write command pulse width
tWP
8
–
10
–
ns
Write command setup time
tWCS
0
–
0
–
ns
Write command to RAS lead time
tRWL
8
–
10
–
ns
Write command to CAS lead time
tCWL
8
–
10
–
ns
Data setup time
tDS
0
–
0
–
ns
16
Data hold time
tDH
8
–
10
–
ns
16
Read-write cycle time
tRWC
113
–
138
–
ns
RAS to WE delay time
tRWD
64
–
77
–
ns
15
CAS to WE delay time
tCWD
27
–
32
–
ns
15
Column address to WE delay time
tAWD
39
–
47
–
ns
15
OE command hold time
tOEH
10
–
13
–
ns
Write Cycle
15
Read-Modify-Write Cycle
Semiconductor Group
9
1998-10-01
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
AC Characteristics (cont’d) 5, 6
TA = 0 to 70 °C, VCC = 5 V ± 10 % / VCC = 3.3 V ± 0.3 V, tT = 2 ns
Parameter
Symbol
Limit Values
-50
Unit Note
-60
min.
max. min.
max.
Hyper Page Mode (EDO) Cycle
Hyper page mode (EDO) cycle time
tHPC
20
–
25
–
ns
CAS precharge time
tCP
8
–
10
–
ns
Access time from CAS precharge
tCPA
–
27
–
32
ns
Output data hold time
tCOH
5
–
5
–
ns
RAS pulse width in EDO mode
tRAS
50
200k
60
200k
ns
CAS precharge to RAS delay
tRHCP
27
–
32
–
ns
OE setup time prior to CAS
tOES
5
–
5
–
ns
7
Hyper Page Mode (EDO) Read-Modify-Write Cycle
Hyper page mode (EDO) read-write cycle
time
tPRWC
58
–
68
–
ns
CAS precharge to WE
tCPWD
41
–
49
–
ns
CAS setup time
tCSR
10
–
10
–
ns
CAS hold time
tCHR
10
–
10
–
ns
RAS to CAS precharge time
tRPC
5
–
5
–
ns
Write to RAS precharge time
tWRP
10
–
10
–
ns
Write hold time referenced to RAS
tWRH
10
–
10
–
ns
tCPT
35
–
40
–
ns
RAS pulse width
tRASS
100k
–
100k
–
ns
17
RAS precharge time
tRPS
95
–
110
–
ns
17
CAS hold time
tCHS
– 50
–
– 50
–
ns
17
CAS-before-RAS Refresh Cycle
CAS-before-RAS Counter Test Cycle
CAS precharge time (CAS-before-RAS
counter test cycle)
Self Refresh Cycle (L-Version only)
Semiconductor Group
10
1998-10-01
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
AC Characteristics (cont’d) 5, 6
TA = 0 to 70 °C, VCC = 5 V ± 10 % / VCC = 3.3 V ± 0.3 V, tT = 2 ns
Parameter
Symbol
Limit Values
-50
Unit Note
-60
min.
max. min.
max.
Test Mode
Write command setup time
tWTS
10
–
10
–
ns
Write command hold time
tWTH
10
–
10
–
ns
CAS hold time
tCHRT
30
–
30
–
ns
RAS hold time in test mode
tRAHT
30
–
30
–
ns
Semiconductor Group
11
1998-10-01
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Notes
All voltages are referenced to VSS.
ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.
ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open.
Address can be changed once or less while RAS = VIL. In case of ICC4 it can be changed once
or less during a hyper page mode (EDO) cycle
5. An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least
one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using
the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of
8 RAS cycles are required.
6. AC measurements assume tT = 2 ns.
7. VIH (MIN.) and VIL (MAX.) are reference levels for measuring timing of input signals. Transition times
are also measured between VIH and VIL.
8. Measured with the specified current load and 100 pF at VOL = 0.8 V and VOH = 2.0 V. Access
time is determined by the latter of tRAC, tCAC, tAA, tCPA, tOEA . tCAC is measured from tristate.
9. Operation within the tRCD (MAX.) limit ensures that tRAC (MAX.) can be met. tRCD (MAX.) is specified as
a reference point only. If tRCD is greater than the specified tRCD (MAX.) limit, then access time is
controlled by tCAC.
10.Operation within the tRAD (MAX.) limit ensures that tRAC (MAX.) can be met. tRAD (MAX.) is specified as
a reference point only. If tRAD is greater than the specified tRAD (MAX.) limit, then access time is
controlled by tAA.
11.Either tRCH or tRRH must be satisfied for a read cycle.
12.tOFF (MAX.), tOEZ (MAX.) define the time at which the output achieves the open-circuit conditions and
are not referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or
CAS, whichever occurs last.
13.Either tDZC or tDZO must be satisfied.
14.Either tCDD or tODD must be satisfied.
15.tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS > tWCS (MIN.), the cycle is an early write cycle and
data out pin will remain open-circuit (high impedance) through the entire cycle; if
tRWD > tRWD (MIN.), tCWD > tCWD (MIN.) and tAWD > tAWD (MIN.), the cycle is a read-write cycle and I/O will
contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the
condition of I/O (at access time) is indeterminate.
16.These parameters are referenced to the CAS leading edge in early write cycles and to the WE
leading edge in read-write cycles.
17.When using Self Refresh mode, the following refresh operations must be performed to ensure
proper DRAM operation:
If row addresses are being refreshed on an evenly distributed manner over the refresh interval
using CBR refresh cycles, then only one CBR cycle must be performed immediately after exit
from Self Refresh.
If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBRBurst) over the refresh interval, then a full set of row refreshes must be performed immediately
before entry to and immediately after exit from Self Refresh.
1.
2.
3.
4.
Semiconductor Group
12
1998-10-01
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
t RC
t RAS
t RP
VIH
RAS
VIL
t CSH
t RCD
t RSH
t CAS
VIH
t CRP
CAS
VIL
t RAD
t ASR
t RAL
t CAH
t ASC
t ASR
VIH
Address
Row
VIL
Column
Row
t RAH
t RCH
t RRH
t RCS
VIH
WE
VIL
t AA
t OEA
VIH
OE
VIL
t DZC
t CDD
t DZO
I/O
(Inputs)
t ODD
VIH
VIL
t OFF
t CAC
t CLZ
VOH
I/O
(Outputs) V
OL
Hi Z
t OEZ
Valid Data OUT
Hi Z
t RAC
"H" or "L"
SPT03025
Read Cycle
Semiconductor Group
13
1998-10-01
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
t RC
t RAS
t RP
VIH
RAS
VIL
t CSH
t RCD
t RSH
t CRP
t CAS
VIH
CAS
VIL
t RAL
t RAD
t ASR
t ASC
t CAH
t ASR
VIH
Address
Row
VIL
Column
t RAH
t CWL
t WCS
VIH
Row
t WP
WE
VIL
t WCH
t RWL
VIH
OE
VIL
t DS
I/O
(Inputs)
t DH
VIH
Valid Data IN
VIL
VOH
I/O
(Outputs) V
OL
Hi Z
"H" or "L"
SPT03026
Write Cycle (Early Write)
Semiconductor Group
14
1998-10-01
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
t RC
t RAS
t RP
VIH
RAS
VIL
t CSH
t RCD
t RSH
t CRP
t CAS
VIH
CAS
VIL
t RAD
t RAL
t CAH
t ASC
t ASR
t ASR
VIH
Address
Row
VIL
Column
Row
t RAH
t CWL
t RWL
t WP
VIH
WE
VIL
t OEH
VIH
OE
VIL
t ODD
t DZO
t DZC
I/O
(Inputs)
t DH
t DS
VIH
Valid Data
VIL
t CLZ
t OEZ
t OEA
VOH
I/O
(Outputs) V
OL
Hi Z
Hi Z
"H" or "L"
SPT03027
Write Cycle (OE Controlled Write)
Semiconductor Group
15
1998-10-01
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
t RWC
t RAS
VIH
RAS
VIL
t CSH
t RP
t RSH
t CAS
t RCD
t CRP
VIH
CAS
VIL
t RAH
t ASR
t CAH
t ASC
t ASR
VIH
Address
Row
Column
Row
VIL
t RAD
t CWL
t AWD
t CWD
t RWL
t WP
t RWD
VIH
WE
VIL
t AA
t RCS
t OEA
t OEH
VIH
OE
VIL
t DZC
t DS
t DZO
I/O
(Inputs)
t DH
VIH
Valid
Data IN
VIL
t ODD
t CAC
t OEZ
t CLZ
VOH
I/O
(Outputs) V
OL
Data
OUT
t RAC
"H" or "L"
SPT03028
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
16
1998-10-01
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
t RAS
t RCD
t RHCP
VIH
RAS
VIL
t HPC
t RP
t RSH
t CAS
t CP
t CRP
t CAS
t CAS
t CRP
VIH
CAS
VIL
t CSH
t RAH
t ASR
t RAL
t CAH
t ASC
t CAH
t CAH
t ASC
Column 2
Column N
t ASC
VIH
Address
Row
Column 1
VIL
t RAD
t RRH
t RCS
t RCH
VIH
WE
VIL
t CAC
t AA
t CPA
t OES
t OEA
t CAC
t AA
t CPA
t OFF
VIH
OE
VIL
t RAC
t AA
t CAC
t CLZ
t COH
t COH
t OEZ
VOH
I/O
(Output) V
OL
Data OUT 1
Data OUT 2
Data OUT N
"H" or "L"
SPT03038
Hyper Page Mode (EDO) Read Cycle
Semiconductor Group
17
1998-10-01
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
t RAS
t RCD
t RHCP
VIH
RAS
VIL
t HPC
t RP
t CP
t CRP
t CAS
t RSH
t CAS
t CAS
t CRP
VIH
CAS
VIL
t CSH
t RAH
t ASR
VIH
Address
VIL
t ASC
Row
Address
t CAH
t ASC
Column 1
t CAH
t RAL
t CAH
t ASC
Column 2
Column N
t RAD
t RWL
t CWL
t WCS
t CWL
t WCS
t WCS
t WCH
t WP
t WCH
t WP
t CWL
t WCH
t WP
VIH
WE
VIL
VIH
OE
VIL
t DH
t DS
I/O
(Input)
t DH
t DS
t DH
t DS
VIH
Data IN 1
Data IN 2
Data IN N
VIL
"H" or "L"
SPT03039
Hyper Page Mode (EDO) Early Write Cycle
Semiconductor Group
18
1998-10-01
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
t RAS
VIH
RAS
VIL
t CSH
t RP
t CP
t RCD
t PRWC
t CAS
t RSH
t CAS
t CAS
t CRP
VIH
CAS
VIL
t ASR
t RAD
t RAH
t ASC
t RAL
t CAH
t CAH
t CAH
t ASC
t ASC
t ASR
VIH
Address
Row
Column
Column
Column
Row
VIL
t RWD
t CWD
t RCS
t CPWD
t CWD
t CWL
t CPWD
t CWD
t CWL
t RWL
t CWL
VIH
WE
VIL
t AWD
t AA
t AWD
t WP
t OEA
t AWD
t WP
t OEA
t WP
t OEA
t OEH
t OEH
t OEH
VIH
OE
VIL
t CLZ
t DZC
t CLZ
t ODD
t CLZ
t CPA
t ODD
t DZC
t DZO
VIH
I/O
(Inputs) V
IL
Data IN
t CAC
t RAC
VOH
I/O
(Outputs) V
t OEZ
t CPA
t ODD
Data IN
t DH
t DS
t DZC
Data IN
t DH
t AA
t DS
t OEZ
t DS
t AA
Data
OUT
Data
OUT
t DH
t CAC
t OEZ
Data
OUT
OL
"H" or "L"
SPT03031
Hyper Page Mode (EDO) Late Write and Read-Modify Write Cycle
Semiconductor Group
19
1998-10-01
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
t RC
t RAS
t RP
VIH
RAS
VIL
t CRP
t RPC
VIH
CAS
VIL
t RAH
t ASR
t ASR
VIH
Row
Address
Row
VIL
VOH
I/O
(Outputs) V
OL
Hi Z
"H" or "L"
SPT03032
RAS-only Refresh Cycle
Semiconductor Group
20
1998-10-01
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
t RC
t RP
t RAS
t RP
VIH
RAS
VIL
t RPC
t CP
t CHR
t RPC
t CSR
t CRP
VIH
CAS
VIL
t WRH
t WRP
VIH
WE
VIL
VIH
OE
VIL
t ODD
I/O
(Inputs)
VIH
VIL
t CDD
t OEZ
VOH
I/O
(Outputs) V
OL
Hi Z
t OFF
"H" or "L"
SPT03033
CAS-before-RAS Refresh Cycle
Semiconductor Group
21
1998-10-01
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
t RC
t RC
t RP
t RP
t RAS
t RAS
VIH
RAS
VIL
t RCD
t RSH
t CHR
t CRP
VIH
CAS
VIL
t RAD
t ASC
t WRP
t RAH
t ASR
t WRH
t CAH
t ASR
VIH
Address
Row
VIL
Column
Row
t RCS
t RRH
VIH
WE
VIL
t AA
t OEA
VIH
OE
VIL
t DZC
t CDD
t ODD
t DZO
I/O
(Inputs)
VIH
VIL
t CLZ
t CAC
t OFF
t RAC
t OEZ
VOH
I/O
(Outputs) V
OL
Valid Data OUT
"H" or "L"
Hi Z
SPT03034
Hidden Refresh Cycle (Read) Cycle
Semiconductor Group
22
1998-10-01
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
t RC
t RC
t RAS
t RP
t RAS
t RP
VIH
RAS
VIL
t RCD
t RSH
t CHR
t CRP
VIH
CAS
VIL
t RAD
t ASC
t RAH
t ASR
t ASR
t CAH
VIH
Address
Row
VIL
Column
Row
t WCS
t WCH
t WP
t WRH
t WRP
VIH
WE
VIL
t DS
t DH
I/O
(Input)
VIN
Valid Data
VIL
VOH
I/O
(Output) V
OL
Hi Z
"H" or "L"
SPT03035
Hidden Refresh Early Write Cycle
Semiconductor Group
23
1998-10-01
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
t RP
t RASS
t RPS
VIH
RAS
~
~
VIL
t RPC
t CP
t CSR
t CHS
t CRP
VIH
CAS
~
~
VIL
t WRP
~
~
VIH
t WRH
WE
VIL
~
~
VIH
OE
~
~
VIL
t ODD
~
~
VIL
~
~
I/O
(Inputs)
VIH
t CDD
t OEZ
~
~
VOH
I/O
(Outputs) V
OL
Hi Z
t OFF
"H" or "L"
SPT03058
Self Refresh
Semiconductor Group
24
1998-10-01
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Read Cycle
t RAS
t RP
VIH
RAS
VIL
t CHR
t CSR
t RSH
t CP
VIH
t CAS
CAS
VIL
t RAL
t CAH
t ASR
t ASC
VIH
Address
Column
VIL
t WRP
Row
t AA
t RRH
VIH
WE
VIL
t WRH
t CAC
t RCS
t RCH
t OEA
VIH
OE
VIL
t CDD
t DZC
VIH
I/O
(Inputs) V
IL
t ODD
t OFF
t DZO
t CLZ
t OEZ
VOH
I/O
(Outputs) V
Write Cycle
Data OUT
t WCS
OL
t RWL
t CWL
t WRP
t WCH
VIH
WE
VIL
t WRH
t DH
VIH
OE
VIL
t DS
VIH
I/O
(Inputs) V
IL
Data IN
VOH
I/O
(Outputs) V
Hi Z
OL
"H" or "L"
SPT03036
CAS-before-RAS Refresh Counter Test Cycle
Semiconductor Group
25
1998-10-01
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
t RC
t RP
t RAS
t RP
VIH
RAS
VIL
t RPC
t CP
t RPC
t CHR
t CRP
t CSR
VIH
CAS
VIL
t RAH
t ASR
VIH
Row
Address
VIL
t WTH
t WTS
VIH
WE
VIL
VIH
OE
VIL
t ODD
I/O
(Inputs)
VIH
Hi Z
VIL
t CDD
t OEZ
VOH
Hi Z
I/O
(Outputs) V
OL
t OFF
"H" or "L"
SPT03042
Test Mode Entry
Semiconductor Group
26
1998-10-01
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Package Outlines
0.5
30˚
0.85 max
0.18 M 24x
15.24
26
21 19
14
1
6 8
13
17.27-0.251)
0.1
0.25 A
7.75 -0.25
6.8 ±0.2
8.63 -0.25
B
0.25 B
0.18 M B
GPJ05628
1.27
0.51-0.1
1)
0.2 +0.1
0.8 min
2.64 ±0.1
3.75 -0.5
Plastic Package P-SOJ-26/24-1 (SMD) (300mil)
(Plastic small outline J-leaded)
A
Index Marking
1) Does not include plastic or metal protrusions of 0.15 max per side
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Semiconductor Group
27
Dimensions in mm
1998-10-01
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
7.62 ±0.13
5˚ max
3
0.15 +0.06
-0.0
1.2 max
1 ±0.05
0.1 ±0.05
Plastic Package P-TSOPII-26/24-1 (400 mil) (SMD)
(Plastic Thin Small Outline Package (Type II))
0.6 -0.2
1.27
9.22 ±0.2
0.4 +0.12
-0.1
0.2 M 24x
26
1
2119
0.1
14
6 8
13
1)
17.14 ±0.13
GPX05857
Index Marking
1)
Does not include plastic or metal protrusion of 0.15 max per side
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Semiconductor Group
28
Dimensions in mm
1998-10-01