Siemens HYB314265BJL-50 256k x 16-bit edo-dynamic ram Datasheet

256K x 16-Bit EDO-Dynamic RAM
HYB 514265BJ-400/40/-45/-50
HYB 314265BJ(L)-45/-50
Preliminary Information
•
262 144 words by 16-bit organization
•
0 to 70 °C operating temperature
•
EDO - Hyper Page Mode
•
Performance:
•
•
Power Supply:
HYB 514265BJ-400
+5 V
±5%
HYB 514265BJ-40
+5 V
±10%
HYB 514265BJ-45
+5 V
±10%
HYB 514265BJ-50
+5 V
±10%
HYB 314265BJ(L)-45 +3.3 V ±0.3 V
-400
-40
-45
-50
trc
69
69
79
89
ns
trac
40
40
45
50
ns
tcac
10
10
12
13
ns
taa
20
20
22
25
ns
thpc
12,5
15
18
20
ns
thpc
80
66
55
50
MHz
Low Power dissipation
- Active(max.):
120mA / 120mA / 105mA / 95 mA
- Standby : TTL Inputs (max.)
2.0 mA
- Standby: CMOS Inputs (max.) 1.0 mA
- Standby (L-version)
200 µA
HYB 314265BJ(L)-50 +3.3 V ±0.3 V
Read, write, read-modify-write, CAS -before
RAS refresh, RAS only refresh, hidden refresh
mode
• Low Power Version (L) with Self Refresh
and 250 µA self refresh current
•
•
2 CAS / 1 WE control
•
All inputs and outputs TTL-compatible
•
512 refresh cycles / 16 ms
512 refresh cycles / 128 ms (L-version)
•
Plastic Packages: P-SOJ-40-3 400 mil width
The HYB 5(3)14265BJ(L) is the new generation dynamic RAM organized as 262 144 words by
16-bit. The HYB 5(3)14265BJ(L) utilizes the SIEMENS 16M-CMOS submicron silicon gate process
as well as advanced circuit techniques to provide wide operation margins, both internally and for the
system user. Multiplexed address inputs permit the HYB 5(3)14265BJ(L) to be packed in a
standard plastic 400mil wide P-SOJ-40-3 package. This package size provides high system bit
densities and is compatible with commonly used automatic testing and insertion equipment.
The HYB314265BJL parts have a very low power “sleep mode“ supported by Self Refresh.
Semiconductor Group
1
6.96
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Ordering Information
Type
Ordering
Code
Package
Description
HYB 514265BJ-400
Q67100-3033
P-SOJ-40-3
5 V 40 ns 256 K x 16 EDO-DRAM
HYB 514265BJ-40
Q67100-3039
P-SOJ-40-3
5 V 40 ns 256 K x 16 EDO-DRAM
HYB 514265BJ-45
Q67100-3035
P-SOJ-40-3
5 V 45 ns 256 K x 16 EDO-DRAM
HYB 514265BJ-50
Q67100-3036
P-SOJ-40-3
5 V 50 ns 256 K x 16 EDO-DRAM
HYB 314265BJ-45
on request
P-SOJ-40-3
3.3 V 45 ns 256 K x 16 EDO- DRAM
HYB 314265BJ-50
on request
P-SOJ-40-3
3.3 V 50 ns 256 K x 16 EDO- DRAM
HYB 314265BJL-45
on request
P-SOJ-40-3
3.3 V Low Power 45 ns 256 K x 16 EDO- DRAM
HYB 314265BJL-50
on request
P-SOJ-40-3
3.3 V Low Power 50 ns 256 K x 16 EDO-DRAM
5 V versions:
3.3 V versions:
Truth Table
RAS
H
L
L
L
L
L
L
L
L
LCAS
UCAS
WE
OE
I/O1-I/O8
I/O9-I/O16
Operation
H
H
L
H
L
L
H
L
L
H
H
H
L
L
H
L
L
L
H
H
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
H
High-Z
High-Z
Dout
High-Z
Dout
Din
Don't care
Din
High-Z
High-Z
High-Z
High-Z
Dout
Dout
Don't care
Din
Din
High-Z
Standby
Refresh
Lower byte read
Upper byte read
Word read
Lower byte write
Upper byte write
Word write
Pin Names
A0-A8
Address Inputs
RAS
Row Address Strobe
UCAS, LCAS
Column Address Strobe
WE
Read/Write Input
OE
Output Enable
I/O1 – I/O16
Data Input/Output
VCC
Power Supply:
+ 5 V for HYB 514265,
+ 3.3 V for HYB 314265
VSS
Ground (0 V)
N.C.
No Connection
Semiconductor Group
2
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Pin Configuration
(top view)
P-SOJ-40-3
Semiconductor Group
3
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Block Diagram
Semiconductor Group
4
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Absolute Maximum Ratings
Operating temperature range ........................................................................................ 0 to + 70 °C
Storage temperature range..................................................................................... – 55 to + 150 °C
Input/output voltage for HYB 514265................................................ – 0.5 to min. (VCC + 0.5, 7.0) V
Power supply voltage for HYB 514265 ........................................................................... – 1 to + 7 V
Input/output voltage for HYB 314265................................................ – 0.5 to min. (VCC + 0.5, 4.6) V
Power supply voltage for HYB 314265 ..................................................................... – 0.5 to + 4.6 V
Data out current (short circuit) ................................................................................................ 50 mA
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics for HYB514265
TA = 0 to 70 °C; VSS = 0 V; VCC = 5 V ± 10 % (± 5 % for -400 version) , tT = 2 ns
Parameter
Symbol
VIH
VIL
VOH
VOL
II(L)
Limit Values
min.
max.
2.4
VCC + 0.5
– 0.5
0.8
2.4
–
–
0.4
– 10
10
Input high voltage
Input low voltage
Output high voltage (IOUT = – 5.0 mA)
Output low voltage (IOUT = 4.2 mA)
Input leakage current, any input
(0 V < VIN < 7 V, all other inputs = 0 V)
Output leakage current
(DO is disabled, 0 V < VOUT < VCC)
Average VCC supply current:
V
V
V
V
µA
1
IO(L)
– 10
10
µA
1
ICC1
–
120
120
105
95
2
mA
2, 3, 4
mA
–
mA
2, 4
-400 version
-40 version
-45 version
-50 version
Standby VCC supply current
ICC2
–
ICC3
–
Unit Notes
1
1
1
1
(RAS = LCAS = UCAS = WE = VIH)
Average VCC supply current during RAS-only
refresh cycles:
-400 version
-40 version
-45 version
-50 version
Semiconductor Group
120
120
105
95
5
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Parameter
Symbol
mA
2, 3, 4
ICC5
Limit Values
min.
max.
–
110
90
75
65
–
1
Average VCC supply current during
hyper page mode (EDO) operation: -400 version
-40 version
-45 version
-50 version
Standby VCC supply current
ICC4
Unit Notes
mA
1
ICC5
–
200
µA
1
ICC6
–
120
120
105
95
mA
2, 4
(RAS = LCAS = UCAS = WE = VCC – 0.2 V)
Standby VCC supply current (L-version only)
(RAS = LCAS = UCAS = WE = VCC – 0.2 V)
Average VCC supply current during
CAS-before-RAS refresh mode:
-400 version
-40 version
-45 version
-50 version
DC Characteristics for 314265
TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 2 ns
Parameter
Symbol
Limit Values
min.
max.
Unit Test
Condition
Input high voltage
VIH
2.0
VCC + 0.5 V
1
Input low voltage
VIL
– 0.5
0.8
V
1
TTL Output high voltage (IOUT = – 2.0 mA)
VOH
2.4
–
V
1
TTL Output low voltage (IOUT = 2 mA)
VOL
–
0.4
V
1
CMOS Output high voltage (IOUT = – 100 µA)
VOH
2.4
–
V
1
CMOS Output low voltage (IOUT = 100 µA)
VOL
–
0.4
V
1
Input leakage current, any input
II(L)
– 10
10
µA
1
IO(L)
– 10
10
µA
1
ICC1
–
105
95
mA
2, 3, 4
2
mA
–
(0 V < VIN <
VCC + 0.3 V, all other inputs = 0 V)
Output leakage current
(DO is disabled, 0 V < VOUT < VCC + 0.3 V)
Average VCC supply current:
-45 version
-50 version
Standby VCC supply current
ICC2
(RAS = LCAS = UCAS = WE = VIH)
Semiconductor Group
6
–
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Parameter
Symbol
Limit Values
min.
Average VCC supply current during
RAS-only refresh cycles:
ICC3
max.
Unit Test
Condition
–
-45 version
-50 version
mA
2, 4
mA
2, 3, 4
105
95
Average VCC supply current during hyper page ICC4
mode (EDO) operation:
-45 version
-50 version
–
Standby VCC supply current
ICC5
–
1
mA
1
ICC5
–
200
µA
1
Average VCC supply current during CASbefore-RAS refresh mode:
ICC6
-45 version
-50 version
–
mA
2, 4
ICC7
–
75
65
(RAS = LCAS = UCAS = WE = VCC – 0.2 V)
Standby VCC supply current (L-version only)
(RAS = LCAS = UCAS = WE = VCC – 0.2 V)
Self Refresh Current (L-version only)
105
95
µA
250
CBR cycle with RAS >trasss(min), CAS held low;
WE = VCC – 0.2 V,
Addresses and Din = VCC – 0.2 V or 0.2 V
Capacitance
TA = 0 to 70 °C; f = 1 MHz
Parameter
Symbol
Limit Values
min.
max.
Unit
Input capacitance (A0 to A8)
CI1
–
5
pF
Input capacitance (RAS, UCAS, LCAS, WE, OE)
CI2
–
7
pF
Output capacitance (l/O1 to l/O16)
CIO
–
7
pF
Semiconductor Group
7
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
AC Characteristics 5) 6)
TA = 0 to 70 °C, tT = 2 ns
Parameter
Limit Values
Symbol
-400
Unit Note
-40
min.
max.
min.
max.
Common Parameters
Random read or write cycle time
tRC
69
–
69
–
ns
RAS precharge time
tRP
25
–
25
–
ns
RAS pulse width
tRAS
40
10k
40
10k
ns
CAS pulse width
tCAS
4.5
10k
6
10k
ns
CAS precharge time
tCP
4
–
5
–
ns
Row address setup time
tASR
0
–
0
–
ns
Row address hold time
tRAH
5
–
5
–
ns
Column address setup time
tASC
0
–
0
–
ns
Column address hold time
tCAH
5
–
5
–
ns
RAS to CAS delaytime
tRCD
9
30
9
30
ns
RAS to column address delay time
tRAD
7
20
7
20
ns
RAS hold time
tRSH
6
–
6
–
ns
CAS hold time
tCSH
32
–
32
–
ns
CAS to RAS precharge time
tCRP
5
–
5
–
ns
Transition time(rise and fall)
tT
1
50
1
50
ns
Refresh period
tREF
16
–
16
–
ms
Access time from RAS
tRAC
–
40
–
40
ns
8, 9
Access time from CAS
tCAC
–
10
–
10
ns
8, 9
Access time from column address
tAA
–
17
–
20
ns
8,10
OE access time
tOEA
–
10
–
10
ns
Column address to RAS lead time
tRAL
20
–
20
–
ns
Read command setup time
tRCS
0
–
0
–
ns
Read command hold time
tRCH
0
–
0
–
ns
11
Read command hold time ref. to RAS
tRRH
0
–
0
–
ns
11
CAS to output inlow-Z
tCLZ
0
–
0
–
ns
8
Output buffer turn-off delay from CAS
tOFF
0
–
0
10
ns
12
7
Read Cycle
Semiconductor Group
8
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Parameter
Limit Values
Symbol
-400
Unit Note
-40
min.
max.
min.
max.
10
Output buffer turn-off delay from OE
tOEZ
0
10
0
Data to OE low delay
tDZO
0
–
0
CAS high to data delay
tCDD
8
–
8
OE high to data delay
tODD
8
–
Data to CAS low delay
tDZC
0
Write command hold time
tWCH
Write command pulse width
ns
12
ns
13
–
ns
14
8
–
ns
14
–
0
–
ns
13
5
–
5
–
ns
tWP
5
–
5
–
ns
Write command setup time
tWCS
0
–
0
–
ns
Write command to RAS lead time
tRWL
10
–
10
–
ns
Write command to CAS lead time
tCWL
10
–
10
–
ns
Data setup time
tDS
0
–
0
–
ns
16
Data hold time
tDH
5
–
5
–
ns
16
Data to CAS low delay
tDZC
0
–
0
–
ns
13
Read-write cycle time
tRWC
93
–
93
–
ns
RAS to WE delay time
tRWD
52
–
52
–
ns
15
CAS to WE delay time
tCWD
22
–
22
–
ns
15
Column address to WE delay time
tAWD
32
–
32
–
ns
15
OE command hold time
tOEH
5
–
5
–
ns
Hyper page mode cycle time
tHPC
12.5
–
15
–
ns
Access time from CAS precharge
tCPA
–
17
–
21
ns
Output data hold time
tCOH
3
–
3
–
ns
RAS pulse width in hyper page mode
tRAS
40
200k
40
200k
ns
RAS hold time from CAS precharge
tRHCP
17
–
21
–
ns
Write Cycle
15
Read-modify-Write Cycle
Hyper Page Mode (EDO) Cycle
Semiconductor Group
9
7
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Parameter
Limit Values
Symbol
-400
Unit Note
-40
min.
max.
min.
max.
Hyper Page Mode (EDO) Read-Modify-Write Cycle
Hyper page mode read/write cycle time
tPRWC
55
–
55
–
ns
CAS precharge to WE delay time
tCPWD
35
–
35
–
ns
CAS setup time
tCSR
5
–
5
–
ns
CAS hold time
tCHR
5
–
5
–
ns
RAS to CAS precharge time
tRPC
5
–
5
–
ns
Write to RAS precharge time
tWRP
10
–
10
–
ns
Write to RAS hold time
tWRH
10
–
10
–
ns
CAS precharge time
tCPT
25
–
25
–
ns
Semiconductor Group
10
CAS before RAS Refresh Cycle
CAS-before-RAS Counter Test Cycle
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
AC Characteristics 5)6)
TA = 0 to 70 ˚C, tT = 2 ns
Parameter
16E
Limit Values
Symbol
-45
Unit Note
-50
min.
max.
min.
max.
Common Parameters
Random read or write cycle time
tRC
79
–
89
–
ns
RAS precharge time
tRP
30
–
35
–
ns
RAS pulse width
tRAS
45
10k
50
10k
ns
CAS pulse width
tCAS
7
10k
8
10k
ns
CAS precharge time
tCP
7
–
8
–
ns
Row address setup time
tASR
0
–
0
–
ns
Row address hold time
tRAH
7
–
8
–
ns
Column address setup time
tASC
0
–
0
–
ns
Column address hold time
tCAH
7
–
8
–
ns
RAS to CAS delay time
tRCD
11
33
12
37
ns
RAS to column address delay
tRAD
9
23
10
25
ns
RAS hold time
tRSH
12
13
–
ns
CAS hold time
tCSH
36
40
–
ns
CAS to RAS precharge time
tCRP
5
–
5
–
ns
Transition time (rise and fall)
tT
1
50
1
50
ns
Refresh period
tREF
–
16
–
16
ms
Refresh period (L-version only)
tREF
–
128
–
128
ms
Access time from RAS
tRAC
–
45
–
50
ns
8, 9
Access time from CAS
tCAC
–
12
–
13
ns
8, 9
Access time from column address
tAA
–
22
–
25
ns
8,10
OE access time
tOEA
–
12
–
13
ns
Column address to RAS lead time
tRAL
23
–
25
–
ns
Read command setup time
tRCS
0
–
0
–
ns
Read command hold time
tRCH
0
–
0
–
ns
11
Read command hold time referenced to RAS
tRRH
0
–
0
–
ns
11
CAS to output in low-Z
tCLZ
0
–
0
–
ns
8
Semiconductor Group
11
7
Read Cycle
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
AC Characteristics (cont’d) 5)6)
TA = 0 to 70 ˚C, tT = 2 ns
Parameter
16E
Limit Values
Symbol
-45
Unit Note
-50
min.
max.
min.
max.
Output buffer turn-off delay
tOFF
0
12
0
13
ns
12
Output turn-off delay from OE
tOEZ
0
12
0
13
ns
12
Data to CAS low delay
tDZC
0
–
0
–
ns
13
Data to OE low delay
tDZO
0
–
0
–
ns
13
CAS high to data delay
tCDD
10
–
10
–
ns
14
OE high to data delay
tODD
10
–
10
–
ns
14
Write command hold time
tWCH
7
–
8
–
ns
Write command pulse width
tWP
7
–
8
–
ns
Write command setup time
tWCS
0
–
0
–
ns
Write command to RAS lead time
tRWL
12
–
13
–
ns
Write command to CAS lead time
tCWL
12
–
13
–
ns
Data setup time
tDS
0
–
0
–
ns
16
Data hold time
tDH
7
–
8
–
ns
16
Read-write cycle time
tRWC
107
–
118
–
ns
RAS to WE delay time
tRWD
59
–
64
–
ns
15
CAS to WE delay time
tCWD
26
–
27
–
ns
15
Column address to WE delay time
tAWD
36
–
39
–
ns
15
OE command hold time
tOEH
7
–
10
–
ns
Hyper page mode (EDO) cycle time
tHPC
18
–
20
–
ns
Access time from CAS precharge
tCPA
–
25
–
27
ns
Output data hold time
tCOH
5
–
5
–
ns
RAS pulse width in EDO mode
tRAS
45
200k
50
200k
ns
CAS precharge to RAS Delay
tRHPC
25
–
27
–
ns
Semiconductor Group
12
Write Cycle
15
Read-modify-Write Cycle
Hyper Page Mode (EDO) Cycle
7
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
AC Characteristics (cont’d) 5)6)
TA = 0 to 70 ˚C, tT = 2 ns
Parameter
16E
Limit Values
Symbol
-45
Unit Note
-50
min.
max.
min.
max.
51
–
58
–
ns
tCPWD
41
–
41
–
ns
CAS setup time
tCSR
5
–
10
–
ns
CAS hold time
tCHR
10
–
10
–
ns
RAS to CAS precharge time
tRPC
5
–
5
–
ns
Write to RAS precharge time
tWRP
10
–
10
–
ns
Write hold time referenced to RAS
tWRH
10
–
10
–
ns
tCPT
30
–
35
–
ns
RAS pulse width
tRASS
100k
–
100k
–
ns
17
RAS precharge
tRPS
110
–
95
–
ns
17
CAS hold time
tCHS
– 50
–
– 50
–
ns
17
Hyper Page Mode (EDO) Read-modify-Write Cycle
Hyper page mode (EDO) read-write cycle time tPRWC
CAS precharge to WE
CAS-before-RAS Refresh Cycle
CAS-before-RAS Counter Test Cycle
CAS precharge time
Self Refresh Cycle (L-version)
Notes:
1) All voltages are referenced to VSS.
2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open.
4) Address can be changed once or less while RAS = VIL. In case of ICC4 it can be changed once or less during
a hyper page mode (EDO) cycle
5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has
to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter,
a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume tT = 2 ns.
Semiconductor Group
13
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also
measured between VIH and VIL.
8) Measured with the specified current load and 50 pF at VOL = 0.8 V and VOH = 2.0 V. Access time is determined
by the latter of tRAC, tCAC, tAA, tCPA , tOEA. tCAC is measured from tristate
.
+ 1.5 V
50 Ohm
Z=50 Ohm
I/O
50 pF
fig.2
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point
only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC.
10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point
only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA.
11) Either tRCH or tRRH must be satisfied for a read cycle.
12) tOFF (max.), tOEZ (max.) define the time at which the output achieves the open-circuit conditions and are not
referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs
last.
13) Either tDZC or tDZO must be satisfied.
14) Either tCDD or tODD must be satisfied.
15) tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain
open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.) and tAWD > tAWD (min.),
the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above
sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate.
16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge
in read-write cycles.
17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM
operation:
If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR
refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh.
If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the
refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately
after exit from Self Refresh.
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HYB 5(3)14265BJ(L)-400/-40/-45/-50
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Read Cycle
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Write Cycle (Early Write)
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Write Cycle (OE Controlled Write)
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Read-Write (Read-Modify-Write) Cycle
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Hyper Page Mode (EDO) Read Cycle
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Hyper Page Mode (EDO) Early Write Cycle
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Hyper Page Mode (EDO) Late Write and Read-Modify-Write Cycles
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RAS-Only Refresh Cycle
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CAS-Before-RAS Refresh Cycle
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CAS before RAS Self Refresh Cycle
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Hidden Refresh Cycle (Read)
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Hidden Refresh Cycle (Early Write)
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CAS-Before-RAS Refresh Counter Test Cycle
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Package Outlines
GPJ09018
P-SOJ-40-3
(Small Outline J-Leaded Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
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Dimensions in mm