Qimonda HYB39S128400FT-7 128-mbit synchronous dram Datasheet

October 2007
HYB39S128400F[E/T](L)
HY[B/I]39S128800F[E/T](L)
HY[B/I]39S128160F[E/T](L)
HYB39S 128407 F E
128-MBit Synchronous DRAM
Green Product
SDRAM
Data Sheet
Rev. 1.32
Data Sheet
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
128-MBit Synchronous DRAM
HYB39S128400F[E/T](L), HY[B/I]39S128800F[E/T](L), HY[B/I]39S128160F[E/T](L)
Revision History: 2007-10, Rev. 1.32
Page
Subjects (major changes since last revision)
All
Adapted Internet Version
23
Corrected number of refresh cycles
Previous Revision: 2007-06, Rev. 1.31
13
Corrected operation command "Power Down / Clock suspend ...” in truth table
15
Corrected text to "After the mode register is set a NOP command is required"
19
Corrected text to "One clock delay is required for mode entry and exit", chapter 3.5
19
Corrected the line "Input Capacitances: CK" in table 10, chapter 4
22
Corrected tCK MIN in table 14
22
Corrected CLE setup time in table 14
Previous Revision: 2007-03, Rev. 1.30
15
Corrected mode register definition
21
IDD for low power option 0.8 mA
22
“Transition time” replaced by “Transition Time of Clock (Rise and Fall)”
4
Added HYI39S128800FT-7, HYI39S128800FE-7, HYI39S128160FT-7, HYI39S128160FE-7 and
HYB39S128407FE-7
Previous Revision: 2006-10, Rev. 1.20
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-01
10122006-I6LJ-WV3H
2
Data Sheet
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
128-MBit Synchronous DRAM
1
Overview
This chapter lists all main features of the product family HY[B/I]39S128[40/80/16][0/7]F[E/T](L) and the ordering information.
1.1
•
•
•
•
•
•
•
•
•
Features
Fully Synchronous to Positive Clock Edge
0 to 70 °C Standard Operating Temperature
-40 to 85 °C Industrial Operating Temperature
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2 & 3
Programmable Wrap Sequence: Sequential or Interleave
Programmable Burst Length: 1, 2, 4, 8 and full page
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
•
•
•
•
•
•
•
•
•
Data Mask for Read / Write control (x4, x8)
Data Mask for Byte Control (x16)
Auto Refresh (CBR) and Self Refresh
Power Down and Clock Suspend Mode
4096 refresh cycles / 64 ms (15.6 μs)
Random Column Address every CLK (1-N Rule)
Single 3.3 V ± 0.3 V Power Supply
LVTTL Interface
Plastic Packages: P(G)–TSOPII–54 400 mil width
TABLE 1
Performance
Product Type Speed Code
–7
Unit
Speed Grade
PC133–222
—
Max. Clock Frequency
fCK3
tCK3
tAC3
tCK2
tAC2
@CL3
@CL2
1.2
143
MHz
7
ns
5.4
ns
7.5
ns
5.4
ns
Description
The HY[B/I]39S128[40/80/16][0/7]F[E/T](L) are four bank Synchronous DRAM’s organized as 32 MBit x4, 16 MBit x8
and 8 Mbit x16 respectively. These synchronous devices achieve high speed data transfer rates for CAS latencies by
employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip
is fabricated with Qimonda’s advanced 0.11 μm 128-MBit DRAM process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products, both electrically and
mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally
supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is
possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and
speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single 3.3 V ± 0.3 V power supply.
All 128-Mbit components are available in P(G)–TSOPII–54 packages.
Rev. 1.32, 2007-10
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Data Sheet
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
128-MBit Synchronous DRAM
TABLE 2
Ordering Information for Lead-Containing Products
Product Type
Speed Grade
Description
Package
143MHz 32M x 4 SDRAM
P-TSOPII-54
Standard Operating Temperature (0 to 70 °C)
HYB39S128400FT-7
PC133–222–520
HYB39S128400FTL-7
HYB39S128800FT-7
143MHz 16M x 8 SDRAM
HYB39S128800FTL-7
HYB39S128160FT-7
143MHz 8M x 16 SDRAM
HYB39S128160FTL-7
Industrial Operating Temperature (-40 to 85 °C)
HYI39S128800FT-7
PC133–222–520
143MHz 16M x 8 SDRAM
HYI39S128160FT-7
P-TSOPII-54
143MHz 8M x 16 SDRAM
TABLE 3
Ordering Information for RoHS Compliant Products
Product Type
Speed Grade
Description
Package
Note
143MHz 32M x 4 SDRAM
PG-TSOPII-54
1)
PG-TSOPII-54
1)
Standard Operating Temperature (0 to 70 °C)
HYB39S128400FE-7
PC133–222–520
HYB39S128400FEL-7
HYB39S128407FE-7
HYB39S128800FE-7
143MHz 16M x 8 SDRAM
HYB39S128800FEL-7
HYB39S128160FE-7
143MHz 8M x 16 SDRAM
HYB39S128160FEL-7
Industrial Operating Temperature (-40 to 85 °C)
HYI39S128800FE-7
HYI39S128160FE-7
PC133–222–520
143MHz 16M x 8 SDRAM
143MHz 8M x 16 SDRAM
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.32, 2007-10
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4
Data Sheet
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
128-MBit Synchronous DRAM
2
Chip Configuration
This chapter contains the pin configuration table, the TSOP package drawing, and the block diagrams for the ×4, ×8, ×16
organization of the SDRAM.
2.1
Pin Description
Listed below are the pin configurations sections for the various signals of the SDRAM
TABLE 4
Pin Configuration of the SDRAM
Ball No.
Name
Pin
Type
Buffer
Type
Function
Clock Signals ×4/×8/×16 Organization
38
CLK
I
LVTTL
Clock Signal CK
37
CKE
I
LVTTL
Clock Enable
Control Signals ×4/×8/×16 Organization
18
RAS
I
LVTTL
17
CAS
I
LVTTL
16
WE
I
LVTTL
19
CS
I
LVTTL
Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE)
Chip Select
Address Signals ×4/×8/×16 Organization
20
BA0
I
LVTTL
21
BA1
I
LVTTL
23
A0
I
LVTTL
24
A1
I
LVTTL
25
A2
I
LVTTL
26
A3
I
LVTTL
29
A4
I
LVTTL
30
A5
I
LVTTL
31
A6
I
LVTTL
32
A7
I
LVTTL
33
A8
I
LVTTL
34
A9
I
LVTTL
22
A10
I
LVTTL
35
A11
I
LVTTL
Rev. 1.32, 2007-10
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Bank Address Signals 1:0
Address Signal, Address Signal 10/Auto precharge
5
Data Sheet
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
128-MBit Synchronous DRAM
Ball No.
Name
Pin
Type
Buffer
Type
Function
Data Signals ×4 Organization
5
DQ0
I/O
LVTTL
11
DQ1
I/O
LVTTL
44
DQ2
I/O
LVTTL
50
DQ3
I/O
LVTTL
Data Signal Bus
Data Signals ×8 Organization
2
DQ0
I/O
LVTTL
5
DQ1
I/O
LVTTL
8
DQ2
I/O
LVTTL
11
DQ3
I/O
LVTTL
44
DQ4
I/O
LVTTL
47
DQ5
I/O
LVTTL
50
DQ6
I/O
LVTTL
53
DQ7
I/O
LVTTL
Data Signal Bus
Data Signals ×16 Organization
2
DQ0
I/O
LVTTL
4
DQ1
I/O
LVTTL
5
DQ2
I/O
LVTTL
7
DQ3
I/O
LVTTL
8
DQ4
I/O
LVTTL
10
DQ5
I/O
LVTTL
11
DQ6
I/O
LVTTL
13
DQ7
I/O
LVTTL
42
DQ8
I/O
LVTTL
44
DQ9
I/O
LVTTL
45
DQ10
I/O
LVTTL
47
DQ11
I/O
LVTTL
48
DQ12
I/O
LVTTL
50
DQ13
I/O
LVTTL
51
DQ14
I/O
LVTTL
53
DQ15
I/O
LVTTL
Data Signal Bus
Data Mask ×4/×8 Organization
39
DQM
I/O
LVTTL
Data Mask
Data Mask ×16 Organization
39
UDQM
I/O
LVTTL
Data Mask Upper Byte
15
LDQM
I/O
LVTTL
Data Mask Lower Byte
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Data Sheet
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
128-MBit Synchronous DRAM
Ball No.
Name
Pin
Type
Buffer
Type
Function
Power Supplies ×4/×8/×16 Organization
9
14
46
41
VDDQ
VDD
VSSQ
VSS
PWR
–
Power Supply
PWR
–
Power Supply
PWR
–
Power Supply Ground for DQs
PWR
–
Power Supply Ground
Not connected ×4 Organization
2, 4, 7, 8, NC
10, 13,
15, 36,
40, 42,
45, 47,
48, 51,
53
NC
–
Not connected
Not connected ×8 Organization
4, 7, 10,
13, 15,
36, 40,
42, 45,
48, 51
NC
NC
–
Not connected
Not connected ×16 Organization
36, 40
NC
NC
Rev. 1.32, 2007-10
10122006-I6LJ-WV3H
–
Not connected
7
Data Sheet
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
128-MBit Synchronous DRAM
2.2
Package P(G)–TSOPII–54
Listed below are the pin outs of the TSOP package.
FIGURE 1
Pin Configuration P(G)-TSOPII-54
[
[
[
9''
9''
9''
966
966
966
'4
'4
1&
1&
'4
'4
9''4
9''4
9''4
9664
9664
9664
'4
1&
1&
1&
1&
'4
'4
'4
'4
'4
'4
'4
9664
9664
9664
9''4
9''4
9''4
'4
1&
1&
1&
1&
'4
'4
'4
1&
1&
'4
'4
9''4
9''4
9''4
9664
9664
9664
'4
1&
1&
1&
1&
'4
'4
'4
'4
'4
'4
'4
9664
9664
9664
9''4
9''4
9''4
'4
1&
1&
1&
1&
'4
966
966
9''
9''
9''
966
/'4
0
1&
1&
1&$ 1&$ 1&$
:(
:(
:(
'40
'40
8'4
0
&$6
&$6
&$6
&.
&.
&.
5$6
5$6
5$6
&.(
&.(
&.(
&6
&6
&6
1&$ 1&$ 1&$
%$
%$
%$
$
$
$
$%$
$%$ $%
$
$
$
$
$
$3
$$3
$$
3
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
$
9''
9''
9''
966
966
966
0336
Rev. 1.32, 2007-10
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Data Sheet
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
128-MBit Synchronous DRAM
3
Functional Description
This chapter list all defined commands and their usage for this Synchronous DRAM family.
TABLE 5
Truth Table: Operation Command
Operation
Bank Active
Device State
Idle3)
CKE
n-11)2)
CKE
n1)2)
DQM
H
X
X
1)2)
BA0
BA11)2)
AP=
A101)2)
Addr. CS1 RAS
1)2)
)2)
1)2)
CAS1 WE
)2)
1)2)
V
V
V
L
L
H
H
Bank Precharge
Any
H
X
X
V
L
X
L
L
H
L
Precharge All
Any
H
X
X
X
H
X
L
L
H
L
Write
Active3)
H
X
X
V
L
V
L
H
L
L
Write with Auto
precharge
Active
3)
H
X
X
V
H
V
L
H
L
L
Read
Active3)
H
X
X
V
L
V
L
H
L
H
3)
H
X
X
V
H
V
L
H
L
H
H
X
X
V
V
V
L
L
L
L
Read with Auto
precharge
Active
Mode Register Set
Idle
No Operation
Any
H
X
X
X
X
X
L
H
H
H
Burst Stop
Active
H
X
X
X
X
X
L
H
H
L
Device Deselect
Any
H
X
X
X
X
X
H
X
X
X
Auto Refresh
Idle
H
H
X
X
X
X
L
L
L
H
Self Refresh Entry
Idle
H
L
X
X
X
X
L
L
L
H
Self Refresh Exit
Idle (Self Refr.)
L
H
X
X
X
X
H
X
X
X
L
H
H
X
Power Down/
Clock Suspend Entry
Active or Idle
or Burst
H
L
X
X
X
X
H
X
X
X
L
H
H
H
Power Down/
Clock Suspend Exit
Active or Idle
or Burst
L
H
X
X
X
X
H
X
X
X
L
H
H
H
Data Write/
Output Enable
Active
H
X
L
X
X
X
X
X
X
X
Data Write/
Output Disable
Active
H
X
H
X
X
X
X
X
X
X
1) V = Valid, x = Don’t Care, L = Low Level, H = High Level
2) CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are provided.
3) This is the state of the banks designated by BA0, BA1 signals.
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Data Sheet
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
128-MBit Synchronous DRAM
%$ %$
$
$
$
$
:%/
$
$
70
Z
UHJDGGU
$
$
$
$
$
$
&/
%7
%/
Z
Z
Z
$
03%6
TABLE 6
Mode Register Definition (BA1:0 = 00B)
Field
Bits
Type
Description
BL
2:0
w
Burst Length
Number of sequential bits per DQ related to one read/write command
Note: All other bit combinations are RESERVED
000B
001B
010B
011B
111B
1
2
4
8
Full Page (Sequential burst type only)
BT
3
Burst Type
Sequential
0B
1B
Interleaved
CL
6:4
CAS Latency
Number of full clocks from read command to first data valid window.
Note: All other bit combinations are RESERVED.
010B 2
011B 3
TM
8:7
Test Mode
Note: All other bit combinations are RESERVED.
00B
WBL
Mode register set
9
Write Burst Length
Burst write
0B
1B
Single bit write
12:10
Reserved, set to zero
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Data Sheet
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
128-MBit Synchronous DRAM
TABLE 7
Burst Length and Sequence
Burst Length
Starting Column Address
A2
A1
A0
Type=Sequential
Type=Interleaved
0
0–1
0–1
1
1–0
1–0
0
0
0–1–2–3
0–1–2–3
0
1
1–2–3–0
1–0–3–2
1
0
2–3–0–1
2–3–0–1
2
4
8
FullPage
Order of Accesses Within a Burst
1
1
3–0–1–2
3–2–1–0
0
0
0
0–1–2–3–4–5–6–7
0–1–2–3–4–5–6–7
0
0
1
1–2–3–4–5–6–7–0
1–0–3–2–5–4–7–6
0
1
0
2–3–4–5–6–7–0–1
2–3–0–1–6–7–4–5
0
1
1
3–4–5–6–7–0–1–2
3–2–1–0–7–6–5–4
1
0
0
4–5–6–7–0–1–2–3
4–5–6–7–0–1–2–3
1
0
1
5–6–7–0–1–2–3–4
5–4–7–6–1–0–3–2
1
1
0
6–7–0–1–2–3–4–5
6–7–4–5–2–3–0–1
1
1
1
7–0–1–2–3–4–5–6
7–6–5–4–3–2–1–0
Cn, Cn+1, Cn+2 ....
Not supported
n
Notes
1.
2.
3.
4.
For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block.
For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the block.
For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access with in the block.
Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
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Data Sheet
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
128-MBit Synchronous DRAM
4
Electrical Characteristics
4.1
Operating Conditions
TABLE 8
Absolute Maximum Ratings
Parameter
Input / Output voltage relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating Temperature for HYB...
Operating Temperature for HYI...
Storage temperature range
Power dissipation per SDRAM component
Data out current (short circuit)
Symbol
Limit Values
VIN, VOUT
VDD
VDDQ
TA
TA
TSTG
PD
IOUT
Unit
Note/
Test Condition
Min.
Max.
– 1.0
+4.6
V
–
– 1.0
+4.6
V
–
– 1.0
+4.6
V
–
0
+70
°C
–
-40
+85
°C
–
-55
+150
°C
–
–
1
W
–
–
50
mA
–
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings
are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated
circuit.
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Data Sheet
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
128-MBit Synchronous DRAM
TABLE 9
DC Characteristics
Parameter
Symbol
Values
Min. Max.
VDD
I/O Supply Voltage
VDDQ
Input high voltage
VIH
Input low voltage
VIL
Output high voltage (IOUT = – 4.0 mA)
VOH
Output low voltage (IOUT = 4.0 mA)
VOL
Input leakage current, any input(0 V < VIN < VDD, all other inputs = 0 V) IIL
Output leakage current(DQs are disabled, 0 V < VOUT < VDDQ)
IOL
Supply Voltage
Unit Note/
Test Condition
3.0
3.6
V
1)2)
3.0
3.6
V
1)2)
2.0
VDDQ+0.3 V
1)2)3)
– 0.3 +0.8
V
1)2)3)
2.4
–
V
1)2)
–
0.4
V
1)2)
–5
+5
μA
1)
–5
+5
μA
1)
1) TA = 0 to 70 ºC
2) All voltages are referenced to VSS
3) VIH may overshoot to VDDQ + 2.0 V for pulse width of < 4ns with 3.3 V. VIL may undershoot to -2.0 V for pulse width < 4.0 ns with 3.3 V.
Pulse width measured at 50% points with amplitude measured peak to DC reference.
TABLE 10
Input and Output Capacitances
Parameter
Symbol
Values1)
Min.
Max.
Unit
Note
Input Capacitances: CK
CI1
2.5
3.5
pF
2)
Input Capacitance
(A0-A11, BA0, BA1, RAS, CAS, WE, CS, CKE, DQM)
CI2
2.5
3.8
pF
2)
Input/Output Capacitance (DQ)
CI0
4.0
6.0
pF
2)
1) Capacitance values are shown for TSOP-54 packages. Capacitance values for TFBGA packages are lower by 0.5 pF
2) TA = 0 to 70 ºC; VDD,VDDQ = 3.3 V ± 0.3 V, f = 1 MHz
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Data Sheet
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
128-MBit Synchronous DRAM
TABLE 11
IDD Conditions
Parameter
Symbol
Operating Current
One bank active, Burst length = 1
IDD1
Precharge Standby Current in Power Down Mode
IDD2P
IDD2N
IDD3N
IDD3P
IDD4
Recharge Standby Current in Non-Power Down Mode
No Operating Current
Active state (max. 4 banks)
Burst Operating Current
Read command cycling
Auto Refresh Current
Auto Refresh command cycling
IDD5
Self Refresh Current (standard components)
Self Refresh Mode, CKE=0.2 V, tCK=infinity
IDD6
Self Refresh Current (low power components)
Self Refresh Mode, CKE=0.2 V, tCK=infinity
TABLE 12
IDD Specifications and Conditions
Symbol
–7
Unit
Note/ Test Condition
80
mA
1)2)3)4)
2
mA
1)2)
22
mA
1)2)
35
mA
1)2)
5
mA
1)2)
65
mA
1)2)4)
146
mA
1)2)5)
25
mA
1)2)
3
mA
1)2)
0.8
mA
1)
Max.
IDD1
IDD2P
IDD2N
IDD3N
IDD3P
IDD4
IDD5
tRC = tRC(min), IO = 0 mA
CS =VIH (min.), CKE ≤VIL(max)
CS =VIH (min.), CKE≥ VIH(min)
CS = VIH(min), CKE ≥VIH(min.)
CS = VIH(min), CKE ≤ VIL(max.)
tRFC= tRFC(min)
tRFC= 15.6 μs
IDD6
Standard components
Low power components at 85 °C
1) Currents values will be added when available.
2) TA = 0 to 70 °C; VSS = 0 V; VDD, VDDQ = 3.3 V ± 0.3 V
3) These parameters depend on the cycle rate. All values are measured at 133 MHz for -7 with the outputs open. Input signals are changed
once during tCK.
4) These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3 and BL=4 is assumed and
the VDDQ current is excluded.
5) tRFC= tRFC(min) “burst refresh”, tRFC= 15.6 μs “distributed refresh”.
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Data Sheet
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
128-MBit Synchronous DRAM
4.2
AC Characteristics
TABLE 13
AC Timing - Absolute Specifications –7
Parameter
Symbol
–7
Unit
Note
PC133– 222
Min.
Max.
Clock and Clock Enable
Clock Frequency
tCK
7
7.5
—
—
ns
ns
CL3 1)2)3)
CL2 1)2)3)
Access Time from Clock
tAC
—
—
5.4
5.4
ns
ns
CL31)2)3)
CL21)2)3)4)5)
Clock High Pulse Width
tCH
tCL
tT
2.5
—
ns
1)2)3)
2.5
—
ns
1)2)3)
0.3
1.2
ns
1)2)3)
tIS
tIH
tCKS
tCKH
tRSC
tSB
1.5
—
ns
1)2)3)6)
0.8
—
ns
1)2)3)6)
1.5
—
ns
1)2)3)6)
0.8
—
ns
1)2)3)6)
2
—
tCK
1)2)3)
0
7
ns
1)2)3)
tRCD
tRP
tRAS
tRC
tRFC
tRRD
tCCD
15
—
ns
1)2)3)7)
15
—
ns
1)2)3)7)
37
100k
ns
1)2)3)7)
60
—
ns
1)2)3)7)
63
—
ns
1)2)3)
14
—
ns
1)2)3)7)
1
—
tCK
1)2)3)
tREF
tSREX
tOH
–
64
ms
1)2)3)
1
—
tCK
1)2)3)
3
—
ns
1)2)3)5)
tLZ
tHZ
tDQZ
0
—
ns
1)2)3)
3
7
ns
1)2)3)
—
2
tCK
1)2)3)
Clock Low Pulse Width
Transition Time of Clock (Rise and Fall)
Setup and Hold Times
Input Setup Time
Input Hold Time
CKE Setup Time
CKE Hold Time
Mode Register Set-up to Active delay
Power Down Mode Entry Time
Common Parameters
Row to Column Delay Time
Row Precharge Time
Row Active Time
Row Cycle Time
Row Cycle Time during Auto Refresh
Activate(a) to Activate(b) Command period
CAS(a) to CAS(b) Command period
Refresh Cycle
Refresh Period (4096 cycles)
Self Refresh Exit Time
Data Out Hold Time
Read Cycle
Data Out to Low Impedance Time
Data Out to High Impedance Time
DQM Data Out Disable Latency
Rev. 1.32, 2007-10
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Data Sheet
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
128-MBit Synchronous DRAM
Parameter
Symbol
–7
Unit
Note
PC133– 222
Min.
Max.
14
—
ns
1)2)3)8)
1)2)3)9)
—
tCK
tCK
Write Cycle
Last Data Input to Precharge
(Write without Auto Precharge)
tWR
Last Data Input to Activate(Write with Auto Precharge)
tDAL(min.)
tDQW
DQM Write Mask Latency
1) TA = 0 to 70 °C; VSS = 0 V; VDD, VDDQ = 3.3 V ± 0.3 V, tT = 1 ns
0
1)2)3)
2) For proper power-up see the operation section of this data sheet.
3) AC timing tests for LV-TTL versions have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition
time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown in figure below.
Specified tAC and tOH parameters are measured with a 50 pF only, without any resistive termination and with an input signal of 1V / ns edge
rate between 0.8 V and 2.0 V.
4) If clock rising time is longer than 1 ns, a time (tT/2 - 0.5) ns has to be added to this parameter.
5) Access time from clock tac is 4.6 ns for PC133 components with no termination and 0 pF load,Data out hold time toh is 1.8 ns for PC133
components with no termination and 0 pF load.
6) If tT is longer than 1 ns, a time (tT - 1) ns has to be added to this parameter.
7) These parameter account for the number of clock cycles and depend on the operating frequency of the clock, as follows:the number of
clock cycles = specified value of timing period (counted in fractions as a whole number)
8) It is recommended to use two clock cycles between the last data-in and the precharge command in case of a write command without AutoPrecharge. One clock cycle between the last data-in and the precharge command is also supported, but restricted to cycle times tCK greater
or equal the specified tWR value, where tck is equal to the actual system clock time.
9) When a Write command with Auto Precharge has been issued, a time of tDAL(min) has be fullfilled before the next Activate Command can
be applied. For each of the terms, if not already an integer, round up to the next highest integer. tCK is equal to the actual system clock time.
FIGURE 2
Measurement conditions for tAC and tOH
t CH
2.4 V
0.4 V
1.4 V
CLOCK
t CL
t IS
tT
t IH
1.4 V
INPUT
tAC
t LZ
tAC
t OH
OUTPUT
1.4 V
I/O
50 pF
t HZ
Measurement conditions for
tAC and tOH
IO.vsd
Rev. 1.32, 2007-10
10122006-I6LJ-WV3H
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Data Sheet
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
128-MBit Synchronous DRAM
5
Package Outlines
FIGURE 3
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Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 1.32, 2007-10
10122006-I6LJ-WV3H
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*3; Data Sheet
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
128-MBit Synchronous DRAM
List of Figures
Figure 1
Figure 2
Figure 3
Pin Configuration P(G)-TSOPII-54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Measurement conditions for tAC and tOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Package Outline PG-TSOPII-54-4 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Rev. 1.32, 2007-10
10122006-I6LJ-WV3H
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Data Sheet
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
128-MBit Synchronous DRAM
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information for Lead-Containing Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering Information for RoHS Compliant Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Configuration of the SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Truth Table: Operation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Mode Register Definition (BA1:0 = 00B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Burst Length and Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input and Output Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
IDD Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
IDD Specifications and Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
AC Timing - Absolute Specifications –7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Rev. 1.32, 2007-10
10122006-I6LJ-WV3H
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Data Sheet
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
128-MBit Synchronous DRAM
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
2.1
2.2
Chip Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package P(G)–TSOPII–54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
4.1
4.2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Rev. 1.32, 2007-10
10122006-I6LJ-WV3H
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Data Sheet
Edition 2007-10
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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