Infineon HYB39S512400AT 512-mbit synchronous dram Datasheet

D a t a S h e e t , R e v. 1 . 3 , M ar c h 2 00 3
H Y B 39 S 5 1 2 4 0 0 A T ( L )
H Y B 39 S 5 1 2 8 0 0 A T ( L )
H Y B 39 S 5 1 2 1 6 0 A T ( L )
512- Mbi t Synchr onous DRAM
SDRAM
M e m or y P r o du c t s
N e v e r
s t o p
t h i n k i n g .
Edition 2004-03
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
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and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
D a t a S h e e t , R e v. 1 . 3 , M ar c h 2 00 3
H Y B 39 S 5 1 2 4 0 0 A T ( L )
H Y B 39 S 5 1 2 8 0 0 A T ( L )
H Y B 39 S 5 1 2 1 6 0 A T ( L )
512- Mbi t Synchr onous DRAM
SDRAM
M e m or y P r o du c t s
N e v e r
s t o p
t h i n k i n g .
HYB 39S512[40/80/16]0AT(L)
Revision History:
Rev. 1.3
Page
Subjects (major changes since last revision)
18
Removed Extended Mode Register
Previous Version:
2004-03
Rev. 1.22
Page
Subjects (major changes since last revision)
17
Corrected Mode Register Definition in chapter 3
all
Various layout and editorial changes
2003-09
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Template: mp_a4_v2.2_2003-10-07.fm
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
2.1
2.2
2.3
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package P-TSOPII-54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
10
11
12
3
3.1
3.2
3.3
3.3.1
3.4
3.5
3.5.1
3.5.2
3.5.3
3.5.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DQM Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
16
16
18
18
19
19
20
20
20
4
4.1
4.2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Data Sheet
5
Rev. 1.3, 2004-03
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Data Sheet
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Signal Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Truth Table: Operation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Burst Length and Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Bank Selection by Address Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Input and Output Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
IDD Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
IDD Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6
Rev. 1.3, 2004-03
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Data Sheet
PinoutP-TSOPII-54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram for 128M × 4 SDRAM ( 13 / 12 / 2 addressing) . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram for 64M × 8 SDRAM ( 13 / 11 / 2 addressing) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram for 32M × 16 SDRAM ( 13 / 10 / 2 addressing) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Measurement conditions for tAC and tOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outlines P-TSOPII-54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
11
12
13
14
26
27
Rev. 1.3, 2004-03
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Overview
1
Overview
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Fully Synchronous to Positive Clock Edge
0 to 70 °C operating temperature
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2 & 3
Programmable Wrap Sequence: Sequential or Interleave
Programmable Burst Length: 1, 2, 4, 8 and full page
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Data Mask for Read / Write control (×4, ×8)
Data Mask for byte control (×16)
Auto Refresh (CBR) and Self Refresh
Power Down and Clock Suspend Mode
8192 refresh cycles / 64 ms (7,8 µs)
Random Column Address every CLK ( 1-N Rule)
Single 3.3 V ± 0.3 V Power Supply
LVTTL Interface versions
Plastic Packages:
P-TSOPII-54 400mil width (x4, x8, x16)
Table 1
Performance
Part Number Speed Code
–7
–7.5
–8
Unit
Speed Grade
PC133 2–2–2
PC133 3–3–3
PC100 2–2–2
–
143
133
125
MHz
7
7.5
8
ns
5.4
5.4
6
ns
7.5
10
10
ns
5.4
6
6
ns
max. Clock Frequency
1.2
fCK
tCK3
tAC3
@CL2 tCK2
tAC2
@CL3
Description
The HYB 39S512[40/80/16]0AT(L) are four bank Synchronous DRAM’s organized as 4 banks × 32MBit ×4, 4
banks × 16MBit ×8 and 4 banks × 8Mbit ×16 respectively. These synchronous devices achieve high speed data
transfer rates for CAS-latencies by employing a chip architecture that prefetches multiple bits and then
synchronizes the output data to a system clock. The chip is fabricated with INFINEON’s advanced 0.14 µm
512MBit DRAM process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products, both electrically
and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge
of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur at higher rate
than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length,
CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a single 3.3 V ± 0.3 V
power supply. All 512Mbit components are housed in P-TSOPII-54 packages.
Data Sheet
8
Rev. 1.3, 2004-03
10082003-L1GD-PVI5
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Overview
Table 2
Ordering Information
Type
Speed Grade
Package
Description
HYB 39S512400AT-7
PC133-222-520
P-TSOP-54-2 (400mil)
143MHz 4B × 32M × 4 SDRAM
HYB 39S512400AT-7.5 PC133-333-520
P-TSOP-54-2 (400mil)
133MHz 4B × 32M × 4 SDRAM
HYB 39S512400AT-8
PC100-222-620
P-TSOP-54-2 (400mil)
125MHz 4B × 32M × 4 SDRAM
HYB 39S512800AT-7
PC133-222-520
P-TSOP-54-2 (400mil)
143MHz 4B × 16M × 8 SDRAM
HYB 39S512800AT-7.5 PC133-333-520
P-TSOP-54-2 (400mil)
133MHz 4B × 16M × 8 SDRAM
HYB 39S512800AT-8
PC100-222-620
P-TSOP-54-2 (400mil)
125MHz 4B × 16M × 8 SDRAM
HYB 39S512160AT-7
PC133-222-520
P-TSOP-54-2 (400mil)
143MHz 4B × 8M × 16 SDRAM
HYB 39S512160AT-7.5 PC133-333-520
P-TSOP-54-2 (400mil)
133MHz 4B × 8M × 16 SDRAM
HYB 39S512160AT-8
PC100-222-620
P-TSOP-54-2 (400mil)
125MHz 4B × 8M × 16 SDRAM
HYB 39S512xx0ATL
PC100-xxx-620
P-TSOP-54-2 (400mil)
Low Power Versions (on request)
Data Sheet
9
Rev. 1.3, 2004-03
10082003-L1GD-PVI5
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Pin Configuration
2
Pin Configuration
2.1
Signal Pin Description
Table 3
Signal Pin Description
Pin
Type
Signal Polarity Function
CLK
Input
Pulse
Positive Clock Input
Edge
The system clock input. All of the SDRAM inputs are sampled on the rising
edge of the clock.
CKE
Input
Level
Active
High
Clock Enable
Activates the CLK signal when high and deactivates the CLK signal when
low, thereby initiating either the Power Down mode, Suspend mode, or the
Self Refresh mode.
CS
Input
Pulse
Active
Low
Chip Select
CS enables the command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new
commands are ignored but previous operations continue.
RAS
CAS
WE
Input
Pulse
Active
Low
Command Signals
When sampled at the positive rising edge of the clock, CAS, RAS, and WE
define the command to be executed by the SDRAM.
A0 - A12
Input
Level
–
Address Inputs
During a Bank Activate command cycle, A0-A12 define the row address
(RA0-RA12) when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An define the column address
(CA0-CAn) when sampled at the rising clock edge. CAn depends upon the
SDRAM organization:
64M x4 SDRAM CAn = CA9, CA11 (Page Length = 2048 bits)
32M x8 SDRAM CAn = CA9 (Page Length = 1024 bits)
16M x16 SDRAM CAn = CA8 (Page Length = 512 bits)
In addition to the column address, A10 (= AP) is used to invoke the
autoprecharge operation at the end of the burst read or write cycle. If A10
is high, autoprecharge is selected and BA0, BA1 defines the bank to be
precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10 (= AP) is used in conjunction
with BA0 and BA1 to control which bank(s) to precharge. If A10 is high, all
four banks will be precharged regardless of the state of BA0 and BA1. If
A10 is low, then BA0 and BA1 are used to define which bank to precharge.
BA0, BA1 Input
Level
–
Bank Select
Bank Select Inputs. Bank address inputs selects which of the four banks a
command applies to.
Input Level
Output
–
Data Input/Output
Data Input/Output pins operate in the same manner as on EDO or FPM
DRAMs.
DQx
Data Sheet
10
Rev. 1.3, 2004-03
10082003-L1GD-PVI5
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Pin Configuration
Table 3
Signal Pin Description
Pin
Type
Signal Polarity Function
DQM
LDQM
UDQM
Input
Pulse
VDD VSS
Active
High
Data Mask
The Data Input/Output mask places the DQ buffers in a high impedance
state when sampled high. In Read mode, DQM has a latency of two clock
cycles and controls the output buffers like an output enable. In Write mode,
DQM has a latency of zero and operates as a word mask by allowing input
data to be written if it is low but blocks the write operation if DQM is high.
One DQM input is present in x4 and x8 SDRAMs, LDQM and UDQM
controls the lower and upper bytes in x16 SDRAMs.
Supply –
–
Power and Ground
Power and ground for the input buffers and the core logic (3.3 V)
VDDQ VSSQ Supply –
–
Power and Ground for DQs
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
NC
–
Not Connected
No internal electrical connection is present.
2.2
–
–
Package P-TSOPII-54
32M x 16
64M x 8
128M x 4
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VDD VDD
DQ0 NC
VDDQ VDDQ
NC
NC
DQ1 DQ0
VSSQ VSSQ
NC
NC
DQ2 NC
VDDQ VDDQ
NC
NC
DQ3 DQ1
VSSQ VSSQ
NC
NC
VDD VDD
NC
NC
WE
WE
CAS CAS
RAS RAS
CS
CS
BA0
BA0
BA1
BA1
A10/APA10/AP
A0
A0
A1
A1
A2
A2
A3
A3
VDD VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
VSS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
VSS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
TSOPII-54 (400 mil x 875 mil, 0.8 mm pitch)
Figure 1
Data Sheet
PinoutP-TSOPII-54
11
Rev. 1.3, 2004-03
10082003-L1GD-PVI5
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Pin Configuration
Block Diagrams
C o lu m n A d d re s s e s
A 0 - A 9 , A P ,,A 1 1 ,A 1 2
BA0, BA1
R o w A d d re s s e s
A0 - A12,
BA0, BA1
R ow
D ecoder
R ow
D ecoder
R ow
D ecoder
M em ory
A rray
M em ory
A rray
M em ory
A rra y
M em ory
A rra y
Bank 0
8192
x 4096
x 4 B it
In p u t B u ffe r
R o w A d d re s s
B u ffe r
Column Decoder
Sense amplifier & I(O) Bus
R ow
D ecoder
Column Decoder
Sense amplifier & I(O) Bus
C o lu m n A d d re s s
B u ffe r
Column Decoder
Sense amplifier & I(O) Bus
C o lu m n A d d re s s
C o u n te r
Bank 1
8192
x 4096
x 4 B it
R e fre s h C o u n te r
Column Decoder
Sense amplifier & I(O) Bus
2.3
Bank 2
8192
x 4096
x 4 B it
O u tp u t B u ffe r
Bank 3
8192
x 4096
x 4 B it
C o n tro l L o g ic &
T im in g G e n e ra to r
CLK
CKE
CS
RAS
CAS
WE
DQM
DQ0 - DQ3
Figure 2
Data Sheet
Block Diagram for 128M × 4 SDRAM ( 13 / 12 / 2 addressing)
12
Rev. 1.3, 2004-03
10082003-L1GD-PVI5
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Pin Configuration
C o lu m n A d d re s s e s
A 0 - A 9 , A P ,A 1 1
BA0, BA1
R o w A d d re s s e s
A0 - A12,
BA0, BA1
R ow
D ecoder
R ow
D ecoder
R ow
D ecoder
M em ory
A rray
M em ory
A rray
M em ory
A rra y
M em ory
A rra y
8192
x 2048
x 8 B it
In p u t B u ffe r
Bank 1
8192
x 2048
x 8 B it
Bank 2
8192
x 2048
x 8 B it
O u tp u t B u ffe r
R e fre s h C o u n te r
Column Decoder
Sense amplifier & I(O) Bus
Bank 0
R o w A d d re s s
B u ffe r
Column Decoder
Sense amplifier & I(O) Bus
R ow
D ecoder
Column Decoder
Sense amplifier & I(O) Bus
C o lu m n A d d re s s
B u ffe r
Column Decoder
Sense amplifier & I(O) Bus
C o lu m n A d d re s s
C o u n te r
Bank 3
8192
x 2048
x 8 B it
C o n tro l L o g ic &
T im in g G e n e ra to r
CLK
CKE
CS
RAS
CAS
WE
DQM
DQ0 - DQ7
Figure 3
Data Sheet
Block Diagram for 64M × 8 SDRAM ( 13 / 11 / 2 addressing)
13
Rev. 1.3, 2004-03
10082003-L1GD-PVI5
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Pin Configuration
A0 - A12,
BA 0, BA 1
C o lu m n A d d re s s
C o u n te r
C o lu m n A d d re s s
B u ffe r
R o w A d d re s s
B u ffe r
R ow
D ecoder
R ow
D ecoder
Bank 0
8192
x 1024
x 1 6 B it
In p u t B u ffe r
M em ory
A rra y
B ank 1
8192
x 1024
x 1 6 B it
M em ory
A rra y
B ank 2
8192
x 1024
x 1 6 B it
O u tp u t B u ffe r
R ow
D ecoder
Column Decoder
Sense amplifier & I(O) Bus
M em ory
A rra y
R e fre s h C o u n te r
R ow
D ecoder
Column Decoder
Sense amplifier & I(O) Bus
Column Decoder
Sense amplifier & I(O) Bus
R o w A d d re s s e s
A 0 - A 9 , A P,
BA 0, BA1
Column Decoder
Sense amplifier & I(O) Bus
C o lu m n A d d re s s e s
M em ory
A rray
Bank 3
x 1024
x 1 6 B it
C o n tro l L o g ic &
T im in g G e n e ra to r
CLK
CKE
CS
RAS
CAS
WE
DQMU
DQML
DQ 0 - DQ 15
Figure 4
Data Sheet
Block Diagram for 32M × 16 SDRAM ( 13 / 10 / 2 addressing)
14
Rev. 1.3, 2004-03
10082003-L1GD-PVI5
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Functional Description
3
Functional Description
3.1
Operation Definition
All SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive edge
of the clock. The following list shows the truth table for the operation commands.
Table 4
Truth Table: Operation Command
Operation
Devics State
CKE CKE DQM BA0
AP=
Addr CS
1)2)
n-11)2) n1)2) 1)2)
BA11)2) A101)2) 1)2)
RAS CAS WE
1)2)
1)2)
1)2)
Bank Active
Idle 3)
H
X
X
V
V
V
L
L
H
H
Bank Precharge
Any
H
X
X
V
L
X
L
L
H
L
Precharge All
Any
H
X
X
X
H
X
L
L
H
L
Active
3)
H
X
X
V
L
V
L
H
L
L
Write with Autoprecharge
Active
3)
H
X
X
V
H
V
L
H
L
L
Read
Active 3)
H
X
X
V
L
V
L
H
L
H
3)
H
X
X
V
H
V
L
H
L
H
Write
Read with Autoprecharge
Active
Mode Register Set
Idle
H
X
X
V
V
V
L
L
L
L
No Operation
Any
H
X
X
X
X
X
L
H
H
H
Burst Stop
Active
H
X
X
X
X
X
L
H
H
L
Device Deselect
Any
H
X
X
X
X
X
H
X
X
X
Auto Refresh
Idle
H
H
X
X
X
X
L
L
L
H
Self Refresh Entry
Idle
H
L
X
X
X
X
L
L
L
H
Self Refresh Exit
Idle
(Self Refr.)
L
H
X
X
X
X
H
X
X
X
L
H
H
X
Active
L
H
X
X
X
X
X
X
X
X
Power Down Entry Idle
(Precharge or active
standby)
Active 4)
H
X
X
X
H
L
X
X
X
X
L
H
H
H
Clock Suspend Exit
Active
L
H
X
X
X
X
X
X
X
X
Power Down Exit
Any
(Power Down)
L
H
X
X
X
X
H
X
X
X
L
H
H
L
Data Write/Output
Enable
Active
H
X
L
X
X
X
X
X
X
X
Data Write/Output
Disable
Active
H
X
H
X
X
X
X
X
X
X
Clock Suspend
Entry
1) V = Valid, x = Don’t Care, L = Low Level, H = High Level
2) CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are
provided.
3) This is the state of the banks designated by BA0, BA1 signals.
4) Power Down Mode can not be entered in a burst cycle. When this command asserted in the burst mode cycle device is in
clock suspend mode.
Data Sheet
15
Rev. 1.3, 2004-03
10082003-L1GD-PVI5
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Functional Description
3.2
Initialization
The default power on state of the mode register is supplier specific and may be undefined. The following power
on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a
conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner. During
power on, all VDD and VDDQ pins must be built up simultaneously to the specified voltage when the input signals
are held in the “NOP” state. The power on voltage must not exceed VDD + 0.3 V on any of the input pins or VDD
supplies. The CLK signal must be started at the same time. After power on, an initial pause of 200 µs is required
followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus
during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all
banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A
minimum of eight Auto Refresh cycles (CBR) are also required.These may be done before or after programming
the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes.
3.3
Mode Register Definition
The Mode register designates the operation mode at the read or write cycle. This register is divided into four fields.
First, a Burst Length Field which sets the length of the burst, Second, an Addressing Selection bit which programs
the column access sequence in a burst cycle (interleaved or sequential). Third, a CAS Latency Field to set the
access time at clock cycle. Fourth, an Operation mode field to differentiate between normal operation (Burst read
and burst Write) and a special Burst Read and Single Write mode. After the initial power up, the mode set
operation must be done before any activate command. Any content of the mode register can be altered by reexecuting the mode set command. All banks must be in precharged state and CKE must be high at least one clock
before the mode set operation. After the mode register is set, a Standby or NOP command is required. Low signals
of RAS, CAS, and WE at the positive edge of the clock activate the mode set operation. Address input data at this
timing defines parameters to be set as shown in the previous table.
Data Sheet
16
Rev. 1.3, 2004-03
10082003-L1GD-PVI5
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Functional Description
MR
Mode Register Definition
BA1
BA0
0
0
A12
A13
(BA[1:0] = 00B)
A11
A10
reg. addr
A9
A8
A7
A6
A5
A4
A3
A2
A1
MODE
CL
BT
BL
w
w
w
w
Field
Bits
Type
Description
BL
[2:0]
w
Burst Length
Number of sequential bits per DQ related to one read/write command
A0
Note: All other bit combinations are RESERVED
000
001
010
011
111
1
2
4
8
Full Page
BT
3
w
Burst Type
See Table 5 for internal address sequence of low order address bits.
0
Sequential
1
Interleaved
CL
[6:4]
w
CAS Latency
Number of full clocks from read command to first data valid window.
Note: All other bit combinations are RESERVED
010 2
011 3
Operating [13:7] w
Mode
Operating Mode
Note: All other bit combinations are RESERVED.
0
1
Data Sheet
burst read / burst write
burst read / single write
17
Rev. 1.3, 2004-03
10082003-L1GD-PVI5
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Functional Description
3.3.1
Burst Length
Table 5
Burst Length and Sequence
Burst Length
Starting Column Address
A2
A1
A0
Type = Sequential
Type = Interleaved
0
0-1
0–1
1
1–0
1–0
0
0
0–1–2–3
0–1–2–3
0
1
1–2–3–0
1–0–3–2
1
0
2–3–0–1
2–3–0–1
2
4
8
Full Page
Order of Accesses Within a Burst
1
1
3–0–1–2
3–2–1–0
0
0
0
0–1–2–3–4–5–6–7
0–1–2–3–4–5–6–7
0
0
1
1–2–3–4–5–6–7–0
1–0–3–2–5–4–7–6
0
1
0
2–3–4–5–6–7–0–1
2–3–0–1–6–7–4–5
0
1
1
3–4–5–6–7–0–1–2
3–2–1–0–7–6–5–4
1
0
0
4–5–6–7–0–1–2–3
4–5–6–7–0–1–2–3
1
0
1
5–6–7–0–1–2–3–4
5–4–7–6–1–0–3–2
1
1
0
6–7–0–1–2–3–4–5
6–7–4–5–2–3–0–1
1
1
1
7–0–1–2–3–4–5–6
7–6–5–4–3–2–1–0
n
n
n
Cn, Cn+1, Cn+2 ....
not supported
Note:
1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the
block.
3. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access within
the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps
within the block.
3.4
Commands
Refresh Mode
SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the CAS -before-RAS
refresh of conventional DRAMs. All banks must be precharged before applying any refresh mode. An on-chip
address counter increments the word and the bank addresses and no bank information is required for either
refresh mode.
The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are held high at a
positive clock transition. The mode restores word line after the refresh and no external precharge command is
necessary. A minimum tRC time is required between two automatic refreshes in a burst refresh mode. The same
rule applies to any access command after the automatic refresh operation.
The chip has an on-chip timer and the Self Refresh mode is available. The mode restores the word lines after RAS,
CAS, and CKE are low and WE is high at a positive clock transition. All external control signals including the clock
are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation. After the exit
command, at least one tRC delay is required prior to any access command.
Data Sheet
18
Rev. 1.3, 2004-03
10082003-L1GD-PVI5
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Functional Description
Auto Precharge
Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS timing accepts one
extra address, CA10, to determine whether the chip restores or not after the operation. If CA10 is high when a
Read Command is issued, the Read with Auto-Precharge function is initiated. If CA10 is high when a Write
Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically enters the
precharge operation a time delay equal to tWR (“write recovery time”) after the last data in.
A burst operation with Auto-Precharge may only be interrupted by a burst start to another bank. It must not be
interrupted by a precharge or a burst stop command.
Precharge Command
There is also a separate precharge command available. When RAS and WE are low and CAS is high at a clock
timing, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are used to define banks as
shown in the following list. The precharge command can be imposed one clock before the last data out for CAS
latency = 2 and two clocks before the last data out for CAS latency = 3. Writes require a time delay twr (“write
recovery time”) of 2 clocks minimum from the last data out to apply the precharge command.
Table 6
Bank Selection by Address Bits
A10
BA0
BA1
0
0
0
Bank 0
0
0
1
Bank 1
0
1
0
Bank 2
0
1
1
Bank 3
1
X
X
all Banks
Burst Termination
Once a burst read or write operation has been initiated, there are several methods in which to terminate the burst
operation prematurely. These methods include using another Read or Write Command to interrupt an existing
burst operation, use a Precharge Command to interrupt a burst cycle and close the active bank, or using the Burst
Stop Command to terminate the existing burst operation but leave the bank open for future Read or Write
Commands to the same page of the active bank. When interrupting a burst with another Read or Write Command
care must be taken to avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions
making it the easiest method to use when terminating a burst operation before it has been completed. If a Burst
Stop command is issued during a burst write operation, then any residual data from the burst write cycle will be
ignored. Data that is presented on the DQ pins before the Burst Stop Command is registered will be written to the
memory.
3.5
Operations
3.5.1
Read and write
When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle starts. According
to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the wordline
are set. A CAS cycle is triggered by setting RAS high and CAS low at a clock timing after a necessary delay, tRCD,
from the RAS timing. WE is used to define either a read (WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or write operations
are allowed at up to a 166 MHz data rate. The numbers of serial data bits are the burst length programmed at the
mode set operation, i.e., one of 1, 2, 4 and 8 and full page. Column addresses are segmented by the burst length
and serial data accesses are done within this boundary. The first column address to be accessed is supplied at
the CAS timing and the subsequent addresses are generated automatically by the programmed burst length and
its sequence. For example, in a burst length of 8 with interleave sequence, if the first address is ‘2’, then the rest
of the burst sequence is 3, 0, 1, 6, 7, 4, and 5.
Data Sheet
19
Rev. 1.3, 2004-03
10082003-L1GD-PVI5
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Functional Description
Full page burst operation is only possible using the sequential burst type and page length is a function of the I/O
organization and column addressing. Full page burst operation does not self terminate once the burst length has
been reached. In other words, unlike burst lengths of 2, 4 and 8, full page burst continues until it is terminated
using another command.
Similar to the page mode of conventional DRAMs, burst read or write accesses on any column address are
possible once the RAS cycle latches the sense amplifiers. The maximum tRAS or the refresh interval time limits the
number of random column accesses. A new burst access can be done even before the previous burst ends. The
interrupt operation at every clock cycle is supported. When the previous burst is interrupted, the remaining
addresses are overridden by the new address with the full burst length. An interrupt which accompanies an
operation change from a read to a write is possible by exploiting DQM to avoid bus contention.
When two or more banks are activated sequentially, interleaved bank read or write operations are possible. With
the programmed burst length, alternate access and precharge operations on two or more banks can realize fast
serial data access modes among many different pages. Once two or more banks are activated, column to column
interleave operation can be performed between different pages.
3.5.2
DQM Function
DQM has two functions for data I/O read and write operations. During reads, when it turns to “high“ at a clock
timing, data outputs are disabled and become high impedance after two clock delay (DQM Data Disable Latency
tDQZ). It also provides a data mask function for writes. When DQM is activated, the write operation at the next clock
is prohibited (DQM Write Mask Latency tDQW = zero clocks).
3.5.3
Suspend Mode
During normal access mode, CKE is held high enabling the clock. When CKE is low, it freezes the internal clock
and extends data read and write operations. One clock delay is required for mode entry and exit (Clock Suspend
Latency tCSL).
3.5.4
Power Down
In order to reduce standby power consumption, a power down mode is available. All banks must be precharged
and the necessary Precharge delay (tRP) must occur before the SDRAM can enter the Power Down mode. Once
the Power Down mode is initiated by holding CKE low, all of the receiver circuits except CLK and CKE are gated
off. The Power Down mode does not perform any refresh operations, therefore the device can’t remain in Power
Down mode longer than the Refresh period (tREF) of the device. Exit from this mode is performed by taking CKE
“high“. One clock delay is required for Power Down mode entry and exit.
Data Sheet
20
Rev. 1.3, 2004-03
10082003-L1GD-PVI5
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Electrical Characteristics
4
Electrical Characteristics
4.1
Operating Conditions
Table 7
Absolute Maximum Ratings
Parameter
Symbol
Values
Voltage on I/O pins relative to VSS
VIN, VOUT
VDD, VDDQ
Power supply voltage
Operating Temperature
TA
Storage temperature range
TSTG
Power dissipation per SDRAM component PD
Data out current (short circuit)
IOUT
Unit
min.
max.
–1.0
+4.6
V
–1.0
+4.6
V
0
+70
°C
–55
+150
°C
–
1
W
–
50
mA
Note/ Test Condition
Attention: Stresses above those listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Maximum ratings are absolute ratings; exceeding only one of these values may cause
irreversible damage to the integrated circuit.
Table 8
Input and Output Capacitances1)
Values2)
Parameter
Symbol
min.
max.
Input Capacitance: CK, CK
CI1
CI2
2.5
3.5
pF
2.5
3.8
pF
CI0
4.0
6.0
pF
Input capacitance
(A0-A12, BA0,BA1,RAS, CAS, WE, CS, CKE, DQM)
Input / Output capacitance (DQ)
Unit
1) TA = 0 to 70 °C; VDD, VDDQ = 3.3 V ± 0.3 V, f = 1 MHz
2) Capacitance values are shown for TSOP-54 packages. Capacitance values for TFBGA packages are lower by 0.5 pF
Data Sheet
21
Rev. 1.3, 2004-03
10082003-L1GD-PVI5
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Electrical Characteristics
Table 9
DC Characteristics1)
Parameter
Symbol
Supply Voltage
I/O Supply Voltage
Input high voltage
Input low voltage
Output high voltage (IOUT = –4.0 mA)
Output low voltage (IOUT = 4.0 mA)
Input leakage current, any input
(0 V < VIN < VDD, all other inputs = 0 V)
Output leakage current
(DQs are disabled, 0 V < VOUT < VDDQ)
Values
min.
max.
Unit Note/
Test Condition
VDD
VDDQ
VIH
VIL
VOH
VOL
IIL
3.0
3.6
V
2)
3.0
3.6
V
2)
2.0
VDDQ+0.3
V
2)3)
–0.3
0.8
V
2)3)
2.4
–
V
2)
–
0.4
V
2)
–5
5
µA
IOL
−5
5
µA
1) TA = 0 to 70 °C
2) All voltages are referenced to Vss
3) VIH may overshoot to VDDQ + 2.0 V for pulse width of < 4ns with 3.3 V. VIL may undershoot to -2.0 V for pulse width < 4.0
ns with 3.3 V. Pulse width measured at 50% points with amplitude measured peak to DC reference.
Table 10
IDD Conditions
Parameter
Symbol
Operating Current
Single bank, burst length 4
IO = 0 mA
IDD1
Precharge Standby Current in Power Down Mode
CS = VIH,min; CKE ≤ VIL,max
IDD2P
Precharge Standby Current in Non-Power Down Mode
CS = VIH(min.) , CKE ≥ VIH(min.)
IDD2N
Active Power-Down Standby Current
one bank active state(max. 4 banks) CS = VIH(min.) ,CKE ≥ VIH(min.)
IDD3N
Active Standby Current
one bank active state (max. 4 banks) CS = VIH(min.), CKE ≤ VIL(max.)
IDD3P
Burst Operating Current
Read command cycling
IDD4
Auto Refresh Current
Auto Refresh command cyclingtRFC = tRFC(min.)
IDD5
Self Refresh Current
Self Refresh Mode, CKE=0.2V, tCK = infinity ×16
IDD6
Data Sheet
22
Rev. 1.3, 2004-03
10082003-L1GD-PVI5
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Electrical Characteristics
Table 11
Symbol
IDD1
IDD2P
IDD2N
IDD3N
IDD3P
IDD4
IDD5
IDD6
1)
IDD Specifications
–7
–7.5
–8
Unit
Note/Test
Condition 1)
Typ.
Max.
Typ.
Max.
Typ.
Max.
131
145
123
145
95
110
mA
2) 3)
0.6
3
0.6
3
0.6
3
mA
2)
25
31
23
31
19
25
mA
2)
27
35
26
35
21
30
mA
2)
2
4
2
4
2
4
mA
2)
102
123
97
123
79
100
mA
2) 3)
270
300
255
300
240
270
mA
tRFC = tRFC(min.) 4)
2.1
4
2.1
4
2.1
4
mA
Standard
TA = 0 to 70 °C; VSS = 0 V, VDD, VDDQ = +3.3 V ± 0.3 V
2) These parameters depend on the cycle rate. All values are measured at 133 MHz for “-7” and “-7.5” and at 100 MHz for
“-8” components with the outputs open. Input signals are changed once during tck.
3) These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3 and BL=4 is
assumed and the VDDQ current is excluded.
4) tRFC = tRFC(min.) “burst refresh”.
Data Sheet
23
Rev. 1.3, 2004-03
10082003-L1GD-PVI5
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Electrical Characteristics
4.2
AC Characteristics
Table 12
AC Characteristics1)2)3)
Parameter
Symbol
–7
–7.5
–8
Unit
PC133-222
PC133-333
PC100-222
min.
max.
min.
max.
min.
max.
Notes
Clock and Clock Enable
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
tCK
7
7.5
–
–
7.5
10
–
–
8
10
–
–
ns
ns
Clock Frequency
CAS Latency = 3
CAS Latency = 2
tCK
–
–
143
133
–
–
133
100
–
–
125
100
MHz
MHz
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
tAC
–
–
5.4
5.4
–
–
5.4
6
–
–
6
6
ns
ns
Clock High Pulse Width
tCH
tCL
tT
2.5
–
2.5
–
3
–
ns
2.5
–
2.5
–
3
–
ns
0.3
1.2
0.3
1.2
0.5
10
ns
tIS
tIH
tCK
tCKH
tRSC
1.5
–
1.5
–
2
–
ns
6)
0.8
–
0.8
–
1
–
ns
6)
1.5
–
1.5
–
2
–
ns
6)
0.8
–
0.8
–
1
–
ns
6)
2
–
2
–
2
–
CLK
tSB
0
7
0
7.5
0
8
ns
tRCD
tRP
tRAS
tRC
tRFC
15
–
20
–
20
–
ns
7)
15
–
20
–
20
–
ns
7)
37
100k
45
100k
48
100k
ns
7)
60
–
67
–
70
–
ns
7)
Activate(a) to Activate(b)
Command period
tRRD
14
–
15
–
16
–
ns
CAS(a) to CAS(b) Command
period
tCCD
1
–
1
–
1
–
CLK
tREF
tSREX
–
64
–
64
–
64
ms
1
–
1
–
1
Clock Low Pulse Width
Transition time
3)4)5)
Setup and Hold Times
Input Setup Time
Input Hold Time
CKE Setup Time
CKE Hold Time
Mode Register Set-up to Active
delay
Power Down Mode Entry Time
Common Parameters
Row to Column Delay Time
Row Precharge Time
Row Active Time
Row Cycle Time
Row Cycle Time during Auto
Refresh
63
67
70
ns
7)
Refresh Cycle
Refresh Period (8192 cycles)
Self Refresh Exit Time
Data Sheet
24
CLK
Rev. 1.3, 2004-03
10082003-L1GD-PVI5
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Electrical Characteristics
Table 12
AC Characteristics1)2)3)
Parameter
Symbol
–7
–7.5
–8
Unit
Notes
3)6)
PC133-222
PC133-333
PC100-222
min.
max.
min.
max.
min.
max.
tOH
tLZ
3
–
3
–
3
–
ns
1
–
1
–
0
–
ns
Data Out to High Impedance
Time
tHZ
3
7
3
7
3
8
ns
DQM Data Out Disable Latency
tDQZ
–
2
–
2
–
2
CLK
tWR
14
–
15
–
16
–
ns
8)
CLK
9)
Read Cycle
Data Out Hold Time
Data Out to Low Impedance
Time
Write Cycle
Last Data Input to Precharge
(Write without AutoPrecharge)
Last Data Input to Activate (Write tDAL(min.)
with Auto Precharge)
DQM Write Mask Latency
1)
tDQW
(tWR/tCK) + (tRP/tCK)
0
–
0
–
0
–
CLK
TA = 0 to 70 C; VSS = 0 V, VDD, VDDQ = 3.3 V ± 0.3 V, tT = 1 ns
2) For proper power-up see the operation section of this data sheet.
3) AC timing tests for LV-TTL versions have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between VIH and VIL. All AC measurements assume TT = 1 ns with the AC output
load circuit shown in figure below. Specified tac and toh parameters are measured with a 50 pF only, without any resistive
termination and with an input signal of 1V / ns edge rate between 0.8 V and 2.0 V.
4) If clock rising time is longer than 1 ns, a time (TT/2 - 0.5) ns has to be added to this parameter.
5) if TT is longer than 1 ns, a time (TT - 1) ns has to be added to this parameter.
6) Access time from clock tac is 4.6 ns for PC133 components with no termination and 0 pF load, Data out hold time toh is
1.8 ns for PC133 components with no termination and 0 pF load.
7) This parameter determines the minimum required number of clock cycles as follows: the required number of clock cycles
is given by the value of the specified parameter divided by the period of the clock. Non-integer values must be rounded up
to the next greater integer value.
8) It is recommended to use two clock cycles between the last data-in and the precharge command in case of a write
command without Auto-Precharge. One clock cycle between the last data-in and the precharge command is also
supported, but restricted to cycle times tck greater or equal the specified tWR value, where tCK is equal to the actual system
clock time.
9) When a Write command with AutoPrecharge has been issued, a time of tDAL(min.) has be fullfilled before the next Activate
Command can be applied. For each of the terms, if not already an integer, round up to the next highest integer. tck is equal
to the actual system clock time.
Data Sheet
25
Rev. 1.3, 2004-03
10082003-L1GD-PVI5
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Electrical Characteristics
t CH
2 .4 V
0 .4 V
1 .4 V
C LOC K
tCL
t IS
tT
t IH
1 .4 V
IN P U T
tA C
t LZ
tAC
t OH
OUTPUT
1 .4 V
I/O
50 pF
t HZ
Measurement conditions for
tAC and tOH
IO.vsd
Figure 5
Data Sheet
Measurement conditions for tAC and tOH
26
Rev. 1.3, 2004-03
10082003-L1GD-PVI5
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Package Outlines
5
Package Outlines
Plastic Package P-TSOPII-54
(400 mil, 0.8 mm lead pitch)
0.8
15˚±5˚
26x 0.8 = 20.8
3)
0.35 +0.1
-0.05
0.1 54x
0.5 ±0.1
11.76 ±0.2
0.2 M 54x
28
6 max
54
10.16 ±0.13 2)
0.15 +0.06
-0.03
1±0.05
15˚±5˚
0.1±0.05
Thin Small Outline Package, SMD
1
27
2.5 max
22.22 ±0.13
1)
GPX09039
Index Marking
1)
Does not include plastic or metal protrusion of 0.15 max per side
Does not include plastic protrusion of 0.25 max per side
3)
Does not include dambar protrusion of 0.13 max per side
2)
Figure 6
Data Sheet
Package Outlines P-TSOPII-54
27
Rev. 1.3, 2004-03
10082003-L1GD-PVI5
http://www.infineon.com
Published by Infineon Technologies AG