8Mx64 bits PC100 SDRAM Unbuffered DIMM based on 8Mx16 SDRAM with LVTTL, 4 banks & 4K Refresh HYM71V65801 X-Series DESCRIPTION The Hyundai HYM71V65801 X-Series are 8Mx64bits Synchronous DRAM Modules. The modules are composed of four 8Mx16bit CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 168pin glass-epoxy printed circuit board. Two 0.22uF and one 0.0022uF decoupling capacitors per each SDRAM are mounted on the PCB. The HYM71V65801 X-Series are Dual In-line Memory Modules suitable for easy interchange and addition of 64Mbytes memory. The HYM71V65801 X-Series are offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. FEATURES • PC100MHz support • SDRAM internal banks : four banks • 168pin SDRAM Unbuffered DIMM • Module bank : one physical bank • Serial Presence Detect with EEPROM • Auto refresh and self refresh • 1.375” (34.93mm) Height PCB with Single Sided components • 4096 refresh cycles / 64ms • Single 3.3 ± 0.3V power supply • All devices pins are compatible with LVTTL interface • Data mask function by DQM • Programmable Burst Length and Burst Type -. 1, 2, 4, 8 or Full Page for Sequential Burst -. 1, 2, 4 or 8 for Interleave Burst • Programmable /CAS Latency -. 2, 3 Clocks ORDERING INFORMATION PART NO. MAX. FREQUENCY HYM71V65801TX-8 125MHz HYM71V65801TX-10P 100MHz HYM71V65801TX-10S 100MHz INTERNAL BANK REF. POWER SDRAM PACKAGE PLATING 4 Banks 4K Normal TSOP-II Gold This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1/Dec.99 1999 Hyundai MicroElectronics PC100 SDRAM Unbuffered DIMM HYM71V65801 X-Series PIN DESCRIPTION PIN NAME DESCRIPTION CK0~CK3 Clock Inputs The System Clock Input. All other inputs are registered to the SDRAM on the rising edge of CLK. CKE0 Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh. /S0, /S2 Chip Select Enables or disables all inputs except CK, CKE and DQM. BA0, BA1 SDRAM Bank Address A0~A11 Address Inputs /RAS Row Address Strobe /CAS Column Address Strobe /WE Write Enable DQM0~DQM7 Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode. DQ0~DQ63 Data Input/Output Multiplexed data input/output pins VCC Power Supply (3.3V) Power supply for internal circuits and input/output buffers VSS Ground Ground SCL SPD Clock Input Serial Presence Detect Clock Input SDA SPD Data Input/Output Serial Presence Detect Data input/output SA0~SA2 SPD Address Input Serial Presence Detect Address input WP Write Protect for SPD Write Protect for Serial Presence Detect on DIMM NC No Connect No Connect or Don’ t Use Rev. 1.1/Dec.99 Select bank to be activated during /RAS activity. Select bank to be read/written during /CAS activity Row address : RA0~RA11, Column address : CA0~CA8 Auto-precharge flag : A10 /RAS define the operation. Refer to the function truth table for details. /CAS define the operation. Refer to the function truth table for details. /WE define the operation. Refer to the function truth table for details. 2 PC100 SDRAM Unbuffered DIMM HYM71V65801 X-Series PIN ASSIGNMENTS FRONT SIDE BACK SIDE FRONT SIDE BACK SIDE PIN NO. NAME PIN NO. NAME PIN NO. NAME PIN NO. NAME 1 VSS 85 VSS 41 VCC 125 *CK1 2 DQ0 86 DQ32 42 CK0 126 NC 3 DQ1 87 DQ33 43 VSS 127 VSS 4 DQ2 88 DQ34 44 NC 128 CKE0 5 DQ3 89 DQ35 45 /S2 129 NC 6 7 VCC DQ4 90 91 VCC DQ36 46 47 DQM2 DQM3 130 131 DQM6 DQM7 8 DQ5 92 DQ37 48 NC 132 NC 9 DQ6 93 DQ38 49 VCC 133 VCC 10 DQ7 94 DQ39 50 51 NC NC 134 135 NC NC NC Architecture Key 52 NC 136 11 DQ8 95 DQ40 53 NC 137 NC 12 VSS 96 VSS 54 VSS 138 VSS 13 14 DQ9 DQ10 97 98 DQ41 DQ42 55 56 DQ16 DQ17 139 140 DQ48 DQ49 15 DQ11 99 DQ43 57 DQ18 141 DQ50 16 DQ12 100 DQ44 58 DQ19 142 DQ51 17 DQ13 101 DQ45 59 VCC 143 VCC 18 19 VCC DQ14 102 103 VCC DQ46 60 61 DQ20 NC 144 145 DQ52 NC 20 DQ15 104 DQ47 62 NC 146 NC 21 NC 105 NC 63 NC 147 NC 22 23 NC VSS 106 107 NC VSS 64 65 VSS DQ21 148 149 VSS DQ53 24 NC 108 NC 66 DQ22 150 DQ54 25 NC 109 NC 67 DQ23 151 DQ55 26 VCC 110 VCC 68 VSS 152 VSS 27 28 /WE DQM0 111 112 /CAS DQM4 69 70 DQ24 DQ25 153 154 DQ56 DQ57 29 DQM1 113 DQM5 71 DQ26 155 DQ58 30 /S0 114 NC 72 DQ27 156 DQ59 31 NC 115 /RAS 73 VCC 157 VCC 32 33 VSS A0 116 117 VSS A1 74 75 DQ28 DQ29 158 159 DQ60 DQ61 34 A2 118 A3 76 DQ30 160 DQ62 35 A4 119 A5 77 DQ31 161 DQ63 36 A6 120 A7 78 VSS 162 VSS 37 38 A8 A10/AP 121 122 A9 BA0 79 80 CK2 NC 163 164 *CK3 NC 39 BA1 123 A11 81 WP 165 SA0 40 VCC 124 VCC 82 SDA 166 SA1 83 84 SCL VCC 167 168 SA2 VCC Voltage Key Note : *. CK1, CK3 are connected with termination R/C. (Refer to the Block Diagram.) Rev. 1.1/Dec.99 3 PC100 SDRAM Unbuffered DIMM HYM71V65801 X-Series BLOCK DIAGRAM Note : 1. The serial resistor values of DQs are 10 Ohms. 2. The padding capacitance of termination R/C for CK1, CK3 is 10pF. Rev. 1.1/Dec.99 4 PC100 SDRAM Unbuffered DIMM HYM71V65801 X-Series SERIAL PRESENCE DETECT BYTE FUNCTION NUMBER DESCRIBED FUNCTION -8 -10P VALUE -10S -8 -10P BYTE0 # of Bytes Written into Serial Memory at Module Manufacturer 128 Bytes 80h BYTE1 Total # of Bytes of SPD Memory Device 256 Bytes 08h BYTE2 Fundamental Memory Type BYTE3 -10S SDRAM 04h # of Row Addresses on This Assembly 12 0Ch BYTE4 # of Column Addresses on This Assembly 9 09h BYTE5 # of Module Banks on This Assembly 1 Banks 01h BYTE6 Data Width of This Assembly 64 Bits 40h BYTE7 Data Width of This Assembly (Continued) - 00h BYTE8 Voltage Interface Standard of This Assembly BYTE9 SDRAM Cycle Time @ /CAS Latency=3 8ns 10ns 10ns 80h A0h A0h BYTE10 Access Time from Clock @ /CAS Latency=3 6ns 6ns 6ns 60h 60h 60h BYTE11 DIMM Configuration Type BYTE12 Refresh Rate/Type BYTE13 Primary SDRAM Width BYTE14 Error Checking SDRAM Width BYTE15 Minimum Clock Delay Back to Back Random Column Address BYTE16 Burst Lengths Supported BYTE17 # of Banks on Each SDRAM Device BYTE18 SDRAM Device Attributes, CAS # Latency BYTE19 SDRAM Device Attributes, CS # Latency BYTE20 SDRAM Device Attributes, Write Latency BYTE21 SDRAM Module Attributes LVTTL 1 01h None 00h 15.625µs / Self Refresh Supported 80h x16 10h None 00h tCCD = 1 CLK 01h 1,2,4,8,Full Page 8Fh 4 Banks 04h /CAS Latency=2,3 06h /CS Latency=0 01h /WE Latency=0 01h Neither Buffered nor Registered 00h +/-10% voltage tolerance, Burst Read Single bit Write, Precharge All, Auto Precharge, Early RAS Precharge 0Eh 2 BYTE22 SDRAM Device Attributes, General BYTE23 SDRAM Cycle Time @ /CAS Latency=2 10ns 10ns 12ns A0h A0h C0h BYTE24 Access Time from Clock @ /CAS Latency=2 6ns 6ns 6ns 60h 60h 60h BYTE25 SDRAM Cycle Time @ /CAS Latency=1 - - - 00h 00h 00h BYTE26 Access Time from Clock @ /CAS Latency=1 - - - 00h 00h 00h BYTE27 Minimum Row Precharge Time (tRP) 20ns 20ns 20ns 14h 14h 14h BYTE28 Minimum Row Active to Row Active Delay (tRRD) 16ns 20ns 20ns 10h 14h 14h BYTE29 Minimum /RAS to /CAS Delay (tRCD) 20ns 20ns 20ns 14h 14h 14h BYTE30 Minimum /RAS Pulse width (tRAS) 48ns 50ns 50ns 30h 32h 32h BYTE31 Module Bank Density BYTE32 Command and Address Signal Input Setup Time 2ns 2ns 2ns 20h 20h 20h BYTE33 Command and Address Signal Input Hold Time 1ns 1ns 1ns 10h 10h 10h BYTE34 Data Signal Input Setup Time 2ns 2ns 2ns 20h 20h 20h BYTE35 Data Signal Input Hold Time 1ns 1ns 1ns 10h 10h 10h BYTE36 –61 Superset Information (may be used in future) BYTE62 SPD Revision BYTE63 Checksum for Bytes 0~62 BYTE64 Manufacturer JEDEC ID Code BYTE65 ~71 ....Manufacturer JEDEC ID Code BYTE72 Manufacturing Location Rev. 1.1/Dec.99 64MB 10h - 00h Intel SPD 1.2A - 12h E7h 0Dh Hyundai JEDEC ID ADh Unused FFh HEI (Korea) HEA (United States) HEU (Europe) NOTE 3, 8 2Dh 01h 02h 03h 5 PC100 SDRAM Unbuffered DIMM HYM71V65801 X-Series Continued BYTE FUNCTION NUMBER DESCRIBED BYTE73 Manufacturer’ s Part Number (Component) BYTE74 Manufacturer’ s Part Number (128Mb based) BYTE75 Manufacturer’ s Part Number (Voltage Interface) BYTE76 FUNCTION -8 -10P VALUE -10S -8 -10P -10S NOTE 7 (SDRAM) 37h 4, 5 1 31h 4, 5 V (3.3V, LVTTL) 56h 4, 5 Manufacturer’ s Part Number (Data Width) 6 36h 4, 5 BYTE77 ....Manufacturer’ s Part Number (Data Width) 5 35h 4, 5 BYTE78 Manufacturer’ s Part Number (Memory Depth) 8 38h 4, 5 BYTE79 Manufacturer’ s Part Number (Refresh) 0 (4K Refresh) 30h 4, 5 BYTE80 Manufacturer’ s Part Number (Internal Banks) 1 (4 Banks) 31h 4, 5 BYTE81 Manufacturer’ s Part Number (Package Type) T (TSOPII) 54h 4, 5 BYTE82 Manufacturer’ s Part Number (Module Type) X (x16 based) 58h 4, 5 BYTE83 Manufacturer’ s Part Number (Hyphen) - (Hyphen) 2Dh BYTE84 Manufacturer’ s Part Number (Min. Cycle Time) BYTE85 ....Manufacturer’ s Part Number (Min. Cycle Time) Blank BYTE86 ....Manufacturer’ s Part Number (Min. Cycle Time) Blank BYTE87 ~90 Manufacturer’ s Part Number BYTE91 BYTE92 BYTE93 Manufacturing Date BYTE94 ....Manufacturing Date BYTE95 ~98 Assembly Serial Number BYTE99 ~125 Manufacturer Specific Data (may be used in future) BYTE126 System Frequency Support BYTE127 Intel Specification Details for 100MHz Support BYTE128 ~256 Unused Storage Locations 8 1 4, 5 1 38h 31h 31h 4, 5 0 0 20h 30h 30h 4, 5 P S 20h 50h 53h 4, 5 Blanks 20h 4, 5 Revision Code (for Component) Process Code - 4, 6 ....Revision Code (for PCB) Process Code - 4, 6 Work Week - 3, 6 Year - 3, 6 Serial Number - 6 None 00h 100MHz Refer to Note7 - 64h A7h A7h 8 A5h 7, 8 00h Note: 1. The bank address is excluded. 2. 1,2,4,8 for Interleave Burst Type. 3. BCD adopted. 4. ASCII adopted. 5. Basically HYUNDAI writes Part No. except for ` HYM ` in Byte 73-90 to use the limited 18 bytes from byte 73 to 90 efficiently. 6. Not fixed but dependent. 7. CLK0, CLK2 connected on the DIMM, TBD junction temp, CL2(3) support, Intel defined Concurrent Auto Precharge support. 8. Refer to Intel SPD Specification Rev.1.2A. Rev. 1.1/Dec.99 6 PC100 SDRAM Unbuffered DIMM HYM71V65801 X-Series ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT 0 ~ 70 °C Ambient Temperature TA Storage Temperature TSTG -55 ~ 125 °C Voltage on any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD relative to VSS VDD, VDDQ -1.0 ~ 4.6 V Short Circuit Output Current IOS 50 MA Power Dissipation PD 4 W Soldering Temperature · Time TSOLDER 260 · 10 °C · Sec Note : Operation at above absolute maximum can adversely affect device reliability. DC OPERATING CONDITION (TA = 0 to 70°C) PARAMETER SYMBOL MIN TYP. MAX UNIT NOTE Power Supply Voltage VCC 3.0 3.3 3.6 V 1 Input High Voltage VIH 2.0 3.0 VCC + 0.3 V 1, 2 Input Low Voltage VIL – 0.3 0 0.8 V 1, 3 Note : 1. All voltage are referenced to VSS = 0V. 2. VIH (max) is acceptable 5.6V AC pulse width with ≤ 3ns of duration. 3. VIL (min) is acceptable –2.0V AC pulse width with ≤ 3ns of duration. AC OPERATING CONDITION (TA = 0 to 70°C, VDD = 3.3 ± 0.3V, VSS = 0V) PARAMETER SYMBOL VALUE UNIT 2.4 / 0.4 V 1.4 V AC Input High / Low Level Voltage VIH / VIL Input Timing Measurement Reference Level Voltage Vtrip Input Rise / Fall Time tR / tF 1 ns Output Timing Measurement Reference Level Voltage Voutref 1.4 V Output Load Capacitance for Access Time Measurement CL *Note pF Note : *. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output circuit. Rev. 1.1/Dec.99 7 PC100 SDRAM Unbuffered DIMM HYM71V65801 X-Series CAPACITANCE (TA = 25°C, f = 1MHz) PARAMETER Input Capacitance Data Input/Output Capacitance PIN SYMBOL MIN MAX TYP. UNIT CK0, CK2 CIN1 15 45 - pF CKE0 CIN2 25 40 - pF /S0, /S2 CIN3 15 30 - pF A0~A11, BA0, BA1 CIN4 30 45 - pF /RAS, /CAS, /WE CIN5 30 45 - pF DQM0~DQM7 CIN6 5 20 - pF DQ0~DQ63 CI/O 5 20 - pF OUTPUT LOAD CIRCUIT Rev. 1.1/Dec.99 8 PC100 SDRAM Unbuffered DIMM HYM71V65801 X-Series DC CHARACTERISTICS I (TA = 0 to 70°C, VDD = 3.3 ± 0.3V) PARAMETER SYMBOL MIN MAX UNIT NOTE Input Leakage Current ILI -4 4 uA 1 Output Leakage Current ILO -1 1 uA 2 Output High Voltage VOH 2.4 - V IOH = -4mA Output Low Voltage VOL - 0.4 V IOL = +4mA Note : 1. VIN = 0 to 3.6V. All other pins are not tested under VIN = 0V. 2. DOUT is disabled. VOUT = 0 to 3.6V. DC CHARACTERISTICS II (TA = 0 to 70°C, VDD = 3.3 ± 0.3V, VSS = 0V) SPEED PARAMETER Operating Current Precharge Standby Current in Power Down Mode SYMBOL Operating -10P -10S 480 480 480 UNIT NOTE mA 1 Burst Length = 1, One bank active tRC ≥ tRC(min), IOL = 0mA IDD2P CKE ≤ VIL(max), tCK = min 8 mA IDD2PS CKE ≤ VIL(max), tCK = ∞ 6 mA IDD2N CKE ≥ VIH(min), /CS ≥ VIH(min), tCK = min Input signals are changed one time during 2clks. All other pins ≥ VDD – 0.2V or ≤ 0.2V 80 mA IDD2NS CKE ≥ VIH(max), tCK = ∞ Input signals are stable. 40 mA IDD3P CKE ≤ VIL(max), tCK = min 28 mA IDD3PS CKE ≤ VIL(max), tCK = ∞ 28 mA IDD3N CKE ≥ VIH(min), /CS ≥ VIH(min), tCK = min Input signals are changed one time during 2clks. All other pins ≥ VDD – 0.2V or ≤ 0.2V 160 mA IDD3NS CKE ≥ VIH(max), tCK = ∞ Input signals are stable. 160 mA Active Standby Current in Non Power Down Mode Burst Mode Current -8 IDD1 Precharge Standby Current in Non Power Down Mode Active Standby Current in Power Down Mode TEST CONDITION IDD4 tCK ≥ tCK(min), IOL = 0mA CL = 3 600 480 480 All banks active CL = 2 480 480 440 Auto Refresh Current IDD5 tRRC ≥ tRRC(min), All banks active Self Refresh Current IDD6 CKE ≤ 0.2V mA 1 1160 mA 2 8 mA Note : 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open. 2. Min. of tRRC (Refresh /RAS cycle time) is shown at AC CHARACTERISTICS II. Rev. 1.1/Dec.99 9 PC100 SDRAM Unbuffered DIMM HYM71V65801 X-Series AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) -8 PARAMETER /CAS Latency = 3 -10S SYMBOL UNIT MIN System Clock Cycle Time -10P tCK3 MAX 8 MIN MAX 10 1000 MIN NOTE MAX 10 1000 ns 3 - ns I - 3 - ns I - 6 - 6 ns 2 - 6 - 6 - 3 - 3 - ns 2 - 2 - 2 - ns 1 tDH 1 - 1 - 1 - ns 1 tAS 2 - 2 - 2 - ns 1 Address Hold Time tAH 1 - 1 - 1 - ns 1 CKE Setup Time tCKS 2 - 2 - 2 - ns 1 CKE Hold Time tCKH 1 - 1 - 1 - ns 1 Command Setup Time tCS 2 - 2 - 2 - ns 1 Command Hold Time tCH 1 - 1 - 1 - ns 1 CLK to Data Output in Low-Z time tOLZ 1 - 1 - 1 - ns /CAS Latency = 3 tOHZ3 3 6 3 6 3 6 /CAS Latency = 2 tOHZ2 3 6 3 6 3 6 tCK2 10 Clock High Pulse Width tCHW 3 - 3 - Clock Low Pulse Width tCLW 3 - 3 /CAS Latency = 3 tAC3 - 6 /CAS Latency = 2 tAC2 - 6 Data-Out Hold Time tOH 3 Data-Input Setup Time tDS Data-Input Hold Time Address Setup Time Access Time from Clock CLK to Data Output in High-Z time /CAS Latency = 2 1000 10 12 ns Note : 1. Assume tR / tF (input rise and fall time ) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter 2. Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter Rev. 1.1/Dec.99 10 PC100 SDRAM Unbuffered DIMM HYM71V65801 X-Series AC CHARACTERISTICS II -8 PARAMETER Cycle Operation -10S UNIT MIN /RAS Time -10P SYMBOL tRC MAX 68 MIN MAX 70 - MIN 70 - ns 20 - ns 100K 50 100K ns 20 - 20 - ns 20 - 20 - ns - 1 - 1 - CLK 0 - 0 - 0 - CLK tDPL 1 - 1 - 1 - CLK tDAL 4 - 3 - 3 - CLK DQM to Data-out Hi-Z tDQZ 2 - 2 - 2 - CLK DQM to Data-in Mask tDQM 0 - 0 - 0 - CLK MRS to New Command tMRD 2 - 2 - 2 - CLK Precharge to Data Output Hi-Z /CAS Latency = 3 tPROZ3 3 - 3 - 3 - /CAS Latency = 2 tPROZ2 2 - 2 - 2 - Power Down Exit Time tPDE 1 - 1 - 1 - CLK Self Refresh Exit Time tSRE 1 - 1 - 1 - CLK Refresh Time tREF - 64 - 64 - 64 ms Auto Refresh NOTE MAX - tRRC 68 70 70 /RAS to /CAS Delay tRCD 20 - 20 - /RAS Active Time tRAS 48 100K 50 /RAS Precharge Time tRP 20 - /RAS to /RAS Bank Active Delay tRRD 16 - /CAS to /CAS Delay tCCD 1 Write Command to Data-in Delay tWTL Data-in to Precharge Command Data-in to Active Command CLK 1 Note : 1. A new command can be given tRRC after self refresh exit. Rev. 1.1/Dec.99 11 PC100 SDRAM Unbuffered DIMM HYM71V65801 X-Series OPERATING OPTION TABLE HYM71V65801TX-8 /CAS LATENCY tRCD tRAS tRC tRP tAC tOH 125MHz (8.0ns) 3CLKS 3CLKS 6CLKS 9CLKS 3CLKS 6ns 3ns 100MHz (10.0ns) 2CLKS 2CLKS 5CLKS 7CLKS 2CLKS 6ns 3ns 83MHz (12.0ns) 2CLKS 2CLKS 4CLKS 6CLKS 2CLKS 6ns 3ns /CAS LATENCY tRCD tRAS tRC tRP tAC tOH 100MHz (10.0ns) 2CLKS 2CLKS 5CLKS 7CLKS 2CLKS 6ns 3ns 83MHz (12.0ns) 2CLKS 2CLKS 5CLKS 7CLKS 2CLKS 6ns 3ns 66MHz (15.0ns) 2CLKS 2CLKS 4CLKS 6CLKS 2CLKS 6ns 3ns /CAS LATENCY tRCD tRAS tRC tRP tAC tOH 100MHz (10.0ns) 3CLKS 2CLKS 5CLKS 7CLKS 2CLKS 6ns 3ns 83MHz (12.0ns) 2CLKS 2CLKS 5CLKS 7CLKS 2CLKS 6ns 3ns 66MHz (15.0ns) 2CLKS 2CLKS 4CLKS 6CLKS 2CLKS 6ns 3ns HYM71V65801TX-10P HYM71V65801TX-10S Rev. 1.1/Dec.99 12 PC100 SDRAM Unbuffered DIMM HYM71V65801 X-Series COMMAND TRUTH TABLE CKEn /CS /RAS /CAS /WE DQM Mode Register Set H X L L L L X OP code H X X X No Operation H X X X L H H H Bank Active H X L L H H X H X L H L H X ADDR A10/ AP CKEn-1 RA BA NOTE V Read L CA V Read with Autoprecharge H Write L H X L H L L X CA V Write with Autoprecharge H Precharge All Banks H X L L H L X Precharge Selected Bank Burst Stop H X DQM H Auto Refresh H H L L L Entry H L L L H X Exit L H H H H L X X V X H X X L H X X X X Self Refresh Entry L X L V X X L H H H H X X X L H H H H X X X L H H H H X X X L V V V L Precharge Power Down H X 1 X X Exit Entry L H H X L X Clock Suspend X Exit L H X X Note : 1. Existing Self Refresh occurs by asynchronously bringing CKE from low to high. 2. X = Don’ t care, H = Logic High, L = logic Low, BA = Bank Address, CA = Column Address, OP code = Operand code, NOP = No operation Rev. 1.1/Dec.99 13 PC100 SDRAM Unbuffered DIMM HYM71V65801 X-Series PACKAGE DIMENSIONS Rev. 1.1/Dec.99 14