INTERSIL ICL3245ECA

ICL3225E, ICL3227E, ICL3245E
®
Data Sheet
February 27, 2006
FN4900.9
±15kV ESD Protected, +3V to +5.5V,
1Microamp, 1Mbps, RS-232 Transceivers
with Enhanced Automatic Powerdown
Features
The Intersil ICL32XXE devices are 3.0V to 5.5V powered
RS-232 transmitters/receivers which meet ElA/TIA-232 and
V.28/V.24 specifications, even at VCC = 3.0V. Additionally,
they provide ±15kV ESD protection (IEC61000-4-2 Air Gap
and Human Body Model) on transmitter outputs and receiver
inputs (RS-232 pins). Targeted applications are PDAs,
Palmtops, and notebook and laptop computers where the
low operational, and even lower standby, power
consumption is critical. Efficient on-chip charge pumps,
coupled with manual and enhanced automatic powerdown
functions, reduce the standby supply current to a 1µA trickle.
Small footprint packaging, and the use of small, low value
capacitors ensure board space savings as well. Data rates
greater than 1Mbps are guaranteed at worst case load
conditions. This family is fully compatible with 3.3V only
systems, mixed 3.3V and 5.0V systems, and 5.0V only
systems.
• ESD Protection for RS-232 I/O Pins to ±15kV (IEC61000)
The ICL3245E is a 3 driver, 5 receiver device that provides a
complete serial port suitable for laptop or notebook
computers. It also includes a noninverting always-active
receiver for “wake-up” capability.
These devices, feature an enhanced automatic
powerdown function which powers down the on-chip powersupply and driver circuits. This occurs when all receiver and
transmitter inputs detect no signal transitions for a period of
30s. These devices power back up, automatically, whenever
they sense a transition on any transmitter or receiver input.
Table 1 summarizes the features of the device represented
by this data sheet, while Application Note AN9863
summarizes the features of each device comprising the
ICL32XXE 3V family.
• Pb-Free Plus Anneal Available (RoHS Compliant)
(see Ordering Info)
• Manual and Enhanced Automatic Powerdown Features
• Drop in Replacements for MAX3225E, MAX3227E,
MAX3245E
• RS-232 Compatible with VCC = 2.7V
• Meets EIA/TIA-232 and V.28/V.24 Specifications at 3V
• Latch-Up Free
• On-Chip Voltage Converters Require Only Four External
0.1µF Capacitors
• Guaranteed Mouse Driveability (ICL3245E)
• “Ready to Transmit” Indicator Output
(ICL3225E/ICL3227E)
• Receiver Hysteresis For Improved Noise Immunity
• Guaranteed Minimum Data Rate . . . . . . . . . . . . . . 1Mbps
• Low Skew at Transmitter/Receiver Input Trip Points . . . 10ns
• Guaranteed Minimum Slew Rate . . . . . . . . . . . . . . 24V/µs
• Wide Power Supply Range . . . . . . . Single +3V to +5.5V
• Low Supply Current in Powerdown State. . . . . . . . . . .1µA
Applications
• Any System Requiring RS-232 Communication Ports
- Battery Powered, Hand-Held, and Portable Equipment
- Laptop Computers, Notebooks, Palmtops
- Modems, Printers and Other Peripherals
- Digital Cameras
- Cellular/Mobile Phones
TABLE 1. SUMMARY OF FEATURES
PART NUMBER
NO. OF NO. OF
Tx.
Rx.
NO. OF
MONITOR Rx.
(ROUTB)
DATA
RATE
(kbps)
Rx. ENABLE
FUNCTION?
READY
OUTPUT?
MANUAL
POWERDOWN?
ENHANCED
AUTOMATIC
POWERDOWN
FUNCTION?
ICL3225E
2
2
0
1000
No
Yes
Yes
Yes
ICL3227E
1
1
0
1000
No
Yes
Yes
Yes
ICL3245E
3
5
1
1000
No
No
Yes
Yes
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2000, 2001, 2003-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ICL3225E, ICL3227E, ICL3245E
Ordering Information
Ordering Information
PART
MARKING
TEMP.
RANGE
(°C)
ICL3225ECA
ICL3225ECA
ICL3225ECAZ
(Note 1)
PART
MARKING
TEMP.
RANGE
(°C)
ICL3245ECBZ
(Note 1)
ICL3245ECBZ
0 to 70
28 Ld SOIC
(Pb-free)
ICL3245ECV
ICL3245ECV
0 to 70
28 Ld TSSOP M28.173
ICL3245ECVZ
(Note 1)
ICL3245ECVZ
0 to 70
28 Ld TSSOP M28.173
(Pb-free)
ICL3245EIA
ICL3245EIA
-40 to 85 28 Ld SSOP
M28.209
ICL3245EIAZ
(Note 1)
ICL3245EIAZ
-40 to 85 28 Ld SSOP
(Pb-free)
M28.209
ICL3245EIB
ICL3245EIB
-40 to 85 28 Ld SOIC
M28.3
PACKAGE
PKG.
DWG. #
PART NO. *
0 to 70
20 Ld SSOP
M20.209
ICL3225ECAZ
0 to 70
20 Ld SSOP
(Pb-free)
M20.209
ICL3225ECP
ICL3225ECP
0 to 70
20 Ld PDIP
E20.3
ICL3225ECPZ
(Note 1)
3225ECPZ
0 to 70
20 Ld PDIP**
(Pb-free)
E20.3
ICL3225EIA
ICL3225EIA
-40 to 85 20 Ld SSOP
M20.209
ICL3225EIAZ
(Note 1)
ICL3225EIAZ
-40 to 85 20 Ld SSOP
(Pb-free)
M20.209
ICL3227ECA
ICL3227ECA
PART NO. *
0 to 70
16 Ld SSOP
M16.209
0 to 70
16 Ld SSOP
(Pb-free)
M16.209
-40 to 85 16 Ld SSOP
M16.209
-40 to 85 16 Ld SSOP
(Pb-free)
M16.209
ICL3227ECAZA 3227ECAZ
(Note 1)
ICL3227EIA
ICL3227EIA
ICL3227EIAZA 3227EIAZ
(Note 1)
ICL3245ECA
ICL3245ECA
0 to 70
28 Ld SSOP
M28.209
ICL3245ECAZ
(Note 1)
ICL3245ECAZ
0 to 70
28 Ld SSOP
(Pb-Free)
M28.209
ICL3245ECB
ICL3245ECB
0 to 70
28 Ld SOIC
M28.3
(Continued)
PACKAGE
PKG.
DWG. #
M28.3
* Most surface mount devices are available on tape and reel; add “-T” to
suffix.
**Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
NOTE:
1. Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Pinouts
ICL3225E (PDIP, SSOP)
TOP VIEW
READY
20 FORCEOFF
1
ICL3227E (SSOP)
TOP VIEW
READY
1
16 FORCEOFF
C1+ 2
19 VCC
C1+ 2
15 VCC
3
18 GND
V+
3
14 GND
C1- 4
17 T1OUT
C1- 4
13 T1OUT
C2+ 5
16 R1IN
C2+ 5
12 FORCEON
C2- 6
15 R1OUT
C2- 6
11 T1IN
V+
V-
14 FORCEON
7
T2OUT 8
13 T1IN
R2IN 9
12 T2IN
V-
7
R1IN 8
10 INVALID
9 R1OUT
11 INVALID
R2OUT 10
2
FN4900.9
February 27, 2006
ICL3225E, ICL3227E, ICL3245E
Pinouts
(Continued)
ICL3245E (SOIC, SSOP, TSSOP)
TOP VIEW
C2+ 1
28 C1+
C2- 2
27 V+
3
26 VCC
R1IN 4
25 GND
R2IN 5
24 C1-
R3IN 6
23 FORCEON
R4IN 7
22 FORCEOFF
R5IN 8
21 INVALID
T1OUT 9
20 R2OUTB
T2OUT 10
19 R1OUT
T3OUT 11
18 R2OUT
T3IN 12
17 R3OUT
T2IN 13
16 R4OUT
T1IN 14
15 R5OUT
V-
Pin Descriptions
PIN
VCC
FUNCTION
System power supply input (3.0V to 5.5V).
V+
Internally generated positive transmitter supply (+5.5V).
V-
Internally generated negative transmitter supply (-5.5V).
GND
Ground connection.
C1+
External capacitor (voltage doubler) is connected to this lead.
C1-
External capacitor (voltage doubler) is connected to this lead.
C2+
External capacitor (voltage inverter) is connected to this lead.
C2-
External capacitor (voltage inverter) is connected to this lead.
TIN
TTL/CMOS compatible transmitter Inputs.
TOUT
RIN
ROUT
±15kV ESD Protected, RS-232 level (nominally ±5.5V) transmitter outputs.
±15kV ESD Protected, RS-232 compatible receiver inputs.
TTL/CMOS level receiver outputs.
ROUTB
TTL/CMOS level, noninverting, always enabled receiver outputs.
INVALID
Active low output that indicates if no valid RS-232 levels are present on any receiver input.
READY
Active high output that indicates when the ICL32XXE is ready to transmit (i.e., V- ≤ -4V).
FORCEOFF Active low to shut down transmitters and on-chip power supply. This overrides any automatic circuitry and FORCEON (see Table 2).
FORCEON
Active high input to override automatic powerdown circuitry thereby keeping transmitters active. (FORCEOFF must be high).
3
FN4900.9
February 27, 2006
ICL3225E, ICL3227E, ICL3245E
Typical Operating Circuits
ICL3225E
+3.3V
C1
0.1µF
C2
0.1µF
T1IN
T2IN
TTL/CMOS
LOGIC LEVELS
R1OUT
R2OUT
+
0.1µF
2
+
4
C1+
5
+
6
C2+
19
VCC
V+
V- 7
C2T1
13
17
T2
12
8
15
16
R1
5kΩ
R2
5kΩ
10
9
1
READY
14
3
C1-
FORCEOFF
INVALID
FORCEON
20
11
+ C3
0.1µF
C4
0.1µF
+
T1OUT
T2OUT
R1IN
RS-232
LEVELS
R2IN
VCC
TO POWER
CONTROL LOGIC
GND
18
ICL3227E
+3.3V
+
0.1µF
C1
0.1µF
C2
0.1µF
T1IN
TTL/CMOS
LOGIC LEVELS
R1OUT
2
+ C1+
4
C15
+ C2+
6
C2-
15
VCC
V+
V- 7
T1
11
13
9
8
READY
FORCEOFF
12
+ C3
0.1µF
C4
+ 0.1µF
T1OUT
R1IN
RS-232
LEVELS
5kΩ
R1
1
3
FORCEON
GND
INVALID
16
10
VCC
TO POWER
CONTROL LOGIC
14
4
FN4900.9
February 27, 2006
ICL3225E, ICL3227E, ICL3245E
Typical Operating Circuits
(Continued)
ICL3245E
+3.3V
+
26
0.1µF
28
C1
0.1µF
+
C2
0.1µF
+
24
1
2
C1+
VCC
27
+
V+
C1C2+
V-
3
C2T1
14
9
T1IN
T2
13
C3
0.1µF
C4
0.1µF
+
T1OUT
10
T2IN
T2OUT
T3
12
RS-232
LEVELS
11
T3IN
T3OUT
20
R2OUTB
TTL/CMOS
LOGIC LEVELS
19
4
R1OUT
R1IN
R1
5kΩ
18
5
R2OUT
R2IN
R2
5kΩ
17
6
R3OUT
R3IN
R3
5kΩ
16
RS-232
LEVELS
7
R4OUT
R4IN
R4
5kΩ
15
8
R5OUT
R5IN
5kΩ
R5
23
FORCEON
VCC
TO POWER
CONTROL LOGIC
22
FORCEOFF
21
INVALID
GND
25
5
FN4900.9
February 27, 2006
ICL3225E, ICL3227E, ICL3245E
Absolute Maximum Ratings
Thermal Information
VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V
Input Voltages
TIN, FORCEOFF, FORCEON. . . . . . . . . . . . . . . . . . . -0.3V to 6V
RIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V
Output Voltages
TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±13.2V
ROUT, INVALID, READY . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V
Short Circuit Duration
TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table
Thermal Resistance (Typical, Note 2)
θJA (°C/W)
20 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . .
80
28 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . .
75
16 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . .
145
20 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . .
135
28 Ld SSOP and TSSOP Packages . . . . . . . . . . . .
100
Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SOIC, SSOP, TSSOP - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
Operating Conditions
Temperature Range
ICL32XXEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
ICL32XXEI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified.
Typicals are at TA = 25°C
PARAMETER
TEST CONDITIONS
TEMP
(°C)
MIN
TYP
MAX
UNITS
25
-
1.0
10
µA
DC CHARACTERISTICS
Supply Current, Automatic
Powerdown
All RIN Open, FORCEON = GND, FORCEOFF = VCC
Supply Current, Powerdown
FORCEOFF = GND
25
-
1.0
10
µA
Supply Current,
Automatic Powerdown Disabled
All Outputs Unloaded, FORCEON = FORCEOFF = VCC
25
-
0.3
1.0
mA
LOGIC AND TRANSMITTER INPUTS AND RECEIVER OUTPUTS
Input Logic Threshold Low
TIN, FORCEON, FORCEOFF
Full
-
-
0.8
V
Input Logic Threshold High
TIN, FORCEON,
FORCEOFF
VCC = 3.3V
Full
2.0
-
-
V
VCC = 5.0V
Full
2.4
-
-
V
Input Leakage Current
TIN, FORCEON, FORCEOFF
Full
-
±0.01
±1.0
µA
Output Leakage Current
FORCEOFF = GND, ICL3245E Only
Full
-
±0.05
±10
µA
Output Voltage Low
IOUT = 1.6mA
Full
-
-
0.4
V
Output Voltage High
IOUT = -1.0mA
Full
-
V
VCC -0.6 VCC -0.1
RECEIVER INPUTS
Input Voltage Range
Full
-25
-
25
V
VCC = 3.3V
25
0.6
1.2
-
V
VCC = 5.0V
25
0.8
1.5
-
V
VCC = 3.3V
25
-
1.5
2.4
V
VCC = 5.0V
25
-
1.8
2.4
V
Input Hysteresis
25
-
0.5
-
V
Input Resistance
25
3
5
7
kΩ
Full
±5.0
±5.4
-
V
Input Threshold Low
Input Threshold High
TRANSMITTER OUTPUTS
Output Voltage Swing
All Transmitter Outputs Loaded with 3kΩ to Ground
6
FN4900.9
February 27, 2006
ICL3225E, ICL3227E, ICL3245E
Electrical Specifications
Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified.
Typicals are at TA = 25°C (Continued)
TEMP
(°C)
MIN
TYP
MAX
UNITS
Full
300
10M
-
Ω
Full
-
±35
±60
mA
VOUT = ±12V, VCC = 0V or 3V to 5.5V,
Automatic Powerdown or FORCEOFF = GND
Full
-
-
±25
µA
T1IN = T2IN = GND, T3IN = VCC, T3OUT Loaded with 3kΩ
to GND, T1OUT and T2OUT Loaded with 2.5mA Each
Full
±5
-
-
V
PARAMETER
TEST CONDITIONS
VCC = V+ = V- = 0V, Transmitter Output = ±2V
Output Resistance
Output Short-Circuit Current
Output Leakage Current
MOUSE DRIVEABILITY
Transmitter Output Voltage
(See Figure 11)
ENHANCED AUTOMATIC POWERDOWN (FORCEON = GND, FORCEOFF = VCC)
Receiver Input Thresholds to
INVALID High
See Figure 6
Full
-2.7
-
2.7
V
Receiver Input Thresholds to
INVALID Low
See Figure 6
Full
-0.3
-
0.3
V
INVALID, READY Output Voltage
Low
IOUT = 1.6mA
Full
-
-
0.4
V
INVALID, READY Output Voltage
High
IOUT = -1.0mA
Full
VCC-0.6
-
-
V
Receiver Positive or Negative
Threshold to INVALID High Delay
(tINVH)
25
-
1
-
µs
Receiver Positive or Negative
Threshold to INVALID Low Delay
(tINVL)
25
-
30
-
µs
Receiver or Transmitter Edge to
Transmitters Enabled Delay (tWU)
(Note 3)
25
-
100
-
µs
Receiver or Transmitter Edge to
Transmitters Disabled Delay
(tAUTOPWDN)
(Note 3)
Full
15
30
60
sec
RL = 3kΩ, One Transmitter CL = 1000pF
Switching
VCC = 3V to 4.5V, CL = 250pF
Full
250
-
-
kbps
Full
1000
-
-
kbps
Full
1000
-
-
kbps
Receiver Input to Receiver tPHL
Output, CL = 150pF
tPLH
25
-
0.15
-
µs
25
-
0.15
-
µs
Receiver Output Enable Time
Normal Operation (ICL3245E Only)
25
-
200
-
ns
Receiver Output Disable Time
Normal Operation (ICL3245E Only)
25
-
200
-
ns
Transmitter Skew
tPHL - tPLH (Note 4)
25
-
25
-
ns
Receiver Skew
tPHL - tPLH (Note 4)
25
-
50
-
ns
Transition Region Slew Rate
VCC = 3.3V, RL = 3kΩ to 7kΩ, Measured From 3V to -3V or
-3V to 3V, CL = 150pF to 1000pF
25
24
-
150
V/µs
Human Body Model
25
-
±15
-
kV
TIMING CHARACTERISTICS
Maximum Data Rate
VCC = 4.5V to 5.5V,
CL = 1000pF
Receiver Propagation Delay
ESD PERFORMANCE
RS-232 Pins (TOUT, RIN)
All Other Pins
IEC61000-4-2 Contact Discharge
25
-
±8
-
kV
IEC61000-4-2 Air Gap Discharge
25
-
±15
-
kV
Human Body Model
25
-
±3
-
kV
NOTES:
3. An “edge” is defined as a transition through the transmitter or receiver input thresholds.
4. Skews are measured at the receiver input switching points (1.4V).
7
FN4900.9
February 27, 2006
ICL3225E, ICL3227E, ICL3245E
Detailed Description
These ICL32XXE interface ICs operate from a single +3V to
+5.5V supply, guarantee a 1Mbps minimum data rate,
require only four small external 0.1µF capacitors, feature low
power consumption, and meet all ElA RS-232C and V.28
specifications. The circuit is divided into three sections: The
charge pump, the transmitters, and the receivers.
Charge-Pump
Intersil’s new ICL32XXE family utilizes regulated on-chip
dual charge pumps as voltage doublers, and voltage
inverters to generate ±5.5V transmitter supplies from a VCC
supply as low as 3.0V. This allows these devices to maintain
RS-232 compliant output levels over the ±10% tolerance
range of 3.3V powered systems. The efficient on-chip power
supplies require only four small, external 0.1µF capacitors
for the voltage doubler and inverter functions at VCC = 3.3V.
See the “Capacitor Selection” section, and Table 3 for
capacitor recommendations for other operating conditions.
The charge pumps operate discontinuously (i.e., they turn off
as soon as the V+ and V- supplies are pumped up to the
nominal values), resulting in significant power savings.
receivers’ Schmitt trigger input stage uses hysteresis to
increase noise immunity and decrease errors due to slow
input signal transitions.
The ICL3245E inverting receivers disable during forced
(manual) powerdown, but not during automatic powerdown
(see Table 2). Conversely, the monitor receiver remains
active even during manual powerdown making it extremely
useful for Ring Indicator monitoring. Standard receivers
driving powered down peripherals must be disabled to
prevent current flow through the peripheral’s protection
diodes (see Figures 2 and 3). This renders them useless for
wake up functions, but the corresponding monitor receiver
can be dedicated to this task as shown in Figure 3.
VCC
RXOUT
RXIN
-25V ≤ VRIN ≤ +25V
5kΩ
FIGURE 1. INVERTING RECEIVER CONNECTIONS
VCC
VCC
Transmitters
The transmitters are proprietary, low dropout, inverting
drivers that translate TTL/CMOS inputs to EIA/TIA-232
output levels. Coupled with the on-chip ±5.5V supplies,
these transmitters deliver true RS-232 levels over a wide
range of single supply system voltages.
Transmitter outputs disable and assume a high impedance
state when the device enters the powerdown mode (see
Table 2). These outputs may be driven to ±12V when
disabled.
All devices guarantee a 1Mbps data rate for full load
conditions (3kΩ and 250pF), VCC ≥ 3.0V, with one
transmitter operating at full speed. Under more typical
conditions of VCC ≥ 3.3V, RL = 3kΩ, and CL = 250pF, one
transmitter easily operates at 1.4Mbps. Transmitter skew is
extremely low on these devices, and is specified at the
receiver input trip points (1.4V), rather than the arbitrary 0V
crossing point typical of other RS-232 families.
Transmitter inputs float if left unconnected, and may cause
ICC increases. Connect unused inputs to GND for the best
performance.
GND ≤ VROUT ≤ VCC
GND
CURRENT
FLOW
VCC
VOUT = VCC
Rx
POWERED
DOWN
UART
Tx
SHDN = GND
GND
OLD
RS-232 CHIP
FIGURE 2. POWER DRAIN THROUGH POWERED DOWN
PERIPHERAL
VCC
TRANSITION
DETECTOR
TO
WAKE-UP
LOGIC
ICL3245E
VCC
Receivers
R2OUTB
All the ICL32XXE devices contain standard inverting
receivers, but only the ICL3245E receivers can tristate, via
the FORCEOFF control line. Additionally, the ICL3245E
includes a noninverting (monitor) receiver (denoted by the
ROUTB label) that is always active, regardless of the state of
any control lines. Both receiver types convert RS-232
signals to CMOS output levels and accept inputs up to ±25V
while presenting the required 3kΩ to 7kΩ input impedance
(see Figure 1) even if the power is off (VCC = 0V). The
8
RX
POWERED
DOWN
UART
VOUT = HI-Z
R2OUT
TX
R2IN
T1IN
T1OUT
FORCEOFF = GND
FIGURE 3. DISABLED RECEIVERS PREVENT POWER DRAIN
FN4900.9
February 27, 2006
ICL3225E, ICL3227E, ICL3245E
TABLE 2. POWERDOWN LOGIC TRUTH TABLE
RCVR OR
XMTR
EDGE
WITHIN 30
SEC?
(NOTE 5)
FORCEOFF FORCEON TRANSMITTER RECEIVER
ROUTB
INPUT
INPUT
OUTPUTS
OUTPUTS OUTPUTS
RS-232
LEVEL
PRESENT
AT
RECEIVER
INPUT?
INVALID
OUTPUT
MODE OF OPERATION
ICL3225E, ICL3227E
NO
H
H
Active
Active
N.A.
No
L
NO
H
H
Active
Active
N.A.
Yes
H
Normal Operation (Enhanced
Auto Powerdown Disabled)
YES
H
L
Active
Active
N.A.
No
L
YES
H
L
Active
Active
N.A.
Yes
H
NO
H
L
High-Z
Active
N.A.
No
L
NO
H
L
High-Z
Active
N.A.
Yes
H
Powerdown Due to Enhanced
Auto Powerdown Logic
X
L
X
High-Z
Active
N.A.
No
L
Manual Powerdown
X
L
X
High-Z
Active
N.A.
Yes
H
Normal Operation (Enhanced
Auto Powerdown Enabled)
ICL322XE - INVALID DRIVING FORCEON AND FORCEOFF (EMULATES AUTOMATIC POWERDOWN)
X
NOTE 6
NOTE 6
Active
Active
N.A.
Yes
H
Normal Operation
X
NOTE 6
NOTE 6
High-Z
Active
N.A.
No
L
Forced Auto Powerdown
H
H
Active
Active
Active
No
L
H
Normal Operation (Enhanced
Auto Powerdown Disabled)
ICL3245E
NO
NO
H
H
Active
Active
Active
Yes
YES
H
L
Active
Active
Active
No
L
YES
H
L
Active
Active
Active
Yes
H
NO
H
L
High-Z
Active
Active
No
L
NO
H
L
High-Z
Active
Active
Yes
H
Powerdown Due to Enhanced
Auto Powerdown Logic
X
L
X
High-Z
High-Z
Active
No
L
Manual Powerdown
X
L
X
High-Z
High-Z
Active
Yes
H
Normal Operation (Enhanced
Auto Powerdown Enabled)
ICL3245E - INVALID DRIVING FORCEON AND FORCEOFF (EMULATES AUTOMATIC POWERDOWN)
X
NOTE 6
NOTE 6
Active
Active
Active
Yes
H
Normal Operation
X
NOTE 6
NOTE 6
High-Z
High-Z
Active
No
L
Forced Auto Powerdown
NOTES:
5. Applies only to the ICL3245E.
6. Input is connected to INVALID Output.
Powerdown Functionality
This 3V family of RS-232 interface devices requires a
nominal supply current of 0.3mA during normal operation
(not in powerdown mode). This is considerably less than the
5mA to 11mA current required of 5V RS-232 devices. The
already low current requirement drops significantly when the
device enters powerdown mode. In powerdown, supply
current drops to 1µA, because the on-chip charge pump
turns off (V+ collapses to VCC, V- collapses to GND), and
the transmitter outputs tristate. Inverting receiver outputs
may or may not disable in powerdown; refer to Table 2 for
details. This micro-power mode makes these devices ideal
for battery powered and portable applications.
Software Controlled (Manual) Powerdown
These three devices allow the user to force the IC into the
low power, standby state, and utilize a two pin approach
where the FORCEON and FORCEOFF inputs determine the
9
IC’s mode. For always enabled operation, FORCEON and
FORCEOFF are both strapped high. To switch between
active and powerdown modes, under logic or software
control, only the FORCEOFF input need be driven. The
FORCEON state isn’t critical, as FORCEOFF dominates
over FORCEON. Nevertheless, if strictly manual control over
powerdown is desired, the user must strap FORCEON high
to disable the enhanced automatic powerdown circuitry.
ICL3245E inverting (standard) receiver outputs also disable
when the device is in powerdown, thereby eliminating the
possible current path through a shutdown peripheral’s input
protection diode (see Figures 2 and 3).
Connecting FORCEOFF and FORCEON together disables
the enhanced automatic powerdown feature, enabling them
to function as a manual SHUTDOWN input (see Figure 4).
With any of the above control schemes, the time required to
exit powerdown, and resume transmission is only 100µs.
FN4900.9
February 27, 2006
ICL3225E, ICL3227E, ICL3245E
by the internal receiver pull down resistors), the INVALID
logic detects the invalid levels and drives the output low. The
power management logic then uses this indicator to power
down the interface block. Reconnecting the cable restores
valid levels at the receiver inputs, INVALID switches high,
and the power management logic wakes up the interface
block. INVALID can also be used to indicate the DTR or
RING INDICATOR signal, as long as the other receiver
inputs are floating, or driven to GND (as in the case of a
powered down driver).
FORCEOFF
PWR
MGT
LOGIC
FORCEON
INVALID
ICL32XXE
I/O
UART
CPU
2.7V
VALID RS-232 LEVEL - INVALID = 1
INDETERMINATE
0.3V
INVALID LEVEL - INVALID = 0
FIGURE 4. CONNECTIONS FOR MANUAL POWERDOWN
WHEN NO VALID RECEIVER SIGNALS ARE
PRESENT
When using both manual and enhanced automatic
powerdown (FORCEON = 0), the ICL32XXE won’t power up
from manual powerdown until both FORCEOFF and
FORCEON are driven high, or until a transition occurs on a
receiver or transmitter input. Figure 5 illustrates a circuit for
ensuring that the ICL32XXE powers up as soon as
FORCEOFF switches high. The rising edge of the Master
Powerdown signal forces the device to power up, and the
ICL32XXE returns to enhanced automatic powerdown mode
an RC time constant after this rising edge. The time constant
isn’t critical, because the ICL32XXE remains powered up for
30 seconds after the FORCEON falling edge, even if there
are no signal transitions. This gives slow-to-wake systems
(e.g., a mouse) plenty of time to start transmitting, and as
long as it starts transmitting within 30 seconds both systems
remain enabled.
POWER
MANAGEMENT
UNIT
MASTER POWERDOWN LINE
0.1µF
FORCEOFF
1MΩ
FORCEON
-0.3V
INDETERMINATE
-2.7V
VALID RS-232 LEVEL - INVALID = 1
FIGURE 6. DEFINITION OF VALID RS-232 RECEIVER LEVELS
Enhanced Automatic Powerdown
Even greater power savings is available by using these devices
which feature an enhanced automatic powerdown function.
When the enhanced powerdown logic determines that no
transitions have occurred on any of the transmitter nor receiver
inputs for 30 seconds, the charge pump and transmitters
powerdown, thereby reducing supply current to 1µA. The
ICL32XXE automatically powers back up whenever it detects a
transition on one of these inputs. This automatic powerdown
feature provides additional system power savings without
changes to the existing operating system.
Enhanced automatic powerdown operates when the
FORCEON input is low, and the FORCEOFF input is high.
Tying FORCEON high disables automatic powerdown, but
manual powerdown is always available via the overriding
FORCEOFF input. Table 2 summarizes the enhanced
automatic powerdown functionality.
ICL32XXE
FORCEOFF
FIGURE 5. CIRCUIT TO ENSURE IMMEDIATE POWER UP
WHEN EXITING FORCED POWERDOWN
T_IN
EDGE
DETECT
S
INVALID Output
The INVALID output always indicates (see Table 2) whether
or not 30µs have elapsed with invalid RS-232 signals (see
Figures 6 and 8) persisting on all of the receiver inputs,
giving the user an easy way to determine when the interface
block should power down. Invalid receiver levels occur
whenever the driving peripheral’s outputs are shut off
(powered down) or when the RS-232 interface cable is
disconnected. In the case of a disconnected interface cable
where all the receiver inputs are floating (but pulled to GND
10
R_IN
30s
TIMER
EDGE
DETECT
AUTOSHDN
R
FORCEON
FIGURE 7. ENHANCED AUTOMATIC POWERDOWN LOGIC
Figure 7 illustrates the enhanced powerdown control logic.
Note that once the ICL32XXE enters powerdown (manually
or automatically), the 30 second timer remains timed out
FN4900.9
February 27, 2006
ICL3225E, ICL3227E, ICL3245E
(set), keeping the ICL32XXE powered down until FORCEON
transitions high, or until a transition occurs on a receiver or
transmitter input.
FORCEON
INVALID
ICL32XXE
The INVALID output signal switches low to indicate that
invalid levels have persisted on all of the receiver inputs for
more than 30µs (see Figure 8), but this has no direct effect
on the state of the ICL32XXE (see the next sections for
methods of utilizing INVALID to power down the device).
INVALID switches high 1µs after detecting a valid RS-232
level on a receiver input. INVALID operates in all modes
(forced or automatic powerdown, or forced on), so it is also
useful for systems employing manual powerdown circuitry.
The time to recover from automatic powerdown mode is
typically 100µs.
FORCEOFF
I/O
UART
CPU
FIGURE 8. CONNECTIONS FOR AUTOMATIC POWERDOWN
WHEN NO VALID RECEIVER SIGNALS ARE
PRESENT
Emulating Standard Automatic Powerdown
If enhanced automatic powerdown isn’t desired, the user can
implement the standard automatic powerdown feature (mimics
the function on the ICL3221E/ICL3223E/ICL3243E) by
connecting the INVALID output to the FORCEON and
FORCEOFF inputs, as shown in Figure 9. After 30µs of invalid
receiver levels, INVALID switches low and drives the
ICL32XXE into a forced powerdown condition. INVALID
switches high as soon as a receiver input senses a valid RS232 level, forcing the ICL32XXE to power on. See the “INVALID
DRIVING FORCEON AND FORCEOFF” section of Table 2 for
an operational summary. This operational mode is perfect for
handheld devices that communicate with another computer via
a detachable cable. Detaching the cable allows the internal
receiver pull-down resistors to pull the inputs to GND (an invalid
RS-232 level), causing the 30µs timer to time-out and drive the
IC into powerdown. Reconnecting the cable restores valid
levels, causing the IC to power back up.
Hybrid Automatic Powerdown Options
For devices which communicate only through a detachable
cable, connecting INVALID to FORCEOFF (with FORCEON
= 0) may be a desirable configuration. While the cable is
attached INVALID and FORCEOFF remain high, so the
enhanced automatic powerdown logic powers down the RS232 device whenever there is 30 seconds of inactivity on the
receiver and transmitter inputs. Detaching the cable allows
the receiver inputs to drop to an invalid level (GND), so
INVALID switches low and forces the RS-232 device to
power down. The ICL32XXE remains powered down until
the cable is reconnected (INVALID = FORCEOFF = 1) and a
transition occurs on a receiver or transmitter input (see
Figure 7). For immediate power up when the cable is
reattached, connect FORCEON to FORCEOFF through a
network similar to that shown in Figure 5.
RECEIVER
INPUTS
INVALID
} REGION
TRANSMITTER
INPUTS
TRANSMITTER
OUTPUTS
tINVH
INVALID
OUTPUT
tINVL
tAUTOPWDN
tAUTOPWDN
tWU
tWU
READY
OUTPUT
V+
VCC
0
V-
FIGURE 9. ENHANCED AUTOMATIC POWERDOWN, INVALID AND READY TIMING DIAGRAMS
11
FN4900.9
February 27, 2006
ICL3225E, ICL3227E, ICL3245E
Ready Output (ICL3225E and ICL3227E Only)
Mouse Driveability
The Ready output indicates that the ICL322XE is ready to
transmit. Ready switches low whenever the device enters
powerdown, and switches back high during power-up when
V- reaches -4V or lower.
The ICL3245E is specifically designed to power a serial mouse
while operating from low voltage supplies. Figure 11 shows the
transmitter output voltages under increasing load current. The
on-chip switching regulator ensures the transmitters will supply
at least ±5V during worst case conditions (15mA for paralleled
V+ transmitters, 7.3mA for single V- transmitter).
The charge pumps require 0.1µF capacitors for 3.3V
operation. For other supply voltages refer to Table 3 for
capacitor values. Do not use values smaller than those listed
in Table 3. Increasing the capacitor values (by a factor of 2)
reduces ripple on the transmitter outputs and slightly
reduces power consumption. C2, C3, and C4 can be
increased without increasing C1’s value, however, do not
increase C1 without also increasing C2, C3, and C4 to
maintain the proper ratios (C1 to the other capacitors).
When using minimum required capacitor values, make sure
that capacitor values do not degrade excessively with
temperature. If in doubt, use capacitors with a larger nominal
value. The capacitor’s equivalent series resistance (ESR)
usually rises at low temperatures and it influences the
amount of ripple on V+ and V-.
TABLE 3. REQUIRED CAPACITOR VALUES
VCC (V)
C1 (µF)
C2, C3, C4 (µF)
3.0 to 3.6
0.1
0.1
4.5 to 5.5
0.047
0.33
3.0 to 5.5
0.1
0.47
Power Supply Decoupling
In most circumstances a 0.1µF bypass capacitor is
adequate. In applications that are particularly sensitive to
power supply noise, decouple VCC to ground with a
capacitor of the same value as the charge-pump capacitor C1.
Connect the bypass capacitor as close as possible to the IC.
Operation Down to 2.7V
ICL32XXE transmitter outputs meet RS-562 levels (±3.7V),
at full data rate, with VCC as low as 2.7V. RS-562 levels
typically ensure inter operability with RS-232 devices.
Transmitter Outputs when Exiting
Powerdown
Figure 10 shows the response of two transmitter outputs
when exiting powerdown mode. As they activate, the two
transmitter outputs properly go to opposite RS-232 levels,
with no glitching, ringing, nor undesirable transients. Each
transmitter is loaded with 3kΩ in parallel with 2500pF. Note
that the transmitters enable only when the magnitude of the
supplies exceed approximately 3V.
12
5V/DIV
FORCEOFF
T1
VCC = +3.3V
C1 - C4 = 0.1µF
2V/DIV
T2
5V/DIV
READY
TIME (20µs/DIV.)
FIGURE 10. TRANSMITTER OUTPUTS WHEN EXITING
POWERDOWN
6
TRANSMITTER OUTPUT VOLTAGE (V)
Capacitor Selection
5
VOUT+
4
VCC = 3.0V
3
2
T1
1
VOUT+
0
T2
-1
ICL3245E
-2
VCC
-3
VOUT -
T3
VOUT -
-4
-5
-6
0
1
2
3
4
5
6
7
8
9
10
LOAD CURRENT PER TRANSMITTER (mA)
FIGURE 11. TRANSMITTER OUTPUT VOLTAGE vs LOAD
CURRENT (PER TRANSMITTER, i.e., DOUBLE
CURRENT AXIS FOR TOTAL VOUT+ CURRENT)
High Data Rates
The ICL32XXE maintain the RS-232 ±5V minimum
transmitter output voltages even at high data rates. Figure
12 details a transmitter loopback test circuit, and Figure 13
illustrates the loopback test result at 250kbps. For this test,
all transmitters were simultaneously driving RS-232 loads in
parallel with 1000pF, at 250kbps. Figure 14 shows the
loopback results for a single transmitter driving 250pF and
FN4900.9
February 27, 2006
ICL3225E, ICL3227E, ICL3245E
an RS-232 load at 1Mbps. The static transmitters were also
loaded with an RS-232 receiver.
5V/DIV.
VCC
+
0.1µF
+
T1IN
VCC
C1+
V+
C1
C1-
+
C3
T1OUT
ICL32XXE
+
V-
C2+
C2
C4
+
C2-
R1OUT
TIN
TOUT
RIN
ROUT
FORCEON
VCC
CL
5k
FORCEOFF
VCC = +3.3V
C1 - C4 = 0.1µF
0.5µs/DIV.
FIGURE 14. LOOPBACK TEST AT 1Mbps (CL = 250pF)
Interconnection with 3V and 5V Logic
FIGURE 12. TRANSMITTER LOOPBACK TEST CIRCUIT
5V/DIV.
T1IN
The ICL32XXE directly interfaces with 5V CMOS and TTL
logic families. Nevertheless, with the ICL32XX at 3.3V, and
the logic supply at 5V, AC, HC, and CD4000 outputs can
drive ICL32XX inputs, but ICL32XX outputs do not reach the
minimum VIH for these logic families. See Table 4 for more
information.
TABLE 4. LOGIC FAMILY COMPATIBILITY WITH VARIOUS
SUPPLY VOLTAGES
VCC
SYSTEM
POWER-SUPPLY SUPPLY
VOLTAGE
VOLTAGE
(V)
(V)
T1OUT
R1OUT
VCC = +3.3V
C1 - C4 = 0.1µF
2µs/DIV.
FIGURE 13. LOOPBACK TEST AT 250kbps (CL = 1000pF)
3.3
3.3
5
5
5
3.3
COMPATIBILITY
Compatible with all CMOS
families.
Compatible with all TTL and
CMOS logic families.
Compatible with ACT and HCT
CMOS, and with TTL. ICL32XX
outputs are incompatible with AC,
HC, and CD4000 CMOS inputs.
±15kV ESD Protection
All pins on ICL32XX devices include ESD protection
structures, but the ICL32XXE family incorporates advanced
structures which allow the RS-232 pins (transmitter outputs
and receiver inputs) to survive ESD events up to ±15kV. The
RS-232 pins are particularly vulnerable to ESD damage
because they typically connect to an exposed port on the
exterior of the finished product. Simply touching the port
pins, or connecting a cable, can cause an ESD event that
might destroy unprotected ICs. These new ESD structures
protect the device whether or not it is powered up, protect
without allowing any latchup mechanism to activate, and
don’t interfere with RS-232 signals as large as ±25V.
13
FN4900.9
February 27, 2006
ICL3225E, ICL3227E, ICL3245E
Human Body Model (HBM) Testing
As the name implies, this test method emulates the ESD
event delivered to an IC during human handling. The tester
delivers the charge through a 1.5kΩ current limiting resistor,
making the test less severe than the IEC61000 test which
utilizes a 330Ω limiting resistor. The HBM method
determines an ICs ability to withstand the ESD transients
typically present during handling and manufacturing. Due to
the random nature of these events, each pin is tested with
respect to all other pins. The RS-232 pins on “E” family
devices can withstand HBM ESD events to ±15kV.
IEC61000-4-2 Testing
The IEC61000 test method applies to finished equipment,
rather than to an individual IC. Therefore, the pins most likely
to suffer an ESD event are those that are exposed to the
outside world (the RS-232 pins in this case), and the IC is
tested in its typical application configuration (power applied)
rather than testing each pin-to-pin combination. The lower
current limiting resistor coupled with the larger charge
storage capacitor yields a test that is much more severe than
Typical Performance Curves
the HBM test. The extra ESD protection built into this
device’s RS-232 pins allows the design of equipment
meeting level 4 criteria without the need for additional board
level protection on the RS-232 port.
AIR-GAP DISCHARGE TEST METHOD
For this test method, a charged probe tip moves toward the
IC pin until the voltage arcs to it. The current waveform
delivered to the IC pin depends on approach speed,
humidity, temperature, etc., so it is difficult to obtain
repeatable results. The “E” device RS-232 pins withstand
±15kV air-gap discharges.
CONTACT DISCHARGE TEST METHOD
During the contact discharge test, the probe contacts the
tested pin before the probe tip is energized, thereby
eliminating the variables associated with the air-gap
discharge. The result is a more repeatable and predictable
test, but equipment limits prevent testing devices at voltages
higher than ±8kV. All “E” family devices survive ±8kV contact
discharges on the RS-232 pins.
VCC = 3.3V, TA = 25°C
110
VOUT+
4
90
+SLEW
SLEW RATE (V/µs)
TRANSMITTER OUTPUT VOLTAGE (V)
6
2
1 TRANSMITTER AT 1Mbps
OTHER TRANSMITTERS AT 30kbps
0
-2
VOUT-
70
50
-SLEW
30
-4
10
-6
0
1000
2000
3000
4000
5000
LOAD CAPACITANCE (pF)
FIGURE 15. TRANSMITTER OUTPUT VOLTAGE vs LOAD
CAPACITANCE
14
0
0
1000
2000
3000
4000
5000
LOAD CAPACITANCE (pF)
FIGURE 16. SLEW RATE vs LOAD CAPACITANCE
FN4900.9
February 27, 2006
ICL3225E, ICL3227E, ICL3245E
Typical Performance Curves
VCC = 3.3V, TA = 25°C (Continued)
90
90
ICL3225E
ICL3227E
80
80
1Mbps
1Mbps
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
70
60
50
40
250kbps
30
70
60
50
250kbps
40
120kbps
30
120kbps
20
20
10
10
0
2000
1000
4000
3000
5000
0
1000
LOAD CAPACITANCE (pF)
2000
3000
4000
5000
LOAD CAPACITANCE (pF)
FIGURE 17. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
FIGURE 18. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
90
3.5
NO LOAD
ALL OUTPUTS STATIC
1Mbps
ICL3245E
80
3.0
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
70
60
50
250kbps
40
30
120kbps
2.5
2.0
1.5
1.0
0.5
20
10
0
1000
2000
3000
4000
5000
LOAD CAPACITANCE (pF)
FIGURE 19. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
FIGURE 20. SUPPLY CURRENT vs SUPPLY VOLTAGE
Die Characteristics
MSUBSTRATE POTENTIAL (POWERED UP)
GND
TRANSISTOR COUNT
ICL3225E: 937
ICL3227E: 825
ICL3245E: 1109
PROCESS
Si Gate CMOS
15
FN4900.9
February 27, 2006
ICL3225E, ICL3227E, ICL3245E
Dual-In-Line Plastic Packages (PDIP)
N
E20.3 (JEDEC MS-001-AD ISSUE D)
E1
INDEX
AREA
1 2 3
20 LEAD DUAL-IN-LINE PLASTIC PACKAGE
N/2
INCHES
-B-
SYMBOL
-AD
E
BASE
PLANE
-C-
SEATING
PLANE
A2
A
L
D1
e
B1
D1
eA
A1
eC
B
0.010 (0.25) M
C
L
C A B S
C
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
MILLIMETERS
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
B1
0.045
0.070
1.55
1.77
8
C
0.008
0.014
0.204
0.355
-
D
0.980
1.060
24.89
26.9
5
D1
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
6
eB
-
0.430
-
10.92
7
L
0.115
0.150
2.93
3.81
4
N
20
20
9
Rev. 0 12/93
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
16
FN4900.9
February 27, 2006
ICL3225E, ICL3227E, ICL3245E
Small Outline Plastic Packages (SSOP)
M16.209 (JEDEC MO-150-AC ISSUE B)
N
INDEX
AREA
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
H
0.25(0.010) M
2
GAUGE
PLANE
3
0.25
0.010
SEATING PLANE
-A-
INCHES
E
-B-
1
B M
A
D
-C-
α
e
C
0.10(0.004)
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.078
-
2.00
-
A1
0.002
-
0.05
-
-
A2
0.065
0.072
1.65
1.85
-
B
0.009
0.014
0.22
0.38
9
C
0.004
0.009
0.09
0.25
-
D
0.233
0.255
5.90
6.50
3
E
0.197
0.220
5.00
5.60
4
e
A2
A1
B
0.25(0.010) M
L
B S
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
0.026 BSC
H
0.292
L
0.022
N
α
NOTES:
MILLIMETERS
0.65 BSC
0.322
7.40
0.037
0.55
16
0°
-
8.20
-
0.95
6
16
8°
0°
7
8°
Rev. 3
6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
17
FN4900.9
February 27, 2006
ICL3225E, ICL3227E, ICL3245E
Shrink Small Outline Plastic Packages (SSOP)
N
INDEX
AREA
M20.209 (JEDEC MO-150-AE ISSUE B)
H
0.25(0.010) M
E
2
INCHES
3
0.25
0.010
SEATING PLANE
-A-
20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
GAUGE
PLANE
-B1
B M
A
D
-C-
α
e
A1
B
0.25(0.010) M
L
A2
C
0.10(0.004)
C A M
B S
SYMBOL
MIN
MAX
MIN
MAX
A
0.068
0.078
1.73
1.99
A1
0.002
0.008’
0.05
0.21
A2
0.066
0.070’
1.68
1.78
B
0.010’
0.015
0.25
0.38
0.004
0.008
0.09
0.20’
D
0.278
0.289
7.07
7.33
3
E
0.205
0.212
5.20’
5.38
4
e
0.026 BSC
H
0.301
L
0.025
α
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
NOTES
C
N
NOTES:
MILLIMETERS
0.65 BSC
0.311
7.65
0.037
0.63
20
0 deg.
9
7.90’
6
0.95
20
8 deg.
0 deg.
7
8 deg.
Rev. 3 11/02
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess
of “B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
18
FN4900.9
February 27, 2006
ICL3225E, ICL3227E, ICL3245E
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
B S
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.6969
0.7125
17.70
18.10
3
E
0.2914
0.2992
7.40
7.60
4
0.05 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.01
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
α
NOTES:
MILLIMETERS
MAX
A1
e
α
MIN
28
0o
28
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
19
FN4900.9
February 27, 2006
ICL3225E, ICL3227E, ICL3245E
Shrink Small Outline Plastic Packages (SSOP)
M28.209 (JEDEC MO-150-AH ISSUE B)
N
28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
2
GAUGE
PLANE
3
0.25
0.010
SEATING PLANE
-A-
INCHES
E
-B-
1
B M
L
A
D
-C-
α
e
B
C
0.10(0.004)
0.25(0.010) M
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.078
-
2.00
-
A1
0.002
-
0.05
-
-
A2
0.065
0.072
1.65
1.85
-
B
0.009
0.014
0.22
0.38
9
C
0.004
0.009
0.09
0.25
-
D
0.390
0.413
9.90
10.50
3
E
0.197
0.220
5.00
5.60
4
e
A2
A1
B S
NOTES:
MILLIMETERS
0.026 BSC
H
0.292
L
0.022
N
α
0.65 BSC
0.322
7.40
0.037
0.55
28
0°
-
0.95
6
28
8°
0°
-
8.20
7
8°
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
Rev. 2 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess of
“B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
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20
FN4900.9
February 27, 2006