PRELIMINARY INFORMATION ICS541 PLL Clock Divider Description Features The ICS541 is a cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 135 MHz at 3.3 V, and by using proprietary Phase Locked Loop (PLL) techniques, produces a divide by 1, 2, 4, or 8 of the input clock. There are two outputs on the chip, one being a low-skew divide by two of the other. So, for instance, if an 80 MHz input clock is used, the ICS541 can produce low skew 80 MHz and 40 MHz clocks, or 40 MHz and 20 MHz clocks, or 20 MHz and 10MHz clocks. The chip has an all-chip power down mode that stops the outputs low, and an OE pin that tristates the outputs. • Packaged in 8 pin SOIC • Low cost clock divider • Low skew (500ps) outputs. One is ÷ 2 of other. • Easy to use with other generators and buffers • Input clock frequency up to 135 MHz at 3.3 V • Input clock frequency up to 156 MHz at 5.0 V • Tolerant of poor input clock duty cycle, jitter. • Output clock duty cycle of 45/55 • Power Down turns off chip • Output Enable • Full CMOS clock swings with 25mA drive capability at TTL levels • Advanced, low power CMOS process • Operating voltages of 3.0 to 5.5 V The ICS541 is a member of the ICS ClockBlocks™ family of clock building blocks. See the ICS542 and ICS543 for other clock dividers, and the ICS300, 501, 502, and 503 for clock multipliers. Block Diagram VDD GND 2 S1, S0 PLL, Divider and Selection Circuitry Input Clock Output Buffer CLK Output Buffer CLK/2 ÷2 OE (both outputs) 1 Revision 082500 Printed 11/14/00 Integrated Circuit Systems, Inc. •525 Race Street• San Jose•CA• 95126• (408)295-9800tel • www.icst.com MDS 541 B PRELIMINARY INFORMATION Pin Assignment ICS541 PLL Clock Divider Clock Decoding Table ICLK 1 8 CLK VDD 2 7 CLK/2 GND 3 6 OE S0 4 5 S1 8 pin SOIC S1 #5 0 0 1 1 S0 #4 0 1 0 1 CLK CLK/2 pin #8 pin #7 Power Down All Input/4 Input/8 Input Input/2 Input/2 Input/4 0 = connect directly to ground. 1 = connect directly to VDD. Pin Descriptions Number 1 2 3 4 5 6 7 8 Name ICLK VDD GND S0 S1 OE CLK/2 CLK Type CI P P I I I O O Description Clock input. Connect to +3.3V or +5V. Connect to ground. Select 0 for output clock. Connect to GND or VDD, per decoding table above. Select 1 for output clock. Connect to GND or VDD, per decoding table above. Output Enable. Tri-states both output clocks when low. Clock output per Table above. Low skew divide by two of pin 8 clock. Clock output per Table above. Key: CI = clock input, I = input, O = output, P = power supply connection External Components The ICS541 requires a 0.01 µF decoupling capacitor to be connected between VDD and GND. It must be connected close to the ICS541 to minimize lead inductance. No external power supply filtering is required for this device. A 33 Ω terminating resistor can be used next to each output pin. If a 3.3 V input clock is applied to the ICLK pin, with the ICS541 at 5 V, the clock must be AC coupled. 2 Revision 082500 Printed 11/14/00 Integrated Circuit Systems, Inc. •525 Race Street• San Jose•CA• 95126• (408)295-9800tel • www.icst.com MDS 541 B PRELIMINARY INFORMATION ICS541 PLL Clock Divider Electrical Specifications Parameter Conditions Minimum Typical ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device) Supply Voltage, VDD Referenced to GND Inputs Referenced to GND -0.5 Clock Output Referenced to GND -0.5 Ambient Operating Temperature 0 Soldering Temperature Max of 10 seconds Storage temperature -65 DC CHARACTERISTICS (VDD = 5.0V unless otherwise noted) Operating Voltage, VDD 3 Input High Voltage, VIH, ICLK only, Note 1 ICLK (Pin 1) (VDD/2)+1 Input Low Voltage, VIL, ICLK only, Note 1 ICLK (Pin 1) Input High Voltage, VIH S0, S1, OE 2 Input Low Voltage, VIL S0, S1, OE Output High Voltage, VOH IOH=-25mA 2.4 Output Low Voltage, VOL IOL=25mA Output High Voltage, VOH, CMOS level IOH=-4mA VDD-0.4 IDD Operating Supply Current, 80 in, 40+20 out No Load, 5.0V 15 IDD Operating Supply Current, 40 in, 40+20 out No Load, 3.3V 8 Short Circuit Current Each Output ±70 Input Capacitance, S1, S0, OE Pins 4, 5, 6 4 AC CHARACTERISTICS (VDD = 5.0V unless otherwise noted) Input Frequency, clock input at VDD = 5V 4 Input Frequency, clock input at VDD = 3.3V 4 Skew of output clocks rising edges at VDD/2 Output Clock Rise Time 0.8 to 2.0V 1 Output Clock Fall Time 2.0 to 0.8V 1 Output Clock Duty Cycle at VDD/2 45 49 to 51 Maximum Units 7 VDD+0.5 VDD+0.5 70 260 150 V V V C C C 5.5 V V V V V V V V mA mA mA pF (VDD/2)-1 0.8 0.4 156 135 500 55 MHz MHz ps ns ns % Note 1: CMOS level input; nominal trip point is VDD/2. 3 Revision 082500 Printed 11/14/00 Integrated Circuit Systems, Inc. •525 Race Street• San Jose•CA• 95126• (408)295-9800tel • www.icst.com MDS 541 B PRELIMINARY INFORMATION ICS541 PLL Clock Divider Package Outline and Package Dimensions (For current dimensional specifications, see JEDEC Publication No. 95.) 8 pin SOIC Symbol A A1 B E C H D E e H h L INDEX AREA 1 2 e Millimeters Min Max 1.35 1.75 0.10 0.24 0.33 0.51 0.19 0.24 4.80 5.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.41 1.27 h x 45° D A1 Inches Min Max 0.0532 0.0688 0.0040 0.0098 0.0130 0.0200 0.0075 0.0098 0.1890 0.1968 0.1497 0.1574 .050 BSC 0.2284 0.2440 0.0099 0.0195 0.0160 0.0500 B C A L Ordering Information Part/Order Number ICS541M ICS541MT Marking ICS541M ICS541M Package 8 pin SOIC 8 pin SOIC on tape and reel Temperature 0 to 70 C 0 to 70 C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. ClockBlocks is a trademark of ICS 4 Revision 082500 Printed 11/14/00 Integrated Circuit Systems, Inc. •525 Race Street• San Jose•CA• 95126• (408)295-9800tel • www.icst.com MDS 541 B