ICST ICS8402AYIT 350mhz, crystal-to-lvcmos / lvttl frequency synthesizer Datasheet

ICS8402I
Integrated
Circuit
Systems, Inc.
350MHZ, CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS8402I is a general purpose, Crystal-toLVCMOS/LVTTL High Frequency Synthesizer and
HiPerClockS™
a member of the HiPerClockS ™ family of High
Performance Clock Solutions from ICS. The
ICS8402I has a selectable TEST_CLK or crystal
inputs. The VCO operates at a frequency range of 250MHz
to 700MHz. The VCO frequency is programmed in steps equal
to the value of the input reference or crystal frequency. The
VCO and output frequency can be programmed using the
serial or parallel interfaces to the configuration logic. The low
phase noise characteristics of the ICS8402I make it an ideal
clock source for Gigabit Ethernet and SONET applications.
• (2) LVCMOS/LVTTL outputs
ICS
• Selectable crystal oscillator interface
or LVCMOS/LVTTL TEST_CLK
• Output frequency range: 15.625MHz - 350MHz
• Crystal input frequency range: 12MHz to 40MHz
• VCO range: 250MHz to 700MHz
• Parallel or serial interface for programming counter
and output dividers
• RMS period jitter: 30ps (maximum)
• Cycle-to-cycle jitter: 100ps (maximum)
• Full 3.3V or mixed 3.3V core/2.5V output supply voltage
• -40°C to 85°C ambient operating temperature
• Lead-Free fully RoHS compliant
BLOCK DIAGRAM
PIN ASSIGNMENT
XTAL_IN
nP_LOAD
M0
M1
M2
M3
M4
OE1
VCO_SEL
OE0
VCO_SEL
32 31 30 29 28 27 26 25
XTAL_SEL
0
XTAL_IN
1
XTAL_OUT
PLL
1
24
XTAL_OUT
M6
2
23
TEST_CLK
M7
3
22
XTAL_SEL
M8
4
21
VDDA
N0
5
20
S_LOAD
N1
6
19
S_DATA
nc
7
18
S_CLOCK
GND
8
17
MR
PHASE DETECTOR
÷M
Q1
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
CONFIGURATION
INTERFACE
LOGIC
TEST
Q0
Q0
GND
1
÷2
÷4
÷8
÷16
Q1
0
OE0
VCO
VDDO
9 10 11 12 13 14 15 16
TEST
MR
ICS8402I
VDD
OSC
M5
OE1
TEST_CLK
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
M0:M8
N0:N1
8402AYI
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1
REV. A DECEMBER 23, 2004
ICS8402I
Integrated
Circuit
Systems, Inc.
350MHZ, CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 25MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the
Input Frequency Characteristics, Table 5, NOTE 1.
put divider to a specific default state that will automatically
occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship between
the VCO frequency, the crystal frequency and the M divider
is defined as follows: fVCO = fxtal x M
The ICS8402I features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth. A fundamental crystal is used as the input to the onchip oscillator. The output of the oscillator is fed into the phase
detector. A 25MHz crystal provides a 25MHz phase detector
reference frequency. The VCO of the PLL operates over a
range of 250MHz to 700MHz. The output of the M divider is
also applied to the phase detector.
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock for a
25MHz reference are defined as 10 ≤ M ≤ 28. The frequency
out is defined as follows: FOUT = fVCO = fxtal x M
N
N
Serial operation occurs when nP_LOAD is HIGH and
S_LOAD is LOW. The shift register is loaded by sampling
the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N
output divider when S_LOAD transitions from LOW-to-HIGH.
The M divide and N output divide values are latched on the
HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH,
data at the S_DATA input is passed directly to the M divider
and N output divider on each rising edge of S_CLOCK. The
serial mode can be used to program the M and N bits and
test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows:
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (either
too high or too low), the PLL will not achieve lock. The output of
the VCO is scaled by a divider prior to being sent to each of
the LVCMOS output buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS8402I support two input modes to program the M divider and N output divider.
The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel
mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the
M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M
divider remains loaded until the next LOW transition on
nP_LOAD or until a serial event occurs. As a result, the M
and N bits can be hardwired to set the M divider and N out-
T1
T0
TEST Output
0
0
LOW
0
1
Shift Register Output
1
0
Output of M divider
1
1
CMOS Fout
SERIAL LOADING
S_CLOCK
T1
S_DATA
t
S_LOAD
S
T0
*NULL
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
H
t
nP_LOAD
S
PARALLEL LOADING
M0:M8, N0:N1
M, N
nP_LOAD
t
S
t
Time
H
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
*NOTE: The NULL timing slot must be observed.
8402AYI
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2
REV. A DECEMBER 23, 2004
ICS8402I
Integrated
Circuit
Systems, Inc.
350MHZ, CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
1
M5
2, 3, 4,
28, 29,
30, 31, 32
M6, M7, M8,
M0, M1,
M2, M3, M4
Input
M divider inputs. Data latched on LOW-to-HIGH transition
Pulldown of nP_LOAD input. LVCMOS / LVTTL interface levels.
5, 6
N0, N1
Input
Pulldown
7
nc
Unused
8, 16
GND
Power
Power supply ground.
9
TEST
Output
Test output which is ACTIVE in the serial mode of operation. Output
driven LOW in parallel mode. LVCMOS / LVTTL interface levels.
10
VDD
Power
Core supply pin.
11, 12
OE1, OE0
Input
13
VDDO
Power
Output supply pin.
14, 15
Q1, Q0
Output
Clock outputs. LVCMOS / LVTTL interface levels.
Input
Description
Pullup
Determines output divider value as defined in Table 3C,
Function Table. LVCMOS / LVTTL interface levels.
No connect.
Pullup
17
MR
Input
Pulldown
18
S_CLOCK
Input
Pulldown
19
S_DATA
Input
Pulldown
20
S_LOAD
Input
Pulldown
21
VDDA
Power
22
XTAL_SEL
Input
23
TEST_CLK
Input
24, 25
XTAL_OUT,
XTAL_IN
Input
26
nP_LOAD
Input
27
VCO_SEL
Input
Output enable. When logic HIGH, the outputs are enabled (default).
When logic LOW, the outputs are in Tri-State. See Table 3D,
OE Function Table. LVCMOS / LVTTL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the outputs to go low. When logic LOW, the
internal dividers and the outputs are enabled. Asser tion of MR
does not effect loaded M, N, and T values.
LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of
S_CLOCK. LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
Analog supply pin.
Pullup
Selects between crystal or test inputs as the PLL reference source.
Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW.
LVCMOS / LVTTL interface levels
Pulldown Test clock input. LVCMOS / LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Parallel load input. Determines when data present at M8:M0 is
Pulldown loaded into M divider, and when data present at N1:N0 sets the
N output divider value. LVCMOS / LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
Pullup
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
8402AYI
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3
REV. A DECEMBER 23, 2004
ICS8402I
Integrated
Circuit
Systems, Inc.
350MHZ, CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
CPD
Power Dissipation Capacitance
(per output)
RPULLUP
Input Pullup Resistor
RPULLDOWN
Input Pulldown Resistor
ROUT
Test Conditions
Minimum
Typical
Maximum
Units
4
pF
VDD, VDDA, VDDO = 3.465V
13
pF
VDD, VDDA = 3.465V, VDDO = 2.625V
11
pF
51
KΩ
51
VDDO = 3.465V
Output Impedance
5
VDDO = 2.625V
7
KΩ
12
Ω
Ω
7
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE
Inputs
Conditions
MR
nP_LOAD
M
N
S_LOAD
S_CLOCK
S_DATA
H
X
X
X
X
X
X
Reset. Forces outputs LOW.
L
L
Data
Data
X
X
X
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
L
↑
Data
Data
L
X
X
L
H
X
X
L
↑
Data
L
H
X
X
↑
L
Data
L
H
X
X
↓
L
Data
M divider and N output divider values are latched.
L
H
X
X
L
X
X
Parallel or serial input do not affect shift registers.
L
H
X
X
H
↑
Data
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
S_DATA passed directly to M divider as it is clocked.
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓ = Falling edge transition
8402AYI
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4
REV. A DECEMBER 23, 2004
ICS8402I
Integrated
Circuit
Systems, Inc.
350MHZ, CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
256
128
64
32
16
8
4
2
1
M8
M7
M6
M5
M4
M3
M2
M1
M0
10
0
0
0
0
0
1
0
1
0
275
11
0
0
0
0
0
1
0
1
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
650
26
0
0
0
0
1
1
0
1
0
675
27
0
0
0
0
1
1
0
1
1
700
28
0
0
0
0
1
1
1
0
0
VCO Frequency
(MHz)
M Divide
250
NOTE 1: These M divide values and the resulting frequencies correspond to cr ystal or TEST_CLK input frequency
of 25MHz.
TABLE 3D. OUTPUT ENABLE & CLOCK ENABLE FUNCTION TABLE
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
N Divider Value
Output Frequency
(MHz)
Minimum Maximum
N1
N0
0
0
2
125
350
0
1
4
62.5
175
1
0
8
31.25
87.5
1
1
16
15.625
43.75
8402AYI
Control Inputs
OE0
OE1
Q0
Q1
0
0
Hi-Z
Hi-Z
0
1
Hi-Z
Enabled
1
0
Enabled
Hi-Z
1
1
Enabled
Enabled
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5
Output
REV. A DECEMBER 23, 2004
ICS8402I
Integrated
Circuit
Systems, Inc.
350MHZ, CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDDO + 0.5V
Package Thermal Impedance, θJA
47.9°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
Test Conditions
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
3.135
3.3
3.465
V
3.135
3.3
3.465
V
2.375
2.5
2.625
V
125
mA
VDDO
Output Supply Voltage
IDD
Power Supply Current
IDDA
Analog Supply Current
18
mA
IDDO
Output Supply Current
10
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C
Symbol
VIH
VIL
IIH
IIL
Parameter
Input
High Voltage
Input
Low Voltage
Input
High Current
Input
Low Current
Test Conditions
VCO_SEL, XTAL_SEL, MR,
S_LOAD, nP_LOAD, S_DATA,
S_CLOCK, OE0, OE1,
N0:N1, M0:M8
TEST_CLK
VCO_SEL, XTAL_SEL, MR,
S_LOAD, nP_LOAD, S_DATA,
S_CLOCK, OE0, OE1,
N0:N1, M0:M8
TEST_CLK
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK,
S_DATA, S_LOAD, nP_LOAD
M5, OE0, OE1,
XTAL_SEL, VCO_SEL
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK,
S_DATA, S_LOAD, nP_LOAD
Maximum
Units
2
VDD + 0.3
V
2
VDD + 0.3
V
-0.3
0.8
V
-0.3
1.3
V
VDD = VIN = 3.465V
150
µA
VDD = VIN = 3.465V
5
µA
M5, OE0, OE1,
XTAL_SEL, VCO_SEL
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
Minimum
Typical
VDD = 3.465V,
VIN = 0V
-5
µA
VDD = 3.465V,
VIN = 0V
-150
µA
VDDO = 3.465V
2.6
V
VDDO = 2.625V
1.8
V
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2.
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6
REV. A DECEMBER 23, 2004
ICS8402I
Integrated
Circuit
Systems, Inc.
350MHZ, CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
fIN
Input
Frequency
Maximum
Units
TEST_CLK; NOTE 1
Test Conditions
Minimum
12
Typical
40
MHz
XTAL_IN XTAL_OUT NOTE 1
12
40
MHz
S_CLOCK
50
MHz
NOTE 1: For the input cr ystal and TEST_CLK frequency range, the M value must be set for the VCO to operate within
the 250MHz to 700MHz range. Using the minimum input frequency of 12MHz, valid values of M are 21 ≤ M ≤ 58.
Using the maximum frequency of 40MHz, valid values of M are 7 ≤ M ≤ 17.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical Maximum
Units
Fundamental
Frequency
12
40
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance (CO)
7
pF
TABLE 7A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
FOUT
Test Conditions
Output Frequency
Minimum
Typical
15.625
Maximum
Units
350
MHz
tjit(cc)
Cycle-to-Cycle Jitter ; NOTE 1, 3
40
100
ps
tjit(per)
Period Jitter, RMS; NOTE 1
8
30
ps
tsk(o)
Output Skew; NOTE 2, 3
80
ps
tR / tF
Output Rise/Fall Time
20% to 80%
M, N to nP_LOAD
tS
Setup Time
0.25
1.1
5
ns
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
M, N to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
tH
Hold Time
odc
Output Duty Cycle
S_CLOCK to S_LOAD
5
IJ 300MHz
40
ns
60
%
PLL Lock Time
1
ms
tLOCK
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
8402AYI
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REV. A DECEMBER 23, 2004
ICS8402I
Integrated
Circuit
Systems, Inc.
350MHZ, CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER
TABLE 7B. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
15.625
Maximum
Units
350
MHz
100
ps
FOUT
Output Frequency
tjit(cc)
Cycle-to-Cycle Jitter ; NOTE 1, 3
tjit(per)
Period Jitter, RMS; NOTE 1
30
ps
tsk(o)
Output Skew; NOTE 2, 3
60
ps
tR / tF
Output Rise/Fall Time
40
20% to 80%
M, N to nP_LOAD
tS
tH
odc
Setup Time
Hold Time
0.25
1.0
5
ns
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
M, N to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
Output Duty Cycle
IJ 300MHz
40
60
%
PLL Lock Time
1
ms
tLOCK
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
8402AYI
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REV. A DECEMBER 23, 2004
ICS8402I
Integrated
Circuit
Systems, Inc.
350MHZ, CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
1.65V±5%
2.05V±5% 1.25V±5%
SCOPE
VDD,
VDDA,
VDDO
VDDO
Qx
LVCMOS
SCOPE
VDD,
VDDA
Qx
LVCMOS
GND
GND
-1.65V±5%
-1.25V±5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
VOH
VREF
V
DDO
Qx
2
V
DDO
Qy
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
2
t sk(o)
Histogram
Reference Point
Mean Period
(Trigger Edge)
(First edge after trigger)
PERIOD JITTER
OUTPUT SKEW
V
V
DDO
V
DDO
2
DDO
2
➤
Q0, Q1
➤
tcycle n
80%
80%
tR
tF
2
tcycle n+1
➤
Clock
Outputs
20%
20%
➤
t jit(cc) = tcycle n –tcycle n+1
1000 Cycles
CYCLE-TO-CYCLE JITTER
OUTPUT RISE/FALL TIME
V
DDO
2
Q0, Q1
Pulse Width
t
odc =
PERIOD
t PW
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. A DECEMBER 23, 2004
ICS8402I
Integrated
Circuit
Systems, Inc.
350MHZ, CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8402I provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VDDA pin.
3.3V
VDD
.01µF
10Ω
VDDA
.01µF
10µF
FIGURE 2. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can
be slightly adjusted for different board layouts.
The ICS8402I has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2,
shown in Figure 3 below were determined using a 25MHz,
XTAL_IN
C1
22p
X1
18pF Parallel Cry stal
XTAL_OUT
C2
22p
ICS8402I
ICS84332
Figure 3. CRYSTAL INPUt INTERFACE
8402AYI
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10
REV. A DECEMBER 23, 2004
ICS8402I
Integrated
Circuit
Systems, Inc.
350MHZ, CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
θ JA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8402I is: 3784
8402AYI
www.icst.com/products/hiperclocks.html
11
REV. A DECEMBER 23, 2004
ICS8402I
Integrated
Circuit
Systems, Inc.
350MHZ, CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
32
N
A
--
--
1.60
A1
0.05
--
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
c
0.09
--
0.20
D
9.00 BASIC
D1
7.00 BASIC
D2
5.60 Ref.
E
9.00 BASIC
E1
7.00 BASIC
E2
5.60 Ref.
e
0.80 BASIC
L
0.45
0.60
0.75
θ
0°
--
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
8402AYI
www.icst.com/products/hiperclocks.html
12
REV. A DECEMBER 23, 2004
ICS8402I
Integrated
Circuit
Systems, Inc.
350MHZ, CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
Temperature
ICS8402AYI
ICS8402AYI
32 Lead LQFP
250 per tray
-40°C to 85°C
ICS8402AYIT
ICS8402AYI
32 Lead LQFP on Tape and Reel
1000
-40°C to 85°C
ICS8402AYILF
TBD
250 per tray
-40°C to 85°C
ICS8402AYILFT
TBD
32 Lead "Lead-Free" LQFP
32 Lead "Lead-Free" LQPF on
Tape and Reel
1000
-40°C to 85°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support
devices or critical medical instruments.
8402AYI
www.icst.com/products/hiperclocks.html
13
REV. A DECEMBER 23, 2004