ICS843207-350 FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER GENERAL DESCRIPTION FEATURES T h e I C S 8 4 3 2 0 7 - 3 5 0 i s a l ow p h a s e - n o i s e ICS frequency margining synthesizer that targets HiPerClockS™ clocking for high performance interfaces such as SPI4.2 and is a member of the HiPerClockS™ family of high performance clock solutions from IDT. In the default mode, each output can be configured individually to generate an 87.5MHz, 175MHZ or 350MHz LVPECL output clock signal from a 14MHz crystal input. There is also a frequency margining mode available where the device can be configured, using control pins, to vary the output frequency up or down from nominal by 5%. The ICS843207-350 is provided in a 48-pin LQFP package. • Seven independently configurable LVPECL outputs at 87.5MHz, 175MHz or 350MHz • Individual high impedance control of each output • Selectable crystal oscillator interface designed for 14MHz, 18pF parallel resonant crystal or LVCMOS single-ended input • Output frequency can be varied ± 5% from nominal • VCO range: 620MHz - 750MHz • Full 3.3V supply mode • 0°C to 70°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages PIN ASSIGNMENT SEL2 SEL3 SEL4 SEL5 SEL6 SEL7 SEL8 SEL9 SEL10 SEL11 SEL12 SEL13 VCCO Q0 nQ0 Q1 nQ1 VEE VCCO Q2 nQ2 Q3 nQ3 VCCO 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 33 4 5 32 48-Pin LQFP 6 7mm x 7mm x 1.4mm 31 package body 30 7 Y Package 8 29 Top View 9 28 27 10 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 VCCA VCC VCCO nQ6 Q6 VEE VCCO nQ5 Q5 nQ4 Q4 VCCO ICS843207-350 BLOCK DIAGRAM 01 ÷2 10 ÷8 11 ÷4 nQ0 Pullup 2 SEL[1:0] Q1 00 HiZ 01 ÷2 10 ÷8 11 ÷4 nQ1 Pullup 2 SEL1 SEL0 nPLL_SEL VCC XTAL_IN XTAL_OUT nXTAL_SEL REF_CLK VEE MR MARGIN MODE 01 ÷2 10 ÷8 11 ÷4 OSC nQ2 Pullup 14MHz 1 0 0 REF_CLK Pulldown 1 1 Phase Detector VCO 620 - 750MHz nQ3 nXTAL_SEL Pulldown ÷50 1 ÷95 ÷105 2 SEL[7:6] 0 Q4 00 HiZ 01 ÷2 10 ÷8 11 ÷4 0 SEL[5:4] Q3 01 ÷2 10 ÷8 11 ÷4 Pullup Predivider ÷2 2 00 HiZ XTAL_OUT SEL[3:2] Q2 00 HiZ nPLL_SEL Pulldown XTAL_IN Q0 00 HiZ nQ4 Pullup 2 Q5 00 HiZ 01 ÷2 10 ÷8 11 ÷4 MODE Pulldown SEL[9:8] nQ5 Pullup 2 SEL[11:10] MARGIN Pulldown MR To O/P Dividers Pulldown 00 HiZ Q6 01 ÷2 10 ÷8 11 ÷4 nQ6 Pullup IDT ™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER 1 2 SEL[13:12] ICS843207CY-350 REV. A DECEMBER 3, 2007 ICS843207-350 FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER PRELIMINARY FUNCTIONAL DESCRIPTION and using the margin pin to change the M feedback divider. Frequency margining mode operation occurs when the MODE input is HIGH. The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. The output of the VCO is scaled by an output divider prior to being sent to the LVPECL output buffer. The divider provides a 50% output duty cycle. The relationship between the crystal input frequency, the M divider, the VCO frequency and the output frequency is provided in Table 1A. When changing back from frequency margining mode to nominal mode, the device will return to the default nominal configuration described above. The ICS843207-350 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A 14MHz fundamental crystal is used as the input to the on chip oscillator. The output of the oscillator is fed into the pre-divider. In frequency margining mode, the 14MHz crystal frequency is divided by 2 and a 7MHz reference frequency is applied to the phase detector. The VCO of the PLL operates over a range of 620MHz to 750MHz. The output of the M divider is also applied to the phase detector. The default mode for the ICS843207-350 is a nominal VCO frequency of 700MHz with each output configurable to divide by 2, 4 or 8. The nominal output frequency can be changed by placing the device into the margining mode using the mode pin TABLE 1A. FREQUENCY SELECT FUNCTION TABLE XTAL (MHz) SELx SELx-1 VCO (MHz) Output Divider Output Frequency (MHz) 14 0 0 70 0 N/A HiZ 14 0 1 700 2 350 14 1 0 700 8 87.5 14 1 1 700 4 175 TABLE 1B. FREQUENCY MARGIN FUNCTION TABLE MODE MARGIN XTAL (MHz) Pre-Divider (P) Feedback Divider VCO (MHz) % Change 1 0 14 2 95 665 -5.0 0 X 14 1 50 700 Nom. Mode 1 1 14 2 105 735 +5.0 IDT ™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER 2 ICS843207CY-350 REV. A DECEMBER 3, 2007 ICS843207-350 FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER PRELIMINARY TABLE 2. PIN DESCRIPTIONS Number Number 1, 7, 12, 25, 30, 34 2, 3 Name Name T ype Type D escription Description VCCO Power Output supply pins. Q0, nQ0 Ouput Differential output pair. LVPECL interface levels. 4, 5 Q1, nQ1 Ouput Differential output pair. LVPECL interface levels. 6, 16, 31 VEE Power Negative supply pins. 8, 9 Q2, nQ2 Ouput Differential output pair. LVPECL interface levels. 10, 11 Q3, nQ3 Ouput 13 MODE Input Pulldown 14 Margin Input Pulldown 15 MR Input Pulldown 17 REF_CLK Input Pulldown 18 nXTAL_SEL Input Pulldown 19, 20 21, 35 XTAL_OUT, XTAL_IN VCC Power 22 nPLL_SEL Input Pulldown Differential output pair. LVPECL interface levels. MODE pin. LOW = default mode. HIGH = frequency margining mode. See Table 4B. LVCMOS/LVTTL interface levels. Sets the frequency to ±5% in frequency margining mode. See Table 1B. LVCMOS/LVTTL interface levels. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go LOW and inver ted outputs nQx to go HIGH. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Reference input clock. LVCMOS/LVTTL interface levels. Cr ystal select pin. Selects between the cr ystal and the reference clock inputs. LVCMOS/LVTTL interface levels. Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the input. Core supply pins. PLL select pin. When HIGH, PLL is bypassed and input is fed directly to the output dividers. When LOW, PLL is enabled. LVCMOS/LVTTL interface levels. 23, 24, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48 26, 27 SEL0, SEL1, SEL2, SEL3, SEL4, SEL5, SEL6, SEL7, SEL8, SEL9, SEL10, SEL11, SEL12, SEL13 Q4, nQ4 Input Pullup Ouput Differential output pair. LVPECL interface levels. 28, 29 Q5, nQ5 Ouput Differential output pair. LVPECL interface levels. 32, 33 Q6, nQ6 Ouput Differential output pair. LVPECL interface levels. 36 VCCA Power Analog supply pin. Input Output divider select pins. See Table 1A. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 3. PIN CHARACTERISTICS Symbol Parameter Test Conditions CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 kΩ RPULLUP Input Pulldown Resistor 51 kΩ TABLE 4A. nXTAL_SEL CONTROL INPUT FUNCTION TABLE Minimum Typical Maximum TABLE 4B. MODE CONTROL INPUT FUNCTION TABLE Input Input Condition nXTAL_SEL 0 Selected Source XTAL_IN, XTAL_OUT MODE 0 Q0:Q6, nQ0:nQ6 Default Mode 1 REF_CLK 1 Frequency Margining Mode IDT ™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER Units 3 ICS843207CY-350 REV. A DECEMBER 3, 2007 ICS843207-350 FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER PRELIMINARY ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 65.7°C/W (0 mps) -65°C to 150°C Storage Temperature, TSTG TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, VCCO = VEE = OV, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V Analog Supply Voltage VCC – 0.13 3.3 VCC V 3.135 3.3 VCC Core Supply Voltage VCCA VCCO Output Supply Voltage 3.465 V IEE Power Supply Current 210 mA ICCA Analog Supply Current 13 mA TABLE 5B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, VEE = OV, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL Input High Current Input Low Current Test Conditions REF_CLK, MARGIN, MODE, nPLL_SEL, MR, nXTAL_SEL SEL[0:13] REF_CLK, MARGIN, MODE, nPLL_SEL, MR, nXTAL_SEL SEL[0:13] Δt/Δv Input Transition Rise/Fall Rate Maximum Units VCC = 3.3V 2 VCC + 0.3 V VCC = 3.3V -0.3 0.8 V VCC = VIN = 3.465 150 µA VCC = VIN = 3.465 5 µA VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V SEL[0:13], MODE IDT ™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER Minimum Typical -5 µA -150 µA 20 4 ns/V ICS843207CY-350 REV. A DECEMBER 3, 2007 ICS843207-350 FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER PRELIMINARY TABLE 5C. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, VEE = OV, TA = 0°C TO 70°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum VCCO - 1.4 Typical VCCO - 0.9 V VOL Output Low Voltage; NOTE 1 VCCO - 2.0 VCCO - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. TABLE 6. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 12.4 14 15 MH z Equivalent Series Resistance (ESR) 40 Ω Shunt Capacitance 7 pF 300 µW Drive Level NOTE: Characterized using an 18pF parallel resonant cr ystal. TABLE 7. AC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, VEE = OV, TA = 0°C TO 70°C Symbol fOUT fIN t jit(Ø) Parameter Output Frequency Input Frequency Test Conditions Minimum Typical Maximum Units N = ÷2 310 350 375 MHz N = ÷4 155 175 187.5 MHz N = ÷8 77.5 87.5 93.75 MHz 12.4 14 15 MHz REF_CLK RMS Phase Jitter, Random; NOTE 1 t R / tF Output Rise/Fall Time odc Output Duty Cycle Mode = LOW 350MHz, (12kHz - 20MHz) Mode = LOW 175MHz, (12kHz - 20MHz) Mode = LOW 87.5MHz, (12kHz - 20MHz) 20% to 80% 300 600 ps Output Divider = ÷2 Output Divider = ≠2 42 46 58 64 % % 1.54 ps 1.48 ps 1.61 ps NOTE 1: Characterized using a 14MHz cr ystal. IDT ™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER 5 ICS843207CY-350 REV. A DECEMBER 3, 2007 ICS843207-350 FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER PRELIMINARY ➤ TYPICAL PHASE NOISE AT 175MHZ 10 Gigabit Ethernet Filter 175MHz Raw Phase Noise Data ➤ NOISE POWER dBc Hz RMS Phase Noise Jitter 12kHz to 20MHz = 1.48ps (typical) ➤ Phase Noise Result by adding 10 Gigabit Ethernet Filter to raw data OFFSET FREQUENCY (HZ) ➤ TYPICAL PHASE NOISE AT 350MHZ 10 Gigabit Ethernet Filter 350MHz Raw Phase Noise Data ➤ ➤ NOISE POWER dBc Hz RMS Phase Noise Jitter 12kHz to 20MHz = 1.54ps (typical) Phase Noise Result by adding 10 Gigabit Ethernet Filter to raw data OFFSET FREQUENCY (HZ) IDT ™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER 6 ICS843207CY-350 REV. A DECEMBER 3, 2007 ICS843207-350 FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER PRELIMINARY PARAMETER MEASUREMENT INFORMATION 2V 2V Phase Noise Plot Qx SCOPE Noise Power VCC, VCCO VCCA Phase Noise Mask LVPECL nQx VEE f1 Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot -1.3V ± 0.165V 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER nQ0:nQ6 80% 80% Q0:Q6 VSW I N G t PW t odc = Clock Outputs PERIOD t PW 20% 20% tR tF x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD IDT ™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER OUTPUT RISE/FALL TIME 7 ICS843207CY-350 REV. A DECEMBER 3, 2007 ICS843207-350 FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER PRELIMINARY APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS843207-350 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA and VCCO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VCCA pin. 3.3V VCC .01μF 10Ω VCCA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE Figure 2 below were determined using a 14MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The ICS843207-350 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in XTAL_OUT C1 27p X1 18pF Parallel Crystal XTAL_IN C2 27p FIGURE 2. CRYSTAL INPUt INTERFACE IDT ™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER 8 ICS843207CY-350 REV. A DECEMBER 3, 2007 ICS843207-350 FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER PRELIMINARY LVCMOS TO XTAL INTERFACE The XTAL_IN input can accept a single-ended LVCMOS signal through an AC couple capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. VDD VDD R1 Ro .1uf Rs Zo = 50 XTAL_IN R2 Zo = Ro + Rs XTAL_OUT FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CRYSTAL INPUTS For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. LVPECL OUTPUTS All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. REF_CLK INPUT For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the REF_CLK to ground. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. IDT ™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER 9 ICS843207CY-350 REV. A DECEMBER 3, 2007 ICS843207-350 FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER PRELIMINARY TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are 3.3V Zo = 50Ω 125Ω FOUT FIN 125Ω Zo = 50Ω Zo = 50Ω FOUT 50Ω 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 4A. LVPECL OUTPUT TERMINATION IDT ™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER 84Ω FIGURE 4B. LVPECL OUTPUT TERMINATION 10 ICS843207CY-350 REV. A DECEMBER 3, 2007 ICS843207-350 FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER PRELIMINARY POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS843207-350. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843207-350 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 210mA = 727.65mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 7 * 30mW = 210mW Total Power_MAX (3.63V, with all outputs switching) = 727.65mW + 210mW = 937.65mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming air flow at 1 meter per second and a multi-layer board, the appropriate value is 55.9°C/W per Table 8 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.938W *55.9°C/W = 122.4°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 8. THERMAL RESISTANCE θJA FOR 48-PIN LQFP, FORCED CONVECTION θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards IDT ™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER 0 1 2.5 65.7°C/W 55.9°C/W 52.4°C/W 11 ICS843207CY-350 REV. A DECEMBER 3, 2007 ICS843207-350 FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER PRELIMINARY 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CCO • For logic high, V OUT (V -V CCO_MAX • =V =V OH_MAX – 0.9V CCO_MAX ) = 0.9V OH_MAX For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V (VCCO_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/R ] * (VCCO_MAX - VOH_MAX) = L L [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/R ] * (VCCO_MAX - VOL_MAX) = L L [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW IDT ™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER 12 ICS843207CY-350 REV. A DECEMBER 3, 2007 ICS843207-350 FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER PRELIMINARY RELIABILITY INFORMATION TABLE 9. θJAVS. AIR FLOW TABLE FOR 48 LEAD LQFP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 65.7°C/W 55.9°C/W 52.4°C/W TRANSISTOR COUNT The transistor count for ICS843207-350 is: 4380 IDT ™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER 13 ICS843207CY-350 REV. A DECEMBER 3, 2007 ICS843207-350 FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER PRELIMINARY PACKAGE OUTLINE - Y SUFFIX FOR 48 LEAD LQFP TABLE 10. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL BBC MINIMUM NOMINAL MAXIMUM 48 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.17 0.22 0.27 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.50 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.50 Ref. e 0.50 BASIC 0.60 0.75 L 0.45 θ 0° -- 7° ccc -- -- 0.08 Reference Document: JEDEC Publication 95, MS-026 IDT ™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER 14 ICS843207CY-350 REV. A DECEMBER 3, 2007 ICS843207-350 FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER PRELIMINARY TABLE 11. ORDERING INFORMATION Part/Order Number 843207CY-350 Marking Package Shipping Packaging Temperature 43207C350 48 Lead LQFP tray 0°C to 70°C 843207CY-350T 43207C350 48 Lead LQFP 1000 tape & reel 0°C to 70°C 843207CY-350LF 3207C350L 48 Lead "Lead-Free" LQFP tray 0°C to 70°C 843207CY-350LFT 3207C350L 48 Lead "Lead-Free" LQFP 1000 tape & reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER 15 ICS843207CY-350 REV. A DECEMBER 3, 2007 ICS843207-350 FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER PRELIMINARY Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA