IDT ICS9UMS9633B Ultra mobile pc/mobile internet device Datasheet

Advance Information
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
ICS9UMS9633B
Recommended Application:
Features/Benefits:
Poulsbo Based Ultra-Mobile PC (UMPC)
•
Supports Dothan ULV CPUs with 67 to 167
MHz CPU outputs
Output Features:
•
Dedicated TEST/SEL and TEST/MODE pins
saves isolation resistors on pins
•
CPU STOP# input for power manangment
•
Fully integrated Vreg
•
Integrated series resistors on differential
outputs
•
1.5V VDD IO operation, 3.3V VDD core and
REF supply pin for REF
•
Industrial Temperature (-40 to +85C) version
available
•
3 - CPU low power differential push-pull pairss
•
3 - SRC low power differential push-pull pairs
•
1 - LCD100 SSCD low power differential
push-pull pair
•
1 - DOT96 low power differential push-pull
pair
•
1 - REF, 14.31818MHz, 3.3V SE output
REF
GNDREF
VDDCORE_3.3
FSC_L
TEST_MODE
TEST_SEL
SCLK
SDATA
VDDCORE_3.3
VDDIO_1.5
DOT96C_LPR
DOT96T_LPR
GNDDOT
GNDLCD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LCD100C_LPR
LCD100T_LPR
VDDIO_1.5
VDDCORE_3.3
*CR#0
GNDSRC
SRCC0_LPR
SRCT0_LPR
*CR#1
VDDCORE_3.3
15
16
17
18
19
20
21
22
23
24
9UMS9633
SSOP Pin Configuration
48
47
46
45
44
43
42
41
40
39
38
37
36
35
VDDREF_3.3
X1
X2
CLKPWRGD#/PD_3.3
CPU_STOP#
CPUT0_LPR
CPUC0_LPR
VDDIO_1.5
GNDCPU
CPUT1_LPR
CPUC1_LPR
VDDCORE_3.3
VDDIO_1.5
GNDCPU
34
33
32
31
30
29
28
27
26
25
CPUT2_LPR
CPUC2_LPR
FSB_L
*CR#2
SRCT2_LPR
SRCC2_LPR
GNDSRC
SRCT1_LPR
SRCC1_LPR
VDDIO_1.5
48 SSOP Package
* indicates inputs with internal pull up of ~10Kohm to 3.3V
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ICS9UMS9633B
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
Advance Information
SSOP Pin Description
PIN #
PIN NAME
1 REF
2 GNDREF
3 VDDCORE_3.3
4
FSC_L
5
TEST_MODE
6
TEST_SEL
7
8
9
10
SCLK
SDATA
VDDCORE_3.3
VDDIO_1.5
11
DOT96C_LPR
12
DOT96T_LPR
13
14
GNDDOT
GNDLCD
15
LCD100C_LPR
16
LCD100T_LPR
17
18
19
20
VDDIO_1.5
VDDCORE_3.3
*CR#0
GNDSRC
21
SRCC0_LPR
22
SRCT0_LPR
23
24
*CR#1
VDDCORE_3.3
TYPE
DESCRIPTION
OUT 14.318 MHz reference clock.
PWR Ground pin for the REF outputs.
PWR 3.3V power for the PLL core
Low threshold input for CPU frequency selection. Refer to input electrical
IN
characteristics for Vil_FS and Vih_FS values.
TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode
IN
while in test mode. Refer to Test Clarification Table.
TEST_SEL: latched input to select TEST MODE
IN
1 = All outputs are tri-stated for test
0 = All outputs behave normally.
IN
Clock pin of SMBus circuitry, 5V tolerant.
I/O Data pin for SMBus circuitry, 3.3V tolerant.
PWR 3.3V power for the PLL core
PWR Power supply for low power differential outputs, nominal 1.5V.
Complement clock of low power differential pair for 96.00MHz DOT clock. No 50ohm
OUT
resistor to GND needed. No Rs needed.
True clock of low power differential pair for 96.00MHz DOT clock. No 50ohm resistor
OUT
to GND needed. No Rs needed.
PWR Ground pin for DOT clock output
PWR Ground pin for LCD clock output
Complement clock of low power differential pair for LCD100 SS clock. No 50ohm
OUT
resistor to GND needed. No Rs needed.
True clock of low power differential pair for LCD100 SS clock. No 50ohm resistor to
OUT
GND needed. No Rs needed.
PWR Power supply for low power differential outputs, nominal 1.5V.
PWR 3.3V power for the PLL core
IN
Clock request for SRC0, 0 = enable, 1 = disable
PWR Ground pin for the SRC outputs
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm
OUT
series resistor. No 50ohm resistor to GND needed.
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series
OUT
resistor. No 50ohm resistor to GND needed.
IN
Clock request for SRC1, 0 = enable, 1 = disable
PWR 3.3V power for the PLL core
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ICS9UMS9633B
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Advance Information
SSOP Pin Description (continued)
PIN #
PIN NAME
25 VDDIO_1.5
26
SRCC1_LPR
27
SRCT1_LPR
28
GNDSRC
29
SRCC2_LPR
30
SRCT2_LPR
31
*CR#2
32
FSB_L
33
CPUC2_LPR
34
CPUT2_LPR
35
36
37
GNDCPU
VDDIO_1.5
VDDCORE_3.3
38
CPUC1_LPR
39
CPUT1_LPR
40
41
GNDCPU
VDDIO_1.5
42
CPUC0_LPR
43
CPUT0_LPR
44
CPU_STOP#
45
CLKPWRGD#/PD_3.3
46
47
48
X2
X1
VDDREF_3.3
TYPE
DESCRIPTION
PWR Power supply for low power differential outputs, nominal 1.5V.
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm
OUT
series resistor. No 50ohm resistor to GND needed.
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series
OUT
resistor. No 50ohm resistor to GND needed.
PWR Ground pin for the SRC outputs
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm
OUT
series resistor. No 50ohm resistor to GND needed.
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series
OUT
resistor. No 50ohm resistor to GND needed.
IN
Clock request for SRC2, 0 = enable, 1 = disable
Low threshold input for CPU frequency selection. Refer to input electrical
IN
characteristics for Vil_FS and Vih_FS values.
Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated
OUT
33ohm series resistor. No 50 ohm resistor to GND needed.
True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm
OUT
series resistor. No 50 ohm resistor to GND needed.
PWR Ground pin for the CPU outputs
PWR Power supply for low power differential outputs, nominal 1.5V.
PWR 3.3V power for the PLL core
Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated
OUT
33ohm series resistor. No 50 ohm resistor to GND needed.
True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm
OUT
series resistor. No 50 ohm resistor to GND needed.
PWR Ground pin for the CPU outputs
PWR Power supply for low power differential outputs, nominal 1.5V.
Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated
OUT
33ohm series resistor. No 50 ohm resistor to GND needed.
True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm
OUT
series resistor. No 50 ohm resistor to GND needed.
IN
Stops all CPU clocks, except those set to be free running clocks
IN
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs
are valid and are ready to be sampled. This is an active low input. / Asynchronous
active high input pin used to place the device into a power down state.
OUT Crystal output, Nominally 14.318MHz
IN
Crystal input, Nominally 14.318MHz.
PWR Power pin for the XTAL and REF clocks, nominal 3.3V
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ICS9UMS9633B
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
FSB_L
CPUC2_LPR
CPUT2_LPR
GNDCPU
VDDCORE_3.3
CPUC1_LPR
CPUT1_LPR
GNDCPU
VDDIO_1.5
CPUT0_LPR
CPUC0_LPR
MLF Pin Configuration
VDDIO_1.5
Advance Information
48 47 46 45 44 43 42 41 40 39 38 37
CPU_STOP#
CLKPWRGD#/PD_3.3
X2
X1
VDDREF_3.3
REF
GNDREF
VDDCORE_3.3
FSC_L
TEST_MODE
TEST_SEL
SCLK_3.3
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
ICS9UMS9633
*CR#2
SRCT2_LPR
SRCC2_LPR
GNDSRC
SRCT1_LPR
SRCC1_LPR
VDDIO_1.5
VDDCORE_3.3
*CR#1
SRCT0_LPR
SRCC0_LPR
GNDSRC
*CR#0
VDDCORE_3.3
VDDIO_1.5
LCD100T_LPR
LCD100C_LPR
GNDLCD
GNDDOT
DOT96T_LPR
DOT96C_LPR
VDDIO_1.5
VDDCORE_3.3
SDATA_3.3
13 14 15 16 17 18 19 20 21 22 23 24
48-pin MLF, 6x6 mm, 0.4mm pitch
* indicates inputs with internal pull up of ~10Kohm to 3.3V
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ICS9UMS9633B
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
Advance Information
MLF Pin Description
PIN #
PIN NAME
1 CPU_STOP#
TYPE
DESCRIPTION
IN
Stops all CPU clocks, except those set to be free running clocks
2
CLKPWRGD#/PD_3.3
IN
3
4
5
6
7
8
X2
X1
VDDREF_3.3
REF
GNDREF
VDDCORE_3.3
9
FSC_L
IN
10
TEST_MODE
IN
11
TEST_SEL
IN
12
13
14
15
SCLK_3.3
SDATA_3.3
VDDCORE_3.3
VDDIO_1.5
IN
I/O
PWR
PWR
16
DOT96C_LPR
OUT
17
DOT96T_LPR
OUT
18
19
GNDDOT
GNDLCD
PWR
PWR
20
LCD100C_LPR
OUT
21
LCD100T_LPR
OUT
22
23
24
VDDIO_1.5
VDDCORE_3.3
*CR#0
PWR
PWR
IN
OUT
IN
PWR
OUT
PWR
PWR
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs
are valid and are ready to be sampled. This is an active low input. / Asynchronous
active high input pin used to place the device into a power down state.
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Power pin for the XTAL and REF clocks, nominal 3.3V
14.318 MHz reference clock.
Ground pin for the REF outputs.
3.3V power for the PLL core
Low threshold input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values.
TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode
while in test mode. Refer to Test Clarification Table.
TEST_SEL: latched input to select TEST MODE
1 = All outputs are tri-stated for test
0 = All outputs behave normally.
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
3.3V power for the PLL core
Power supply for low power differential outputs, nominal 1.5V.
Complement clock of low power differential pair for 96.00MHz DOT clock. No 50ohm
resistor to GND needed. No Rs needed.
True clock of low power differential pair for 96.00MHz DOT clock. No 50ohm resistor
to GND needed. No Rs needed.
Ground pin for DOT clock output
Ground pin for LCD clock output
Complement clock of low power differential pair for LCD100 SS clock. No 50ohm
resistor to GND needed. No Rs needed.
True clock of low power differential pair for LCD100 SS clock. No 50ohm resistor to
GND needed. No Rs needed.
Power supply for low power differential outputs, nominal 1.5V.
3.3V power for the PLL core
Clock request for SRC0, 0 = enable, 1 = disable
IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device
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ICS9UMS9633B
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
Advance Information
MLF Pin Description (continued)
PIN #
PIN NAME
25 GNDSRC
26
SRCC0_LPR
27
SRCT0_LPR
28
29
30
*CR#1
VDDCORE_3.3
VDDIO_1.5
31
SRCC1_LPR
32
SRCT1_LPR
33
GNDSRC
34
SRCC2_LPR
35
SRCT2_LPR
36
*CR#2
37
FSB_L
38
CPUC2_LPR
39
CPUT2_LPR
40
41
42
GNDCPU
VDDIO_1.5
VDDCORE_3.3
43
CPUC1_LPR
44
CPUT1_LPR
45
46
GNDCPU
VDDIO_1.5
47
CPUC0_LPR
48
CPUT0_LPR
TYPE
DESCRIPTION
PWR Ground pin for the SRC outputs
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm
OUT
series resistor. No 50ohm resistor to GND needed.
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series
OUT
resistor. No 50ohm resistor to GND needed.
IN
Clock request for SRC1, 0 = enable, 1 = disable
PWR 3.3V power for the PLL core
PWR Power supply for low power differential outputs, nominal 1.5V.
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm
OUT
series resistor. No 50ohm resistor to GND needed.
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series
OUT
resistor. No 50ohm resistor to GND needed.
PWR Ground pin for the SRC outputs
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm
OUT
series resistor. No 50ohm resistor to GND needed.
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series
OUT
resistor. No 50ohm resistor to GND needed.
IN
Clock request for SRC2, 0 = enable, 1 = disable
Low threshold input for CPU frequency selection. Refer to input electrical
IN
characteristics for Vil_FS and Vih_FS values.
Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated
OUT
33ohm series resistor. No 50 ohm resistor to GND needed.
True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm
OUT
series resistor. No 50 ohm resistor to GND needed.
PWR Ground pin for the CPU outputs
PWR Power supply for low power differential outputs, nominal 1.5V.
PWR 3.3V power for the PLL core
Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated
OUT
33ohm series resistor. No 50 ohm resistor to GND needed.
True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm
OUT
series resistor. No 50 ohm resistor to GND needed.
PWR Ground pin for the CPU outputs
PWR Power supply for low power differential outputs, nominal 1.5V.
Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated
OUT
33ohm series resistor. No 50 ohm resistor to GND needed.
True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm
OUT
series resistor. No 50 ohm resistor to GND needed.
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ICS9UMS9633B
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
Advance Information
Funtional Block Diagram
REF
X1
X2
OSC
SRC(2:0)
CPU, SRC
SS-PLL
CPU(2:0)
LCD
SS-PLL
LCD100_SSC
96M
Non-SS
PLL
DOT96MHz
FSLC
FSLB
CKPWRGD/PD#
CPU_STOP#
CR#(2:0)
TESTSEL
Control
Logic
TESTMODE
SMBDAT
SMBCLK
Power Groups
Pin Number
Description
VDD GND
41, 46
Low power outputs
40, 45 CPUCLK
42
VDDCORE_3.3V
30
Low power outputs
25, 33 SRCCLK
29
VDDCORE_3.3V
22
Low power outputs
LCDCLK
19
23
VDDCORE_3.3V
15
Low power outputs
18 DOT 96Mhz
14
VDDCORE_3.3V
Xtal, REF
5
7
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ULTRA MOBILE PC/MOBILE INTERNET DEVICE
Advance Information
Absolute Maximum Ratings
PARAMETER
SYMBOL
CONDITIONS
3.3V Supply Voltage
VDDxxx_3.3
Supply Voltage
3.9
V
1,2
1.5V Supply Voltage
VDDxxx_1.5
Supply Voltage
2.1
V
1,2
VDD_3.3+
0.3V
V
1,2,3
V
1
3.3_Input High Voltage
VIH3.3
3.3V Inputs
Minimum Input Voltage
VIL
Any Input
Storage Temperature
Input ESD protection
Ts
ESD prot
MIN
MAX
GND - 0.5
°
-
-65
Human Body Model
2000
V
1,2
Man Machine Model
200
V
1,2
1
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied, nor guaranteed.
3
Maximum input voltage is not to exceed maximum VDD
150
UNITS Notes
C
1,2
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS Notes
Ambient Operating Temp
Tambient
No Airflow
0
70
°C
1
3.3V Supply Voltage
VDDxxx_3.3
3.3V +/- 5%
3.135
3.465
V
1
1.5V Supply Voltage
VDDxxx_1.5
1.5V +/- 5%
1.425
1.575
V
1
3.3V Input High Voltage
VIHSE3.3
Single-ended inputs
2
VDD + 0.3
V
1
3.3V Input Low Voltage
VILSE3.3
Single-ended inputs
VSS - 0.3
0.8
V
1
Input Leakage Current
IIN
-5
5
uA
1
Input Leakage Current
IINRES
VIN = VDD , VIN = GND
Inputs with pull or pull down
resistors (CR# pins)
VIN = VDD , VIN = GND
-200
200
uA
1
Output High Voltage
VOHSE
Single-ended outputs, IOH = -1mA
V
1
Output Low Voltage
Low Threshold InputHigh Voltage
Low Threshold InputLow Voltage
VOLSE
Single-ended outputs, IOL = 1 mA
0.4
V
1
VIH_FS
3.3 V +/-5%
0.7
1.5
V
1
VIL_FS
3.3 V +/-5%
VSS - 0.3
0.35
V
1
IDD_DEFAULT
3.3V supply, LCDPLL off
55
mA
1
IDD_LCDEN
60
mA
1
50
mA
1
IDD_PD3.3
3.3V supply, LCDPLL enabled
1.5V supply, Differential IO current,
all outputs enabled
3.3V supply, Power Down Mode
1
mA
1
IDD_PDIO
1.5V IO supply, Power Down Mode
0.1
mA
1
Input Frequency
Fi
VDD = 3.3 V
15
MHz
2
Pin Inductance
Lpin
7
nH
1
CIN
Logic Inputs
5
pF
1
Input Capacitance
COUT
Output pin capacitance
6
pF
1
CINX
X1 & X2 pins
5
pF
1
fSSMOD
Triangular Modulation
33
kHz
1
Operating Supply Current
IDD_IO
Power Down Current
Spread Spectrum Modulation
Frequency
2.4
1.5
IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device
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Advance Information
AC Electrical Characteristics - Input/Common Parameters
PARAMETER
SYMBOL
Clk Stabilization
TSTAB
Tdrive_SRC
T DRSRC
Tdrive_PD#
TDRPD
Tdrive_CPU
T DRSRC
Tfall_PD#
T FALL
Trise_PD#
T RISE
CONDITIONS
From VDD Power-Up or deassertion of PD# to 1st clock
SRC output enable after
PCI_STOP# de-assertion
Differential output enable after
PD# de-assertion
CPU output enable after
CPU_STOP# de-assertion
MIN
Fall/rise time of PD# and
CPU_STOP# inputs
MAX
UNITS Notes
1.8
ms
1
15
ns
1
300
us
1
10
ns
1
5
ns
1
5
ns
1
AC Electrical Characteristics - Low Power Differential Outputs
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
Rising Edge Slew Rate
tSLR
Differential Measurement
0.5
4
UNITS NOTES
V/ns
1,2
0.5
1,2
Falling Edge Slew Rate
tFLR
Differential Measurement
4
V/ns
Rise/Fall Time Variation
tSLVAR
Single-ended Measurement
125
ps
1
Maximum Output Voltage
VHIGH
Includes overshoot
1150
mV
1
Minimum Output Voltage
VLOW
Includes undershoot
-300
mV
1
Differential Voltage Swing
VSWING
Differential Measurement
300
mV
1
300
550
mV
1,3,4
140
mV
1,3,5
55
%
1
Crossing Point Voltage
VXABS
Single-ended Measurement
Crossing Point Variation
VXABSVAR
Single-ended Measurement
Duty Cycle
DCYC
Differential Measurement
CPU Jitter - Cycle to Cycle
CPUJ C2C
Differential Measurement
85
ps
1
SRC Jitter - Cycle to Cycle
SRCJ C2C
Differential Measurement
125
ps
1
DOT Jitter - Cycle to Cycle
DOTJ C2C
Differential Measurement
250
ps
1
CPU[2:0] Skew
CPUSKEW10
Differential Measurement
100
ps
1
SRC[2:0] Skew
SRCSKEW
Differential Measurement
250
ps
1
45
Electrical Characteristics - REF-14.318MHz
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
Long Accuracy
ppm
see Tperiod min-max values
-300
300
ppm
Clock period
Tperiod
14.318MHz output nominal
69.8203
69.8622
ns
2
Absolute min/max period
Tabs
14.318MHz output nominal
69.8203
70.86224
ns
2
Output High Voltage
VOH
IOH = -1 mA
2.4
V
1
Output Low Voltage
VOL
IOL = 1 mA
0.4
V
1
Output High Current
IOH
-33
-33
mA
1
Output Low Current
IOL
30
38
mA
1
VOH @MIN = 1.0 V,
VOH@MAX = 3.135 V
VOL @MIN = 1.95 V,
VOL @MAX = 0.4 V
UNITS Notes
1,2
Rising Edge Slew Rate
tSLR
Measured from 0.8 to 2.0 V
1
4
V/ns
1
Falling Edge Slew Rate
tFLR
Measured from 2.0 to 0.8 V
1
4
V/ns
1
Duty Cycle
dt1
VT = 1.5 V
45
55
%
1
Jitter
tjcyc-cyc
VT = 1.5 V
1000
ps
1
IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device
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ICS9UMS9633B
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
Advance Information
Electrical Characteristics - SMBus Interface
PARAMETER
SYMBOL
SMBus Voltage
VDD
CONDITIONS
Low-level Output Voltage
Current sinking at
VOLSMB = 0.4 V
SCLK/SDATA
Clock/Data Rise Time
SCLK/SDATA
Clock/Data Fall Time
Maximum SMBus Operating
Frequency
VOLSMB
@ IPULLUP
IPULLUP
SMB Data Pin
T FI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
F SMBUS
Block Mode
T RI2C
MIN
MAX
2.7
3.3
V
1
0.4
V
1
mA
1
1000
ns
1
300
ns
1
100
kHz
1
4
UNITS Notes
Notes on Electrical Characteristics:
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured through Vswing centered around differential zero
3
Vxabs is defined as the voltage where CLK = CLK#
4
Only applies to the differential rising edge (CLK rising and CLK# falling)
Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of
CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets
CLK#. The average cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate
calculations.
5
6
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz
7
Operation under these conditions is neither implied, nor guaranteed.
8
Maximum input voltage is not to exceed maximum VDD
9
See PCI Clock-to-Clock Delay Figure
Clock Periods Differential Outputs with Spread Spectrum Enabled
Measurement Window
Symbol
1 Clock
1us
0.1s
0.1s
0.1s
1us
1 Clock
Lg-
-SSC
-ppm error
0ppm
+ ppm error
+SSC
Lg+
Short-term Long-Term
Average
Average
Period
Long-Term
Average
Short-term
Average
Period
Absolute
Period
Signal
Name
Definition
Minimum
Absolute
Period
9.99900
Minimum
Absolute
Period
9.99900
Nominal
Maximum
Maximum
Maximum
SRC 100
Minimum
Absolute
Period
9.87400
10.00000
10.00100
10.05130
10.17630
Units
ns
Notes
1,2
CPU 100
9.91400
9.99900
9.99900
10.00000
10.00100
10.05130
10.13630
ns
1,2
CPU 133
7.41425
7.49925
7.49925
7.50000
7.50075
7.53845
7.62345
ns
1,2
CPU 166
5.91440
5.99940
5.99940
6.00000
6.00060
6.03076
6.11576
ns
1,2
Units
ns
Notes
1,2
Clock Periods Differential Outputs with Spread Spectrum Disabled
Measurement Window
Symbol
1 Clock
1us
0.1s
0.1s
0.1s
1us
1 Clock
Lg-
-SSC
-ppm error
0ppm
+ ppm error
+SSC
Lg+
Short-term Long-Term
Average
Average
Period
Long-Term
Average
Short-term
Average
Period
Maximum
Maximum
Absolute
Period
Definition
Minimum
Absolute
Period
Minimum
Absolute
Period
9.99900
Nominal
Maximum
10.00000
10.00100
10.17630
CPU 100
9.91400
9.99900
10.00000
10.00100
10.13630
ns
1,2
CPU 133
7.41425
7.49925
7.50000
7.50075
7.62345
ns
1,2
CPU 166
5.91440
5.99940
6.00000
6.00060
6.11576
ns
1,2
10.16560
10.41560
10.41670
DOT 96
1
Guaranteed by design and characterization, not 100% tested in production.
10.41770
10.66770
ns
1,2
Signal Name
SRC 100
Minimum
Absolute
Period
9.87400
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device
1423—01/20/09
10
ICS9UMS9633B
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
Table 1: CPU Frequency Select Table
CPU
SRC
DOT
1
1
FSLC
FSLB
MHz
MHz
MHz
0
0
133.33
96.00
0
1
166.67 100.00
1
1
0
1
Advance Information
LCD
MHz
REF
MHz
100.00 14.318
100.00
Reserved
1. FSLC is a low-threshold input.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
Table 2: LCD Spread Select Table (Pin 20/21)
B1b5
B1b4
B1b3
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Table 3: CPU N-step Programming
CPU
(MHz)
133.33
166.67
100.00
200.00
Spread
Comment
%
-0.5%
LCD100
-1%
LCD100
-2%
LCD100
-2.5%
LCD100
+/- 0.25% LCD100
+/-0.5% LCD100
+/-1%
LCD100
+/-1.25% LCD100
P
3
3
4
2
Default N
(hex)
64
7D
64
64
Fcpu
= 4MHz x N/P
= 4MHz x N/P
= 4MHz x N/P
= 4MHz x N/P
CPU Power Management Table
SMBus Register
PD
CPU_STOP#
CPU
CPU#
OE
0
Enable
Running Running
1
X
Enable
Low/20K
Low
1
0
Enable
High
Low
0
0
X
Low/20K
Low
Disable
SRC, LCD, DOT Power Management Table
PD
CR_x#
SMBus Register
OE
0
1
0
0
0
X
1
X
Enable
X
Enable
Disable
SRC
SRC#
Running Running
Low/20K
Low
Low/20K
Low
Low/20K
Low
DOT/LCD DOT#/LCD#
Running
Low/20K
Running
Low/20K
Running
Low
Running
Low
REF Power Management Table
PD
SMBus Register
OE
REF
0
1
0
Enable
X
Disable
Running
Low
Low
IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device
1423—01/20/09
11
ICS9UMS9633B
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
Advance Information
General I2C serial interface information for the ICS9UMS9633B
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2(H)
WR
WRite
Controller (Host)
T
starT bit
Slave Address D2(H)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device
Not acknowledge
stoP bit
1423—01/20/09
12
ICS9UMS9633B
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
Byte
Bit(s)
7
6
5
4
3
2
1
0
Byte
Bit(s)
7
6
5
4
3
2
1
0
Advance Information
0
PLL & Divider Enable Register
Pin #
Name
Description
This bit controls whether the PLL driving the CPU
PLL1 Enable
and SRC clocks is enabled or not.
This bit controls whether the PLL driving the DOT
PLL2 Enable
and clock is enabled or not.
This bit controls whether the PLL driving the LCD
PLL3 Enable
clock is enabled or not.
Reserved
This bit controls whether the CPU output divider is
enabled or not.
CPU Divider Enable
NOTE: This bit should be automatically set to ‘0’ if
bit 7 is set to ‘0’.
This bit controls whether the SRC output divider is
SRC Output Divider
enabled or not.
Enable
NOTE: This bit should be automatically set to ‘0’ if
bit 7 is set to ‘0’.
This bit controls whether the LCD output divider is
LCD Output Divider
enabled or not.
Enable
NOTE: This bit should be automatically set to ‘0’ if
bit 5 is set to ‘0’.
This bit controls whether the DOT output divider is
DOT Output Divider
enabled or not.
Enable
NOTE: This bit should be automatically set to ‘0’ if
bit 6 is set to ‘0’.
1
PLL SS Enable/Control Register
Pin #
Name
Description
This bit controls whether PLL1 has spread enabled
or not. Spread spectrum for PLL1 is set at -0.5%
PLL1 SS Enable
down-spread. Note that PLL1 drives the CPU and
SRC clocks.
PLL3 SS Enable
PLL3 FS Select
This bit controls whether PLL3 has spread enabled
or not. Note that PLL3 drives the SSC clock, and
that the spread spectrum amount is set in bits 3-5.
These 3 bits select the frequency of PLL3 and the
SSC clock when Byte 1 Bit 6 (PLL3 Spread
Spectrum Enable) is set.
Reserved
Reserved
Reserved
IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device
Type
0
1
Default
RW
0 = Disabled
1 = Enabled
1
RW
0 = Disabled
1 = Enabled
1
RW
0 = Disabled
1 = Enabled
1
0
RW
0 = Disabled
1 = Enabled
1
RW
0 = Disabled
1 = Enabled
1
RW
0 = Disabled
1 = Enabled
1
RW
0 = Disabled
1 = Enabled
1
Type
0
1
Default
RW
0 = Disabled
1 = Enabled
1
RW
0 = Disabled
1 = Enabled
1
RW
See Table 2: LCD Spread
Select Table
0
0
0
0
0
0
1423—01/20/09
13
ICS9UMS9633B
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
Byte
Bit(s)
7
6
5
4
3
2
1
0
Byte
Bit(s)
7
6
5
Advance Information
2
Output Enable Register
Pin #
Name
Description
This bit controls whether the CPU[0] output buffer
CPU0 Enable
is enabled or not.
This bit controls whether the CPU[1] output buffer
CPU1 Enable
is enabled or not.
This bit controls whether the CPU[2] output buffer
CPU2 Enable
is enabled or not.
This bit controls whether the SRC[0] output buffer
SRC0 Enable
is enabled or not.
This bit controls whether the SRC[1] output buffer
SRC1 Enable
is enabled or not.
This bit controls whether the SRC[2] output buffer
SRC2 Enable
is enabled or not.
This bit controls whether the DOT output buffer is
DOT Enable
enabled or not.
This bit controls whether the LCD output buffer is
LCD100 Enable
enabled or not.
3
Output Control Register
Pin #
Name
REF Enable
Description
Reserved
Reserved
This bit controls whether the REF output buffer is
enabled or not.
Type
0
1
Default
RW
0 = Disabled
1 = Enabled
1
RW
0 = Disabled
1 = Enabled
1
RW
0 = Disabled
1 = Enabled
1
RW
0 = Disabled
1 = Enabled
1
RW
0 = Disabled
1 = Enabled
1
RW
0 = Disabled
1 = Enabled
1
RW
0 = Disabled
1 = Enabled
1
RW
0 = Disabled
1 = Enabled
1
Type
0
1
Default
0
0
RW
0 = Disabled
1 = Enabled
1
4
REF Slew
These bits control the edge rate of the REF clock.
RW
3
2
1
0
This bit controls whether the CPU[0] output buffer
is free-running or stoppable. If it is set to stoppable
CPU0 Stop Enable
the CPU[0] output buffer will be disabled with the
assertion of CPU_STP#.
This bit controls whether the CPU[1] output buffer
is free-running or stoppable. If it is set to stoppable
CPU1 Stop Enable
the CPU[1] output buffer will be disabled with the
assertion of CPU_STP#.
This bit controls whether the CPU[2] output buffer
is free-running or stoppable. If it is set to stoppable
CPU2 Stop Enable
the CPU[2] output buffer will be disabled with the
assertion of CPU_STP#.
IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device
00 = Slow Edge Rate
01 = Medium Edge Rate
10 = Fast Edge Rate
11 = Reserved
10
RW
Free Running
Stoppable
0
RW
Free Running
Stoppable
0
RW
Free Running
Stoppable
0
1423—01/20/09
14
ICS9UMS9633B
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
Byte
Bit(s)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
4
CPU PLL N Register
Pin #
Name
Byte
Bit(s)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
5
CPU PLL/N Register
Pin #
Name
CPU N Div7
CPU N Div6
CPU N Div5
CPU N Div4
CPU N Div3
CPU N Div2
CPU N Div1
CPU N Div0
Byte
Bit(s)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
6
Pin #
Reserved
Name
Byte
Bit(s)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
7
Pin #
Reserved
Name
Advance Information
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
N Divider Prog bit 8
CPU N Div8
Control Function
See Table 3: CPU N-step Programming
Type
0
1
Default
1
1
1
1
1
1
1
0
0
1
Default
X
X
X
X
X
X
X
X
RW
Type
RW
RW
RW
RW
RW
RW
RW
RW
Default depends on latched
input frequency.
Default for CPU = 166 is 7Dh.
Default for all other frequencies
is 64h.
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
0
1
Default
1
1
1
1
0
0
1
1
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
0
1
Default
0
0
0
0
0
0
0
0
IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device
1423—01/20/09
15
ICS9UMS9633B
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
Byte
Bit(s)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
8
Pin #
Byte
Bit(s)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Name
Advance Information
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
0
1
Default
0
0
0
0
0
0
0
0
9
LCD100 PLL N Register
Pin #
Name
Control Function
LCD100 N Div7
LCD100 N Div6
LCD100 N Div5
N Divider Programming Byte9 bit(7:0) and Byte8
LCD100 N Div4
bit7
LCD100 N Div3
LCD100 N Div2
LCD100 N Div1
LCD100 N Div0
Type
R
R
R
R
R
R
R
R
0
1
Default
X
X
X
X
X
X
X
X
Byte
Bit(s)
7
6
5
4
3
2
1
0
10
Status Readback Register
Pin #
Name
37
FSB
9
FSC
24
CR0# Readbk
28
CR1# Readbk
36
CR2# Readbk
Type
R
R
R
R
R
Byte
Bit(s)
7
6
5
4
3
2
1
0
11
Revision ID/Vendor ID Register
Pin #
Name
Rev Code Bit 3
Rev Code Bit 2
Rev Code Bit 1
Rev Code Bit 0
Vendor ID bit 3
Vendor ID bit 2
Vendor ID bit 1
Vendor ID bit 0
Byte
Bit(s)
7
6
5
4
3
2
1
0
12
Device ID Register
Pin #
Name
DEV_ID3
DEV_ID2
DEV_ID1
DEV_ID0
Description
Frequency Select B
Frequency Select C
Real time CR0# State Indicator
Real time CR1# State Indicator
Real time CR2# State Indicator
Reserved
Reserved
Reserved
Description
Revision ID
(0 for A rev)
Vendor ID
Description
Device ID MSB
Device ID 2
Device ID 1
Device ID LSB
Reserved
Reserved
Reserved
Reserved
IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device
See N-step programming
formula
0
1
See Table 1: CPU Frequency
Select Table
CR0# is Low CR0# is High
CR1# is Low CR1# is High
CR2# is Low CR2# is High
Type
R
R
R
R
R
R
R
R
0
Type
R
R
R
R
0
1
Vendor specific
1
Default
Latch
Latch
X
X
X
0
0
0
Default
X
X
X
X
0
0
0
1
Default
0
0
1
1
0
0
0
0
1423—01/20/09
16
ICS9UMS9633B
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
Byte
Bit(s)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
13
Pin #
Reserved Register
Name
Byte
Bit(s)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
14
Pin #
Reserved Register
Name
Byte
Bit(s)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
15 Byte Count Register
Pin #
Name
BC5
BC4
BC3
BC2
BC1
BC0
Advance Information
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
0
1
Default
0
0
0
0
0
0
0
0
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
0
1
Default
0
0
0
0
0
0
0
0
Control Function
Reserved
Reserved
Byte Count 5
Byte Count 4
Byte Count 3
Byte Count 2
Byte Count 1
Byte Count LSB
Type
0
1
Default
0
0
0
0
1
1
1
1
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Enables CPU N programming
Enables LCD N programming
Type
0
1
RW
RW
Disabled
Disabled
Enabled
Enabled
RW
RW
RW
RW
RW
RW
Specifies Number of bytes to
be read back during an SMBus
read.
Default is 0xF.
Bytes 16:40 are reserved
Byte
Bit(s)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
41
N Program Enable Register
Pin #
Name
CPU N Enable
LCD N Enable
IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device
Default
0
0
0
0
0
0
0
0
1423—01/20/09
17
ICS9UMS9633B
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
Advance Information
Test Clarification Table
Comments
HW
TEST_SEL
HW PIN
Power-up w/ TEST_SEL = 1 to enter test mode
Cycle power to disable test mode
TEST_MODE -->low Vth input
TEST_MODE is a real time input
TEST_MODE
OUTPUT
HW PIN
<0.35V
X
NORMAL
>0.7V
<0.35V
HI-Z
>0.7V
>0.7V
REF/N
IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device
1423—01/20/09
18
ICS9UMS9633B
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
Advance Information
MLF Top Mark Information (9UMS9633BKLF)
48 47 46 45 44 43 42 41 40 39 38 37
1
2
3
4
5
6
7
8
9
10
11
12
ICS
UMS9633BL
YYWW
C of O
#######
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
Line 1. Company name
Line 2. Part Number
Line 3. YYWW = Date Code
Line 3. Country of Origin
Line 4. ####### = Lot Number
IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device
1423—01/20/09
19
ICS9UMS9633B
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
Advance Information
(Ref.)
Seating Plane
(N D -1)x e
(Ref.)
A1
Index Area
ND & N
Even
L
A3
N
N
Anvil
Singulation
1
E2
(N -1)x e
(Ref.)
E2
2
Sawn
Singulation
b
(Re f.)
A
D
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
are Even
2
OR
Top View
(Typ.)
e
2 If N & N
D
e
D2
2
ND & N
Odd
Thermal
Base
D2
0. 08
C
C
THERMALLY ENHANCED, VERY THIN, FINE PITCH
QUAD FLAT / NO LEAD PLASTIC PACKAGE
DIMENSIONS
SYMBOL
A
A1
A3
b
e
DIMENSIONS
MIN.
MAX.
0.8
1.0
0
0.05
0.20 Reference
0.18
0.3
0.40 BASIC
SYMBOL
N
ND
NE
D x E BASIC
D2 MIN. / MAX.
E2 MIN. / MAX.
L MIN. / MAX.
48L
TOLERANCE
48
12
12
6.00 x 6.00
3.95 / 4.25
3.95 / 4.25
0.30 / 0.50
Ordering Information
9UMS9633BKLFT
Example:
XXXX B K LF T
Designation for tape and reel packaging
Lead Free, RoHS Compliant
Package Type
K = MLF
Revision Designator
Device Type
IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device
1423—01/20/09
20
ICS9UMS9633B
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
Advance Information
SYMBOL
A
A1
b
c
D
E
E1
e
h
L
N
a
300 mil SSOP
In Millimeters
COMMON DIMENSIONS
MIN
MAX
2.41
2.80
0.20
0.40
0.20
0.34
0.13
0.25
SEE VARIATIONS
10.03
10.68
7.40
7.60
0.635 BASIC
0.38
0.64
0.50
1.02
SEE VARIATIONS
0°
8°
In Inches
COMMON DIMENSIONS
MIN
MAX
.095
.110
.008
.016
.008
.0135
.005
.010
SEE VARIATIONS
.395
.420
.291
.299
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
0°
8°
VARIATIONS
N
48
D mm.
MIN
15.75
D (inch)
MAX
16.00
MIN
.620
MAX
.630
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
9UMS9633BFLFT
Example:
XXXX B F LF T
Designation for tape and reel packaging
Lead Free, RoHS Compliant
Package Type
F = SSOP
Revision Designator
Device Type
IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device
1423—01/20/09
21
ICS9UMS9633B
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
Advance Information
Revision History
Rev.
0.1
0.2
0.3
0.4
0.5
Issue Date Description
12/06/07 Initial Release
1. Byte 4 default value changed to FF hex
02/27/08 2. Byte 6 default value changed to F3 hex.
1. Corrected Reference in Byte 5 to CPU NDIV8. Should refer to
Byte 4, bit 0.
2. Corrected Reference in LCD100 NDIV to only refer to Byte 9
3. Corrected headings in clock period table.
4. Added N-step programming info.
05/21/08 5. Corrected Byte 4 default value
11/12/08 Removed reference to 1.5V inputs
01/20/09 Updated SMBus byte 4/5; added CPU N-Step Programming table
Page #
-
Various
11,15
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Printed in USA
22