ICX282AK
Diagonal 11mm (Type 2/3) Frame Readout CCD Image Sensor with Square Pixel for Color Cameras
Description
The ICX282AK is a diagonal 11mm (Type 2/3)
interline CCD solid-state image sensor with a square
pixel array and 5.07M effective pixels. Frame readout
allows all pixels' signals to be output independently
within approximately 1/3.75 second. In addition, output
is possible using various addition and pulse elimination
methods. This chip features an electronic shutter with
variable charge-storage time. Adoption of a design
specially suited for frame readout ensures a saturation
signal level equivalent to that when using field readout.
High resolution and high color reproductively are
achieved through the use of Ye, Cy, Mg and G
complementary color mosaic filters as the color filters.
Further, high sensitivity and low dark current are
achieved through the adoption of Super HAD CCD
technology.
This chip is suitable for applications such as
electronic still cameras, PC input cameras, etc.
24 pin DIP (Plastic)
Features
• High horizontal and vertical resolution
• Supports 10 types of readout modes
Frame readout mode, 2× speed mode (1), 2× speed mode (2), 8× speed mode,
center scan mode (1), center scan mode (2), center scan mode (3),
center scan mode (4), AF mode (1), AF mode (2)
• Square pixel
• Horizontal drive frequency: 22.5MHz
• No voltage adjustments (reset gate and substrate bias are not adjusted.)
• Ye, Cy, Mg and G complementary color mosaic filters on chip
• High sensitivity, low dark current, excellent anti-blooming characteristics
• Continuous variable-speed shutter
V
• Horizontal register, reset gate: 3.3V drive
• 24-pin high-precision plastic package
Pin 1
2
Device Structure
12
• Interline CCD image sensor
58
H
Pin 13
• Image size:
Diagonal 11mm (Type 2/3)
• Total number of pixels:
2658 (H) × 1970 (V) approx. 5.24M pixels
• Number of effective pixels: 2588 (H) × 1960 (V) approx. 5.07M pixels
Optical black position
• Number of active pixels: 2580 (H) × 1944 (V) approx. 5.02M pixels
(Top View)
• Number of recommended recording pixels:
2560 (H) × 1920 (V) approx. 4.92M pixels
• Chip size:
9.74mm (H) × 7.96mm (V)
• Unit cell size:
3.4µm (H) × 3.4µm (V)
• Optical black:
Horizontal (H) direction: Front 12 pixels, rear 58 pixels
Vertical (V) direction:
Front 8 pixels, rear 2 pixels
• Number of dummy bits:
Horizontal 28
Vertical 1 (even fields only)
• Substrate material:
Silicon
8
∗ Super HAD CCD is a registered trademark of Sony Corporation. Super HAD CCD is a CCD that drastically improves sensitivity by introducing
newly developed semiconductor technology by Sony Corporation into Sony's high-performance HAD (Hole-Accumulation Diode) sensor.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E01626A31-PS
ICX282AK
GND
Vφ1C
Vφ1B
Vφ1A
NC
NC
Vφ2
Vφ3C
Vφ3B
Vφ3A
Vφ4
12
11
10
9
8
7
6
5
4
3
2
1
Vertical register
GND
Block Diagram and Pin Configuration
(Top View)
Ye
Cy
Ye
Cy
G
Mg
G
Mg
Ye
Cy
Ye
Cy
G
Mg
G
Mg
Ye
Cy
Ye
Cy
G
Mg
G
Mg
Ye
Cy
Ye
Cy
G
Mg
G
Mg
Note)
Horizontal register
GND
NC
21
22
23
24
Hφ2A
Hφ1B
20
Hφ1A
19
VL
18
CSUB
17
φSUB
16
Hφ2B
VDD
15
φRG
14
VOUT
Note)
13
: Photo sensor
Pin Description
Pin No. Symbol
Description
Pin No.
Symbol
Description
1
Vφ4
Vertical register transfer clock
13
VOUT
Signal output
2
Vφ3A
Vertical register transfer clock
14
VDD
Supply voltage
3
Vφ3B
Vertical register transfer clock
15
φRG
Reset gate clock
4
Vφ3C
Vertical register transfer clock
16
Hφ2B
Horizontal register transfer clock
5
Vφ2
Vertical register transfer clock
17
Hφ1B
Horizontal register transfer clock
6
NC
18
GND
GND
7
NC
19
NC
8
Vφ1A
Vertical register transfer clock
20
φSUB
9
Vφ1B
Vertical register transfer clock
21
CSUB
Substrate clock
Substrate bias∗1
10
Vφ1C
Vertical register transfer clock
22
VL
Protective transistor bias
11
GND
GND
23
Hφ1A
Horizontal register transfer clock
12
GND
GND
24
Hφ2A
Horizontal register transfer clock
∗1 DC bias is generated within the CCD, so that this pin should be grounded externally through a
capacitance of 0.1µF.
–2–
ICX282AK
Absolute Maximum Ratings
Item
Ratings
Unit
–40 to +12
V
–50 to +15
V
–50 to +0.3
V
–40 to +0.3
V
CSUB – φSUB
–25 to
V
VDD, VOUT, φRG, CSUB – GND
–0.3 to +22
V
–10 to +18
V
–10 to +6.5
V
–0.3 to +28
V
–0.3 to +15
V
to +15
V
–6.5 to +6.5
V
–10 to +16
V
Storage temperature
–30 to +80
°C
Guaranteed temperature of performance
–10 to +60
°C
Operating temperature
–10 to +75
°C
VDD, VOUT, φRG – φSUB
Vφ1α, Vφ3α – φSUB (α =
Against φSUB
A to C)
Vφ2, Vφ4, VL – φSUB
Hφ1β, Hφ2β, GND – φSUB (β =
Against GND
Vφ1α, Vφ2, Vφ3α, Vφ4 – GND (α =
Hφ1β, Hφ2β – GND (β =
Against VL
A, B)
Vφ1α, Vφ3α – VL (α =
A to C)
A, B)
A to C)
Vφ2, Vφ4, Hφ1β, Hφ2β, GND – VL (β =
A, B)
Voltage difference between vertical clock input pins
Between input
clock pins
Hφ1β – Hφ2β (β =
A, B)
Hφ1β, Hφ2β – Vφ4 (β =
A, B)
∗1 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
+16V (Max.) is guaranteed for turning on or off power supply.
–3–
Remarks
∗1
ICX282AK
Bias Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
Supply voltage
VDD
14.55
15.45
V
Protective transistor bias
VL
15.0
∗1
Substrate clock
φSUB
∗2
Reset gate clock
φRG
∗2
Remarks
∗1 VL setting is the VVL voltage of the vertical clock waveform, or the same voltage as the VL power supply
for the V driver should be used.
∗2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated
within the CCD.
DC Characteristics
Item
Supply current
Symbol
Min.
Typ.
Max.
Unit
IDD
4.0
7.0
10.0
mA
Remarks
Clock Voltage Conditions
Item
Readout clock voltage
Vertical transfer clock
voltage
Horizontal transfer
clock voltage
Reset gate clock
voltage
Substrate clock voltage
Symbol
Waveform
diagram
Remarks
Min.
Typ.
Max. Unit
VVT
14.55
15.0
15.45
V
1
VVH1, VVH2
–0.05
0
0.05
V
2
VVH3, VVH4
–0.2
0
0.05
V
2
VVL1, VVL2,
VVL3, VVL4
–8.0
–7.5
–7.0
V
2
VVL = (VVL3 + VVL4)/2
VφV
6.8
7.5
8.05
V
2
VφV = VVHn – VVLn (n = 1 to 4)
VVH = (VVH1 + VVH2)/2
VVH3 – VVH
–0.25
0.1
V
2
VVH4 – VVH
–0.25
0.1
V
2
VVHH
0.6
V
2
High-level coupling
VVHL
0.9
V
2
High-level coupling
VVLH
0.9
V
2
Low-level coupling
VVLL
0.5
V
2
Low-level coupling
VφH
3.0
3.3
3.6
V
3
VHL
–0.05
0
0.05
V
3
VCR
0.5
1.65
V
3
VφRG
3.0
3.3
3.6
V
4
VRGLH – VRGLL
0.4
V
4
Low-level coupling
VRGL – VRGLm
0.5
V
4
Low-level coupling
23.5
V
5
VφSUB
21.5
22.5
–4–
Cross-point voltage
ICX282AK
Clock Equivalent Circuit Constant
Item
Symbol
Min.
Typ.
Max. Unit Remarks
CφV1γ, CφV3γ
1800
pF
CφV1B, CφV3B
6800
pF
CφV2, CφV4
5600
pF
CφV1γ 2, CφV3γ4
560
pF
CφV1B2, CφV3B4
680
pF
CφV23γ, CφV41γ
180
pF
CφV23B, CφV41B
270
pF
CφV1γ 3γ
56
pF
CφV1B3B
330
pF
CφV1γ 3B, CφV1B3γ
91
pF
CφV24
120
pF
CφV1γ1B, CφV3γ 3B
100
pF
Capacitance between horizontal transfer clock
and GND
CφH1
82
pF
CφH2
62
pF
Capacitance between horizontal transfer clocks
CφHH
110
pF
Capacitance between reset gate clock and GND
CφRG
5
pF
Capacitance between substrate clock and GND
CφSUB
1500
pF
R1γ, R3γ
62
Ω
R1B, R2, R3B, R4
43
Ω
Vertical transfer clock ground resistor
RGND
16
Ω
Horizontal transfer clock series resistor
RφH
7.5
Ω
Capacitance between vertical transfer clock
and GND
Capacitance between vertical transfer clocks
Vertical transfer clock series resistor
Note 1) γ = A, C for each vertical transfer clock capacitance.
Note 2) The relationships of V1A = V1C and V3A = V3C are established for each vertical transfer clock
capacitance.
Note 3) CφV1A1C and CφV3A3C are sufficiently small relative to other capacitance between vertical transfer
clocks, and are also below the measurement limit, so these are omitted from the equivalent circuit
diagrams and the above table.
Vφ2
Vφ1γ (γ = A, C)
R1γ
R2
CφV1γ 3γ
CφV24
CφV1γ 2
CφV23γ
Vφ3γ (γ = A, C)
R3γ
RφH
RφH
Hφ1A
Hφ2A
CφV23B
CφV1B2
CφV2
CφV1γ
CφV1γ 1B
CφV1B3γ
CφV1B
CφV4
CφV41γ
CφV3γ
CφV3γ 3B
CφV3B CφV1γ 3B
RφH
Hφ2B
CφHH
CφV3γ 4
CφH1
Vφ1B
R1B
RφH
Hφ1B
CφV41B
RGND
CφV3B4
CφV1B3B
R3B
CφH2
Vφ3B
R4
Vφ4
Horizontal transfer clock equivalent circuit
Vertical transfer clock equivalent circuit
–5–
ICX282AK
Drive Clock Waveform Conditions
(1) Readout clock waveform
100%
90%
φM
VVT
φM
2
10%
0%
tr
twh
0V
tf
(2) Vertical transfer clock waveform
Vφ1A, Vφ1B, Vφ1C
VVH1
Vφ3A, Vφ3B, Vφ3C
VVHH
VVH
VVHH
VVHL
VVHL
VVHL
VVL1
VVHH
VVHH
VVH3
VVH
VVHL
VVL3
VVLH
VVLH
VVLL
VVLL
VVL
VVL
Vφ2
Vφ4
VVHH
VVHH
VVH
VVH
VVHH
VVHH
VVHL
VVHL
VVH2 VVHL
VVH4
VVLH
VVL2VVLH
VVLL
VVLL
VVL4
VVL
VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2
VφV = VVHn – VVLn (n = 1 to 4)
VVHL
–6–
VVL
ICX282AK
(3) Horizontal transfer clock waveform
tr
twh
tf
Hφ2A, Hφ2B
90%
VCR
VφH
twl
VφH
2
10%
VHL
Hφ1A, Hφ1B
two
Cross-point voltage for the Hφ1 rising side of the horizontal transfer clocks Hφ1 and Hφ2 waveforms is VCR.
The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.
(4) Reset gate clock waveform
tr
twh
tf
VRGH
RG waveform
twl
VφRG
Point A
VRGLH
VRGL
VRGLL
VRGLm
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG.
In addition, VRGL is the average value of VRGLH and VRGLL.
VRGL = (VRGLH + VRGLL)/2
Assuming VRGH is the minimum value during the interval with twh, then:
VφRG = VRGH – VRGL
Negative overshoot level during the falling edge of RG is VRGLm.
(5) Substrate clock waveform
100%
90%
φM
VφSUB
10%
VSUB
0%
(A bias generated within the CCD)
tr
twh
–7–
φM
2
tf
ICX282AK
Clock Switching Characteristics (Horizontal drive frequency: 22.5MHz)
Item
Symbol
Readout clock
VT
twh
twl
tr
tf
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
2.47 2.67
0.5
0.5
Vφ1A, Vφ1B,
Vertical transfer Vφ1C, Vφ2,
Vφ3A, Vφ3B,
clock
Vφ3C, Vφ4
15
µs
350 ns
Horizontal
transfer clock
Hφ1A, Hφ1B 13
16
13
16
6.5 9.5
6.5 9.5
Hφ2A, Hφ2B 13
16
13
16
6.5 9.5
6.5 9.5
Reset gate
clock
φRG
8
Substrate clock φSUB
Item
Symbol
Horizontal
transfer clock
Hφ1A, Hφ1B,
Hφ2A, Hφ2B
6
31
3
2.0 2.58
two
Min. Typ. Max.
11
16
ns
Remarks
During
readout
When using
CXD3400N
During
imaging,
tf ≥ tr – 2ns
ns
3
0.5
Unit
0.5
µs
During drain
charge
Unit Remarks
ns
Spectral Sensitivity Characteristics (excludes lens characteristics and light source characteristics)
1.0
Ye
Cy
0.8
Relative Response
G
0.6
0.4
0.2
Mg
0
400
450
500
550
Wave Length [nm]
–8–
600
650
700
ICX282AK
Image Sensor Characteristics
Item
(Ta = 25°C)
Symbol
Min.
Typ.
Sensitivity
S
264
330
Sensitivity
comparison
RMgG
0.75
1.35
RYeCy
1.10
1.43
Vsat
450
Vsat2
900
Saturation signal
Smear
Sm
Max.
Unit
Measurement
method
mV
1
–84
–86
–78
–80
–72
20
Video signal shading SH
25
1/30s accumulation,
no line addition∗1, ∗2
2
mV
–92
Remarks
dB
No line addition∗1
2-line addition∗3
3
Ta = 60°C
4
Frame readout mode∗4
2× speed mode (1)∗5
8× speed mode
%
5
Zone 0 and I
Zone 0 to II'
Dark signal
Vdt
16
mV
6
Ta = 60°C, 3.75 frame/s
Dark signal shading
∆Vdt
8
mV
7
Ta = 60°C, 3.75 frame/s, ∗6
Lag
Lag
0.5
%
8
∗1 Frame readout mode, 2× speed mode (1), and center scan modes (1), (2), (3) and (4).
∗2 When the accumulation time is constant, 2-line addition modes have a sensitivity double that of modes
without line addition.
∗3 2× speed mode (2), 8× speed mode, and AF mode (1), (2)
∗4 After closing the mechanical shutter, the smear can be reduced to below the detection limit by performing
vertical register sweep operation. This is also the same for 2× speed mode (2) and center scan modes (3)
and (4).
∗5 Smear can be reduced by approximately 30dB to a level of approximately –116dB (typ.) by performing the
following sequence.
Vertical register high-speed transfer → Readout (SG) → Mechanical shutter closed → Signal output
∗6 Excludes vertical dark signal shading caused by vertical register high-speed transfer.
Zone Definition of Video Signal Shading
2588 (H)
4
4
8
H
8
V
10
H
8
Zone 0, I
1960 (V)
8
Zone II, II'
V
10
Ignored region
Effective pixel region
–9–
ICX282AK
Measurement System
CCD signal output [∗A]
CCD
C.D.S
AMP
S/H
G/Ye channel signal output [∗B]
S/H
Mg/Cy channel signal output [∗C]
Note) Adjust the amplifier gain so that the gain between [∗A] and [∗B], and between [∗A] and [∗C] equals 1.
Image Sensor Characteristics Measurement Method
Measurement conditions
(1) In the following measurements, the device drive conditions are at the typical values of the bias and clock
voltage conditions, and the frame readout mode is used.
(2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical
black level (OB) is used as the reference for the signal output, which is taken as the value of the Y signal
output or chroma signal output of the measurement system.
Color coding of this image sensor & Composition of luminance (Y) and chroma (color difference) signals
B2
B1
Ye
Cy
Ye
Cy
G
Mg
G
Mg
Ye
Cy
Ye
Cy
G
Mg
G
Mg
A2
The complementary color filters of this image sensor are
arranged in the layout shown in the figure on the left.
For frame readout, the A1 and A2 lines are output as signals in
the A field, and the B1 and B2 lines in the B field.
A1
Horizontal register
Color Coding Diagram
These signals are processed to form the Y signal and chroma (color difference) signal sa follws.
The approximation:
Y ={G + Mg + Ye + Cy} × 1/4
= 1/4 {2B + 3G +2R}
is used for the Y signal, and the approximation:
R – Y = {(Mg + Ye) – (G +Cy}
= {2R –G}
B – Y = {(Mg + Cy) – (G +Ye)}
= {2B –G}
are used for the chroma (color difference) signal.
– 10 –
ICX282AK
Readout modes list
The readout method, frame rate, number of output lines and other information for each readout mode are
shown in the table below.
Mode
Frame
readout
Readout
method
Frame
readout
2× speed (1) 2/4 lines
High-speed
Addition
sweep for
preventing smear method
NTSC
PAL
Number of output
effective image data
lines
Frame rate [frame/s]
Yes
None
3.75
3.57
1960
Yes
None
7.49
7.14
980
Yes
Vertical
2 lines
6.66
6.25
980
2× speed (2)
Frame
readout
8× speed
4/16 lines
None
Vertical
2 lines
29.97
25
245
Center scan
(1)
2/4 lines
None
None
14.985
12.5
NTSC: 484, PAL: 587
Center scan
(2)
2/4 lines
None
None
26.35
246
Center scan
(3)
Frame
readout
Yes
None
7.02
968
Center scan
(4)
Frame
readout
Yes
None
11.988
10
NTSC: 492, PAL: 620
AF (1)
4/16 lines
None
Vertical
2 lines
59.94
50
NTSC: 104, PAL: 128
AF (2)
4/16 lines
None
Vertical
2 lines
119.88
100
NTSC: 34, PAL: 46
– 11 –
ICX282AK
Description of frame readout mode
The output methods for the following readout modes are shown below.
Frame readout mode
1st field
VOUT
2× speed mode (1)
2/4-line readout
2nd field
17 (V1A)
G
Mg
17 (V1A)
G
Mg
17 (V1A)
G
Mg
16 (V3B)
Ye
Cy
16 (V3B)
Ye
Cy
16 (V3B)
Ye
Cy
15 (V1B)
G
Mg
15 (V1B)
G
Mg
15 (V1B)
G
Mg
14 (V3A)
Ye
Cy
14 (V3A)
Ye
Cy
14 (V3A)
Ye
Cy
13 (V1C)
G
Mg
13 (V1C)
G
Mg
13 (V1C)
G
Mg
12 (V3B)
Ye
Cy
12 (V3B)
Ye
Cy
12 (V3B)
Ye
Cy
11 (V1B)
G
Mg
11 (V1B)
G
Mg
11 (V1B)
R
Mg
10 (V3A)
Ye
Cy
10 (V3A)
Ye
Cy
10 (V3A)
Ye
Cy
9 (V1C)
G
Mg
9 (V1C)
G
Mg
9 (V1C)
G
Mg
8 (V3B)
Ye
Cy
8 (V3B)
Ye
Cy
8 (V3B)
Ye
Cy
7 (V1B)
G
Mg
7 (V1B)
G
Mg
7 (V1B)
G
Mg
6 (V3C)
Ye
Cy
6 (V3C)
Ye
Cy
6 (V3C)
Ye
Cy
5 (V1A)
G
Mg
5 (V1A)
G
Mg
5 (V1A)
G
Mg
4 (V3B)
Ye
Cy
4 (V3B)
Ye
Cy
4 (V3B)
Ye
Cy
3 (V1B)
G
Mg
3 (V1B)
G
Mg
3 (V1B)
G
Mg
2 (V3C)
Ye
Cy
2 (V3C)
Ye
Cy
2 (V3C)
Ye
Cy
1 (V1A)
G
Mg
1 (V1A)
G
Mg
1 (V1A)
G
Mg
VOUT
VOUT
Note) Blacked out portions in the diagram indicate pixels which are not read out.
1. Frame readout mode
In this mode, all pixel signals are divided into two fields and output.
All pixel signals are read out independently, making this mode suitable for high resolution image capturing.
2. 2× speed mode (1) 2/4-line readout
All effective area signals are output in half the time of frame readout mode by reading out 2 lines for every 4
lines.
The number of output lines is halved, but all color signals can be output in a single field, so exposure
completed is read out (SG), making high-speed shutter operation possible.
However, note that the G/Mg and Ye/Cy line readout timings have a time difference of approximately 6.7µs
(150clk).
In addition, using high-speed sweep transfer and the mechanical shutter is recommended to suppress
smear.
Smear is reduced by approximately 30dB by performing the following sequence.
Vertical register high-speed transfer → Readout (SG) → Mechanical shutter closed → Signal output
– 12 –
ICX282AK
2× speed mode (2) 2-line addition
1st field
VOUT
8× speed mode
4/16-line readout
2nd field
17 (V1A)
G
Mg
17 (V1A)
G
Mg
17 (V1A)
G
Mg
16 (V3B)
Ye
Cy
16 (V3B)
Ye
Cy
16 (V3B)
Ye
Cy
15 (V1B)
G
Mg
15 (V1B)
G
Mg
15 (V1B)
G
Mg
14 (V3A)
Ye
Cy
14 (V3A)
Ye
Cy
14 (V3A)
Ye
Cy
13 (V1C)
G
Mg
13 (V1C)
G
Mg
13 (V1C)
G
Mg
12 (V3B)
Ye
Cy
12 (V3B)
Ye
Cy
12 (V3B)
Ye
Cy
11 (V1B)
G
Mg
11 (V1B)
G
Mg
11 (V1B)
G
Mg
10 (V3A)
Ye
Cy
10 (V3A)
Ye
Cy
10 (V3A)
Ye
Cy
9 (V1C)
G
Mg
9 (V1C)
G
Mg
9 (V1C)
G
Mg
8 (V3B)
Ye
Cy
8 (V3B)
Ye
Cy
8 (V3B)
Ye
Cy
7 (V1B)
G
Mg
7 (V1B)
G
Mg
7 (V1B)
G
Mg
6 (V3C)
Ye
Cy
6 (V3C)
Ye
Cy
6 (V3C)
Ye
Cy
5 (V1A)
G
Mg
5 (V1A)
G
Mg
5 (V1A)
G
Mg
4 (V3B)
Ye
Cy
4 (V3B)
Ye
Cy
4 (V3B)
Ye
Cy
3 (V1B)
G
Mg
3 (V1B)
G
Mg
3 (V1B)
G
Mg
2 (V3C)
Ye
Cy
2 (V3C)
Ye
Cy
2 (V3C)
Ye
Cy
1 (V1A)
G
Mg
1 (V1A)
G
Mg
1 (V1A)
G
Mg
VOUT
VOUT
Note) Blacked out portions in the diagram indicate pixels which are not read out.
3. 2× speed mode (2) 2-line addition
In this mode, the G/Mg line is read out in the 1st field and the Ye/Cy line in the 2nd field, 2 lines are
transferred during the horizontal blanking period, and 2 lines are added in the horizontal register.
All pixel signals are divided into two fields and output in approximately half the time (slightly longer than half)
of frame readout mode.
At this time, the sensitivity (for 1/30s accumulation) and saturation signal level are double that during frame
readout mode, allowing high sensitivity imaging with a wide dynamic range.
4. 8× speed mode, 4/16-line readout
All effective area signals are output in 1/8 the time of frame readout mode by reading out 4 lines for every 16
lines, transferring 4 lines during the horizontal blanking period, and adding 2 lines in the horizontal register.
The number of output lines is 245 lines.
However, note that the G/Mg and Ye/Cy line readout timings have a time difference of approximately 6.7µs
(150clk).
This mode emphasizes processing speed over vertical resolution, making it suitable for AE/AF and other
control and for image verification on LCD viewfinders.
– 13 –
ICX282AK
Center scan mode (1) 484-line output
Center scan mode (2) 246-line output
Undesired portion
(Swept by vertical register high-speed transfer)
V: 968 pixels
Undesired portion
(Swept by vertical register high-speed transfer)
V: 492 pixels
Picture center cut-out portion
Picture center cut-out portion
5. Center scan mode (1) 484-line output
This mode sweeps the undesired portions by vertical register high-speed transfer, and outputs only the vertical
968-pixel region of the picture center by reading out 2 lines for every 4 lines (like 2× speed mode (1)).
The number of output lines is 484 lines.
The frame rate is increased (approximately 15 frames/s) by setting the number of vertical output lines to that
of VGA mode, making this mode suitable for VGA moving pictures. (However, the angle of view is equivalent
to 2× electronic zoom.)
6. Center scan mode (2) 246-line output
This mode sweeps the undesired portions by vertical register high-speed transfer, and outputs only the vertical
492-pixel region of the picture center by reading out 2 lines for every 4 lines (like 2× speed mode (1)).
The number of output lines is 246 lines.
This mode is suitable for enlarged display when verifying image on LCD viewfinders.
Center scan mode (3) 968-line output
Center scan mode (4) 492-line output
Undesired portion
(Swept by vertical register high-speed transfer)
V: 968 pixels
Undesired portion
(Swept by vertical register high-speed transfer)
V: 492 pixels
Picture center cut-out portion
– 14 –
Picture center cut-out portion
ICX282AK
7. Center scan mode (3) 968-line output
This mode sweeps the undesired portions by vertical register high-speed transfer, and outputs only the
vertical 968-pixel region of the the picture center divided into two fields (like frame readout mode).
The number of output lines is 968 lines.
This mode is used to shorten the frame rate when shooting 2× electronic zoom image.
8. Center scan mode (4) 492-line output
This mode sweeps the undesired portions by vertical register high-speed transfer, and outputs only the
vertical 492-pixel region of the picture center divided into two fields (like frame readout mode).
The number of output lines is 492 lines.
This mode is used to shorten the frame rate when shooting 4× electronic zoom image.
AF mode (1), (2)
Undesired portion
(Swept by vertical register high-speed transfer)
Picture center cut-out portion
AF mode (2)
V: 272 pixels
AF mode (1)
V: 832 pixels
9. AF modes (1), (2)
The AF modes are used to achieve even higher-speed AF control than 8× speed mode.
AF mode (1) outputs only the vertical 832-pixel (in NTSC mode) region of the picture center at
approximately 60 frames/s by reading out 4 lines for every 16 lines (like 8× speed mode).
AF mode (2) outputs only the vertical 272-pixel (in NTSC mode) region of the picture center at
approximately 120 frames/s by reading out 4 lines for every 16 lines (like 8× speed mode).
The number of output lines for each mode is shown below.
AF mode (1)
AF mode (2)
NTSC mode
60 frame/s
104 lines
120 frame/s
34 lines
PAL mode
50 frame/s
128 lines
100 frame/s
46 lines
– 15 –
ICX282AK
Definition of standard imaging conditions
(1) Standard imaging condition I:
Use a pattern box (luminance: 706cd/m2, color temperature of 3200K halogen source) as a subject.
(Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR
cut filter and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined
as the standard sensitivity testing luminous intensity.
(2) Standard imaging condition II:
Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.
Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is
adjusted to the value indicated in each testing item by the lens diaphragm.
1.
Sensitivity
Set to the standard imaging condition I. After selecting the electronic shutter mode with a shutter
speed of 1/100s, measure the signal outputs (VG, VMg, VYe and VCy) at the center of each G, Mg, Ye and
Cy channel screen, and substitute the values into the following formulas.
V = (VG + VMg + VYe + VCy)/4
S = V × 100 [mV]
30
2.
Saturation comparison
Set to the standard imaging condition II: Adjust the luminous intensity so that the average value of the G/
Mg/Ye/Cy channel signal output is 150mV, and then measure the Mg signal output (SMg [mV]) and G signal
output (SG [mV]), and the Ye signal output (SYe [mV]) and Cy signal output (SCy [mV]) at the center of the
screen. Substitute the values into the following formulas.
RMgG = SMg/SG
RYeCy = SYe/SCy
3.
Satutation signal
Set to standaed imageing condition II. After adjusting the luminous intensity to 10 times the intsnsity with the
avarage value of the G/Mg/Ye/Cy channel signal output, 150mV, measure the minimum values of the G,
Mg, Ye and Cy signal outputs.
4.
Smear
Set to the standard imaging condition II. With the lens diaphragm at F5.6 to F8, first adjust the luminous
intensity to 500 times the intensity with the average value of the G/Mg/Ye/Cy channel signal output,
150mV. After the readout clock is stopped and the charge drain is executed by the electronic shutter at the
respective H blankings, measure the maximum value (VSm [mV]) independent of the G, Mg, Ye and Cy
signal outputs, and substitute the values into the following formula.
The smear for modes other than frame readout mode is calculated from the storage time and signal
addition method. As a result, 2× speed mode (2) is the same, 2× speed mode (1) is double, and 8× speed
mode is 4 times that for frame readout mode.
Sm = 20 × log ( VSm × 1 × 1 ) [dB] (1/10V method conversion value)
500
150
10
– 16 –
ICX282AK
5.
Video signal shading
Set to the standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjusting the luminous
intensity so that the average value of the G/Mg/Ye/Cy channel signal output is 200mV. Then measure the
maximum value (Vmax [mV]) and minimum value (Vmin [mV]) of the G/Mg/Ye/Cy channel signal output
and substitute the values into the following formula.
SH = (Vmax – Vmin)/150 × 100 [%]
6.
Dark signal
Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature of 60°C
and the device in the light-obstructed state, using the horizontal idle transfer level as a reference.
7.
Dark signal shading
After measuring 6, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark
signal output and substitute the values into the following formula.
∆Vdt = Vdmax – Vdmin [mV]
8.
Lag
Adjust the G/Mg/Ye/Cy channel output generated by the strobe light to 150mV. After setting the strobe light
so that it strobes with the following timing, measure the residual signal amount (Vlag). Substitute the value
into the following formula.
Lag = (Vlag/150) × 100 [%]
VD
V1A/V1B/V1C
Light
Strobe light timing
G/Mg/Ye/Cy channel
signal output 150mV
Output
– 17 –
Vlag (lag)
ICX282AK
Drive Circuit
–7.5V 15V
3.3V
0.1
1/35V
1
20
XSUB
2
19
XV3
3
18
XSG3B
4
17
XSG3A
5
0.1
XV1
6
15
XSG1B
7
14
XSG1A
8
13
XV4
9
12
XV2
10
11
1
20
2
19
1
2
3
4
5
6
7
8
9
10 11 12
3
18
Vφ4
Vφ3B
Vφ3C
Vφ2
NC
NC
Vφ1A
Vφ1B
Vφ1C
16
Vφ3A
CXD3400N
100k
4
17
0.1
47
2SK1875
CSUB
VL
Hφ1A
GND
VOUT
13
3.3/20V
VDD
8
XSG1C
0.1
φRG
14
CCD OUT
1.8k
ICX282
(BOTTOM VIEW)
Hφ2B
7
16
Hφ1B
15
CXD3400N
GND
6
NC
5
XV1
φSUB
XSG3C
0.1
Hφ2A
XV3
GND
0.1
0.01
24 23 22 21 20 19 18 17 16 15 14 13
9
12
10
11
Hφ2A
Hφ1A
Hφ2B
Hφ1B
φRG
VR1 (2.7k)
0.1
Substrate bias
control signal
VSUB Cont.
Substrate bias
φSUB pin voltage
0.1
1M
Mechanical
shutter mode
tf ≈ 20ms
tr ≈ 2ms
3.3/16V
0.1
VSUB Cont.
GND
Internally
generated value
VSUB
Notes)
Substrate bias control
1. The saturation signal level decreases when exposure is performed using the mechanical shutter, so control
the substrate bias.
2. A saturation signal level equivalent to that for continuous exposure can be assured by connecting a 2.7kΩ
grounding registor to the CCD CSUB pin.
Drive timing precautions
1. Blooming occurs in modes (2× speed (1), 8× speed, etc.) where exposure is not completed by closing the
mechanical shutter, so do not ground the connected 2.7kΩ resistor.
2. tf is slow, so the internally generated voltage VSUB may not drop to a sufficiently low level if the substrate
bias control signal is not set to high level 30ms before entering the exposure period and the 2.7kΩ resistor
connected to the CSUB pin is not grounded.
3. The blooming signal generated during exposure in mechanical shutter mode is swept by providing one
field or more (two fields is recommended) of idle transfer through vertical register high-speed sweep
transfer from the time the mechanical shutter closes until sensor readout is performed. However, note that
the VL potential and the φSUB pin DC voltage sag at this time.
4. When exposure time is several seconds or more, we recommend the sequence that the substrate bias
control is performed just before the completion of exposure (Mechanical shutter is closed.), not before the
start of exposure.
– 18 –
Drive Timing Chart (Vertical Sequence)
Act.
× Speed Mode → Frame Readout Mode (or 2×
× Speed Mode (1)) / Electronic Shutter Normal Operation
8×
8× speed mode
Frame readout mode
Exposure operation
8× speed mode
VD
V1A
V1B/C
V2
V3A
– 19 –
V3B/C
V4
SUB
A
B
C
D
E
F
TRG
Mechanical
shutter
OPEN
CLOSE
OPEN
VSUB
Cont.
CCD
OUT
A output signal B output signal C output signal
D output signal (ODD)
D output signal (EVEN)
Output after
frame readout
E output signal F output signal
ICX282AK
∗ The B and C output signals contain a blooming component and should therefore not be used.
∗ Apply 20 or more electronic shutter pulses at the start of exposure for the recording image. If less than 20 pulses are applied, the electronic shutter may occur a discharge error.
Drive Timing Chart (Vertical Sequence)
Act.
× Speed Mode → 2×
× Speed Mode (1) / Electronic Shutter Normal Operation
8×
8× speed mode
Exposure operation
2× speed mode (1)
8× speed mode
VD
V1A
V1C
V1B
V2
– 20 –
V3A
V3C
V3B
V4
SUB
A
B
C
D
E
F
G
H
TRG
Mechanical
shutter
OPEN
CLOSE
OPEN
D output signal
Output after 2×
Speed Mode (1)
VSUB
Cont.
A output signal B output signal C output signal
E output signal F output signal G output signal H output signal
∗ The substrate bias control signal (VSUB Cont.) should not be used in the above sequence.
∗ Apply 20 or more electronic shutter pulses at the start of exposure for the recording image. If less than 20 pulses are applied, the electronic shutter may occur a discharge error.
ICX282AK
CCD
OUT
Drive Timing Chart (Vertical Sequence)
Act.
× Speed Mode → 2×
× Speed Mode (1) / High-speed Shutter Operation
8×
8× speed mode
Exposure operation
2× speed mode (1)
8× speed mode
VD
V1A
V1C
V1B
V2
– 21 –
V3A
V3C
V3B
V4
SUB
A
B
C
D
E
F
G
H
TRG
Mechanical
shutter
OPEN
CLOSE
OPEN
D output signal
Output after 2×
Speed Mode (1)
VSUB
Cont.
A output signal B output signal C output signal
E output signal F output signal G output signal H output signal
∗ The substrate bias control signal (V SUB Cont.) should not be used in the above sequence.
∗ Apply 20 or more electronic shutter pulses at the start of exposure for the recording image. If less than 20 pulses are applied, the electronic shutter may occur a discharge error.
ICX282AK
CCD
OUT
Drive Timing Chart (Vertical Sync)
NTSC/PAL
Frame Readout Mode
All pixel output period
Exposure period
VD
"a"
"d"
2177 2076
1
1
2
2
3
3
2072 2072
2068 2068
1084 1084
1069 1069
1060 1060
70
70
"c"
1055 1055
10
10
PAL
1
2
3
NTSC
1
2
3
HD
"b"
V1A/B/C
V2
V4
SUB
TRG
Mechanical
shutter
OPEN
CLOSE
OPEN
1954
1956
1958
1960
2
4
6
8
2
4
6
8
10
CCD
OUT
1953
1955
1957
1959
VSUB
Cont.
1
3
5
7
1
3
5
7
9
– 22 –
V3A/B/C
ICX282AK
∗ 2894fH. However, 2076H in NTSC mode is 950 clk, and 2177H in PAL mode is 2656 clk.
Also, the number of high-speed sweep transfer stages and the transfer speed differ for the 1st field and 2nd field sides, so the fields should not be reversed.
Drive Timing Chart (Vertical Sync)
Frame Readout Mode
Center Scan Mode (3) 968-line output
Center Scan Mode (4) 492-line output
''a'' Enlarged
166
89
1440
270
1380
2894
1
62
2894
1
62
270
H1A/B
166
1470
V1A/B/C
89
141
219
141
219
V2
193
193
V3A/B/C
– 23 –
115
1410
245
115
245
V4
''b'' Enlarged
297
1620
V1A/B/C
1560
1680
V2
1530 1590
1650
V3A/B/C
1710
ICX282AK
323
V4
Drive Timing Chart (Vertical Sync)
Frame Readout Mode / Center Scan Mode (3) / Center Scan Mode (4)
2×
× Speed Mode (1)
Center Scan Mode (1)
Center Scan Mode (2)
''c'' Enlarged
Frame readout mode / Center scan mode (3) / Center scan mode (4): 71H
2× speed mode: 48H, Center scan mode (1): 11H, Center scan mode (2): 17H
270
2894
1
62
270
2894
1
62
H1A/B
V1A/B/C
V3A/B/C
#1
#2
#3
#4
26
26
26
26
V4
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
– 24 –
V2
Frame readout mode:
Center scan mode (3):
Center scan mode (4):
2× speed mode (1):
Center scan mode (1):
Center scan mode (2):
#1970
#1970
#1970
#1335
#305
#472
ICX282AK
Drive Timing Chart (Vertical Sync)
Frame Readout Mode / Center Scan Mode (3) / Center Scan Mode (4)
''d'' Enlarged
Frame readout mode / Center scan mode (3) / Center scan mode (4): 25H
270
2894
1
62
270
2894
1
62
H1A/B
V1A/B/C
V2
#1
#2
#3
#4
18
18
18
18
V4
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
– 25 –
V3A/B/C
Frame readout mode: #986
Center scan mode (3): #986
Center scan mode (4): #986
ICX282AK
Drive Timing Chart (Horizontal Sync)
Frame readout mode
2×
× speed mode (1) 2/4-line readout
Center scan mode (1) 484-line output
Center scan mode (2) 246-line output
Center scan mode (3) 968-line output
Center scan mode (4) 492-line output
270
298
208
1
28
1
62
1
5
2894
315
Ignored pixel 4 bits
Ignored pixel 4 bits
12
58
1
1
CLK
RG
SHP
SHD
1
V1A/B/C
27
1
104
77
1
– 26 –
1
1
79
V2
1
51
78
1
131
V3A/B/C
1
77
1
V4
1
130
53
1
25
H1A/B
H2A/B
1
SUB
1
114
58
1
36
ICX282AK
Drive Timing Chart (Vertical Sync)
NTSC/PAL
× Speed Mode (1)
2×
2/4-line readout
Exposure period
Signal output period
VD
1089 1038
1036 1036
1030 1030
48
48
"e"
1020 1020
10
10
"c"
60
1
2
3
PAL
60
NTSC
1
2
3
HD
V1A/C
V1B
V2
V3B
V4
SUB
TRG
Mechanical
shutter
OPEN
CLOSE
OPEN
CCD
OUT
ICX282AK
∗ 2894fH. However, 1038H in NTSC mode is 1922 clk, and 1089H in PAL mode is 1328 clk.
1949
1950
1953
1954
1957
1958
VSUB
Cont.
2
5
6
1
2
5
6
9
10
– 27 –
V3A/C
Drive Timing Chart (Vertical Sync)
× Speed Mode (1) 2/4-line readout
2×
Center Scan Mode (1) 484-line output
Center Scan Mode (2) 246-line output
''e'' Enlarged
1380 1440
270
2894
1
62
270
2894
1
62
H1A/B
89
166
1470
166
89
166
1470
166
V1A/C
V1B
141
219
1560
219
V2
– 28 –
1530 1590
193
193
193
193
V3A/C
V3B
115
1410
1500
245
V4
ICX282AK
Drive Timing Chart (Vertical Sync)
NTSC/PAL
× Speed Mode (2)
2×
2-line addition
Signal output period
Exposure period
VD
"f"
586
586
1161 1090
1
1
2
2
3
3
573
573
"i"
1080 1080
565
565
561
66
66
"h"
561
10
10
PAL
1
2
3
NTSC
1
2
3
HD
"g"
V1A/B/C
V2
V4
SUB
TRG
CLOSE
CCD
OUT
1954 1956
1958 1960
3
7
3
7
11
15
19
VSUB
Cont.
4
8
4
8
12
16
20
OPEN
2
6
2
6
10
14
18
OPEN
1953 1955
1957 1959
Mechanical
shutter
1
5
1
5
9
13
17
– 29 –
V3A/B/C
ICX282AK
∗ 3102fH. However, 1089H and 1090H in NTSC mode are 1700 clk and 1699 clk, respectively, and 1161H in PAL mode is 1680 clk.
Also, the number of high-speed sweep transfer stages and the transfer speed differ for the 1st field and 2nd field sides, so the fields should not be reversed.
× Speed Mode (2)
2×
Drive Timing Chart (Vertical Sync)
2-line addition
'' f '' Enlarged
166
89
297
478
1380
374
3102
1
62
478
3102
1
62
H1A/B
1440
1470
166
V1A/B/C
374
297
89
141
219
349
427
141
219
349
427
V2
193
270
401
193
270
401
V3A/B/C
115
245
323
1410
453
115
245
323
453
– 30 –
V4
''g'' Enlarged
505
1620
V1A/B/C
1560
1680
V2
1530 1590
1650
V3A/B/C
531
1710
ICX282AK
V4
Drive Timing Chart (Vertical Sync)
× Speed Mode (2)
2×
2-line addition
''h'' Enlarged
2× Speed Mode (2): 67H
478
3102
1
62
478
3102
1
62
H1A/B
V1A/B/C
V2
#1
#2
#3
#4
26
26
26
26
V4
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
– 31 –
V3A/B/C
2× Speed Mode (2): #1970
ICX282AK
Drive Timing Chart (Vertical Sync)
2×
× Speed Mode (2)
2-line addition
'' i '' Enlarged
2× Speed Mode (2): 23H
478
3102
1
62
478
3102
1
62
H1A/B
V1A/B/C
V2
#1
#2
#3
#4
18
18
18
18
V4
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
– 32 –
V3A/B/C
2× Speed Mode (2): #986
ICX282AK
2×
× Speed Mode (2)
Drive Timing Chart (Horizontal Sync)
2-line addition
478
506
416
1
28
1
62
1
5
3102
523
Ignored pixel 4 bits
Ignored pixel 4 bits
12
58
1
1
CLK
RG
SHP
SHD
1
V1A/B/C
27
1
1
– 33 –
1
1
53
1
130
1
78
131
1
77
1
130
1
51
78
1
131
1
V3A/B/C
104
1
77
1
79
1
V2
V4
131
1
1
77
1
77
130
1
78
25
H1A/B
H2A/B
1
SUB
1
322
58
1
36
ICX282AK
1925
1934
1941
1950
1957
6
5
14
21
30
37
1925
1934
1941
1950
1957
6
5
14
21
30
37
2
1
10
17
26
33
1921
1930
1937
1946
1953
2
1
10
17
26
33
– 34 –
CCD
OUT
1921
1930
1937
1946
1953
NTSC
PAL
15
20
15
20
"j"
10
15
20
10
15
20
298 249
1
1
2
2
3
3
4
4
5
5
NTSC/PAL
245 245
10
10
298 249
1
1
2
2
3
3
4
4
5
5
245 245
Drive Timing Chart (Vertical Sync)
× Speed Mode
8×
VD
HD
"j"
V1A
V1B/C
V2
V3A
V3B/C
V4
∗ 3022fH. However, 249H in NTSC mode is 1294 clk, and 298H in PAL mode is 2466 clk.
ICX282AK
Drive Timing Chart (Vertical Sync)
× Speed Mode
8×
AF Mode (1)
AF Mode (2)
'' j '' Enlarged
73
398
1530 1590
3022
1
62
398
3022
1
62
H1A/B
1440
1320
V1A
73
V1B/C
94
1500
1410
– 35 –
V2
1380 1440
1470
1290
V3A
V3B/C
84
1350
1560
V4
ICX282AK
× Speed Mode
8×
AF Mode (1)
AF Mode (2)
Ignored pixel 4 bits
398
426
336
1
28
1
62
1
5
3022
Ignored pixel 4 bits
443
Drive Timing Chart (Horizontal Sync)
12
58
1
1
CLK
RG
SHP
SHD
1 11
1
1
V1A/B/C
1
– 36 –
1
1
1
22
53
1
1
53
1
52
1
1
32
1
52
1
1
52
1
32
1
53
1
31
1
32
42
31
1
52
1
32
1
1
53
31
1
52
31
1
1
31
32
53
1
V3A/B/C
V4
1
32
1
V2
1
53
31
53
1
31
52
1
1
20
32
1
31
52
1 10
32
H1A/B
H2A/B
11
SUB
1
245
58
1
33
ICX282AK
Drive Timing Chart (Vertical Sync)
NTSC/PAL
Center Scan Mode (1)
484-line output (in NTSC mode)
VD
"e"
33
12
12
33
9
9
"c"
20
519
1
2
3
622
1
2
3
"k"
"e"
20
33
12
12
33
9
9
"c"
20
519
1
2
3
PAL
20
NTSC
622
1
2
3
HD
"k"
V1A/C
V1B
V2
V3B
501
502
505
506
509
2
CCD
OUT
501
502
505
506
509
510
V4
2
– 37 –
V3A/C
∗ 2894fH. However, 519H in NTSC mode is 2408 clk, and 622H in PAL mode is 2826 clk.
ICX282AK
Drive Timing Chart (Vertical Sync)
Center Scan Mode (1) / Center Scan Mode (3)
Center Scan Mode (2) / Center Scan Mode (4)
''k'' Enlarged
Center Scan Mode (1) / Center Scan Mode (3): 18H
Center Scan Mode (2) / Center Scan Mode (4): 27H
89
270
2894
1
62
270
2894
1
62
H1A/B
166
V1A/B/C
141
219
V2
115
245
#1
27
26
26
25
27
26
26
25
V4
27
26
26
25
27
26
26
25
– 38 –
193
V3A/B/C
Center Scan Mode (1): #250
Center Scan Mode (3): #250
Center Scan Mode (2): #369
Center Scan Mode (4): #369
ICX282AK
Drive Timing Chart (Vertical Sync)
Center Scan Mode (2)
246-line output
VD
"c"
"k"
"e"
"c"
"e"
46
25
17
9
295
1
2
3
46
25
17
9
295
1
2
3
HD
"k"
V1A/C
V1B
V2
V3B
737
738
741
742
2
CCD
OUT
737
738
741
742
745
746
V4
2
– 39 –
V3A/C
∗ 2894fH.
ICX282AK
Drive Timing Chart (Vertical Sync)
Center Scan Mode (3)
968-line output
All pixel output period
Exposure period
VD
"c"
"a"
"k"
"d"
1106
1
2
3
621
601
586
576
91
70
10
1
2
3
HD
"b"
"k"
V1A/B/C
V2
V4
SUB
TRG
Mechanical
shutter
OPEN
CLOSE
OPEN
498
500
502
504
505
2
CCD
OUT
497
499
501
502
503
VSUB
Cont.
1
– 40 –
V3A/B/C
Also, the number of high-speed sweep transfer stages and the transfer speed differ for the 1st field and 2nd field sides, so the fields should not be reversed.
ICX282AK
∗ 2894fH.
Drive Timing Chart (Vertical Sync)
NTSC/PAL
Center Scan Mode (4)
492-line output (in NTSC mode)
All pixel output period
Exposure period
VD
"a"
"b"
647
649
1
2
3
647
778
1
2
3
372
372
"d"
400
357
357
"k"
400
347
70
70
347
10
10
"c"
99
1
2
3
PAL
99
NTSC
1
2
3
HD
"k"
V1A/B/C
V2
V4
SUB
TRG
Mechanical
shutter
OPEN
CLOSE
OPEN
736
738
740
742
2
CCD
OUT
735
737
739
741
VSUB
Cont.
1
– 41 –
V3A/B/C
ICX282AK
∗ 2894fH. However, 649H in NTSC mode is 1563 clk, and 778H in PAL mode is 1362 clk.
Also, the number of high-speed sweep transfer stages and the transfer speed differ for the 1st field and 2nd field sides, so the fields should not be reversed.
Drive Timing Chart (Vertical Sync)
NTSC/PAL
AF Mode (1)
VD
"j"
"m"
20
10
10
"l"
20
125
1
2
3
4
5
149
1
2
3
4
5
10
10
"m"
20
125
1
2
3
4
5
PAL
20
NTSC
149
1
2
3
4
5
HD
"j"
"l"
V1A
V1B/C
V3A
V3B/C
565
574
581
590
597
6
565
574
581
590
597
561
570
577
586
593
2
561
570
577
586
593
CCD
OUT
6
V4
2
– 42 –
V2
∗ 3022fH. However, 125H in NTSC mode is 647 clk, and 149H in PAL mode is 2744 clk.
ICX282AK
Drive Timing Chart (Vertical Sync)
AF Mode (1)
AF Mode (2)
'' l '' Enlarged
AF Mode (1): 8H, AF Mode (2): 12H
398
3022
1
62
398
3022
1
62
H1A/B
73
V1A/B/C
31 53 31 53
94
V2
32 52 32 52
– 43 –
V3A/B/C
31 53 31 53
84
V4
32 52 32 52
#1
#2
#3
#4
AF Mode (1): #276
AF Mode (2): #420
ICX282AK
Drive Timing Chart (Vertical Sync)
AF Mode (1)
AF Mode (2)
''m'' Enlarged
AF Mode (1): 8H, AF Mode (2): 12H
398
3022
1
62
398
3022
1
62
H1A/B
73
V1A/B/C
31 53 31 53
94
V2
– 44 –
32 52 32 52
V3A/B/C
31 53 31 53
84
V4
32 52 32 52
#1
#2
#3
#4
AF Mode (1): #285
AF Mode (2): #421
ICX282AK
Drive Timing Chart (Vertical Sync)
NTSC/PAL
AF Mode (2)
VD
"j"
20
10
10
"m"
"l"
20
63
1
2
3
4
5
75
1
2
3
4
5
10
10
"m"
20
63
1
2
3
4
5
PAL
20
NTSC
75
1
2
3
4
5
HD
"j"
"l"
V1A
V1B/C
V2
V3B/C
849 853
6
2
CCD
OUT
849 853
858 862
865 869
6
V4
2
– 45 –
V3A
∗ 3022fH. However, 63H in NTSC mode is 324 clk, and 75H in PAL mode is 1372 clk.
ICX282AK
ICX282AK
Notes on Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material.
Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensors.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.
2) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W
soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering
tool, use a thermal controller of the zero-cross On/Off type and connect it to ground.
3) Dust and dirt protection
Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and
dirt. Clean glass plates with the following operations as required, and use them.
a) Perform all assembly operations in a clean room (class 1000 or less).
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized
air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if grease stained. Be careful not to scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
e) When a protective tape is applied before shipping, just before use remove the tape applied for
electrostatic protection. Do not reuse the tape.
4) Installing (attaching)
a) Remain within the following limits when applying a static load to the package. Do not apply any load
more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to
limited portions. (This may cause cracks in the package.)
Cover glass
50N
50N
1.2Nm
Plastic package
Compressive strength
Torsional strength
b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the
package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for
installation, use either an elastic load, such as a spring plate, or an adhesive.
– 46 –
ICX282AK
c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated
voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area,
and indicated values should be transferred to other locations as a precaution.
d) The notch of the package is used for directional index, and that can not be used for reference of fixing.
In addition, the cover glass and seal resin may overlap with the notch of the package.
e) If the leads are bent repeatedly and metal, etc., clash or rub against the package, the dust may be
generated by the fragments of resin.
f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyano-acrylate
instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference)
5) Others
a) Do not expose to strong light (sun rays) for long periods, as color filters will be discolored. When high
luminous objects are imaged with the exposure level controlled by the electronic iris, the luminance of
the image-plane may become excessive and discoloring of the color filter will possibly be accelerated. In
such a case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the
power-off mode should be properly arranged. For continuous using under cruel condition exceeding the
normal using condition, consult our company.
b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
c) Brown stains may be seen on the bottom or side of the package. But this does not affect the CCD
characteristics.
– 47 –
Package Outline
Unit: mm
24 pin DIP
13
2.35
D
A
13
to
2.5
8.0
24
24
2.35
2.35
14.4
2.35
0.5
0.25
14.2 ± 0.1
7.1
2.5
8.2
B
13.2
C
0.8
12
13.7
1
0.5
2.5
2.9
13.0
0.8
– 48 –
3.5 ± 0.3
B
0.15
16.0 ± 0.1
1. “A” is the center of the effective image area.
2.4
2. The two points “B” of the package are the horizontal reference.
The point “B'” of the package is the vertical reference.
0.3
1.27
0.3
PACKAGE STRUCTURE
3. The bottom “C” of the package, and the top of the cover glass “D”
are the height reference.
4. The center of the effective image area relative to “B” and “B'”
is (H, V) = (8.0, 7.1) ± 0.075mm
5. The rotation angle of the effective image area relative to H and V is ±1˚.
6. The height from the bottom “C” to the effective image area is 1.41 ± 0.10mm.
The height from the top of the cover glass “D” to the effective image area is 1.49 ± 0.15mm.
Plastic
LEAD TREATMENT
GOLD PLATING
7. The tilt of the effective image area relative to the bottom “C” is less than 50µm.
The tilt of the effective image area relative to the top “D” of the cover glass is less than 50µm
LEAD MATERIAL
42 ALLOY
8. The thickness of the cover glass is 0.5mm, and the refractive index is 1.5.
PACKAGE MASS
1.23g
DRAWING NUMBER
AS-A9-02(E)
9. The notches on the bottom of the package are used only for directional index, they must
not be used for reference of fixing.
ICX282AK
Sony Corporation
PACKAGE MATERIAL