FAST CMOS BUFFER/CLOCK DRIVER IDT49FCT3805/A Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • • • • • • • • • • 0.5 MICRON CMOS Technology Guaranteed low skew < 500ps (max.) Very low duty cycle distortion < 1.0ns (max.) Very low CMOS power levels TTL compatible inputs and outputs Inputs can be driven from 3.3V or 5V components Two independent output banks with 3-state control 1:5 fanout per bank ‘Heartbeat’ monitor output Available in DIP, SOIC, SSOP, QSOP, Cerpack and LCC packages • Military product compliant to MIL-STD-883, Class B • VCC = 3.3V ± 0.3V The FCT3805/A is a 3.3 volt, non-inverting clock driver built using advanced dual metal CMOS technology. The device consists of two banks of drivers, each with a 1:5 fanout and its own output enable control. The device has a "heartbeat" monitor for diagnostics and PLL driving. The MON output is identical to all other outputs and complies with the output specifications in this document. The FCT3805/A offers low capacitance inputs with hysteresis. The FCT3805/A is designed for high speed clock distribution where signal quality and skew are critical. The FCT 3805 also allows single point-to-point transmission line driving in applications such as address distribution, where one signal must be distributed to multiple receivers with low skew and high signal quality. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS OEA INA INB 5 OA 1-OA 5 5 OB 1-OB 5 OE B VCCA 1 20 VCCB OA1 2 19 OB1 OA2 3 18 OB2 OA3 4 17 OB3 16 GNDB 15 OB4 14 OB5 P20-1 D20-1 SO20-2 SO20-7 SO20-8 & E20-1 GNDA 5 OA4 6 OA5 7 GNDQ 8 13 MON OEA 9 12 OEB INA 10 11 INB 3102 drw 02 OA3 4 GNDA 5 OA4 6 OA5 7 GNDQ 8 2 1 OB1 3 VCCB OA1 INDEX VCCA 3102 drw 01 OA2 DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW MON 20 19 L20-2 18 OB2 17 OB3 16 GNDB 15 OB4 14 OB5 MON OEB INB INA OEA 9 10 11 12 13 3102 drw 03 LCC TOP VIEW The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES 1996 Integrated Device Technology, Inc. 9.5 OCTOBER 1995 DSC-3102/4 1 IDT49FCT3805/A FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES FUNCTION TABLE(1) PIN DESCRIPTION Pin Names OEA, OEB Description 3-State Output Enable Inputs (Active LOW) INA, INB Clock Inputs OAn, OBn Clock Outputs MON Monitor Output Inputs 3102 tbl 01 Outputs OEA, OEB INA, INB OAn, OBn MON L L L L L H H H H L Z L H H Z H NOTE: 1. H = HIGH, L = LOW, Z = High Impedance ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating VTERM(2) Terminal Voltage with Respect to GND VTERM(3) Terminal Voltage with Respect to GND VTERM(4) Terminal Voltage with Respect to GND TA Operating Temperature TBIAS Temperature Under Bias TSTG Storage Temperature I OUT DC Output Current Commercial Military –0.5 to +4.6 –0.5 to +4.6 –0.5 to +7.0 –0.5 to +7.0 3102 tbl 02 CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Unit V V –0.5 to VCC + 0.5 –0.5 to VCC + 0.5 V 0 to +70 –55 to +125 °C –55 to +125 –65 to +135 °C –55 to +125 –65 to +150 °C –60 to +60 –60 to +60 mA Conditions VIN = 0V Typ. 3.5 VOUT = 0V 3.5 Max. Unit 5.0 pF 5.0 NOTE: 1. This parameter is measured at characterization but not tested. pF 3102 lnk 04 3102 lnk 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Vcc terminals. 3. Input terminals. 4. Output and I/O terminals. 9.5 2 IDT49FCT3805/A FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0°C to +70°C, V CC = 3.3V ± 0.3V; Military: TA = –55°C to +125°C, VCC = 3.3V ± 0.3V Symbol VIH Parameter Input HIGH Level (Input pins) Test Conditions(1) Guaranteed Logic HIGH Level Min. 2.0 Typ.(2) — Max. 5.5 2.0 — VCC+0.5 Guaranteed Logic LOW Level –0.5 — 0.8 V VI = 5.5V — — ±1 µA VI = VCC — — ±1 VI = GND — — ±1 VI = GND — — ±1 VO = V CC — — ±1 VO = GND — — ±1 — –0.7 –1.2 V –36 –60 –110 mA Input HIGH Level (I/O pins) VIL Input LOW Level Unit V (Input and I/O pins) II H Input HIGH Current (Input pins)(6) Input HIGH Current (I/O II L VCC = Max. pins)(6) Input LOW Current (Input pins)(6) Input LOW Current (I/O pins)(6) I OZH High Impedance Output Current VCC = Max. pins) (6) I OZL (3-State Output VIK Clamp Diode Voltage VCC = Min., IIN = –18mA I ODH Output HIGH Current VCC = 3.3V, V IN = V IH or VIL, VO = 1.5V(3) I ODL Output LOW Current VCC = 3.3V, V IN = V IH or VIL, VO = 1.5V(3) VOH Output HIGH Voltage VCC = Min. I OH = –0.1mA VIN = VIH or V IL VCC = Min. I OH = –6mA MIL. I OH = –8mA COM'L. I OL = 0.1mA VIN = VIH or V IL VOL I OFF Output LOW Voltage Input Power Off Leakage (6) Current(4) I OS Short Circuit VH Input Hysteresis I CCL Quiescent Power Supply Current I CCH I CCZ 50 90 200 mA VCC– 0.2 — — V 2.4 (5) 3.0 — — — 0.2 I OL = 16mA — 0.2 0.4 I OL = 24mA — 0.3 0.50 — — ±1 µA –60 –135 –240 mA VCC = 0V, VIN ≤ 4.5V VCC = Max., VO = µA GND(3) V — 150 — mV VCC = Max., COM'L. — 0.1 10 µA VIN = GND or VCC MIL. — 0.1 100 — NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 3.3V, +25°C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC -0.6V at rated current. 6. The test limit for this parameter is ±5µA at TA = –55°C. 9.5 3102 lnk 05 3 IDT49FCT3805/A FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES POWER SUPPLY CHARACTERISTICS Test Conditions(1) Min. Typ.(2) Max. Unit — 2.0 30 µA VIN = VCC VIN = GND — 0.035 0.06 mA/ MHz VCC = Max. Outputs Open fo = 25MHz 50% Duty Cycle OEA = OEB =VCC Mon. Output Toggling VIN = VCC VIN = GND — 0.9 1.6 mA VIN = VCC –0.6V VIN = GND — 0.9 1.6 VCC = Max. Outputs Open fo = 50MHz 50% Duty Cycle OEA = OEB = GND Eleven Outputs Toggling VIN = VCC VIN = GND — 20.0 33.0 (5) VIN = VCC –0.6V VIN = GND — 20.0 33.0 (5) Symbol Parameter ∆ICC Quiescent Power Supply Current TTL Inputs HIGH VCC = Max. VIN = VCC –0.6V(3) ICCD Dynamic Power Supply Current (4) VCC = Max. Outputs Open OEA = OEB = GND Per Output Toggling 50% Duty Cycle IC Total Power Supply Current (6) NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3. Per TTL driven input (VIN = VCC -0.6V); all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. 5. Values for these conditions are examples of the IC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fONO) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ∆ICC = Power Supply Current for a TTL High Input (VIN = VCC -0.6V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fO = Output Frequency NO = Number of Outputs at fO All currents are in milliamps and all frequencies are in megahertz. 9.5 3102 tbl 06 4 IDT49FCT3805/A FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE(3,4) FCT3805 Com'l. Mil. Symbol Parameter tPLH Propagation Delay INA to OAn, INB to OBn tPHL tR Output Rise Time FCT3805A Com'l. Mil. Condition(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. CL = 50pF 1.5 5.8 1.5 5.0 RL = 500Ω — 2.0 — — 2.0 — Unit ns ns tF Output Fall Time — 2.0 — — 2.0 — ns tSK(o) Output skew: skew between outputs of all banks of same package (inputs tied together) — 0.7 — — 0.5 — ns tSK(p) Pulse skew: skew between opposite transitions of same output (|t PHL–t PLH|) — 1.2 — — 1.0 — ns tSK(t) Package skew: skew between outputs of different packages at same power supply voltage, temperature, package type and speed grade — 1.5 — — 1.2 — ns tPZL tPZH tPLZ tPHZ Output Enable Time OEA to OAn, OEB to OBn Output Disable Time OEA to OAn, OEB to OBn 1.5 6.5 1.5 6.0 ns 1.5 5.5 1.5 5.0 ns 3102 tbl 07 NOTES: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. tPLH, tPHL, tSK(t) production tested. All other parameters guaranteed but not production tested. 4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew. 9.5 5 IDT49FCT3805/A FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS TEST CIRCUIT FOR ALL OUTPUTS ENABLE AND DISABLE TIME SWITCH POSITION 6.0V V CC Test Disable LOW Enable LOW Disable HIGH Enable HIGH GND 500Ω V OUT V IN Pulse Generator D.U.T. GND 3102 tbl 08 DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 50pF 500Ω RT Switch 6.0V 3102 drw 04 OUTPUT SKEW- tSK(o) PACKAGE DELAY 3V 1.5V INPUT INPUT 0V tPLH tPLH1 3V 1.5V 0V VOH tPHL1 tPHL VOH 2.0V 0.8V OUTPUT 1.5V VOL OUTPUT 1 tSK(o) 1.5V tSK(o) VOL 1.5V VOL OUTPUT 2 tF tR VOH tPLH2 tPHL2 tSK(o) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1| 3102 drw 05 3102 drw 06 PACKAGE SKEW- tSK(t) PULSE SKEW- tSK(p) 3V 1.5V 0V INPUT tPHL tPLH OUTPUT VOH 1.5V VOL INPUT tPHL1 tPLH1 PACKAGE 1 OUTPUT tSK(t) PACKAGE 2 OUTPUT tSK(p) = |tPHL - tPLH| 3V 1.5V 0V 3102 drw 07 tPLH2 tSK(t) tPHL2 VOH 1.5V VOL VOH 1.5V VOL tSK(t) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1| 3102 drw 08 ENABLE AND DISABLE TIMES ENABLE DISABLE 3V CONTROL INPUT 1.5V 0V t OUTPUT NORMALLY LOW t PLZ PZL SWITCH CLOSED 0.3V V OL t t PZH OUTPUT NORMALLY HIGH SWITCH OPEN 3.5V 3.5V 1.5V PHZ 0.3V VOH 1.5V 0V 0V 3102 drw 09 NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: f ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns 9.5 6 IDT49FCT3805/A FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT 49FCT XXX Device Type XX Package X Process/ Temperature Range Blank B Commercial MIL-STD-883, Class B P D E L SO PY Q Plastic DIP CERDIP CERPACK Leadless Chip Carrier Small Outline IC Shrink Small Outline IC Quarter-size Small Outline IC 3805 3805A Non-Inverting 3.3V Buffer/Clock Driver 3102 drw 10 9.5 7