IDT54/74FCT823A/B/C HIGH-PERFORMANCECMOSBUFFER MILITARY AND COMMERCIAL TEMPERATURE RANGES HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER FEATURES: IDT54/74FCT823A/B/C DESCRIPTION: • Equivalent to AMD's Am29823 bipolar registers in pinout/ function, speed, and output drive over full temperature and voltage supply extremes • IDT54/74FCT823A equivalent to FAST™ speed • IDT54FCT823B 25% faster than FAST • IDT74FCT823C 40% faster than FAST • Buffered common Clock Enable (EN) and Asynchronous Clear Input (CLR) • IOL = 48mA (commercial) and 32mA (military) • Clamp diodes on all inputs for ringing suppression • CMOS power levels (1mW typ. static) • TTL input and output compatibility • CMOS output level compatible • Substantially lower input current levels than AMD's bilopar µA max.) Am29800 series (5µ • MIlitary product compliant to MIL-STD-883, Class B • Available in the following packages: – Commercial: SOIC – Military: CERDIP, LCC The FCT823 series is built using an advanced dual metal CMOS technology. The FCT823 bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The FCT823 is a 9-bit wide buffered register with Clock Enable (EN) and Clear (CLR) – ideal for parity bus interfacing in high-performance microprogrammed systems. The FCT823 high-performance interface family is designed for highcapacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. All inputs have clamp diodes and all outputs are designed for low-capacitance bus loading in high-impedance state. FUNCTIONAL BLOCK DIAGRAM D0 EN CLR DN 14 11 D CL CP CP OE Q D CL CP Q Q Q 13 1 Y0 The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES YN JUNE 2002 1 © 2002 Integrated Device Technology, Inc. DSC-5426/3 IDT54/74FCT823A/B/C HIGH-PERFORMANCECMOSBUFFER MILITARY AND COMMERCIAL TEMPERATURE RANGES D1 3 22 Y1 D2 4 21 Y2 D2 5 D3 5 20 Y3 D3 6 24 Y3 D4 7 23 Y4 NC 8 22 NC 8 17 Y6 D5 9 21 Y5 D7 9 16 Y7 D6 10 20 Y6 D8 10 15 Y8 D7 11 12 19 Y7 CLR 11 14 EN GND 12 13 CP 13 CERDIP/ SOIC TOP VIEW VTERM(2) Rating Terminal Voltage Terminal Voltage Commercial Military –0.5 to +7 –0.5 to +7 V –0.5 to VCC –0.5 to VCC V 18 0 to +70 –55 to +125 °C D D Operating Temperature TBIAS Temperature under BIAS –55 to +125 –65 to +135 °C TSTG Storage Temperature –55 to +125 –65 to +150 °C PT Power Dissipation 0.5 0.5 W IOUT DC Output Current 120 120 mA Conditions Typ. Max. Unit VIN = 0V 6 10 pF COUT Output Capacitance VOUT = 0V 8 12 pF CLR PIN DESCRIPTION CAPACITANCE (TA = +25°C, F = 1.0MHz) Input Capacitance EN Y CP EN CLR OE NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. 2. Input and Vcc terminals only. 3. Output and I/O terminals only. CIN 9 Q CP TA Parameter(1) 17 9 Unit with Respect to GND Symbol 16 LOGIC SYMBOL with Respect to GND VTERM(3) 15 LCC TOP VIEW ABSOLUTE MAXIMUM RATINGS(1) Symbol 14 Y8 D6 EN Y5 CP 18 26 Y2 NC 7 27 1 GND D5 28 25 Y4 19 2 CLR 6 3 D8 D4 4 Y1 Y0 Y0 2 INDEX VCC D0 23 NC VCC OE 24 D0 1 OE D1 PIN CONFIGURATION NOTE: 1. This parameter is measured at characterization but not tested. 2 Pin Name I/O Description Dx I D flip-flop data inputs CLR I For both inverting and non-inverting registers, when the clear input is LOW and OE is LOW, the Qx outputs are LOW. When the clear input is HIGH, data can be entered into the register. CP I Clock Pulse for the Register; enters data into the register on the LOW-to-HIGH transition. Yx O Register 3-state outputs EN I Clock Enable. When the clock enable is LOW, data on the DI input is transferred to the QI output on the LOW-to-HIGH clock transition. When the clock enable is HIGH, the QI outputs do not change state, regardless of the data or clock input transitions. OE I Output Control. When the OE input is HIGH, the Yx outputs are in the high impedance state. When the OE input is LOW, the TRUE register data is present at the Yx outputs. IDT54/74FCT823A/B/C HIGH-PERFORMANCECMOSBUFFER MILITARY AND COMMERCIAL TEMPERATURE RANGES FUNCTION TABLE(1) Inputs OE H H H L H L H H L L CLR H H L L H H H H H H EN L L X X H H L L L L Dx L H X X X X L H L H CP ↑ ↑ X X X X ↑ ↑ ↑ ↑ Internal/ Outputs Qx Yx L Z H Z L Z L L NC Z NC NC L Z H Z L L H H Function High Z Clear Hold Load NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance ↑ = LOW-to-HIGH Transition DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC - 0.2V Commercial: TA = 0°C to +70°C, VCC = 5.0V ±5%, Military: TA = -55°C to +125°C, VCC = 5.0V ±10% Symbol Test Conditions(1) Parameter Min. Typ.(2) Max. Unit VIH Input HIGH Level Guaranteed Logic HIGH Level 2 — — V VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V IIH Input HIGH Current VI = VCC — — 5 VI = 2.7V — — 5(4) VI = 0.5V — — –5(4) VI = GND — — –5 VO = VCC VO = 2.7V VO = 0.5V VO = GND — — — — — — — — — –0.7 10 10(4) –10(4) –10 –1.2 –75 VHC VHC 2.4 2.4 — — — — –120 VCC VCC 4.3 4.3 GND GND 0.3 0.3 — — — — — VLC VLC(4) 0.5 0.5 VCC = Max. IIL Input LOW Current IOZH VCC = Max. IOZL Off State (High Impedance) Output Current VIK Clamp Diode Voltage VCC = Min., IIN = –18mA IOS VOH VOL Short Circuit Current Output HIGH Voltage Output LOW Voltage GND(3) VCC = Max., VO = VCC = 3V, VIN = VLC or VHC, IOH = –32µA VCC = Min IOH = –300µA VIN = VIH or VIL IOH = –15mA MIL IOH = –24mA COM'L VCC = 3V, VIN = VLC or VHC, IOL = 300µA VCC = Min IOL = 300µA VIN = VIH or VIL IOL = 32mA MIL IOL = 48mA COM'L NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient and maximum loading. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not ttested. 3 µA µA V mA V V IDT54/74FCT823A/B/C HIGH-PERFORMANCECMOSBUFFER MILITARY AND COMMERCIAL TEMPERATURE RANGES POWER SUPPLY CHARACTERISTICS VLC = 0.2V; VHC = VCC - 0.2V Min. Typ.(2) Max. Unit VCC = Max. VIN ≥ VHC; VIN ≤ VLC — 0.2 1.5 mA Quiescent Power Supply Current TTL Inputs HIGH VCC = Max. VIN = 3.4V(3) — 0.5 2 mA Dynamic Power Supply Current(4) VCC = Max. Outputs Open OE = EN = GND One Input Toggling 50% Duty Cycle VIN ≥ VHC VIN ≤ VLC — 0.15 0.25 mA/ MHz Total Power Supply Current(6) VCC = Max. Outputs Open fCP = 10MHz VIN ≥ VHC VIN ≤ VLC (FCT) — 1.7 4 mA VIN = 3.4V VIN = GND — 2.2 6 VCC = Max. Outputs Open fCP = 10MHz VIN ≥ VHC VIN ≤ VLC (FCT) — 4 7.8(5) 50% Duty Cycle OE = EN = GND at fi = 2.5MHz Eight Bits Toggling VIN = 3.4V VIN = GND — 6.2 16.8(5) Symbol Parameter ICC Quiescent Power Supply Current ∆ICC ICCD IC Test Conditions(1) 50% Duty Cycle OE = EN = GND One Bit Toggling at fi = 5MHz 50% Duty Cycle NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of ∆ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi) ICC = Quiescent Current ∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for register devices (zero for non-register devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz. 4 IDT54/74FCT823A/B/C HIGH-PERFORMANCECMOSBUFFER MILITARY AND COMMERCIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE 54/74FCT823A Com'l. Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tH tPHL tREM tW tW Parameter Propagation Delay CP to Yx (OE = LOW) Output Enable Time, OE to Yx Output Disable Time, OE to Yx Set-up Time HIGH or LOW, Dx to CP Set-up Time HIGH or LOW, EN to CP Hold Time HIGH or LOW, Dx to CP Hold Time HIGH or LOW, EN to CP Propagation Delay, CLR to Yx Recovery Time, CLR to CP CP Pulse Width HIGH or LOW CLR Pulse Width HIGH or LOW Mil. 54FCT823B Mil. Min.(2) Max. — 8.5 74FCT823C Com'l. Min.(2) Max. — 6 Condition(1) CL = 50pF RL = 500Ω Min.(2) — Max. 10 Min.(2) — Max. 11.5 CL = 300pF(3) RL = 500Ω CL = 50pF RL = 500Ω CL = 300pF(3) RL = 500Ω CL = 5pF(3) RL = 500Ω CL = 50pF RL = 500Ω CL = 50pF RL = 500Ω — 20 — 20 — 16 — 12.5 — 12 — 13 — 9 — 7 — 23 — 25 — 16 — 12.5 — 7 — 8 — 7 — 6.2 — 8 — 9 — 8 — 6.5 4 — 4 — 3 — 3 — ns 2 2 — 6 7 6 — — 14 — — — 2 2 — 7 7 7 — — 15 — — — 1.5 0 — 6 6 6 — — 9.5 — — — 1.5 0 — 6 6 6 — — 8 — — — ns ns ns ns ns ns NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. These parameters are guaranteed but not tested. 5 Unit ns ns ns IDT54/74FCT823A/B/C HIGH-PERFORMANCECMOSBUFFER MILITARY AND COMMERCIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS V CC SWITCH POSITION 7.0V 500Ω V OUT VIN Pulse Generator D.U.T . 50pF RT 500Ω CL Test Switch Open Drain Disable Low Enable Low Closed All Other Tests Open DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Octal link Test Circuits for All Outputs DATA INPUT tH tSU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. 3V 1.5V 0V 3V 1.5V 0V tREM tSU LOW-HIGH-LOW PULSE tW 3V 1.5V 0V HIGH-LOW-HIGH PULSE 3V 1.5V 0V tH 1.5V 1.5V Octal link Pulse Width Octal link Set-Up, Hold, and Release Times ENABLE SAME PHASE INPUT TRANSITION tPLH tPHL OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V VOH 1.5V VOL DISABLE 3V 1.5V 0V CONTROL INPUT tPZL OUTPUT NORMALLY LOW 3V 1.5V 0V OUTPUT NORMALLY HIGH Octal link Propagation Delay SWITCH CLOSED tPZH SWITCH OPEN tPLZ 3.5V 3.5V 1.5V 0.3V VOL tPHZ 0.3V 1.5V 0V Enable and Disable Times VOH 0V Octal link NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; ZO ≤ 50Ω; tF ≤ 2.5ns; tR ≤ 2.5ns. 6 IDT54/74FCT823A/B/C HIGH-PERFORMANCECMOSBUFFER MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT XX FCT XXXX Temp. Range Device Type XX Package X Process Blank B Commercial MIL-STD-883, Class B SO Commercial Options Small Outline IC D L Military Options CERDIP Leadless Chip Carrier 823A 823B 823C High Performance CMOS Bus Interface Register, 9-Bit 54 74 – 55°C to +125°C – 40°C to +85°C DATA SHEET DOCUMENT HISTORY 6/27/2002 Updated according to PDNs Logic-00-07 and Logic-01-04 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 7 for Tech Support: [email protected] (408) 654-6459