IDT54/74FCT543T/AT/CT/DT IDT54/74FCT2543T/AT/CT FAST CMOS OCTAL LATCHED TRANSCEIVER Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • Common features: – Low input and output leakage ≤1µA (max.) – CMOS power levels – True TTL input and output compatibility – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) – Meets or exceeds JEDEC standard 18 specifications – Product available in Radiation Tolerant and Radiation Enhanced versions – Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) – Available in DIP, SOIC, SSOP, QSOP, CERPACK and LCC packages • Features for FCT543T: – Std., A, C and D speed grades – High drive outputs (-15mA IOH, 64mA IOL) – Power off disable outputs permit “live insertion” • Features for FCT2543T: – Std., A, and C speed grades – Resistor outputs (-15mA IOH, 12mA IOL Com.) (-12mA IOH, 12mA IOL Mil.) – Reduced system switching noise The FCT543T/FCT2543T is a non-inverting octal transceiver built using an advanced dual metal CMOS technology. This device contains two sets of eight D-type latches with separate input and output controls for each set. For data flow from A to B, for example, the A-to-B Enable (CEAB) input must be LOW in order to enter data from A0–A7 or to take data from B0–B7, as indicated in the Function Table. With CEAB LOW, a LOW signal on the A-to-B Latch Enable (LEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the 3-state B output buffers are active and reflect the data present at the output of the A latches. Control of data from B to A is similar, but uses the CEBA, LEBA and OEBA inputs. The FCT2543T has balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot and controlled output fall times-reducing the need for external series terminating resistors. FCT2xxxT parts are plug-in replacements for FCTxxxT parts. FUNCTIONAL BLOCK DIAGRAM DETAIL A D Q B0 LE Q A0 D LE A1 B1 A2 A3 B2 B3 A4 A5 DETAIL A x 7 A6 A7 B4 B5 B6 B7 OEBA OEAB CEBA LEBA CEAB 2613 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. LEAB MILITARY AND COMMERCIAL TEMPERATURE RANGES 1995 Integrated Device Technology, Inc. 6.17 JANUARY 1995 DSC-4203/5 1 IDT54/74FCT543T/AT/CT/DT - 2543T/AT/CT FAST CMOS OCTAL LATCHED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES A0 OEBA LEBA NC Vcc CEBA B0 PIN CONFIGURATIONS INDEX 24 2 23 3 22 4 5 6 7 8 9 P24-1 D24-1 SO24-2 SO24-7 SO24-8 & E24-1 21 20 19 18 17 16 10 15 11 14 12 13 Vcc CEBA B0 B1 B2 B3 B4 B5 B6 B7 LEAB OEAB 4 A1 A2 A3 NC A4 A5 A6 3 2 5 28 27 26 25 1 6 24 7 23 8 L28-1 9 10 22 21 20 11 19 12 13 14 15 16 17 18 B1 B2 B3 NC B4 B5 B6 A7 CEAB GND NC OEAB LEAB B7 LEBA OEBA A0 A1 A2 A3 A4 A5 A6 A7 CEAB GND 1 2613 drw 02 2613 drw 03 DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW LCC TOP VIEW FUNCTION TABLE(1, 2) PIN DESCRIPTION Pin Names OEAB OEBA CEAB CEBA LEAB LEBA For A-to-B (Symmetric with B-to-A) Description A-to-B Output Enable Input (Active LOW) Latch Status Inputs Output Buffers CEAB LEAB OEAB A-to-B Enable Input (Active LOW) H — — Storing B-to-A Enable Input (Active LOW) — H — Storing A-to-B Latch Enable Input (Active LOW) — — H — B-to-A Latch Enable Input (Active LOW) L L L Transparent Current A Inputs L H L Storing Previous* A Inputs B-to-A Output Enable Input (Active LOW) A0–A7 A-to-B Data Inputs or B-to-A 3-State Outputs B0–B7 B-to-A Data Inputs or A-to-B 3-State Outputs 2613 tbl 01 (1) ABSOLUTE MAXIMUM RATINGS Symbol Rating Commercial VTERM(2) Terminal Voltage –0.5 to +7.0 with Respect to GND VTERM(3) Terminal Voltage –0.5 to with Respect to VCC +0.5 GND TA Operating 0 to +70 Temperature TBIAS Temperature –55 to +125 Under Bias TSTG Storage –55 to +125 Temperature PT Power Dissipation 0.5 Military –0.5 to +7.0 Unit V –0.5 to VCC +0.5 V I OUT DC Output Current –60 to +120 –55 to +125 °C –65 to +135 °C –65 to +150 °C 0.5 W –60 to +120 mA A-to-B B0–B7 High Z — High Z NOTES: 2613 tbl 02 1. * Before LEAB LOW-to-HIGH Transition H = HIGH Voltage Level L = LOW Voltage Level — = Don’t Care or Irrelevant 2. A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA and OEBA. CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V Typ. 6 VOUT = 0V 8 Max. Unit 10 pF 12 NOTE: 1. This parameter is measured at characterization but not tested. pF 2613 lnk 04 2613 lnk 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Input and VCC terminals only. 3. Outputs and I/O terminals only. 6.17 2 IDT54/74FCT543T/AT/CT/DT - 2543T/AT/CT FAST CMOS OCTAL LATCHED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10% Symbol VIH VIL Parameter Input HIGH Level Test Conditions(1) Guaranteed Logic HIGH Level Input LOW Level Input HIGH Current (4) II L Input LOW Current (4) I OZH High Impedance Output Current II H I OZL (3-State Output Min. 2.0 Typ.(2) — Max. — Unit V Guaranteed Logic LOW Level — — 0.8 V VCC = Max. — — ±1 µA VI = 2.7V VCC = Max. pins) (4) Current (4) II Input HIGH VIK Clamp Diode Voltage VH Input Hysteresis I CC Quiescent Power Supply Current VI = 0.5V — — ±1 VO = 2.7V — — ±1 VO = 0.5V — — ±1 µA VCC = Max., VI = VCC (Max.) — — ±1 µA VCC = Min., IIN = –18mA — –0.7 –1.2 V — — 200 — mV — 0.01 1 VCC = Max., VIN = GND or VCC mA 2613 lnk 05 OUTPUT DRIVE CHARACTERISTICS FOR 543T/AT/CT/DT Symbol VOH VOL Output LOW Voltage I OS Short Circuit Current I OFF Test Conditions(1) VCC = Min. I OH = –6mA MIL. VIN = VIH or V IL I OH = –8mA COM'L. I OH = –12mA MIL. I OH = –15mA COM'L. VCC = Min. I OL = 48mA MIL. VIN = VIH or V IL I OL = 64mA COM'L. VCC = Max., VO = GND (3) Parameter Output HIGH Voltage Input/Output Power Off Leakage(5) VCC = 0V, VIN or V O ≤ 4.5V Min. 2.4 Typ.(2) 3.3 Max. — Unit V 2.0 3.0 — V — 0.3 0.55 V –60 –120 –225 mA — — ±1 µA 2613 lnk 06 OUTPUT DRIVE CHARACTERISTICS FOR 2543T/AT/CT/DT Symbol I ODL Parameter Output LOW Current Test Conditions(1) VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V (3) Min. 16 Typ.(2) 48 Max. — Unit mA I ODH Output HIGH Current VCC = 5V, VIN = VIH or V IL, VOUT = 1.5V (3) –16 –48 — mA VOH Output HIGH Voltage 2.4 3.3 — V VOL Output LOW Voltage VCC = Min. VIN = VIH or VIL VCC = Min. VIN = VIH or V IL — 0.3 0.50 V I OH = –12mA MIL. I OH = –15mA COM'L. I OL = 12mA NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25°C ambient. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. The test limit for this parameter is ±5µA at TA = –55°C. 5. This parameter is guaranteed but not tested. 6.17 2613 lnk 07 3 IDT54/74FCT543T/AT/CT/DT - 2543T/AT/CT FAST CMOS OCTAL LATCHED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES POWER SUPPLY CHARACTERISTICS Symbol Test Conditions(1) Parameter ∆ICC Quiescent Power Supply Current TTL Inputs HIGH VCC = Max. VIN = 3.4V(3) ICCD Dynamic Power Supply Current(4) VCC = Max., Outputs Open CEAB and OEAB = GND CEBA = VCC One Input Toggling 50% Duty Cycle VIN = VCC VIN = GND VCC = Max., Outputs Open fCP = 10MHz (LEAB) 50% Duty Cycle CEAB and OEAB = GND CEBA = VCC One Bit Toggling at fi = 5MHz 50% Duty Cycle VIN = VCC VIN = GND VCC = Max., Outputs Open fCP = 10MHz (LEAB) 50% Duty Cycle CEAB and OEAB = GND CEBA = VCC Eight Bits Toggling at fi = 2.5MHz 50% Duty Cycle VIN = VCC VIN = GND IC Total Power Supply Current(6) VIN = 3.4V VIN = GND VIN = 3.4V VIN = GND Min. Typ.(2) Max. 0.5 2.0 mA FCTxxxT — 0.15 0.25 mA/ MHz FCT2xxxT — 0.06 0.12 FCTxxxT — 1.5 3.5 FCT2xxxT — 0.6 2.2 FCTxxxT — 2.0 5.5 FCT2xxxT — 1.1 4.2 FCTxxxT — 3.8 7.3(5) FCT2xxxT — 1.5 4.0(5) FCTxxxT — 6.0 16.3(5) FCT2xxxT — 3.8 13.0(5) NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi) ICC = Quiescent Current ∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz. 6.17 Unit — mA 2613 tbl 08 4 IDT54/74FCT543T/AT/CT/DT - 2543T/AT/CT FAST CMOS OCTAL LATCHED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE FCT543T/ FCT543AT/ FCT2543T FCT2543AT Com'l. Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tW Parameter Propagation Delay Transparant Mode An to Bn or Bn to An Propagation Delay LEBA to An, LEAB to Bn Output Enable Time OEBA or OEAB to An or Bn CEBA or CEAB to An or Bn Output Disable Time OEBA or OEAB to An or Bn CEBA or CEAB to An or Bn Set-up Time, HIGH or LOW An or Bn to LEBA or LEAB Hold Time, HIGH or LOW An or Bn to LEBA or LEAB LEBA or LEAB Pulse Width LOW Condition(1) CL = 50pF RL = 500Ω Mil. Com'l. Mil. Min.(2) 1.5 Max. 8.5 Min.(2) 1.5 Max. 10.0 Min.(2) 1.5 Max. 6.5 Min. (2) 1.5 Max. 7.5 Unit ns 1.5 12.5 1.5 14.0 1.5 8.0 1.5 9.0 ns 1.5 12.0 1.5 14.0 1.5 9.0 1.5 10.0 ns 1.5 9.0 1.5 13.0 1.5 7.5 1.5 8.5 ns 3.0 — 3.0 — 2.0 — 2.0 — ns 2.0 — 2.0 — 2.0 — 2.0 — ns 5.0 — 5.0 — 5.0 — 5.0 — ns 2513 tbl 09 FCT543CT/ FCT2543CT Com'l. Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tW Parameter Propagation Delay Transparant Mode An to Bn or Bn to An Propagation Delay LEBA to An, LEAB to Bn Output Enable Time OEBA or OEAB to An or Bn CEBA or CEAB to An or Bn Output Disable Time OEBA or OEAB to An or Bn CEBA or CEAB to An or Bn Set-up Time, HIGH or LOW An or Bn to LEBA or LEAB Hold Time, HIGH or LOW An or Bn to LEBA or LEAB LEBA or LEAB Pulse Width LOW FCT543DT Mil. Com'l. Mil. Condition(1) Min.(2) 1.5 1.5 Max. 4.4 Min. (2) 1.5 Max. 6.1 Min.(2) CL = 50pF RL = 500Ω Max. 5.3 Min.(2) — Max. — Unit ns 1.5 7.0 1.5 8.0 1.5 5.0 — — ns 1.5 8.0 1.5 9.0 1.5 5.4 — — ns 1.5 6.5 1.5 7.5 1.5 4.3 — — ns 2.0 — 2.0 — 1.5 — — — ns 2.0 — 2.0 — 1.5 — — — ns 5.0 — 5.0 — 3.0 (3) — — — ns NOTES: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This limit is guaranteed but not tested. 2513 tbl 10 6.17 5 IDT54/74FCT543T/AT/CT/DT - 2543T/AT/CT FAST CMOS OCTAL LATCHED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS SWITCH POSITION TEST CIRCUITS FOR ALL OUTPUTS V CC 7.0V 500Ω Pulse Generator Switch Open Drain Disable Low Closed Enable Low V OUT VIN Test Open All Other Tests D.U.T. 50pF RT 2513 lnk 11 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 500Ω CL 2513 drw 05 SET-UP, HOLD AND RELEASE TIMES DATA INPUT tH tSU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tREM tSU PULSE WIDTH 3V 1.5V 0V 3V 1.5V 0V LOW-HIGH-LOW PULSE 1.5V tW 3V 1.5V 0V HIGH-LOW-HIGH PULSE 1.5V 2513 drw 07 3V 1.5V 0V tH 2513 drw 06 PROPAGATION DELAY ENABLE AND DISABLE TIMES ENABLE SAME PHASE INPUT TRANSITION tPLH tPHL OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V DISABLE 3V CONTROL INPUT tPZL VOH 1.5V VOL OUTPUT NORMALLY LOW 3V 1.5V 0V SWITCH CLOSED tPLZ 3.5V 1.5V tPZH OUTPUT NORMALLY HIGH 2513 drw 08 SWITCH OPEN 1.5V 0V 3.5V 0.3V VOL tPHZ 0.3V 1.5V 0V VOH 0V 2513 drw 09 NOTES: 1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns 6.17 6 IDT54/74FCT543T/AT/CT/DT - 2543T/AT/CT FAST CMOS OCTAL LATCHED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT X FCT Temperature Range X XXXX X X Family Device Type Package Process Blank B Commercial MIL-STD-883, Class B P D SO L E PY Q Plastic DIP CERDIP Small Outline IC Leadless Chip Carrier CERPACK Shrink Small Outline Package Quarter-size Small Outline Package 543T 543AT 543CT 543DT Octal Latched Transceiver Blank 2 High Drive Balanced Drive 54 74 -55°C to +125°C 0° to +70°C 2613 drw 10 6.17 7