IDT IDT70V9079L15PF High-speed 3.3v 64/32k x 8 synchronous dual-port static ram Datasheet

HIGH-SPEED 3.3V 64/32K x 8
SYNCHRONOUS
DUAL-PORT STATIC RAM
Features:
◆
◆
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 6.5/7.5/9/12/15ns (max.)
– Industrial: 9ns (max.)
Low-power operation
– IDT70V9089/79S
Active: 429mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V9089/79L
Active: 429mW (typ.)
Standby: 660mW (typ.)
Flow-Through or Pipelined output mode on either port via
the FT/PIPE pin
◆
◆
◆
◆
◆
IDT70V9089/79S/L
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 4ns setup to clock and 1ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time, 100MHz operation in the Pipelined output mode
LVTTL- compatible, single 3.3V (±0.3V) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Available in a 100 pin Thin Quad Flatpack (TQFP) package
Functional Block Diagram
R/WL
OEL
R/WR
OER
CE0L
CE1L
FT/PIPEL
1
0
0/1
0/1
1
CE0R
CE1R
1
0
0/1
0
0
1
0/1
FT/PIPER
,
I/O0L - I/O7L
I/O0R - I/O7R
I/O
Control
I/O
Control
A15R(1)
A15L(1)
A0L
CLKL
ADSL
CNTENL
CNTRSTL
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A0R
CLKR
ADSR
CNTENR
CNTRSTR
3750 drw 01
NOTE:
1. A15 X is a NC for ID70V9079.
MAY 2004
1
©2004 Integrated Device Technology, Inc.
DSC 3750/8
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Description:
The IDT70V9089/79 is a high-speed 64/32K x 8 bit synNchronous
Dual-Port RAM. The memory array utilizes Dual-Port memory cells to
allow simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold times.
The timing latitude provided by this approach allows systems to be
designed with very short cycle times.
Industrial and Commercial Temperature Ranges
With an input data register, the IDT70V9089/79 has been optimized for
applications having unidirectional or bidirectional data flow in bursts. An
automatic power down feature, controlled by CE0 and CE1, permits the
on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 429mW of power.
Pin Configurations(2,3,4)
NC
NC
A6L
A5L
A4L
A3L
A2L
A1L
A0L
CNTENL
CLKL
ADSL
VSS
ADSR
CLKR
CNTENR
A0R
A1R
A2R
A3R
A4R
A5R
A6R
NC
NC
01/15/04
Index
NC
NC
A7L
A8L
A9L
A10L
A11L
A12L
A13L
A14L
A15L(1)
NC
VDD
NC
NC
NC
NC
CE 0L
CE 1L
CNTRSTL
R/WL
OEL
FT/PIPEL
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
2
74
73
3
4
72
1
5
71
6
7
70
69
8
68
67
9
10
11
IDT70V9089/79PF
PN100-1(5)
66
65
100-PIN TQFP
TOP VIEW(6)
64
63
62
12
13
14
61
60
15
16
17
59
19
58
57
20
56
21
55
22
54
23
24
53
52
18
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
A7R
A8R
A9R
A10R
A11R
A12R
A13R
A14R
A15R(1)
NC
VSS
NC
NC
NC
NC
CE0R
CE1R
CNTRSTR
R/WR
OER
FT/PIPER
VSS
NC
GND
NC
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
VSS
I/OIL
I/O0L
VDD
VSS
I/O0R
I/O1R
I/O2R
VDD
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
NC
NC
NC
3750 drw 02
NOTES:
1. A15X is a NC for ID70V9079.
2. All Vcc pins must be connected to power supply.
3. All GND pins must be connected to ground.
4. Package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
2
6.42
,
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
CE0L, CE1L
CE0R, CE1R
Chip Enables
R/WL
R/WR
Read/Write Enable
OEL
OER
Output Enable
A0L - A15L(1)
A0R - A15R(1)
Address
I/O0L - I/O7L
I/O0R - I/O7R
Data Input/Output
CLKL
CLKR
Clock
ADSL
ADSR
Address Strobe
CNTENL
CNTENR
Counter Enable
CNTRSTL
CNTRSTR
Counter Reset
FT/PIPEL
FT/PIPER
Flow-Through/Pipeline
VDD
Power (3.3V)
VSS
Ground (0V)
NOTE:
1. A15X is a NC for ID70V9079.
2. LB and UB are single buffered regardless of state of FT/PIPE.
3. CEo and CE1 are single buffered when FT/PIPE = VIL,
CEo and CE 1 are double buffered when FT/PIPE = VIH,
i.e. the signals take two cycles to deselect.
3750 tbl 01
Truth Table I—Read/Write and
Enable Control(1,2,3)
OE
CLK
CE0
CE1
R/W
I/O0-7
X
↑
H
X
X
High-Z
Deselected - Power Down
X
↑
X
L
X
High-Z
Deselected - Power Down
X
↑
L
H
L
DATAIN
Write
L
↑
L
H
H
DATAOUT
Read
H
X
L
H
X
High-Z
Mode
Outputs Disabled
3750 tbl 02
NOTES:
1. "H" = VIH, "L" = V IL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
Truth Table II—Address Counter Control(1,2,3)
External
Address
Previous
Internal
Address
Internal
Address
Used
CLK
An
X
An
↑
ADS
L(4)
CNTEN
CNTRST
I/O(3)
X
H
DI/O (n)
MODE
External Address Used
X
An
An + 1
↑
H
L
H
DI/O(n+1)
Counter Enabled—Internal Address generation
X
An + 1
An + 1
↑
H
H
H
DI/O(n+1)
External Address Blocked—Counter disabled (An + 1 reused)
A0
↑
X
(4)
X
X
X
(5)
DI/O(0)
L
Counter Reset to Address 0
NOTES:
1. "H" = V IH, "L" = VIL, "X" = Don't Care.
2. CE 0 and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS and CNTRST are independent of all other signals including CE0 and CE1.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE1.
6.42
3
3750 tbl 03
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Recommended DC Operating
Conditions
Recommended Operating
Temperature and Supply Voltage(1)
Grade
Commercial
Industrial
Industrial and Commercial Temperature Ranges
Symbol
Ambient
Temperature
GND
VDD
0OC to +70OC
0V
3.3V + 0.3V
-40OC to +85OC
0V
3.3V + 0.3V
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
3750 tbl 04
Parameter
VDD
Supply Voltage
VSS
Ground
VIH
Input High Voltage
VIL
Input Low Voltage
Min.
Typ.
Max.
Unit
3.0
3.3
3.6
V
0
0
0
2.2
____
(2)
-0.3
V
VDD + 0.3V
____
(1)
0.8
V
V
3750 tbl 05
NOTES:
1. VTERM must not exceed VDD +0.3V.
2. VIL > -1.5V for pulse width less than 10ns.
Absolute Maximum Ratings(1)
Symbol
Capacitance (TA = +25°C, f = 1.0MHz)
Commercial
& Industrial
Unit
Terminal Voltage
with Respect
to GND
-0.5 to +4.6
V
TBIAS
Temperature
Under Bias
-55 to +125
o
C
TSTG
Storage Temperature
-65 to +150
o
C
TJN
Junction Temperature
+150
o
C
IOUT
DC Output Current
VTERM(2)
Rating
Symbol
CIN
Parameter(1)
Input Capacitance
(3)
COUT
Output Capacitance
Conditions(2)
Max.
Unit
V IN = 3dV
9
pF
V OUT = 3dV
10
pF
3750 tbl 07
50
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
mA
3750 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD +0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VDD + 0.3V.
3. Ambient Temperature Under Bias. Chip Deselected.
4
6.42
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V)
70V9089/79S
Symbol
Parameter
Test Conditions
70V9089/79L
Min.
Max.
Min.
Max.
Unit
|ILI|
Input Leakage Current(1)
VDD = 3.3V, VIN = 0V to VDD
___
10
___
5
µA
|ILO|
Output Leakage Current
CE0 = VIH or CE1 = VIL, VOUT = 0V to VDD
___
10
___
5
µA
VOL
Output Low Voltage
IOL = +4mA
___
0.4
___
0.4
V
VOH
Output High Voltage
IOH = -4mA
2.4
___
2.4
___
V
3750 tbl 08
NOTE:
1. At VDD < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(6) (VDD = 3.3V ± 0.3V)
70V9089/79X6
Com'l Only
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current
(Both Ports CMOS Level Inputs)
Full Standby Current
(One Port CMOS Level Inputs)
Test Condition
Version
70V9089/79X7
Com'l Only
70V9089/79X9
Com'l
& Ind
Typ.(4)
Max.
Typ. (4)
Max.
Typ. (4)
Max.
Unit
mA
COM'L
S
L
220
220
395
350
200
200
335
290
180
180
260
225
IND
S
L
____
____
____
____
____
____
____
____
180
180
270
235
COM'L
S
L
70
70
145
130
60
60
115
100
50
50
75
65
IND
S
L
____
____
____
____
____
____
____
____
50
50
85
75
CE"A" = VIL and
CE"B" = VIH(3)
Active Port Outputs Disabled,
f=fMAX(1)
COM'L
S
L
150
150
280
250
130
130
240
210
110
110
170
150
IND
S
L
____
____
____
____
____
____
____
____
110
110
180
160
Both Ports CER and
CEL > VDD - 0.2V
VIN > VDD - 0.2V or
VIN < 0.2V, f = 0(2)
COM'L
S
L
1.0
0.4
5
3
1.0
0.4
5
3
1.0
0.4
5
3
IND
S
L
____
____
____
____
____
____
____
____
1.0
0.4
5
3
CE"A" < 0.2V and
CE"B" > VDD - 0.2V(5)
VIN > VDD - 0.2V or
VIN < 0.2V, Active Port
Outputs Disabled, f = fMAX(1)
COM'L
S
L
140
140
270
240
120
120
230
200
100
100
160
140
IND
S
L
____
____
____
____
____
____
____
____
100
100
170
150
CEL and CER = VIL
Outputs Disabled
f = fMAX(1)
CEL and CER = VIH
f = fMAX(1)
mA
mA
mA
mA
3750 tbl 09a
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. I CC DC(f=0) = 90mA (Typ).
5. CEX = V IL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE 0X < 0.2V and CE1X > VDD - 0.2V
CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6. 'X' in part number indicates power rating (S or L).
6.42
5
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(6) (VDD = 3.3V ± 0.3V)(Cont'd)
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current
(Both Ports CMOS Level Inputs)
Full Standby Current
(One Port CMOS Level Inputs)
Test Condition
Version
70V9089/79X12
Com'l Only
70V9089/79X15
Com'l Only
Typ.(4)
Max.
Typ.(4)
Max.
Unit
mA
COM'L
S
L
150
150
240
205
130
130
220
185
IND
S
L
____
____
____
____
____
____
____
____
COM'L
S
L
40
40
65
50
30
30
55
35
IND
S
L
____
____
____
____
____
____
____
____
CE"A" = VIL and
CE"B" = VIH(3)
Active Port Outputs Disabled,
f=fMAX(1)
COM'L
S
L
100
100
160
140
90
90
150
130
IND
S
L
____
____
____
____
____
____
____
____
Both Ports CER and
CEL > VDD - 0.2V
VIN > VDD - 0.2V or
VIN < 0.2V, f = 0(2)
COM'L
S
L
1.0
0.4
5
3
1.0
0.4
5
3
IND
S
L
____
____
____
____
____
____
____
____
CE"A" < 0.2V and
CE"B" > VDD - 0.2V(5)
VIN > VDD - 0.2V or
VIN < 0.2V, Active Port
Outputs Disabled, f = fMAX(1)
COM'L
S
L
90
90
150
130
80
80
140
120
IND
S
L
____
____
____
____
____
____
____
____
CEL and CER = VIL
Outputs Disabled
f = fMAX(1)
CEL and CER = VIH
f = fMAX(1)
mA
mA
mA
mA
3750 tbl 09b
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 90mA (Typ).
5. CEX = V IL means CE 0X = V IL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE 0X < 0.2V and CE1X > VDD - 0.2V
CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6. 'X' in part number indicates power rating (S or L).
6
6.42
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns Max.
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
Figures 1,2 and 3
3750 tbl 10
3.3V
3.3V
590Ω
590Ω
DATAOUT
DATAOUT
30pF
435Ω
5pF*
435Ω
3750 drw 03
3750 drw 04
Figure 2. Output Test Load
(For tCKLZ , tCKHZ, tOLZ, and tOHZ ).
*Including scope and jig.
Figure 1. AC Output Test load.
8
7
-10 pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
6
5
tCD1,
tCD2
(Typical, ns)
4
3
2
1
0
-1
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
3750 drw 05
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.42
7
,
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3,4) (VDD = 3.3V ± 0.3, TA = 0°C to +70°C)
Symbol
tCYC1
Parameter
Clock Cycle Time (Flow-Through)
(2)
(2)
70V9089/79X6
Com'l Only
70V9089/79X7
Com'l Only
70V9089/79X9
Com'l
& Ind
Min.
Max.
Min.
Max.
Min.
Max.
Unit
19
____
22
____
25
____
ns
ns
tCYC2
Clock Cycle Time (Pipelined)
10
____
12
____
15
____
tCH1
Clock High Time (Flow-Through)(2)
6.5
____
7.5
____
12
____
ns
tCL1
(2)
tCH2
Clock Low Time (Flow-Through)
6.5
____
7.5
____
12
____
ns
(2)
4
____
5
____
6
____
ns
(2)
4
____
5
____
6
____
ns
Clock High Time (Pipelined)
tCL2
Clock Low Time (Pipelined)
tR
Clock Rise Time
____
3
____
3
____
3
ns
tF
Clock Fall Time
____
3
____
3
____
3
ns
tSA
Address Setup Time
3.5
____
4
____
4
____
ns
tHA
Address Hold Time
0
____
0
____
1
____
ns
tSC
Chip Enable Setup Time
3.5
____
4
____
4
____
ns
tHC
Chip Enable Hold Time
0
____
0
____
1
____
ns
tSW
R/W Setup Time
3.5
____
4
____
4
____
ns
tHW
R/W Hold Time
0
____
0
____
1
____
ns
tSD
Input Data Setup Time
3.5
____
4
____
4
____
ns
tHD
Input Data Hold Time
0
____
0
____
1
____
ns
ns
ADS Setup Time
3.5
____
4
____
4
____
tHAD
ADS Hold Time
0
____
0
____
1
____
ns
tSCN
CNTEN Setup Time
3.5
____
4
____
4
____
ns
tHCN
CNTEN Hold Time
0
____
0
____
1
____
ns
ns
tSAD
tSRST
CNTRST Setup Time
3.5
____
4
____
4
____
tHRST
CNTRST Hold Time
0
____
0
____
1
____
ns
tOE
Output Enable to Data Valid
____
6.5
____
7.5
____
9
ns
ns
(1)
tOLZ
Output Enable to Output Low-Z
2
____
2
____
2
____
tOHZ
Output Enable to Output High-Z(1)
1
7
1
7
1
7
ns
tCD1
Clock to Data Valid (Flow-Through)(2)
____
15
____
18
____
20
ns
____
6.5
____
7.5
____
9
ns
2
____
2
____
2
____
ns
(2)
tCD2
Clock to Data Valid (Pipelined)
tDC
Data Output Hold After Clock High
(1)
tCKHZ
Clock High to Output High-Z
2
9
2
9
2
9
ns
tCKLZ
Clock High to Output Low-Z(1)
2
____
2
____
2
____
ns
ns
Port-to-Port Delay
tCWDD
Write Port Clock High to Read Data Delay
____
24
____
28
____
35
tCCS
Clock-to-Clock Setup Time
____
9
____
10
____
15
ns
3750 tbl 11a
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
This parameter is guaranteed by device characterization, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPE = V IH. Flow-through parameters (tCYC1, tCD1) apply when
FT/PIPE = VIL for that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a
DC signal, i.e. steady state during operation.
4. 'X' in part number indicates power rating (S or L).
8
6.42
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3,4) (VDD = 3.3V ± 0.3, TA = 0°C to +70°C)(Cont'd)
Symbol
tCYC1
tCYC2
tCH1
tCL1
tCH2
Parameter
Clock Cycle Time (Flow-Through)(2)
Clock Cycle Time (Pipelined)
(2)
Clock High Time (Flow-Through)
Clock Low Time (Flow-Through)
(2)
(2)
(2)
Clock High Time (Pipelined)
(2)
70V9089/79X12
Com'l Only
70V908979X15
Com'l Only
Min.
Max.
Min.
Max.
Unit
30
____
35
____
ns
20
____
25
____
ns
12
____
12
____
ns
12
____
12
____
ns
8
____
10
____
ns
ns
tCL2
Clock Low Time (Pipelined)
8
____
10
____
tR
Clock Rise Time
____
3
____
3
ns
tF
Clock Fall Time
____
3
____
3
ns
tSA
Address Setup Time
4
____
4
____
ns
tHA
Address Hold Time
1
____
1
____
ns
tSC
Chip Enable Setup Time
4
____
4
____
ns
tHC
Chip Enable Hold Time
1
____
1
____
ns
tSW
R/W Setup Time
4
____
4
____
ns
tHW
R/W Hold Time
1
____
1
____
ns
tSD
Input Data Setup Time
4
____
4
____
ns
tHD
Input Data Hold Time
1
____
1
____
ns
ADS Setup Time
4
____
4
____
ns
ADS Hold Time
1
____
1
____
ns
CNTEN Setup Time
4
____
4
____
ns
tHCN
CNTEN Hold Time
1
____
1
____
ns
tSRST
CNTRST Setup Time
4
____
4
____
ns
tHRST
CNTRST Hold Time
1
____
1
____
ns
tOE
Output Enable to Data Valid
____
12
____
15
ns
tOLZ
Output Enable to Output Low-Z(1)
2
____
2
____
ns
tSAD
tHAD
tSCN
tOHZ
tCD1
(1)
Output Enable to Output High-Z
Clock to Data Valid (Flow-Through)
(2)
(2)
tCD2
Clock to Data Valid (Pipelined)
tDC
Data Output Hold After Clock High
(1)
1
7
1
7
ns
____
25
____
30
ns
____
12
____
15
ns
2
____
2
____
ns
tCKHZ
Clock High to Output High-Z
2
9
2
9
ns
tCKLZ
Clock High to Output Low-Z(1)
2
____
2
____
ns
ns
Port-to-Port Delay
tCWDD
Write Port Clock High to Read Data Delay
____
40
____
50
tCCS
Clock-to-Clock Setup Time
____
15
____
20
ns
3750 tbl 11b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
This parameter is guaranteed by device characterization, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPE = V IH. Flow-through parameters (tCYC1, tCD1) apply when
FT/PIPE = VIL for that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a
DC signal, i.e. steady state during operation.
4. 'X' in part number indicates power rating (S or L).
6.42
9
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Flow-Through Output
(FT/PIPE"X" = VIL)(3,6)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
tSC
tHC
(4)
CE1
R/W
(5)
ADDRESS
tSW
tHW
tSA
tHA
An
An + 1
tCKHZ (1)
Qn
DATAOUT
tCKLZ
An + 3
tDC
tCD1
OE
An + 2
Qn + 1
(1)
tOHZ
Qn + 2
(1)
tOLZ
tDC
(1)
(2)
tOE
3750 drw 06
Timing Waveform of Read Cycle for Pipelined Output (FT/PIPE"X" = VIH)(3,6)
t CYC2
tCH2
tCL2
CLK
CE0
tSC
tSC
tHC
tHC
(4)
CE1
R/W
(5)
ADDRESS
tSW
tHW
tSA
tHA
An
An + 1
(1 Latency)
An + 2
tDC
tCD2
DATAOUT
Qn
tCKLZ
An + 3
Qn + 1
(1)
tOHZ
Qn + 2
(1)
tOLZ
(1)
(2)
OE
tOE
3750 drw 07
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
3. ADS = VIL, CNTEN and CNTRST = VIH.
4. The output is disabled (High-impedance state) by CE0 = VIH or CE1 = VIL following the next rising edge of clock. Refer to Truth Table 1.
5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
6. "x" denotes Left or Right port. The diagram is with respect to that port.
10
6.42
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of a Bank Select Pipelined Read(1,2)
tCH2
tCYC2
tCL2
CLK
tSA
tHA
A0
ADDRESS(B1)
tSC
tHC
CE0(B1)
tSC
tHC
tCD2
tCD2
Q0
DATAOUT(B1)
tSA
(3)
tCD2
Q3
tCKLZ
(3)
tCKHZ (3)
tHA
A0
tSC
A6
A5
A4
A3
A2
A1
tSC
CE0(B2)
tCKHZ
Q1
tDC
tDC
ADDRESS(B2)
A6
A5
A4
A3
A2
A1
tHC
tHC
tCKHZ(3)
tCD2
DATAOUT(B2)
tCKLZ(3)
tCD2
Q2
Q4
tCKLZ (3)
3750 drw 08
Timing Waveform of a Bank Select Flow-Through Read(6)
tCH1
tCYC1
tCL1
CLK
tSA
ADDRESS(B1)
CE0(B1)
tHA
A0
tSC
tHC
tSC
tCD1
tHC
tCD1
tCKHZ
D0
DATAOUT(B1)
tSA
tCD1
D3
tCKLZ
(1)
D5
tCKHZ (1)
tCKLZ
(1)
tHA
A0
tSC
tCD1
tDC
A1
A6
A5
A4
A3
A2
tSC
CE0(B2)
(1)
D1
tDC
ADDRESS(B2)
A6
A5
A4
A3
A2
A1
tHC
tHC
tCD1
DATAOUT(B2)
tCKLZ
(1)
tCKHZ
(1)
tCD1
D2
tCKLZ
NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70V9089/79 for this waveform,
and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. OE and ADS = VIL; CE1(B1) , CE1(B2) , R/W, CNTEN, and CNTRST = VIH.
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4. CE 0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
5. OE = V IL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
6. If t CCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If t CCS > maximum specified, then data from right port READ is not valid until tCCS + t CD1. tCWDD does not apply in this case.
6.42
11
(1)
tCKHZ
(1)
D4
3750 drw 08a
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform Port-to-Port Flow-Through Read(1,2,3,5)
CLK "A"
tSW tHW
R/W "A"
tSA
ADDRESS "A"
NO
MATCH
MATCH
tSD
DATAIN "A"
tHA
tHD
VALID
tCCS (4)
CLK "B"
tCD1
R/W "B"
tSW tHW
tSA
ADDRESS "B"
tHA
NO
MATCH
MATCH
tCWDD (4)
tCD1
DATAOUT "B"
VALID
VALID
tDC
tDC
3750 drw 09
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
3. OE = VIL for the Port "B", which is being read from. OE = VIH for the Port "A", which is being written to.
4. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + t CD1. tCWDD does not apply in this case.
5. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
12
6.42
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
tSW tHW
R/W
tSW tHW
(4)
ADDRESS
An
tSA tHA
An +1
An + 2
An + 4
An + 3
An + 2
tSD tHD
DATAIN
Dn + 2
tCD2
(2)
tCKHZ (1)
tCKLZ
(1)
tCD2
Qn + 3
Qn
DATAOUT
READ
NOP
(5)
WRITE
READ
3750 drw 10
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
tCH2
tCYC2
tCL2
CLK
CE0
tSC
tHC
CE1
tSW tHW
R/W
ADDRESS(4)
tSW tHW
An
tSA tHA
An +1
An + 2
tSD
DATAIN
(2)
DATAOUT
An + 3
Dn + 3
Dn + 2
tCD2
Qn
tOHZ
An + 4
An + 5
tHD
tCKLZ(1)
tCD2
Qn + 4
(1)
OE
READ
WRITE
READ
3750 drw 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE 0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
13
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3)
tCH1
tCYC1
tCL1
CLK
CE0
tSC
tHC
CE1
tSW tHW
R/W
tSW tHW
(4)
An
tSA tHA
ADDRESS
An +1
An + 2
An + 4
An + 3
An + 2
tSD tHD
DATAIN
Dn + 2
tCD1
(2)
tCD1
tCD1
Qn
DATAOUT
Qn + 1
tDC
tCKHZ
READ
NOP
(1)
(5)
tCKLZ
WRITE
tCD1
Qn + 3
tDC
READ
(1)
3750 drw 12
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(3)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
CE1
tSW tHW
tSW tHW
R/W
ADDRESS
(4)
An
tSA tHA
An +1
DATAIN
(2)
DATAOUT
An + 2
tSD tHD
An + 3
Dn + 2
Dn + 3
tDC
tCD1
Qn
tOHZ
An + 4
tOE
tCD1
(1)
(1)
An + 5
tCKLZ
tCD1
Qn + 4
tDC
OE
READ
WRITE
READ
3750 drw 13
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
14
6.42
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
tSAD tHAD
ADS
tSAD tHAD
CNTEN
tSCN tHCN
tCD2
DATAOUT
Qx - 1(2)
Qn + 2(2)
Qn + 1
Qn
Qx
Qn + 3
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
3750 drw 14
Timing Waveform of Flow-Through Counter Read with
Address Counter Advance(1)
tCH1
tCYC1
tCL1
CLK
tSA
ADDRESS
tHA
An
tSAD tHAD
ADS
tSAD tHAD
tSCN tHCN
CNTEN
tCD1
DATAOUT
Qx(2)
Qn
Qn + 1
Qn + 2
Qn + 3(2)
Qn + 4
tDC
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
READ
WITH
COUNTER
3750 drw 15
NOTES:
1. CE0 and OE = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data
output remains constant for subsequent clocks.
6.42
15
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-Through or Pipelined Outputs)(1)
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 2
An + 1
An + 4
An + 3
tSAD tHAD
ADS
CNTEN
tSD tHD
Dn + 1
Dn
DATAIN
WRITE
EXTERNAL
ADDRESS
Dn + 1
Dn + 4
Dn + 3
Dn + 2
WRITE
WRITE
WITH COUNTER COUNTER HOLD
WRITE WITH COUNTER
3750 drw 16
Timing Waveform of Counter Reset (Pipelined Outputs)(2)
tCH2
tCYC2
tCL2
CLK
tSA tHA
(4)
An
ADDRESS
INTERNAL(3)
ADDRESS
Ax (6)
0
1
An + 1
An + 2
An + 1
An
tSW tHW
R/W
ADS
tSAD tHAD
CNTEN
tSCN tHCN
tSRST tHRST
CNTRST
tSD
tHD
D0
DATAIN
(5)
Q1
Q0
DATAOUT
COUNTER
RESET
(6)
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS n
Qn
READ
ADDRESS n+1
NOTES:
3750 drw 17
1. CE0 and R/W = VIL; CE1 and CNTRST = VIH.
2. CE0 = VIL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.ADDR0 will be accessed. Extra cycles are
shown here simply for clarification.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance.
The ‘An +1’ address is written to during this cycle.
16
6.42
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Functional Description
Depth and Width Expansion
The IDT70V9089/79 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold times
on address, data, and all critical control inputs. All internal registers are
clocked on the rising edge of the clock signal, however, the self-timed
internal write pulse is independent of the LOW to HIGH transition of the clock
signal.
An asynchronous output enable is provided to ease asynchronous
bus interfacing. Counter enable inputs are also provided to stall the
operation of the counter registers for fast interleaved memory applications.
A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down
the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT70V9089/79's for depth
expansion configurations. When the Pipelined output mode is enabled, two
cycles are required with CE0 LOW and CE1 HIGH to re-activate the
outputs.
The IDT70V9089/79 features dual chip enables (refer to Truth Table
I) in order to facilitate rapid and simple depth expansion with no requirements for external logic. Figure 4 illustrates how to control the various chip
enables in order to expand two devices in depth.
The IDT70V9089/79 can also be used in applications requiring
expanded width, as indicated in Figure 4. Since the banks are allocated
at the discretion of the user, the external controller can be set up to drive
the input signals for the varioius devices as required to allow for 16-bit or
wider applications.
A16/A15(1)
IDT70V9089/79
CE0
CE1
CE1
VDD
CE1
IDT70V9089/79
VDD
CE1
CE0
CE0
Control Inputs
CE0
Control Inputs
Control Inputs
IDT70V9089/79
IDT70V9089/79
Control Inputs
3750 drw 18
Figure 4. Depth and Width Expansion with IDT70V9089/79
NOTE:
1. A16 is for ID70V9089. A15 is for ID70V9079.
6.42
17
,
CNTRST
CLK
ADS
CNTEN
R/W
OE
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
IDT
XXXXX
A
99
Device
Type
Power
Speed
A
Package
A
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF
100-pin TQFP (PN100-1)
6
7
9
12
15
Commercial
Commercial
Commercial
Commercial
Commercial
S
L
Standard Power
Low Power
Only
Only
& Industrial
Only
Only
Speed in nanoseconds
,
70V9089 512K (64K x 8-Bit) Synchronous Dual-Port RAM
70V9079 256K (32K x 8-Bit) Synchronous Dual-Port RAM
3750 drw 19
Ordering Information for Flow-through Devices
Old Flow-through Part
New Combined Part
70V908S/L25
70V9089S/L12
70V908S/L30
70V9089S/L15
3750 tbl 12
Old Flow-through Part
New Combined Part
70V908S/L25
70V9079S/L12
70V908S/L30
70V9079S/L15
3750 tbl 13
IDT Clock Solution for IDT70V9089/79 Dual-Port
Dual-Port I/O Specitications
IDT Dual-Port
Part Number
Voltage
70V9089/79
3.3
Clock Specifications
I/O
Input
Capacitance
Input Duty
Cycle
Requirement
Maximum
Frequency
Jitter
Tolerance
LVTTL
9pF
40%
100
150ps
IDT
PLL
Clock Device
IDT
Non-PLL Clock
Device
2305
2308
2309
49FCT3805
49FCT3805D/E
74FCT3807
74FCT3807D/E
3750 tbl 14
18
6.42
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Datasheet Document History
1/18/99:
6/11/99:
11/12/99:
3/31/00:
1/10/01:
01/15/04:
05/11/04:
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Added additional notes to pin configurations
Page 14 Added Depth and Width Expansion section.
Page 3 Deleted note 6 for Table II
Replaced IDT logo
Combined Pipelined 70V9089 family and Flow-through 70V908 family offerings into one data sheet
Changed ±200mV in waveform notes to 0mV
Added corresponding part chart with ordering information
Page 3 Changed information in Truth Table II
Page 4 Increased storage temperature parameters
Clarified TA parameter
Page 5 DC Electrical parameters–changed wording from "open" to "disabled"
Removed Preliminary Status
Consolidated multiple devices into one datasheet
Changed naming conventions from VCC to VDD and from GND to Vss
Removed I-temp footnote from tables
Page 2 Added date revision to pin configuration
Page 4 Added JunctionTemperature to Absolute Maximum Ratings Table
Added Ambient Temperature footnote
Page 5 Added I-temp numbers for 9ns speed to the DC Electrical Characteristics Table
Added 6ns & 7ns speeds DC power numbers to the DC Electrical Characteristics Table
Page 7 Added I-temp for 9ns speed to AC Electrical CharacteristicsTable
Added 6ns & 7ns speeds AC timing numbers to the AC Electrical Characteristics Table
Page 16 Added 6ns & 7ns speeds grade and 9ns I-temp to ordering information
Added IDT Clock Solution Table
Page 1 & 17 Replaced  IDT logo with TM new logo
Page 1 & 19 Added 7ns speed grade to ordering information
Page 5 Added 7ns speed DC power numbers to the DC Electrical Characteristics Table
Page 8 Added 7ns speed AC timing numbers to the AC Electrical Characteristics Table
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6.42
19
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