IDT7198S IDT7198L CMOS STATIC RAMs 64K (16K x 4-BIT) Added Chip Select and Output Controls Integrated Device Technology, Inc. nized as 16K x 4. It is fabricated using IDT’s high-performance, high-reliability technology—CMOS. This state-of-theart technology, combined with innovative circuit design techniques, provides a cost effective approach for memory intensive applications. Access times as fast as 20ns are available. The IDT7198 offers a reduced power standby mode, ISB1, which is activated when CS1 or CS2 goes HIGH. This capability decreases power, while enhancing system reliability. The low-power version (L) also offers a battery backup data retention capability where the circuit typically consumes only 30µW when operating from a 2V battery. All inputs and outputs are TTL-compatible and operate from a single 5V supply. The lDT7198 is packaged in either a 24-pin ceramic DlP, 28-pin leadless chip carrier, and 24-pin CERPACK. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. FEATURES: • Fast Output Enable (OE) pin available for added system flexibility • Multiple Chip Selects (CS1, CS2) simplify system design and operation • High speed (equal access and cycle times) — Military: 20/25/35/45/55/70/85ns (max.) • Low power consumption • Battery back-up operation—2V data retention (L version only) • 24-pin CERDIP, high-density 28-pin leadless chip carrier, and 24-pin CERPACK packaging available • Produced with advanced CMOS technology • Bidirectional data inputs and outputs • Inputs/outputs TTL-compatible • Military product compliant to MIL-STD-883, Class B DESCRIPTION: The IDT7198 is a 65,536 bit high-speed static RAM orga- FUNCTIONAL BLOCK DIAGRAM A0 VCC GND 65,536-BIT MEMORY ARRAY DECODER A13 I/O0 I/O1 I/O2 COLUMN I/O INPUT DATA CONTROL I/O3 CS1 CS2 WE1 OE 2985 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY TEMPERATURE RANGE 1994 Integrated Device Technology, Inc. MAY 1994 6.4 DSC-1027/4 1 IDT7198S/L CMOS STATIC RAM 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls MEMORY CONTROL MILITARY TEMPERATURE RANGE PIN DESCRIPTIONS The IDT7198 64K high-speed CMOS static RAM incorporates two additional memory control features (an extra chip select and an output enable pin) which offer additional benefits in many system memory applications. Both chip selects, Chip Select 1 (CS1) and Chip Select 2 (CS2), must be LOW to select the memory. If either chip select is pulled HIGH, the memory will be deselected and remain in the standby mode. This dual chip select feature (CS1, CS2) also brings the convenience of improved system speeds to the large memory designer by reducing the external logic required to perform decoding. Name Description A0–A13 Address Inputs CS1 Chip Select 1 CS2 Chip Select 2 WE Write Enable OE Output Enable I/O0–I/O3 Data I/O VCC Power GND Ground 2985 tbl 01 TRUTH TABLE(1) PIN CONFIGURATIONS Mode A0 A1 A2 A3 A4 A5 A6 A7 A8 1 24 2 3 23 22 4 21 5 20 D24-1 E24-1 6 8 19 18 17 9 16 CS 1 10 15 OE 11 16 GND 12 15 7 V CC A 13 A 12 A 11 A 10 A9 CS 2 I/O 3 I/O 2 I/O 1 I/O 0 CS1 CS2 WE OE I/O Power Standby H X X X High-Z Standby Standby X H X X High-Z Standby Read L L H L DOUT Active Write L L L X DIN Active Read L L H H High-Z Active NOTE: 1. H = VIH, L = VIL, X = don't care. WE 2985 drw 02 ABSOLUTE MAXIMUM RATINGS(1) DIP/SOJ/CERPACK TOP VIEW Symbol VTERM A0 NC NC V CC NC 3 4 1 28 27 26 5 25 6 24 7 23 L28-2 8 22 9 21 10 20 11 19 18 12 13 14 15 16 17 OE GND CS 2 WE I/O 0 A1 A2 A3 A4 A5 A6 A7 A8 CS 1 2 NC A 13 A 12 A 11 A 10 A9 I/O3 I/O2 I/O1 Rating Mil. Unit Terminal Voltage with Respect to GND –0.5 to +7.0 V Operating Temperature –55 to +125 °C TBIAS Temperature Under Bias –65 to +135 °C TSTG Storage Temperature –65 to +150 °C TA INDEX 2985 tbl 02 PT IOUT Power Dissipation 1.0 W DC Output Current 50 mA NOTE: 2985 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2985 drw 03 LCC TOP VIEW 6.4 2 IDT7198S/L CMOS STATIC RAMS 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls RECOMMENDED DC OPERATING CONDITIONS Symbol MILITARY TEMPERATURE RANGE RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V GND Supply Voltage 0 0 0 V VIH Input High Voltage 2.2 — 6.0 V VIL Input Low Voltage –0.5(1) — 0.8 V Grade Ambient Temperature Military –55°C to +125°C GND VCC 0V 5V ± 10% 2985 tbl 06 CAPACITANCE (TA = +25°C, f = 1.0MHz, VCC = 0V) Parameter(1) Symbol NOTE: 2985 tbl 05 1. VIL (min.) = -3.0V for pulse width less than 20ns, once per cycle. CIN Input Capacitance CI/O I/O Capacitance Conditions Max. Unit VIN = 0V 7 pF VOUT = 0V 7 pF NOTE: 2985 tbl 04 1. This parameter is determined by device characterization, but is not production tested. DC ELECTRICAL CHARACTERISTICS VCC = 5.0V ± 10%, Military Temperature Range Only IDT7198S Symbol Parameter Test Condition IDT7198L Min. Max. Min. Max. Unit |ILI| Input Leakage Current VCC = Max., VIN = GND to VCC — 10 — 5 µA |ILO| Output Leakage Current VCC = Max., CS = VIH, VOUT = GND to VCC — 10 — 5 µA VOL Output Low Voltage IOL = 10mA, VCC = Min. 0.5 — 0.5 V IOL = 8mA, VCC = Min. — 0.4 — 0.4 IOH = –4mA, VCC = Min. 2.4 — 2.4 — VOH Output High Voltage V 2985 tbl 07 AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V AC Test Load See Figures 1 and 2 2985 tbl 10 5V 5V 480Ω 480Ω DATA OUT DATA OUT 255Ω 255Ω 30pF* 2985 drw 05 5pF* 2985 drw 06 Figure 1. AC Test Load Figure 2. AC Test Load (for tCLZ1, 2, tOLZ, tCHZ1, 2, tOHZ, tOW and tWHZ) *Includes scope and jig capacitances 6.4 3 IDT7198S/L CMOS STATIC RAM 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls MILITARY TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS(1) (VCC = 5V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V) Symbol ICC1 ICC2 ISB ISB1 7198S20 7198L20 7198S25 7198L25 7198S35 7198L35 Power Military Military Military Military Military Military Unit Operating Power Supply Current, CS1 and CS2 ≤ VIL, Outputs Open VCC = Max., f = 0(2) S 105 105 105 105 105 105 mA L 80 80 80 80 80 80 Dynamic Operating Current, CS1 and CS2 ≤ VIL, Outputs Open VCC = Max., f = fMAX(2) S 160 155 140 140 140 140 L 130 120 115 110 110 105 Standby Power Supply Current (TTL Level), CS1 or CS2 ≥ VIH, VCC = Max., Outputs Open, f = fMAX(2) S 70 60 50 50 50 50 L 50 40 35 35 35 35 Full Standby Power Supply Current (CMOS Level) CS1 or CS2 ≥ V HC, VCC= Max., VIN ≥ VHC or VIN ≤ VLC, f = 0(2) S 25 20 20 20 20 20 L 1.5 1.5 1.5 1.5 1.5 1.5 Parameter 7198S45 7198S55/70 7198S85 7198L45 7198L55/70 7198L85 NOTES: 1. All values are maximum guaranteed values. 2. At f = fMAX address and data inputs are cycling at the maximum frequency of read cycles of 1/tRC. f = 0 means no input lines change. mA mA mA 2985 tbl 06 DATA RETENTION CHARACTERISTICS OVER MILITARY TEMPERATURE RANGE (L Version Only) VLC = 0.2V, VHC = VCC - 0.2V Typ. (1) VCC @ Symbol Parameter VDR VCC for Data Retention ICCDR Data Retention Current tCDR(3) Chip Deselect to Data Retention Time tR(3) Operation Recovery Time (3) |ILI| Test Condition Min. — 2.0v Max. VCC @ 3.0V 2.0V 3.0V Unit 2.0 — — — — V — 10 15 600 900 µA 0 — — — — ns or CS2 ≥ VHC VIN ≥ VHC or ≤ VLC CS1 tRC(2) — — — — ns — — — 2 2 µA Input Leakage Current NOTES: 2985 tbl 09 1. TA = +25°C. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed by device characterization but is not production tested. LOW VCC DATA RETENTION WAVEFORM VCC 4.5V 4.5V VDR ≥2V t CDR CS DATA RETENTION MODE V IH VDR tR V IH 2985 drw 04 6.4 4 IDT7198S/L CMOS STATIC RAMS 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls MILITARY TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, Military Temperature Range) 7198S20 7198L20 Symbol Parameter 7198S25 7198L25 7198S35/45 7198L35/45 7198S55 7198L55 7198S70 7198L70 7198S85 7198L85 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Read Cycle tRC tAA — 35/45 — 55 — 70 — 85 — ns 19 — 25 — 35/45 — 55 — 70 — 85 ns Chip Select-1,2 Access Time — 20 — 25 — 35/45 — 55 — 70 — 85 ns (2) Chip Select-1,2 to Output in Low-Z 5 — 5 — 5 5 — 5 — 5 — ns Output Enable to Output Valid — 9 — 11 — 20/25 — 35 — 45 — 55 ns Output Enable to Output in Low-Z 5 — 5 — 5 — 5 — 5 — 5 — ns Chip Select 1,2 to Output in High-Z — 8 — 10 — 14 — 20 — 25 — 30 ns Output Disable to Output in High-Z — 8 — 9 — 15 — 20 — 25 — 30 ns tCHZ1,2 (2) tOH 25 — (2) tOHZ — Address Access Time tOE tOLZ 20 (1) tACS1,2 tCLZ1,2 Read Cycle Time (2) — Output Hold from Address Change 5 — 5 — 5 — 5 — 5 — 5 — ns tPU (2) Chip Select to Power Up Time 0 — 0 — 0 — 0 — 0 — 0 — ns tPD (2) Chip Deselect to Power Down Time — 20 — 25 — 35/45 — 55 — 70 — 85 ns NOTES: 1. Both chip selects must be active low for the device to be selected. 2. This parameter is guaranteed by device characterization but is not production tested. 2985 tbl 11 TIMING WAVEFORM OF READ CYCLE NO. 1(1) tRC ADDRESS tAA tOH OE tOLZ CS1, tOE (5) tOHZ (5) 2 tACS1, 2 tCLZ1, 2 tCHZ1, 2 (5) (5) DATA VALID DATAOUT 2985 drw 07 NOTES: 1. WE is HIGH for Read cycle. 2. Device is continuously selected, CS1 is LOW, CS2 is LOW. 3. Address valid prior to or coincident with CS1 and or CS2 transition LOW. 4. OE is LOW. 5. Transition is measured ±200mV from steady state voltage. 6.4 5 IDT7198S/L CMOS STATIC RAM 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls MILITARY TEMPERATURE RANGE TIMING WAVEFORM OF READ CYCLE NO. 2(1, 2, 4) tRC ADDRESS tAA tOH tOH PREVIOUS DATA VALID DATAOUT DATA VALID 2985 drw 08 TIMING WAVEFORM OF READ CYCLE NO. 3(1, 3, 4) CS1,2 tCHZ1, 2 tACS1, 2 (5) tCLZ1, 2 (5) DATAOUT DATA VALID tPU tPD ICC VCC SUPPLY CURRENT ISB 2985 drw 09 NOTES: 1. WE is HIGH for Read cycle. 2. Device is continuously selected, CS1 is LOW, CS2 is LOW. 3. Address valid prior to or coincident with CS1 and or CS2 transition LOW. 4. OE is LOW. 5. Transition is measured ±200mV from steady state voltage. AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges) 7198S20 7198L20 Symbol Parameter 7198S25 7198L25 7198S35/45 7198L35/45 Min. Max. Min. Max. Min. 7198S55 7198L55 7198S70 7198L70 7198S85 7198L85 Max. Min. Max. Min. Max. Min. Max. Unit Write Cycle Write Cycle Time 17 — 20 — 30/40 — 50 — 60 — 75 — ns tCW1,2(1) Chip Select to End-of-Write 17 — 20 — 25/35 — 50 — 60 — 75 — ns 17 — 20 — 25/35 — 50 — 60 — 75 — ns tWC tAW Address Valid to End-of-Write tAS Address Set-up Time 0 — 0 — 0 — 0 — 0 — 0 — ns tWP Write Pulse Width 17 — 20 — 25/35 — 50 — 60 — 75 — ns tWR1,2 Write Recovery Time 0 — 0 — 0 — 0 — 0 — 0 — ns tWHZ(2) Write Enable to Output in High-Z — 5/6 — 7 — 10/15 — 25 — 30 — 40 ns tDW Data Valid to End-of-Write 10 — 13 — 15/20 — 25 — 30 — 35 — ns tDH Data Hold Time 0 — 0 — 0 — 0 — 0 — 0 — ns tOW(2) Output Active from End-of-Write 5 — 5 — 5 — 5 — 5 — 5 — NOTES: 1. Both chip selects must be active low for the device to be selected. 2. This parameter is guaranteed by device characterization but is not production tested. 6.4 ns 2985 tbl 12 6 IDT7198S/L CMOS STATIC RAMS 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls MILITARY TEMPERATURE RANGE TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1, 2, 3, 7) tWC ADDRESS OE tAW CS1, 2 tWP (7) tAS tWR WE tWHZ (6) tOW (6) (4) DATAOUT (4) tDW DATAIN tDH DATA VALID 2985 drw 10 TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1) tWC ADDRESS tAW CS1, 2 tAS tCW tWR WE tDW DATAIN tDH DATA VALID 2985 drw 11 NOTES: 1. WE, CS1 or CS2 must be HIGH during all address transitions. 2. A write occurs during the overlap (tWP) of a LOW WE, a LOW CS1 and a LOW CS2. 3. tWR is measured from the earlier of CS1, CS2 or WE going HIGH to the end of the write cycle. 4. During this period, the I/O pins are in the output state, and input signals must not be applied. 5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, outputs remain in the high-impedance state. 6. Transition is measured ±200mV from steady state. 7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 6.4 7 IDT7198S/L CMOS STATIC RAM 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls MILITARY TEMPERATURE RANGE ORDERING INFORMATION IDT7198 X XX X B Device Type Power Speed Package Process/ Temperature Range 6.4 B Military (–55°C to +125°C) Compliant to MIL-STD-883, Class B D L E 300 mil Ceramic DIP (D24-1) Leadless Chip Carrier (L28-2) CERPACK (E24-1) 20 25 35 45 55 70 85 Military Only Military Only Military Only Military Only Military Only Military Only Military Only S L Standard Power Low Power Speed in nanoseconds 2985 drw 12 8